JPH09259031A - Frame memory access control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the access interruption of plotting owing to the generation of access for refresh and transferring screen display data. SOLUTION: A refresh control circuit 140 generates three kinds of refresh requests 141, 142 and 143 different in the degree of emergency in access. A serial data control circuit 150 similarly generates three kinds of data transfer requests for screen display 151, 152 and 153 different in the degree of emergency in access. A plotting data control circuit 160 generates the access of plotting data. A frame memory control circuit 170 arbitrates the access requests of the respective control circuits 140, 150 and 160. The refresh request and the data transfer request with the high degree of emergency are selected by a circuit which actually accesses to a frame memory 180. When the degree of emergency is low, plotting access 161 is selected in accordance with the access state of plotting data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame memory access control method that is accessed by a plurality of types of access requests, and more particularly to accessing a frame memory for drawing data, such as a screen drawing device having a frame memory.
The present invention relates to a frame memory access control method suitable when refresh access and data transfer access for screen display are mixed.

[0002]

2. Description of the Related Art Conventionally, in a screen drawing apparatus or the like, a frame memory access request is issued for refreshing the frame memory and creating serial data for screen display while accessing drawing data to the frame memory. Due to the peculiarity of the request, the drawing data access is always interrupted and the processing is performed. Since it is necessary to confirm the screen display for these requests, a counter is used and access requests are generated at a certain fixed timing, so that there is no flexibility. Therefore, page access (a faster access method than the normal single access that can be used when continuously reading and writing data within the same ROW address of the memory) is used for accessing the frame memory of drawing data. In this case, the interruption for access other than the access of the drawing data causes a time for ending the page access and a time for starting the page access again.

In Japanese Patent Laid-Open No. 1-1201785, it has been proposed to improve the efficiency of memory access for screen display. Here, however, the drawing data is accessed to the frame memory as low-speed access, and arbitration is performed. Therefore, it does not affect the drawing performance of the system so much.

[0004]

With the increase in the speed of the system bus connected to the screen drawing device, the access time for drawing for the drawing, which occupies the entire available access time of the frame memory, is the performance of the entire screen drawing device. Is affecting. Therefore, the occurrence of a time difference with respect to the frame memory due to the interruption of page access unnecessarily deteriorates the performance. This is not limited to the screen drawing device, and generally, when multiple types of access requests are arbitrated to access the frame memory, an access request with a high arbitration priority is accessed during access to the frame memory with an access request with a low arbitration priority. The same applies when the access occurs and the access is interrupted.

An object of the present invention is to improve the performance of a device utilizing a frame memory by minimizing the interruption of access to the frame memory for an access request having a low arbitration priority due to the occurrence of an access request having a high arbitration priority. Is to let.

[0006]

According to the present invention, in a frame memory access control for accessing a frame memory by arbitrating a plurality of types of access requests, which generally occur independently of each other, access requests with high arbitration priority are accessed. In the case of an access request that occurs in multiple levels according to the urgency and that requires an urgent priority with high arbitration priority, the access request is selected as is, but in the case of an access request that does not require an emergency and has a high arbitration priority. First, depending on the access state of the access request having the low arbitration priority, the access request having the low arbitration priority is selected.

For example, in a screen drawing device having a frame memory, a refresh access request and a data transfer access request for screen display are generated by being divided into a plurality of levels according to the urgency of access, and a refresh access request with a high degree of urgency is generated. Alternatively, the data transfer access request selects the access request as it is. However, in the case of a refresh access request or a data transfer access request having a low degree of urgency, these access requests are selected only when the access of the drawing access request is not hindered. That is what I did. As a result, if access for refreshing or creating serial data for screen display occurs while accessing the drawing data to the frame memory, and if it is not urgent, access the drawing data. It is possible to give priority to the interruption of drawing data access.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described in detail below with reference to the drawings by taking the case of application to a screen drawing device as an example.

FIG. 1 is an overall block diagram of a screen drawing apparatus according to an embodiment of the present invention. In the figure, 10 is a central processing unit (CPU), 100 is a screen drawing device, and 200 is a display device, and the CPU 10 and the screen drawing device 100 are generally connected by a system bus.

The screen drawing apparatus 100 comprises a control circuit 110, a frame memory 180, and a display data conversion circuit 190. The frame memory 180 is a DRAM (dynamic random access memory) or a VRAM (video
Random access memory). The VRAM is a memory for a specific purpose such as a screen drawing device that can read and write data in parallel and can also read and write data in serial. The display data conversion circuit 190 sequentially converts the serial data output from the frame memory 180 into a display device 2 such as a CRT.
A circuit for converting to 00 data. For CRT, there is a DAC (digital-analog converter) or the like.

The control circuit 110 includes a bus control circuit 120, a refresh control circuit 140, and a serial data control circuit 1.
50, a drawing data control circuit 160 and a frame memory control circuit 170, each connected to the internal bus 130.

The bus control circuit 120 is a control circuit for sending drawing data and the like of the system bus to the internal bus 130. The refresh control circuit 140 is the frame memory 18
This is a circuit for controlling refresh access required to hold 0 data, and in this embodiment, three-step (three-level) refresh requests 141, 142, 143 are output according to the urgency of access. It shall be. The serial data control circuit 150 is a circuit for controlling the data in the frame memory 180 to be read and sent as serial data to the display conversion circuit 190 for screen display on the display device 200. Similarly, in the present embodiment, Data transfer access requests 151, 152, and 153 in three stages (three levels) are output according to the urgency of access. The drawing data control circuit 160 is a frame memory 180.
Is a circuit for controlling the generation and processing of the drawing data written in, and outputs the drawing access request 161. The frame memory control circuit 170 is a circuit that arbitrates access requests that can be simultaneously generated from the control circuits 140, 150, and 160 to the frame memory 180 and actually accesses the frame memory 180. The frame memory control circuit 170 includes a control circuit 14
When an access request of 0, 150, or 160 is accepted, the acceptance signal 171 is sent to the control circuit of the access request source.
Return 172 or 173.

FIG. 2 is a diagram showing a detailed configuration of the refresh control circuit 140. In the figure, a refresh counter 20 is a free-run counter capable of counting the time required to satisfy the refresh regulation of the frame memory 180. The refresh counter 20
Are initialized by a refresh request acceptance signal 171 output from the frame memory control circuit 170 when a refresh access request from the refresh control circuit 140 to the frame memory 180 is accepted. The adder (1) 24 outputs the result of adding the increment value (1) 22 to the output value of the refresh counter 20. Similarly, for the adder (2) 25, the refresh counter 2
The result of adding the increment value (2) 23 to the output value of 0 is output. Here, the increment value is increment value 1 <increment value 2. The comparison circuit (1) 26 compares the output value of the refresh counter 20 with the comparison value 21, and if they match, the refresh request 1
41 is output. The comparison circuit (2) 27 has an adder (1)
The output value of 24 is compared with the comparison value 21, and if they match, the refresh request 142 is output, and similarly, the comparison circuit (3) 2
8 compares the output value of the adder (2) 25 with the comparison value 21, and outputs a refresh request 143 if they match.

Refresh requests 141, 142, 143
Are 143, 142, 141 in the order of occurrence.
Are output in this order. Here, the refresh request 141
Indicates that the refresh should be performed immediately, and the refresh request 142 indicates that the refresh should be performed soon. Also, the refresh request 14
3 indicates that it is necessary to refresh after a while. That is, the urgency of the refresh request is 143 →
It becomes higher in the order of 142 → 141.

Similarly to the refresh control circuit 140, the serial data control circuit 150 also has three types of data transfer requests 15 generated in different time sequences.
1, 152, 153 are created and output to the frame memory control circuit 170.

FIG. 3 is a diagram showing a detailed configuration of the frame memory control circuit 170. Frame memory control circuit 1
Reference numeral 70 is a memory access type determination circuit 30 that arbitrates frame memory access requests input from the control circuits 140, 150, and 160, and determines whether the drawing data of the drawing data control circuit 160 can be accessed in page mode. A page mode access determination circuit 31 for performing access, and RAS (row address sequence) for actually accessing the frame memory 180, C
It comprises a frame memory access control circuit 32 for generating various sequences such as AS (column address sequence).

The page mode access determination circuit 31 is an access request processing circuit 3 of the memory access type determination circuit 30.
5 selects the drawing access request 161 from the drawing data control circuit 160, the drawing access request 161
Are continuously input, and the continuous access is to the same ROW address of the frame memory 180, the page mode signal 36 is output.

The memory access type decision circuit 30 comprises decision circuits 33 and 34 and an access request processing circuit 35. The determination circuit (1) 33 includes three types of refresh requests 141, 142, 143 from the refresh control circuit 140,
An access request 161 from the drawing data control circuit 160,
Also, the page mode access decision circuit 31 inputs the page moji signal 36, and the refresh access request 3
It is determined whether or not 7 should be output. In the case of the present embodiment, the determination circuit (1) 33 prioritizes the drawing access to the frame memory 180 when the drawing access request 161 is input when the refresh access request 143 of low urgency is input. The output of the refresh access request 37 is suppressed, and the refresh access request 37 is output when the drawing access request 161 is not input. In addition, a refresh request 142 of medium urgency
Is input, the drawing access request 161 is prioritized only when the drawing access request 161 to the frame memory 180 is present and the page mode signal 35 is output from the page mode access determination circuit 31. The output of the refresh access request 37 is suppressed, and when the page mode ends, the refresh access request 37 is output. When the refresh request 141 with the highest urgency is input, it is necessary to refresh immediately.
Immediately, the refresh access request 37 is output. The concrete logic circuit of the judgment circuit (1) 33 is as shown in FIG. Also in the determination circuit (2) 34, three types of data transfer requests 151, 152, 153 from the serial data control circuit 150 having different degrees of urgency, and the drawing data control circuit 1
The drawing access request 161 from the page 60 and the page mode signal 36 from the page mode access determination circuit 31 are input, and the data transfer access request 38 is output with the same configuration as in FIG. The access request processing circuit 35 arbitrates each access request of the refresh access request 37, the data transfer access request 38, and the drawing access request 161, and assigns the determined memory access type to the frame access control circuit 32 and the page mode access determination circuit 31. Simultaneously with the notification, access request acceptance signals 171, 172, 173 are issued to the access request source control circuit corresponding to the determined memory access type. The arbitration priority of the access request processing circuit 35 is in the order of the refresh access request 37, the data transfer access request 38, and the drawing access request 161.

According to the present embodiment, the frame memory access of the drawing data is performed by giving the increment value (22, 23, etc. in FIG. 2) an appropriate value for restricting the generation condition of the refresh access request and the data transfer access request. The frequency of interrupts during page mode access in is extremely low, and the time for accessing drawing data to the frame memory can be effectively used.

In FIG. 2, three kinds of comparison values 21 are prepared, so that the increment values 22, 23, the adder 24,
It is also possible to eliminate 25. Further, in this embodiment, the level is divided into three, but if it is two or more, some effect can be expected. When the size or configuration of the frame memory is changed, the desired effect can always be obtained by changing the parameter such as the increment value.

Although the case where the present invention is applied to the screen drawing apparatus has been described above as an example, the present invention is not limited to the screen drawing apparatus, and various types of frame memories having a frame memory are provided without departing from the scope of the invention. It goes without saying that it can be applied to a device.

[0022]

As described above, according to the frame memory access control method of the present invention, the interruption of the frame memory access of the access request having the low arbitration priority can be suppressed to the minimum. Especially when applied to a screen drawing device, it is possible to reduce interruption of drawing access due to access for refresh or data transfer for screen display, which occurs while accessing drawing data to the frame memory. It is possible to increase the ratio of drawing data access to the entire memory access.

[Brief description of drawings]

FIG. 1 is a block diagram of an overall configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing a specific configuration example of a refresh control circuit of FIG.

FIG. 3 is a diagram showing a configuration example of a frame memory control circuit in FIG.

FIG. 4 is a diagram showing a specific configuration example of a determination circuit in FIG.

[Explanation of symbols]

 100 screen drawing device 140 refresh control circuit 141 to 143 refresh access request 150 serial data control circuit 150 to 153 data transfer access request 160 drawing data control circuit 161 drawing access request 170 frame memory control circuit 171, 172, 173 access request acceptance signal 180 Frame memory 190 Display data conversion circuit 200 Display device

Claims (3)

[Claims] 1. A frame memory access control method for accessing a frame memory by arbitrating a plurality of types of access requests independently generated, wherein a plurality of access requests with high arbitration priority are generated according to the urgency of access. The access request with high arbitration priority that requires urgency is selected as it is, and in the case of the access request with high arbitration priority that does not require emergency, the access request with low arbitration priority is selected. A frame memory access control method, characterized in that an access request having either a high arbitration priority or a low arbitration priority is selected according to an access state. 2. The frame memory access control method according to claim 1, wherein when the configuration of the frame memory is changed, the level dividing parameter is changed. 3. A screen drawing device having a frame memory, an access request for refreshing (hereinafter referred to as refresh access request), an access request for data transfer of screen display (hereinafter referred to as data transfer access request), and drawing. Is a frame memory access control method for arbitrating an access request (hereinafter, referred to as a drawing access request) for accessing a frame memory, wherein a plurality of refresh access requests and data transfer access requests are generated according to the urgency of the access. In the case of the refresh access request or the data transfer access request requiring urgency, the access request is selected and the drawing access is selected in the case of the refresh access request or the data transfer access request requiring no emergency. A frame memory access control method, wherein the refresh access request or the data transfer access request is selected only when the access of the access request is not hindered.