JPH06259314A - Memory controller - Google Patents

Abstract

PURPOSE:To provide the memory controller which is small in circuit scale and performs memory control fast. CONSTITUTION:A memory device 4 has a data transfer mode. A memory access request device 1 sends a request to access data to the memory device 4. A transfer request device 2 sends a request to transfer data to the memory device 4. An arbitration device 3 arbitrates the memory access request signal from the memory access request device 1 and the transfer request signal from the transfer request device 2, and outputs a memory control signal for memory access to the memory device 4 by being supplied with a memory access status signal from the memory access request device 1 when the memory access request signal is selected as a result of the arbitration and a memory control signal for transfer and a memory control signal for refreshing successively to the memory device 4 by being supplied with a transfer status signal from the transfer request device 2 when the transfer request signal is selected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control device for controlling a dynamic memory.

[0002]

2. Description of the Related Art In recent years, as computers have become faster and memories have become faster, there has been a demand for faster memory control devices. The conventional memory control device includes a memory access request device 31 and a transfer request device 32 as shown in FIG.
And an arbitration device 33, a memory device 34, and a refresh request device 35.

In this conventional memory control device, when accessing the memory device 34, the memory access request device 31 generates a memory access request signal at an arbitrary time, and the transfer request device 32 transfers the data. The transfer request signal is generated at the required time, and the refresh request device 35 generates the refresh request signal at the required refresh time. When the arbitration device 33 arbitrates a plurality of request signals and, as a result, selects the memory access request signal, the memory access request device 31.
A memory control signal is generated based on the memory access status signal from the memory device 34 and output to the memory device 34, and when the transfer request signal is selected, the memory control signal is generated based on the transfer status signal from the transfer request device 32. When the refresh request signal is output to the memory device 34 and selected, the memory control signal is created based on the refresh status signal from the refresh request device 35 and output to the memory device 34.

FIG. 6 is an explanatory diagram of a timing chart of input / output signals of the arbitration device 33 in the conventional memory control device. In the memory device 34, if the row address is the same in successive memory accesses, the input can be omitted. When the memory access request device 31 continuously generates the memory access request signal MREQ, the transfer request device 32 generates the transfer request signal TREQ, and the refresh request device 35 generates the refresh request signal RREQ. 2 is a timing chart of. The memory device 34 is
When the memory control signal RAS falls, the row address is fetched, when the memory control signal CAS falls, the column address is fetched, and when the memory control signal RAS falls, the transfer mode is designated. If the memory control signal RAS is at a high level at the fall of the memory control signal CAS, the internal counter is used for refreshing.

[0005]

However, in the above-mentioned conventional configuration, since the generation of the transfer request and the generation of the refresh request are independent of each other, the memory access request is
It is necessary to subject both the transfer request and the refresh request to arbitration, and an overhead for arbitration is generated every time the transfer request and the refresh request are generated, resulting in a problem that the speed cannot be increased. In addition, since there are multiple requests subject to arbitration other than memory access requests,
There is a problem that the circuit becomes complicated and the circuit scale becomes large.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a memory control device having a small circuit scale and capable of performing memory control at high speed.

[0007]

According to a first aspect of the present invention, there is provided a memory device having a data transfer mode, and a memory access request device for requesting data access to the memory device.
Arbitration is performed between a transfer request device that requests data transfer to the memory device, a memory access request signal from the memory access request device and a transfer request signal from the transfer request device, and the result of the arbitration is the memory access request signal. When the memory access request signal is selected, the memory access status signal is supplied from the memory access requesting device to output a memory control signal for memory access to the memory device. When the transfer request signal is selected, the transfer request is transmitted. An arbitration device that continuously outputs a memory control signal for transfer and a memory control signal for refresh to the memory device when a transfer status signal is supplied from the device. .

According to a second aspect of the present invention, the arbitration device continuously supplies a memory control signal for refreshing to the memory device based on the refresh status signal for determining the number of times of memory access for refreshing from the transfer requesting device. It is characterized in that it is configured to output a plurality of times.

[0009]

In the invention of claim 1, the memory device has a data transfer mode. The memory access requesting device requests data access to the memory device. The transfer request device requests the memory device to transfer data. The arbitration device is
Arbitration between the memory access request signal from the memory access request device and the transfer request signal from the transfer request device,
If the memory access request signal is selected as a result of arbitration,
When the memory access request signal is supplied from the memory access request device, a memory control signal for memory access is output to the memory device. When the transfer request signal is selected, the transfer request device supplies the transfer status signal. As a result, the memory control signal for transfer and the memory control signal for refresh are continuously output to the memory device.

According to another aspect of the invention, the arbitration device continuously supplies a memory control signal for refresh to the memory device based on a refresh status signal for determining the number of times of memory access for refresh from the transfer request device. Output multiple times.

[0011]

Embodiments of the present invention will now be described in detail with reference to the drawings. (Embodiment 1) FIG. 1 is a block diagram of a memory control device according to a first embodiment of the present invention. This memory control device comprises a memory access request device 1, a transfer request device 2, and an arbitration device 3.
And a memory device 4. The memory access requesting device 1 requests the memory device 4 for data access.
The transfer requesting device 2 requests the memory device 4 to transfer data. The arbitration device 3 arbitrates the memory access request signal from the memory access request device 1 and the transfer request signal from the transfer request device 2, and when the memory access request signal is selected as a result of the arbitration, the memory access request device 1 When a transfer request signal is selected by outputting a memory control signal for memory access to the memory device 4 by supplying a memory access status signal from the transfer request signal from the transfer request device 2. , And continuously outputs a memory control signal for transfer and a memory control signal for refresh. The memory device 4 has a data transfer mode.

FIG. 2 shows a mode in which the memory device 4 can omit the input if the row address is the same in successive memory accesses, and the memory access request device 1 continuously outputs the memory access request signal MREQ. 6 is an example of a timing chart of the input / output signals of the arbitration device 3 when the transfer request device 2 does not generate the transfer request signal TREQ.

The operation of the arbitration device 3 when the memory access request signal MREQ having the same row address is generated five times in succession will be described. First memory access request signal MREQ from the memory access request device 1
On the other hand, the memory access request device 1 supplies the memory access status signal to generate the memory control signals RAS and CAS. First, the memory control signal RAS is set to the low level, and then the memory control signal CAS is set to the low level. Output to the memory device 4. Next, since the row address is the same for the memory access request signal MREQ from the second time onward, the memory control signal RAS is fixed to the low level, and then the memory control signal CAS is set to the low level and the high level. , And the memory control signal RAS is set to the high level after the access is completed.

FIG. 3 shows a mode in which the memory device 4 can omit the input if the row address is the same in successive memory accesses, and the memory access request device 1 continuously outputs the memory access request signal MREQ. 6 is an example of a timing chart of input / output signals of the arbitration device 3 when the transfer request device 2 generates a transfer request signal TREQ.

Here, the arbitration device in the case where the memory access request signal MREQ having the same row address is generated five times in succession and the transfer request device 2 generates the transfer request signal TREQ after the end of the first memory access request. The operation of No. 3 will be described. In response to the first memory access request signal MREQ from the memory access requesting device 1, the memory access requesting device 1 supplies the memory access status signal to the memory control signals RAS, CAS, D.
T is created, first the memory control signal RAS is set to low level, and then the memory control signal CAS is set to low level. Next, the transfer request from the transfer request device 2 is accepted, and the memory control signal for transfer and the memory control signal for refresh are continuously output to the memory device 4. afterwards,
Since the row address is the same for the second and subsequent memory access requests, the memory control signal RAS is fixed at the low level, and then the output of the memory control signal CAS is changed to the low level and the high level four times. It is inverted and the memory control signal RAS is set to the high level after the access is completed.

As described above, the memory device 4 having the data transfer mode, the memory access request device 1 for requesting the memory device 4 for data access, the transfer request device 2 for requesting the memory device 4 for data transfer, and the memory access. Memory access request signal from request device 1 and transfer request device 2
When a memory access request signal is selected as a result of the arbitration, a memory access request signal is supplied from the memory access request device 1 to the memory device 4 for memory access. When the memory control signal is output and the transfer request signal is selected, the transfer status signal is supplied from the transfer request device 2, whereby the memory device 4 receives the memory control signal for transfer and the memory control signal for refresh. Since a plurality of memory access interruption factors are processed by one-time arbitration, it is possible to realize efficient memory access by reducing the arbitration overhead.

In the first embodiment, the memory device 4 is
Although there is a mode in which the input can be omitted if the row address is the same in successive memory accesses, and the internal counter is used for refreshing, the configuration is not necessarily required. In the first embodiment, the case where the memory accesses having the same row address are consecutively described has been described, but it is clear that the effect of the present invention does not occur only in such a case.

In the first embodiment, the number of refreshes executed when the transfer request is accepted is one, but it may be plural. (Embodiment 2) FIG. 4 is a block diagram of a memory control device according to a second embodiment of the present invention. This memory control device includes a memory access request device 11, a transfer request device 12, an arbitration device 13, and a memory device 14. It has and. The memory access requesting device 11 requests the memory device 14 for data access. The transfer request device 12 requests the memory device 14 for data transfer. The arbitration device 13 arbitrates the memory access request signal from the memory access request device 11 and the transfer request signal from the transfer request device 12, and when the memory access request signal is selected as a result of the arbitration, the memory access request device 11 Is supplied with a memory access status signal, a memory control signal for memory access is output to the memory device 14, and when the transfer request signal is selected, the transfer request signal is supplied from the transfer request device 12. , A memory control signal for transfer and a memory control signal for refresh are continuously output to the memory device 14. The memory control signal for refresh is continuously output from the arbitration device 13 to the memory device 14 a plurality of times based on the refresh status signal from the transfer requesting device 12 that determines the number of memory accesses for refreshing. . Memory device 1
4 has a data transfer mode. That is, the difference from FIG. 1 is that the transfer requesting device 12 outputs a refresh status signal indicating the number of refreshes to the arbitration device 13.

Next, the operation will be described. Similar to the first embodiment, when a transfer request is output from the transfer request device 12, at the same time, a refresh status signal indicating the number of refreshes to be performed is output. Arbitration device 13
When the transfer request is received as a result of the arbitration, after outputting the memory control signal for transfer to the memory device 14, the memory control signal for refreshing the number of times specified by the refresh status signal is continuously supplied to the memory device 14. And output.

As described above, the arbitration device 13 continuously supplies the memory device 14 with a memory control signal for refreshing based on the refresh status signal from the transfer requesting device 12 which determines the number of times of memory access for refreshing. Since it is configured to output multiple times, any refresh cycle can be realized.

[0021]

As described above, according to the present invention, a memory device having a data transfer mode, a memory access request device for requesting data access to the memory device, and a transfer request device for requesting data transfer to the memory device. Arbitrating a memory access request signal from the memory access request device and a transfer request signal from the transfer request device,
When the memory access request signal is selected as a result of the arbitration, a memory access status signal is supplied from the memory access request device, thereby outputting a memory control signal for memory access to the memory device, and transferring the transfer request. When a signal is selected, a transfer status signal is supplied from the transfer request device, and an arbitration device that continuously outputs a memory control signal for transfer and a memory control signal for refresh to the memory device. Since a plurality of memory access interruption factors can be processed by one arbitration, the arbitration overhead is small, and therefore the circuit scale is small and the memory control can be performed at high speed.

Further, the arbitration device outputs the memory control signal for refreshing to the memory device a plurality of times continuously based on the refresh status signal which determines the number of times of memory access for refreshing from the transfer requesting device. Then, an arbitrary refresh cycle can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram of a memory control device according to a first embodiment of the present invention.

FIG. 2 is a timing chart of input / output signals of the arbitration device included in the memory control device according to the first embodiment of the present invention.

FIG. 3 is a timing chart of input / output signals of the arbitration device included in the memory control device according to the first embodiment of the present invention.

FIG. 4 is a block diagram of a memory control device according to a second embodiment of the present invention.

FIG. 5 is a block diagram of a conventional memory control device.

FIG. 6 is a timing chart of input / output signals of an arbitration device provided in a conventional memory control device.

[Explanation of symbols]

 1 Memory Access Request Device 2 Transfer Request Device 3 Arbitration Device 4 Memory Device 11 Memory Access Request Device 12 Transfer Request Device 13 Arbitration Device 14 Memory Device

Claims (2)

[Claims] 1. A memory device having a data transfer mode, a memory access request device for requesting data access to the memory device, a transfer request device for requesting data transfer to the memory device, Arbitration is performed between the memory access request signal and the transfer request signal from the transfer request device, and when the memory access request signal is selected as a result of the arbitration, a memory access status signal is supplied from the memory access request device. When a memory control signal for memory access is output to the memory device and the transfer request signal is selected, a transfer status signal is supplied from the transfer request device,
An arbitration device that continuously outputs a memory control signal for transfer and a memory control signal for refresh to the memory device, and a memory control device. 2. The arbitration device is configured to continuously output a memory control signal for refreshing to the memory device a plurality of times based on a refresh status signal that determines the number of times of memory access for refreshing from the transfer requesting device. The memory control device according to claim 1, wherein: