JP5148029B2 - 構成可能な機能ユニットを備えるデータプロセッサ及びそのようなデータプロセッサを使用する方法 - Google Patents
構成可能な機能ユニットを備えるデータプロセッサ及びそのようなデータプロセッサを使用する方法 Download PDFInfo
- Publication number
- JP5148029B2 JP5148029B2 JP2000600174A JP2000600174A JP5148029B2 JP 5148029 B2 JP5148029 B2 JP 5148029B2 JP 2000600174 A JP2000600174 A JP 2000600174A JP 2000600174 A JP2000600174 A JP 2000600174A JP 5148029 B2 JP5148029 B2 JP 5148029B2
- Authority
- JP
- Japan
- Prior art keywords
- instruction
- instructions
- reconfigurable
- bits
- functional unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
- G06F9/3893—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator
- G06F9/3895—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros
- G06F9/3897—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros with adaptable data path
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Logic Circuits (AREA)
- Executing Machine-Instructions (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP99200431 | 1999-02-15 | ||
| EP99200431.7 | 1999-02-15 | ||
| PCT/EP2000/000590 WO2000049496A1 (en) | 1999-02-15 | 2000-01-26 | Data processor with a configurable functional unit and method using such a data processor |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2002537599A JP2002537599A (ja) | 2002-11-05 |
| JP2002537599A5 JP2002537599A5 (enExample) | 2007-03-29 |
| JP5148029B2 true JP5148029B2 (ja) | 2013-02-20 |
Family
ID=8239894
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000600174A Expired - Lifetime JP5148029B2 (ja) | 1999-02-15 | 2000-01-26 | 構成可能な機能ユニットを備えるデータプロセッサ及びそのようなデータプロセッサを使用する方法 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US6721884B1 (enExample) |
| EP (1) | EP1073951A1 (enExample) |
| JP (1) | JP5148029B2 (enExample) |
| KR (1) | KR100731371B1 (enExample) |
| WO (1) | WO2000049496A1 (enExample) |
Families Citing this family (76)
| Publication number | Priority date | Publication date | Assignee | Title |
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| DE19651075A1 (de) | 1996-12-09 | 1998-06-10 | Pact Inf Tech Gmbh | Einheit zur Verarbeitung von numerischen und logischen Operationen, zum Einsatz in Prozessoren (CPU's), Mehrrechnersystemen, Datenflußprozessoren (DFP's), digitalen Signal Prozessoren (DSP's) oder dergleichen |
| US6542998B1 (en) | 1997-02-08 | 2003-04-01 | Pact Gmbh | Method of self-synchronization of configurable elements of a programmable module |
| US7373440B2 (en) * | 1997-12-17 | 2008-05-13 | Src Computers, Inc. | Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors in a dual in-line memory module format |
| US7565461B2 (en) | 1997-12-17 | 2009-07-21 | Src Computers, Inc. | Switch/network adapter port coupling a reconfigurable processing element to one or more microprocessors for use with interleaved memory controllers |
| US6076152A (en) * | 1997-12-17 | 2000-06-13 | Src Computers, Inc. | Multiprocessor computer architecture incorporating a plurality of memory algorithm processors in the memory subsystem |
| DE50115584D1 (de) | 2000-06-13 | 2010-09-16 | Krass Maren | Pipeline ct-protokolle und -kommunikation |
| US7595659B2 (en) | 2000-10-09 | 2009-09-29 | Pact Xpp Technologies Ag | Logic cell array and bus system |
| US8058899B2 (en) | 2000-10-06 | 2011-11-15 | Martin Vorbach | Logic cell array and bus system |
| ATE498158T1 (de) * | 2000-11-06 | 2011-02-15 | Broadcom Corp | Umkonfigurierbares verarbeitungssystem und - verfahren |
| GB0028079D0 (en) * | 2000-11-17 | 2001-01-03 | Imperial College | System and method |
| JP3636986B2 (ja) | 2000-12-06 | 2005-04-06 | 松下電器産業株式会社 | 半導体集積回路 |
| EP1346280A1 (en) | 2000-12-20 | 2003-09-24 | Koninklijke Philips Electronics N.V. | Data processing device with a configurable functional unit |
| US9037807B2 (en) | 2001-03-05 | 2015-05-19 | Pact Xpp Technologies Ag | Processor arrangement on a chip including data processing, memory, and interface elements |
| US7581076B2 (en) | 2001-03-05 | 2009-08-25 | Pact Xpp Technologies Ag | Methods and devices for treating and/or processing data |
| US7444531B2 (en) | 2001-03-05 | 2008-10-28 | Pact Xpp Technologies Ag | Methods and devices for treating and processing data |
| US20040133745A1 (en) | 2002-10-28 | 2004-07-08 | Quicksilver Technology, Inc. | Adaptable datapath for a digital processing system |
| US7653710B2 (en) | 2002-06-25 | 2010-01-26 | Qst Holdings, Llc. | Hardware task manager |
| US6836839B2 (en) | 2001-03-22 | 2004-12-28 | Quicksilver Technology, Inc. | Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements |
| US7752419B1 (en) | 2001-03-22 | 2010-07-06 | Qst Holdings, Llc | Method and system for managing hardware resources to implement system functions using an adaptive computing architecture |
| US7489779B2 (en) | 2001-03-22 | 2009-02-10 | Qstholdings, Llc | Hardware implementation of the secure hash standard |
| US7962716B2 (en) | 2001-03-22 | 2011-06-14 | Qst Holdings, Inc. | Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements |
| US7400668B2 (en) | 2001-03-22 | 2008-07-15 | Qst Holdings, Llc | Method and system for implementing a system acquisition function for use with a communication device |
| US6577678B2 (en) | 2001-05-08 | 2003-06-10 | Quicksilver Technology | Method and system for reconfigurable channel coding |
| EP2224330B1 (de) | 2001-06-20 | 2012-05-09 | Krass, Maren | Verfahren und gerät zum partitionieren von grossen rechnerprogrammen |
| US7996827B2 (en) | 2001-08-16 | 2011-08-09 | Martin Vorbach | Method for the translation of programs for reconfigurable architectures |
| DE10249204A1 (de) * | 2001-10-29 | 2003-05-28 | Siemens Ag | Rekonfigurierbare digitale Logikeinheit |
| GB2382175A (en) * | 2001-11-20 | 2003-05-21 | Hewlett Packard Co | Reconfigurable processor |
| US7046635B2 (en) | 2001-11-28 | 2006-05-16 | Quicksilver Technology, Inc. | System for authorizing functionality in adaptable hardware devices |
| US6986021B2 (en) | 2001-11-30 | 2006-01-10 | Quick Silver Technology, Inc. | Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements |
| US8412915B2 (en) | 2001-11-30 | 2013-04-02 | Altera Corporation | Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements |
| US7602740B2 (en) | 2001-12-10 | 2009-10-13 | Qst Holdings, Inc. | System for adapting device standards after manufacture |
| US7215701B2 (en) | 2001-12-12 | 2007-05-08 | Sharad Sambhwani | Low I/O bandwidth method and system for implementing detection and identification of scrambling codes |
| US7577822B2 (en) | 2001-12-14 | 2009-08-18 | Pact Xpp Technologies Ag | Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization |
| US7403981B2 (en) | 2002-01-04 | 2008-07-22 | Quicksilver Technology, Inc. | Apparatus and method for adaptive multimedia reception and transmission in communication environments |
| JP3723775B2 (ja) * | 2002-01-10 | 2005-12-07 | 松下電器産業株式会社 | データ処理装置 |
| WO2003071418A2 (en) * | 2002-01-18 | 2003-08-28 | Pact Xpp Technologies Ag | Method and device for partitioning large computer programs |
| US8914590B2 (en) | 2002-08-07 | 2014-12-16 | Pact Xpp Technologies Ag | Data processing method and device |
| US7493375B2 (en) | 2002-04-29 | 2009-02-17 | Qst Holding, Llc | Storage and delivery of device features |
| US7660984B1 (en) | 2003-05-13 | 2010-02-09 | Quicksilver Technology | Method and system for achieving individualized protected space in an operating system |
| US7328414B1 (en) | 2003-05-13 | 2008-02-05 | Qst Holdings, Llc | Method and system for creating and programming an adaptive computing engine |
| JP3934493B2 (ja) | 2002-06-28 | 2007-06-20 | 富士通株式会社 | 集積回路及びシステム開発方法 |
| US8108656B2 (en) | 2002-08-29 | 2012-01-31 | Qst Holdings, Llc | Task definition for specifying resource requirements |
| WO2004038599A1 (de) | 2002-09-06 | 2004-05-06 | Pact Xpp Technologies Ag | Rekonfigurierbare sequenzerstruktur |
| US7937591B1 (en) | 2002-10-25 | 2011-05-03 | Qst Holdings, Llc | Method and system for providing a device which can be adapted on an ongoing basis |
| US7225324B2 (en) | 2002-10-31 | 2007-05-29 | Src Computers, Inc. | Multi-adaptive processing systems and techniques for enhancing parallelism and performance of computational functions |
| US7478031B2 (en) | 2002-11-07 | 2009-01-13 | Qst Holdings, Llc | Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information |
| US8276135B2 (en) | 2002-11-07 | 2012-09-25 | Qst Holdings Llc | Profiling of software and circuit designs utilizing data operation analyses |
| US7225301B2 (en) | 2002-11-22 | 2007-05-29 | Quicksilver Technologies | External memory controller node |
| US7020746B2 (en) * | 2003-01-28 | 2006-03-28 | Microsoft Corporation | Method and system for an atomically updated, central cache memory |
| US7581081B2 (en) | 2003-03-31 | 2009-08-25 | Stretch, Inc. | Systems and methods for software extensible multi-processing |
| US7613900B2 (en) | 2003-03-31 | 2009-11-03 | Stretch, Inc. | Systems and methods for selecting input/output configuration in an integrated circuit |
| US8001266B1 (en) | 2003-03-31 | 2011-08-16 | Stretch, Inc. | Configuring a multi-processor system |
| US7590829B2 (en) * | 2003-03-31 | 2009-09-15 | Stretch, Inc. | Extension adapter |
| US7609297B2 (en) | 2003-06-25 | 2009-10-27 | Qst Holdings, Inc. | Configurable hardware based digital imaging apparatus |
| US7373642B2 (en) | 2003-07-29 | 2008-05-13 | Stretch, Inc. | Defining instruction extensions in a standard programming language |
| US7418575B2 (en) * | 2003-07-29 | 2008-08-26 | Stretch, Inc. | Long instruction word processing with instruction extensions |
| US7526632B1 (en) * | 2003-10-22 | 2009-04-28 | Stretch, Inc. | System, apparatus and method for implementing multifunctional memory in reconfigurable data path processing |
| US7237055B1 (en) * | 2003-10-22 | 2007-06-26 | Stretch, Inc. | System, apparatus and method for data path routing configurable to perform dynamic bit permutations |
| US7584345B2 (en) | 2003-10-30 | 2009-09-01 | International Business Machines Corporation | System for using FPGA technology with a microprocessor for reconfigurable, instruction level hardware acceleration |
| US9047094B2 (en) * | 2004-03-31 | 2015-06-02 | Icera Inc. | Apparatus and method for separate asymmetric control processing and data path processing in a dual path processor |
| US8484441B2 (en) | 2004-03-31 | 2013-07-09 | Icera Inc. | Apparatus and method for separate asymmetric control processing and data path processing in a configurable dual path processor that supports instructions having different bit widths |
| US7949856B2 (en) * | 2004-03-31 | 2011-05-24 | Icera Inc. | Method and apparatus for separate control processing and data path processing in a dual path processor with a shared load/store unit |
| TW200617703A (en) * | 2004-11-30 | 2006-06-01 | Tokyo Electron Ltd | Dynamically reconfigurable processor |
| JP4450737B2 (ja) * | 2005-01-11 | 2010-04-14 | 富士通株式会社 | 半導体集積回路 |
| US20060265485A1 (en) * | 2005-05-17 | 2006-11-23 | Chai Sek M | Method and apparatus for controlling data transfer in a processing system |
| US7603492B2 (en) * | 2005-09-20 | 2009-10-13 | Motorola, Inc. | Automatic generation of streaming data interface circuit |
| US7890686B2 (en) | 2005-10-17 | 2011-02-15 | Src Computers, Inc. | Dynamic priority conflict resolution in a multi-processor computer system having shared resources |
| US7716100B2 (en) * | 2005-12-02 | 2010-05-11 | Kuberre Systems, Inc. | Methods and systems for computing platform |
| JPWO2007074583A1 (ja) * | 2005-12-27 | 2009-06-04 | パナソニック株式会社 | 再構成可能な演算器を持つプロセッサ |
| KR100681199B1 (ko) * | 2006-01-11 | 2007-02-09 | 삼성전자주식회사 | 코어스 그레인 어레이에서의 인터럽트 처리 방법 및 장치 |
| US20080120497A1 (en) * | 2006-11-20 | 2008-05-22 | Motorola, Inc. | Automated configuration of a processing system using decoupled memory access and computation |
| KR101581882B1 (ko) | 2009-04-20 | 2015-12-31 | 삼성전자주식회사 | 재구성 가능한 프로세서 및 그 재구성 방법 |
| EP2526494B1 (en) | 2010-01-21 | 2020-01-15 | SVIRAL, Inc. | A method and apparatus for a general-purpose, multiple-core system for implementing stream-based computations |
| US8661424B2 (en) * | 2010-09-02 | 2014-02-25 | Honeywell International Inc. | Auto-generation of concurrent code for multi-core applications |
| US9698790B2 (en) * | 2015-06-26 | 2017-07-04 | Advanced Micro Devices, Inc. | Computer architecture using rapidly reconfigurable circuits and high-bandwidth memory interfaces |
| US11106467B2 (en) | 2016-04-28 | 2021-08-31 | Microsoft Technology Licensing, Llc | Incremental scheduler for out-of-order block ISA processors |
Family Cites Families (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4763242A (en) * | 1985-10-23 | 1988-08-09 | Hewlett-Packard Company | Computer providing flexible processor extension, flexible instruction set extension, and implicit emulation for upward software compatibility |
| US5128871A (en) * | 1990-03-07 | 1992-07-07 | Advanced Micro Devices, Inc. | Apparatus and method for allocation of resoures in programmable logic devices |
| US5222030A (en) * | 1990-04-06 | 1993-06-22 | Lsi Logic Corporation | Methodology for deriving executable low-level structural descriptions and valid physical implementations of circuits and systems from high-level semantic specifications and descriptions thereof |
| JPH04213167A (ja) * | 1990-12-07 | 1992-08-04 | Ricoh Co Ltd | 回路設計方式 |
| JP3183415B2 (ja) * | 1992-02-25 | 2001-07-09 | 川崎製鉄株式会社 | 論理合成方法 |
| US5260942A (en) * | 1992-03-06 | 1993-11-09 | International Business Machines Corporation | Method and apparatus for batching the receipt of data packets |
| JPH064335A (ja) * | 1992-06-23 | 1994-01-14 | Nec Corp | 命令動作試験装置 |
| US5684980A (en) * | 1992-07-29 | 1997-11-04 | Virtual Computer Corporation | FPGA virtual computer for executing a sequence of program instructions by successively reconfiguring a group of FPGA in response to those instructions |
| US5892961A (en) * | 1995-02-17 | 1999-04-06 | Xilinx, Inc. | Field programmable gate array having programming instructions in the configuration bitstream |
| US5748979A (en) * | 1995-04-05 | 1998-05-05 | Xilinx Inc | Reprogrammable instruction set accelerator using a plurality of programmable execution units and an instruction page table |
| US5933642A (en) * | 1995-04-17 | 1999-08-03 | Ricoh Corporation | Compiling system and method for reconfigurable computing |
| US5794062A (en) * | 1995-04-17 | 1998-08-11 | Ricoh Company Ltd. | System and method for dynamically reconfigurable computing using a processing unit having changeable internal hardware organization |
| US5819067A (en) * | 1996-02-23 | 1998-10-06 | Advanced Micro Devices, Inc. | Computer system configured to translate a computer program into a second computer program prior to executing the computer program |
| DE19634031A1 (de) * | 1996-08-23 | 1998-02-26 | Siemens Ag | Prozessor mit Pipelining-Aufbau |
| US6047115A (en) * | 1997-05-29 | 2000-04-04 | Xilinx, Inc. | Method for configuring FPGA memory planes for virtual hardware computation |
| US5943501A (en) * | 1997-06-27 | 1999-08-24 | Wisconsin Alumni Research Foundation | Multiple processor, distributed memory computer with out-of-order processing |
| JP3194364B2 (ja) * | 1997-06-27 | 2001-07-30 | 日本電気株式会社 | プログラマブル機能ブロック |
| JPH1185507A (ja) * | 1997-09-05 | 1999-03-30 | Mitsubishi Electric Corp | 中央処理装置およびマイクロコンピュータシステム |
-
2000
- 2000-01-26 KR KR1020007011394A patent/KR100731371B1/ko not_active Expired - Lifetime
- 2000-01-26 JP JP2000600174A patent/JP5148029B2/ja not_active Expired - Lifetime
- 2000-01-26 EP EP00903638A patent/EP1073951A1/en not_active Withdrawn
- 2000-01-26 WO PCT/EP2000/000590 patent/WO2000049496A1/en not_active Ceased
- 2000-02-11 US US09/501,642 patent/US6721884B1/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| KR100731371B1 (ko) | 2007-06-21 |
| WO2000049496A1 (en) | 2000-08-24 |
| US6721884B1 (en) | 2004-04-13 |
| JP2002537599A (ja) | 2002-11-05 |
| EP1073951A1 (en) | 2001-02-07 |
| KR20010042690A (ko) | 2001-05-25 |
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