JP5145715B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP5145715B2
JP5145715B2 JP2007004496A JP2007004496A JP5145715B2 JP 5145715 B2 JP5145715 B2 JP 5145715B2 JP 2007004496 A JP2007004496 A JP 2007004496A JP 2007004496 A JP2007004496 A JP 2007004496A JP 5145715 B2 JP5145715 B2 JP 5145715B2
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semiconductor chip
semiconductor device
insulating substrate
soldered
silicon dioxide
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JP2008172066A (en
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勝道 上▲柳▼
利幸 横前
両角　　朗
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Fuji Electric Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/26175—Flow barriers
    • H—ELECTRICITY
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
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    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]

Description

本発明は、半導体チップを絶縁基板に搭載した半導体装置及びその製造方法に関し、特に、両面に導電パターンを有する複数の絶縁基板を放熱板に半田付けした半導体装置及びその製造方法に関する。   The present invention relates to a semiconductor device in which a semiconductor chip is mounted on an insulating substrate and a manufacturing method thereof, and more particularly to a semiconductor device in which a plurality of insulating substrates having conductive patterns on both surfaces are soldered to a heat sink and a manufacturing method thereof.

パワーモジュールなど、駆動時に熱を発生する半導体チップを有する半導体装置は、製造時にその半導体チップを搭載した絶縁基板を半田付けにより金属ベースへ接合させている。その際、例えば市販のソルダレジストを金属ベースへ印刷して、乾燥させることにより、半田流れを防止することが行われている（例えば、特許文献１参照）。   In a semiconductor device having a semiconductor chip that generates heat when driven, such as a power module, an insulating substrate on which the semiconductor chip is mounted is joined to a metal base by soldering during manufacture. At that time, for example, a solder solder is prevented from being printed by printing a commercially available solder resist on a metal base and drying it (see, for example, Patent Document 1).

一方で、上記の半田流れを防止するために、レーザービームにより金属ベースへ酸化膜や凹みを形成する方法もあるが、この方法では半田の量が多くなると（厚さ０．０５ｍｍ以上）、ほとんど効果がない。   On the other hand, in order to prevent the above-described solder flow, there is a method of forming an oxide film or a dent on a metal base by a laser beam, but in this method, when the amount of solder increases (thickness 0.05 mm or more), almost has no effect.

また、半田流れを防止する方法としては、ダム材を所定のパターンで描画して金属ベース上に配置することも提案されている（例えば、特許文献２参照）。さらに、アルミニウム基板の表面にメタライズ層を形成し、その表面にレジストパターンを形成することも提案されている（例えば、特許文献３参照）。   Further, as a method for preventing the solder flow, it has been proposed to draw a dam material in a predetermined pattern and arrange it on a metal base (for example, see Patent Document 2). Further, it has been proposed to form a metallized layer on the surface of an aluminum substrate and form a resist pattern on the surface (see, for example, Patent Document 3).

従来では、モジュール全体を絶縁性のゲルで覆って耐圧を確保しているが、最近ではエポキシなどの絶縁樹脂によって封止する構造のモジュールが開発されてきている。この構造にすることで、半導体チップとＤＣＢ（Direct Copper Bonding）絶縁基板との半田付け部分やＤＣＢ絶縁基板と銅（Ｃｕ）ベースとの半田付け部分の応力が緩和され、信頼性が向上する。しかし、封止する絶縁樹脂と各部材との密着性が確保されずに隙間が発生すると、逆に絶縁構造が確保できず、性能が劣化してしまうことがある。
特開平６−２４４２２４号公報（段落番号〔００１０〕） 特開２００６−２１６７２９号公報 特開２００４−２６６１０３号公報 Conventionally, the entire module is covered with an insulating gel to ensure a withstand voltage, but recently, a module having a structure sealed with an insulating resin such as epoxy has been developed. With this structure, the stress at the soldered portion between the semiconductor chip and the DCB (Direct Copper Bonding) insulating substrate and the soldered portion between the DCB insulating substrate and the copper (Cu) base is relaxed, and the reliability is improved. However, if a gap occurs without ensuring the adhesion between the insulating resin to be sealed and each member, the insulating structure cannot be ensured, and the performance may deteriorate.
JP-A-6-244224 (paragraph number [0010]) JP 2006-216729 A JP 2004-266103 A

ところで、上記のような従来の半導体装置及びその製造方法において、ソルダレジストを使用する場合は、印刷用のスクリーンを製版製作することと、印刷から乾燥までの工程に時間と費用がかかるという問題点がある。また、ソルダレジストは一般にエポキシ樹脂などの有機物であるので、半田による耐熱がそれほど高くなく、例えば水素ガス雰囲気中のフラックスレス半田付けの際に、ソルダレジストからのアウトガスの発生により半田付け性が阻害され、装置が汚染されるなどの問題があり、使用が制限されている。   By the way, when using a solder resist in the conventional semiconductor device and its manufacturing method as described above, it is time-consuming and expensive to make a printing screen and from printing to drying. There is. In addition, solder resist is generally an organic material such as epoxy resin, so the heat resistance by solder is not so high. For example, during fluxless soldering in a hydrogen gas atmosphere, solderability is hindered by the generation of outgas from the solder resist. However, there are problems such as contamination of the device, and its use is restricted.

また、ダム材を所定のパターンで描画して金属ベース上に配置する場合、あるいはメタライズ層を形成して、その表面にレジストパターンを形成する場合には、密着性に問題がある。   In addition, when the dam material is drawn in a predetermined pattern and disposed on the metal base, or when a metallized layer is formed and a resist pattern is formed on the surface thereof, there is a problem in adhesion.

本発明は、このような点に鑑みてなされたものであり、容易に低コストで良好な半田付け性が得られるとともに、密着性が強く、良好な封止性が得られ、信頼性が向上する半導体装置及びその製造方法を提供することを目的とする。   The present invention has been made in view of the above points, and can easily obtain good solderability at low cost, and has high adhesion, good sealing properties, and improved reliability. An object of the present invention is to provide a semiconductor device and a manufacturing method thereof.

本発明では上記課題を解決するために、両面に導電パターンを有する絶縁基板の一方の面に半導体チップを搭載し、他方の面を放熱板に半田付けした半導体装置において、前記放熱板は、前記絶縁基板を半田付けしない部分に、前記放熱板に結合されたＳｉＯＨ基を含む二酸化珪素膜を有することを特徴とする半導体装置が提供される。 In the present invention, in order to solve the above problem, in a semiconductor device in which a semiconductor chip is mounted on one surface of an insulating substrate having conductive patterns on both surfaces and the other surface is soldered to a heat dissipation plate, the heat dissipation plate includes: There is provided a semiconductor device having a silicon dioxide film containing a SiOH group bonded to the heat radiating plate in a portion where the insulating substrate is not soldered.

このような半導体装置によれば、放熱板の絶縁基板を半田付けしない部分にＳｉＯＨ基を含む二酸化珪素膜を形成しているので、容易に低コストで良好な半田付け性が得られるとともに、密着性が強く、良好な封止性が得られ、信頼性が向上する。 According to such a semiconductor device, since the silicon dioxide film containing the SiOH group is formed on the portion of the heat sink where the insulating substrate is not soldered, good solderability can be easily obtained at a low cost. It has strong properties, good sealing properties are obtained, and reliability is improved.

また、本発明では上記課題を解決するために、両面に導電パターンを有する絶縁基板の一方の面に半導体チップを半田付けしてセルユニットを形成する工程と、放熱板の前記セルユニットを半田付けしない部分にＳｉＯＨ基を含む二酸化珪素膜を結合させて形成する工程と、前記セルユニットを前記放熱板に半田付けする工程と、を有することを特徴とする半導体装置の製造方法が提供される。 Further, in the present invention, in order to solve the above problems, a step of soldering a semiconductor chip to one surface of an insulating substrate having a conductive pattern on both sides to form a cell unit, and soldering the cell unit of a heat sink There is provided a method for manufacturing a semiconductor device, comprising: a step of bonding a silicon dioxide film containing a SiOH group to a portion not to be bonded; and a step of soldering the cell unit to the heat sink.

このような半導体装置の製造方法によれば、放熱板の絶縁基板を半田付けしない部分にＳｉＯＨ基を含む二酸化珪素膜が形成されるので、容易に低コストで良好な半田付け性が得られるとともに、密着性が強く、良好な封止性が得られ、信頼性が向上する。 According to such a method for manufacturing a semiconductor device, since a silicon dioxide film containing a SiOH group is formed on a portion of the heat sink where the insulating substrate is not soldered, good solderability can be easily obtained at low cost. Adhesiveness is strong, good sealing properties are obtained, and reliability is improved.

本発明の半導体装置及びその製造方法は、放熱板の絶縁基板を半田付けしない部分にＳｉＯＨ基を含む二酸化珪素膜を形成するので、容易に低コストで良好な半田付け性が得られるとともに、密着性が強く、良好な封止性が得られ、信頼性が向上するという利点がある。
In the semiconductor device and the manufacturing method of the present invention, a silicon dioxide film containing a SiOH group is formed on a portion of the heat sink where the insulating substrate is not soldered, so that good solderability can be easily obtained at low cost and adhesion. There is an advantage that the property is strong, a good sealing property is obtained, and the reliability is improved.

以下、本発明の実施の形態の半導体装置及びその製造方法を図面を参照して説明する。
図１は本発明の第１の実施の形態の半導体装置の製造工程を示す図である。第１の実施の形態の半導体装置は、両面に導電パターンを有する複数の絶縁基板の一方の面に半導体チップを搭載し、他方の面を金属製の放熱板に半田付けしており、放熱板は、絶縁基板を半田付けしない部分に、放熱板に結合された絶縁性の無機質層を有している。 Hereinafter, a semiconductor device and a manufacturing method thereof according to embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a diagram showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention. In the semiconductor device of the first embodiment, a semiconductor chip is mounted on one surface of a plurality of insulating substrates having conductive patterns on both surfaces, and the other surface is soldered to a metal heat sink. Has an insulating inorganic layer bonded to a heat sink at a portion where the insulating substrate is not soldered.

半導体チップとしては、例えば縦方向に電流が流れる縦型のスイッチング素子で構成されている。
第１の実施の形態の半導体装置の製造工程は、両面に導電パターンを有する絶縁基板の一方の面に半導体チップを半田付けしてセルユニットを形成する工程と、半導体チップで発生した熱を放熱させる放熱板の上記セルユニットを半田付けしない部分にメタルマスクにより絶縁性の無機質層を結合させて形成する工程と、上記セルユニットを放熱板に半田付けする工程と、半導体チップ、絶縁基板及び記放熱板の所定部分を樹脂で封入する工程とを有している。 The semiconductor chip is constituted by, for example, a vertical switching element in which current flows in the vertical direction.
The manufacturing process of the semiconductor device according to the first embodiment includes a step of soldering a semiconductor chip to one surface of an insulating substrate having conductive patterns on both sides to form a cell unit, and dissipating heat generated in the semiconductor chip. A step of bonding an insulating inorganic layer with a metal mask to a portion of the heat sink to which the cell unit is not soldered, a step of soldering the cell unit to the heat sink, a semiconductor chip, an insulating substrate, and a memory And encapsulating a predetermined portion of the heat sink with resin.

具体的には、セルユニットを半田付けする前に未半田領域に無機質層を形成するが、まず図１の（ａ）に示すように、放熱板である金属ベース１上の無機質処理する部分に貫通穴を有するマスク材２などを用いて、燃焼化学気相蒸着により二酸化珪素（ＳｉＯ2）をコーティングする。このとき、有機珪素（Ｓｉ−Ｃ）化合物＋ＬＰＧ（液化石油ガス）３が金属ベース１上に供給され、次の反応によって無機質付着粒子（ＳｉＯ2＋ＳｉＯＨ基）のガラス材がコーティングされ、無機質層４が形成される。 Specifically, before soldering the cell unit, an inorganic layer is formed in the unsoldered region. First, as shown in FIG. 1A, the inorganic processing portion on the metal base 1 as a heat sink is formed. Silicon dioxide (SiO 2 ) is coated by combustion chemical vapor deposition using a mask material 2 having through holes. At this time, an organic silicon (Si—C) compound + LPG (liquefied petroleum gas) 3 is supplied onto the metal base 1, and a glass material of inorganic adhered particles (SiO 2 + SiOH group) is coated by the following reaction, and the inorganic layer 4 Is formed.

有機珪素＋酸素（空気）＋ＬＰＧ⇒二酸化珪素＋水蒸気（Ｈ2Ｏ）＋二酸化炭素（ＣＯ2）
上記処理によってコーティング形成された無機質層４は、２つの機能を有している。１つの機能は、図１の（ｂ）に示すように、二酸化珪素膜がコーティングされて無機質層４が半田漏れ防止領域となるため、その部分に半田が漏れなくなる。つまり、半田の漏れ抑制が可能となり、このため、上記のセルユニットを構成する回路基板５と回路基板５との間などの半田ブリッジを抑制することができる。６は回路基板５を接合している半田である。もう１つの機能は、同図の（ｃ）に示すように、二酸化珪素膜の表面には多数のＳｉ−ＯＨ基が存在するため、表面を絶縁樹脂７で封止する場合、無機質層４が接着剤密着向上領域となり、絶縁樹脂７との酸素結合が強化され、密着性を向上させることができる。 Organic silicon + oxygen (air) + LPG => silicon dioxide + water vapor (H 2 O) + carbon dioxide (CO 2 )
The inorganic layer 4 formed by coating by the above processing has two functions. One function is that, as shown in FIG. 1B, the silicon dioxide film is coated and the inorganic layer 4 becomes a solder leakage prevention region, so that the solder does not leak to that portion. In other words, solder leakage can be suppressed, and therefore, a solder bridge between the circuit board 5 and the circuit board 5 constituting the cell unit can be suppressed. Reference numeral 6 denotes solder for joining the circuit board 5. Another function is that, as shown in FIG. 6C, since the surface of the silicon dioxide film has a large number of Si—OH groups, when the surface is sealed with the insulating resin 7, the inorganic layer 4 is It becomes an adhesive contact | adhesion improvement area | region, an oxygen bond with the insulating resin 7 is strengthened, and adhesiveness can be improved.

ここで、回路基板５は、セラミックス基板の表裏両面に直接接合法（Direct Bonding）や活性金属接合法（Active Metal Bonding）などにより導体パターンを接合して形成された放熱絶縁基板であり、実施の形態では、銅をセラミックス基板の表裏両面に接合した前述のＤＣＢ基板を用いている。   Here, the circuit board 5 is a heat-dissipating insulating substrate formed by bonding conductor patterns to the front and back surfaces of a ceramic substrate by a direct bonding method or an active metal bonding method. In the embodiment, the above-described DCB substrate in which copper is bonded to both the front and back surfaces of the ceramic substrate is used.

また、半導体チップは、例えばＩＧＢＴ（Insulated Gate Bipolar Transistor）などのパワーモジュール用の素子であり、半田６により回路基板５に接合される。金属ベース１は、回路基板５に搭載されている上記の半導体チップで発生した熱を放熱させる機能を持つヒートシンクであり、例えばニッケル（Ｎｉ）めっきされた銅板が用いられる。   The semiconductor chip is an element for a power module such as an IGBT (Insulated Gate Bipolar Transistor), and is joined to the circuit board 5 by solder 6. The metal base 1 is a heat sink having a function of dissipating heat generated by the semiconductor chip mounted on the circuit board 5, and for example, a nickel (Ni) plated copper plate is used.

本実施の形態の無機質層４は、金属ベース１上に所定のパターンで形成されるが、上記の燃焼化学気相蒸着法の他に、プラズマ溶射法、エアロゾルデポジション法、コールドスプレー法などでも形成することができる。そして、このような無機質層４を金属ベース１上に形成することで、半田の流動を制限でき、エポキシ樹脂などの有機物からなるソルダレジストとして用いた場合のように、半田付け時のアウトガスの発生もなく、装置の汚染も回避することができる。   The inorganic layer 4 of the present embodiment is formed in a predetermined pattern on the metal base 1, but in addition to the above-described combustion chemical vapor deposition method, a plasma spraying method, an aerosol deposition method, a cold spray method, etc. Can be formed. Then, by forming such an inorganic layer 4 on the metal base 1, the flow of solder can be limited, and outgassing during soldering is generated as when used as a solder resist made of an organic material such as an epoxy resin. In addition, contamination of the device can be avoided.

このように、本実施の形態では、放熱板である金属ベース１上の回路基板５を半田付けしない部分に絶縁性の無機質層４を形成するので、容易に低コストで良好な半田付け性が得られるとともに、密着性が強く、良好な封止性が得られ、信頼性が向上する。   As described above, in this embodiment, since the insulating inorganic layer 4 is formed on the portion where the circuit board 5 on the metal base 1 which is a heat radiating plate is not soldered, good solderability can be easily achieved at low cost. In addition to being obtained, the adhesiveness is strong, a good sealing property is obtained, and the reliability is improved.

ここで、実施の形態の酸素を含む無機質層４は、上記のソルダレジストとして機能するほか、金属ベース１に強固に結合していることと、半導体チップの封止樹脂との密着性が高いことから、樹脂封止の性能（密着性）が向上する。また、封止樹脂にエポキシ樹脂を選択した場合、無機質層４の酸素とエポキシ樹脂との結合により、他の樹脂と比べて密着性が向上する。   Here, the inorganic layer 4 containing oxygen in the embodiment functions as the solder resist, and is firmly bonded to the metal base 1 and has high adhesion to the sealing resin of the semiconductor chip. Therefore, the resin sealing performance (adhesion) is improved. Moreover, when an epoxy resin is selected as the sealing resin, the adhesion between oxygen and the epoxy resin in the inorganic layer 4 is improved as compared with other resins.

図２は本発明の第２の実施の形態の半導体装置の製造工程を示す図である。第２の実施の形態の半導体装置は、回路基板５に半田１１により接合されて搭載された半導体チップ１２と半導体チップ１２の間、及び半導体チップ１２と電極の間をアルミニウム（Ａｌ）の金属ワイヤ１３で電気的に接続している。そして、それらの上を絶縁樹脂７で覆って封止している。   FIG. 2 is a diagram showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention. The semiconductor device according to the second embodiment includes an aluminum (Al) metal wire between the semiconductor chip 12 and the semiconductor chip 12 mounted on the circuit board 5 by being joined by the solder 11 and between the semiconductor chip 12 and the electrode. 13 is electrically connected. Then, they are covered with an insulating resin 7 and sealed.

本実施の形態においても、上述の第１の実施の形態と同様、図２の（ａ）に示すように、金属ベース１上に不図示のマスク材を用いて半田領域（未処理）Ａには二酸化珪素の膜がコーティングされないようにし、未半田領域（無機質処理）Ｂには二酸化珪素の膜がコーティングされるように燃焼化学気相蒸着処理を施す。この処理によって、回路基板５に半導体チップ１２を酸化還元炉で半田付けしても、隣接する回路基板５間に半田ブリッジが発生するのを防止することができる。   Also in the present embodiment, as in the first embodiment described above, as shown in FIG. 2A, a mask material (not shown) is used on the metal base 1 to form a solder region (unprocessed) A. The silicon dioxide film is not coated, and the unsoldered region (inorganic treatment) B is subjected to a combustion chemical vapor deposition process so that the silicon dioxide film is coated. With this process, even if the semiconductor chip 12 is soldered to the circuit board 5 with an oxidation-reduction furnace, it is possible to prevent a solder bridge from occurring between adjacent circuit boards 5.

次に、同図の（ｂ）に示すように、金属ワイヤ１３によって電気的接続を行った後、同図の（ｃ）に示すように、絶縁樹脂７で封止する。これにより、容易に低コストで良好な半田付け性が得られる。   Next, as shown in (b) of the figure, after being electrically connected by the metal wire 13, it is sealed with an insulating resin 7 as shown in (c) of the figure. Thereby, good solderability can be easily obtained at low cost.

図３は本発明の第３の実施の形態の半導体装置の製造工程を示す図である。第３の実施の形態の半導体装置は、回路基板５に半田１１により接合されて搭載された半導体チップ１２の上面にヒートスプレッダー１５を半田１６により接合し、その上面に導体板であるリードフレーム１７を半田１８により接合している。そして、半導体チップ１２、ヒートスプレッダー１５及びリードフレーム１７を絶縁樹脂７で封止する。また、回路基板５、金属ベース１もしくはリードフレーム１７の絶縁樹脂７と接する部分にも燃焼化学気相蒸着処理により絶縁性の無機質層１９を形成する。   FIG. 3 is a diagram showing a manufacturing process of the semiconductor device according to the third embodiment of the present invention. In the semiconductor device of the third embodiment, a heat spreader 15 is joined to the upper surface of a semiconductor chip 12 mounted on the circuit board 5 by solder 11 and soldered, and a lead frame 17 as a conductor plate is joined to the upper surface. Are joined by solder 18. Then, the semiconductor chip 12, the heat spreader 15, and the lead frame 17 are sealed with the insulating resin 7. An insulating inorganic layer 19 is also formed on the circuit board 5, the metal base 1, or the portion of the lead frame 17 in contact with the insulating resin 7 by combustion chemical vapor deposition.

第３の実施の形態の製造工程は、半導体チップ１２を、両面に導電パターンを有する回路基板５に半田付けしてセルユニットを形成する工程と、半導体チップ１２で発生した熱を放熱させる金属ベース１の上記セルユニットを半田付けしない部分にメタルマスクにより絶縁性の無機質層４を形成する工程と、半導体チップ１２の上面にヒートスプレッダー１５を半田付けし、その上面にリードフレーム１７を接合する工程と、上記ヒートスプレッダー１５もしくはリードフレーム１７の表面に絶縁性の無機質層１９を形成する工程と、セルユニットを金属ベース１に半田付けする工程と、半導体チップ１２、回路基板５及び金属ベース１の所定部分を絶縁樹脂７で封入する工程とを有している。   The manufacturing process of the third embodiment includes a step of soldering the semiconductor chip 12 to the circuit board 5 having conductive patterns on both sides to form a cell unit, and a metal base that radiates heat generated in the semiconductor chip 12. A step of forming an insulating inorganic layer 4 with a metal mask on a portion of the cell unit where the cell unit is not soldered, a step of soldering a heat spreader 15 to the upper surface of the semiconductor chip 12, and a lead frame 17 being bonded to the upper surface. A step of forming an insulating inorganic layer 19 on the surface of the heat spreader 15 or the lead frame 17, a step of soldering the cell unit to the metal base 1, the semiconductor chip 12, the circuit board 5, and the metal base 1 And a step of enclosing a predetermined portion with an insulating resin 7.

本実施の形態においても、上述の第１、第２の実施の形態と同様、図３の（ａ）に示すように、金属ベース１上に不図示のマスク材を用いて半田領域（未処理）Ａには二酸化珪素の膜がコーティングされないようにし、未半田領域（無機質処理）Ｂには二酸化珪素の膜がコーティングされるように燃焼化学気相蒸着処理を施す。この処理によって、回路基板５に半導体チップ１２を酸化還元炉で半田付けしても、隣接する回路基板５間に半田ブリッジが発生するのを防止することができる。   Also in the present embodiment, as in the first and second embodiments described above, as shown in FIG. 3A, a solder region (unprocessed) is used on the metal base 1 using a mask material (not shown). ) A is prevented from being coated with a silicon dioxide film, and a non-soldered region (inorganic treatment) B is subjected to a combustion chemical vapor deposition process so that a silicon dioxide film is coated. With this process, even if the semiconductor chip 12 is soldered to the circuit board 5 with an oxidation-reduction furnace, it is possible to prevent a solder bridge from occurring between adjacent circuit boards 5.

次に、同図の（ｂ）に示すように、予め二酸化珪素膜を所定の箇所に被膜した金属製のリードフレーム１７を半田付けして電気的接続を行った後、同図の（ｃ）に示すように、絶縁樹脂７で封止する。これにより、容易に低コストで良好な半田付け性が得られるとともに、リードフレーム１７の表面、半導体チップ１２の表面などと絶縁樹脂７との密着性を確保することができる。   Next, as shown in (b) of the figure, a metal lead frame 17 previously coated with a silicon dioxide film at a predetermined location is soldered and electrically connected, and then (c) of the figure. As shown in FIG. Thereby, good solderability can be easily obtained at low cost, and adhesion between the surface of the lead frame 17 and the surface of the semiconductor chip 12 and the insulating resin 7 can be ensured.

ここで、リードフレーム１７は、上記の半田１８による接続以外に、レーザー溶接あるいは超音波接続などが行われる場合もあるが、接続前にリードフレーム１７だけで表面に燃焼化学気相蒸着処理を施すと効率的である。また、レーザー溶接する箇所には、レーザー光の吸収を阻害しないように、その部分を避けて選択的に二酸化珪素膜を形成するとよい。   Here, the lead frame 17 may be subjected to laser welding or ultrasonic connection in addition to the connection by the solder 18 described above, but before the connection, the surface is subjected to the combustion chemical vapor deposition process only by the lead frame 17. And is efficient. Further, it is preferable to selectively form a silicon dioxide film at a place where laser welding is performed so as not to inhibit the absorption of laser light.

本発明の第１の実施の形態の半導体装置の製造工程を示す図である。It is a figure which shows the manufacturing process of the semiconductor device of the 1st Embodiment of this invention. 本発明の第２の実施の形態の半導体装置の製造工程を示す図である。It is a figure which shows the manufacturing process of the semiconductor device of the 2nd Embodiment of this invention. 本発明の第３の実施の形態の半導体装置の製造工程を示す図である。It is a figure which shows the manufacturing process of the semiconductor device of the 3rd Embodiment of this invention.

符号の説明Explanation of symbols

１ 金属ベース
２ マスク材
３ 有機珪素化合物＋ＬＰＧ
４，１４，１９ 無機質層
５ 回路基板
６，１１，１６，１８ 半田
７ 絶縁樹脂
１２ 半導体チップ
１３ 金属ワイヤ
１５ ヒートスプレッダー
１７ リードフレーム 1 Metal base 2 Mask material 3 Organosilicon compound + LPG
4, 14, 19 Inorganic layer 5 Circuit board 6, 11, 16, 18 Solder 7 Insulating resin 12 Semiconductor chip 13 Metal wire 15 Heat spreader 17 Lead frame

Claims (7)

両面に導電パターンを有する絶縁基板の一方の面に半導体チップを搭載し、他方の面を放熱板に半田付けした半導体装置において、
前記放熱板は、前記絶縁基板を半田付けしない部分に、前記放熱板に結合されたＳｉＯＨ基を含む二酸化珪素膜を有することを特徴とする半導体装置。 In a semiconductor device in which a semiconductor chip is mounted on one surface of an insulating substrate having a conductive pattern on both sides and the other surface is soldered to a heat sink,
2. The semiconductor device according to claim 1, wherein the heat radiating plate has a silicon dioxide film containing a SiOH group bonded to the heat radiating plate in a portion where the insulating substrate is not soldered. 両面に導電パターンを有する絶縁基板の一方の面に半導体チップを搭載し、他方の面を放熱板に半田付けし、前記半導体チップの搭載面を樹脂で封止した半導体装置において、
前記絶縁基板もしくは前記放熱板は、前記樹脂と接する部分に、前記絶縁基板もしくは前記放熱板にそれぞれ結合されたＳｉＯＨ基を含む二酸化珪素膜を有することを特徴とする半導体装置。 In a semiconductor device in which a semiconductor chip is mounted on one surface of an insulating substrate having a conductive pattern on both sides, the other surface is soldered to a heat sink, and the mounting surface of the semiconductor chip is sealed with a resin,
The semiconductor device according to claim 1, wherein the insulating substrate or the heat radiating plate has a silicon dioxide film containing SiOH groups bonded to the insulating substrate or the heat radiating plate at a portion in contact with the resin. 両面に導電パターンを有する絶縁基板の一方の面に半導体チップを搭載し、他方の面を放熱板に半田付けした半導体装置において、
前記半導体チップの上面に半田付けしたヒートスプレッダーと、
前記ヒートスプレッダーの上面に接合した導体板と、
前記半導体チップ、前記ヒートスプレッダー及び前記導体板の全面を封止する樹脂を有し、
前記絶縁基板、前記放熱板もしくは前記導体板は、前記樹脂と接する部分に、前記絶縁基板、前記放熱板もしくは前記導体板にそれぞれ結合されたＳｉＯＨ基を含む二酸化珪素膜を形成したことを特徴とする半導体装置。 In a semiconductor device in which a semiconductor chip is mounted on one surface of an insulating substrate having a conductive pattern on both sides and the other surface is soldered to a heat sink,
A heat spreader soldered to the upper surface of the semiconductor chip;
A conductor plate joined to the upper surface of the heat spreader;
Having a resin for sealing the entire surface of the semiconductor chip, the heat spreader and the conductor plate;
The insulating substrate, the heat radiating plate, or the conductor plate is characterized in that a silicon dioxide film containing SiOH groups bonded to the insulating substrate, the heat radiating plate, or the conductor plate is formed on a portion in contact with the resin. Semiconductor device. 両面に導電パターンを有する絶縁基板の一方の面に半導体チップを半田付けしてセルユニットを形成する工程と、  Forming a cell unit by soldering a semiconductor chip to one surface of an insulating substrate having a conductive pattern on both sides;
放熱板の前記セルユニットを半田付けしない部分にＳｉＯＨ基を含む二酸化珪素膜を結合させて形成する工程と、  A step of bonding a silicon dioxide film containing a SiOH group to a portion of the radiator plate where the cell unit is not soldered;
前記セルユニットを前記放熱板に半田付けする工程と、  Soldering the cell unit to the heat sink;
を有することを特徴とする半導体装置の製造方法。  A method for manufacturing a semiconductor device, comprising: 両面に導電パターンを有する絶縁基板の一方の面に半導体チップを半田付けしてセルユニットを形成する工程と、  Forming a cell unit by soldering a semiconductor chip to one surface of an insulating substrate having a conductive pattern on both sides;
放熱板の前記セルユニットを半田付けしない部分にＳｉＯＨ基を含む二酸化珪素膜を結合させて形成する工程と、  A step of bonding a silicon dioxide film containing a SiOH group to a portion of the radiator plate where the cell unit is not soldered;
前記セルユニットを前記放熱板に半田付けする工程と、  Soldering the cell unit to the heat sink;
前記半導体チップ、前記絶縁基板及び前記放熱板を樹脂で封止する工程と、  Sealing the semiconductor chip, the insulating substrate and the heat sink with resin;
を有することを特徴とする半導体装置の製造方法。  A method for manufacturing a semiconductor device, comprising: 両面に導電パターンを有する絶縁基板の一方の面に半導体チップを半田付けするとともに、前記半導体チップの上面にヒートスプレッダーを半田付けしてセルユニットを形成する工程と、  Soldering a semiconductor chip to one surface of an insulating substrate having conductive patterns on both sides, and soldering a heat spreader to the upper surface of the semiconductor chip to form a cell unit;
導体板の表面にＳｉＯＨ基を含む二酸化珪素膜を結合させて形成する工程と、  Forming a silicon dioxide film containing SiOH groups on the surface of the conductor plate; and
放熱板の前記セルユニットを半田付けしない部分にＳｉＯＨ基を含む二酸化珪素膜を結合させて形成する工程と、  A step of bonding a silicon dioxide film containing a SiOH group to a portion of the radiator plate where the cell unit is not soldered;
前記セルユニットを前記放熱板に半田付けする工程と、  Soldering the cell unit to the heat sink;
前記ヒートスプレッダーの上面に前記導体板を接合する工程と、  Bonding the conductor plate to the upper surface of the heat spreader;
前記半導体チップ、前記ヒートスプレッダー及び前記導体板の全面を樹脂で封止する工程と、  Sealing the entire surface of the semiconductor chip, the heat spreader and the conductor plate with a resin;
を有することを特徴とする半導体装置の製造方法。  A method for manufacturing a semiconductor device, comprising: 絶縁性の前記二酸化珪素膜を形成する工程では、マスク処理を行い、そのマスク処理によって露出した部分に直接無機質の二酸化珪素を積層することを特徴とする請求項４乃至６のいずれか一項に記載の半導体装置の製造方法。  7. The step of forming the insulating silicon dioxide film performs a mask process, and directly deposits inorganic silicon dioxide on a portion exposed by the mask process. The manufacturing method of the semiconductor device of description.
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