JP2013046004A - Insulating circuit board, semiconductor module, and manufacturing method therefor - Google Patents
Insulating circuit board, semiconductor module, and manufacturing method therefor Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 91
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 75
- 229910010272 inorganic material Inorganic materials 0.000 claims abstract description 71
- 239000011147 inorganic material Substances 0.000 claims abstract description 71
- 239000002245 particle Substances 0.000 claims abstract description 56
- 229910052751 metal Inorganic materials 0.000 claims abstract description 26
- 239000002184 metal Substances 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims abstract description 25
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims abstract description 22
- 239000011368 organic material Substances 0.000 claims abstract description 22
- 239000011344 liquid material Substances 0.000 claims abstract description 15
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 26
- 239000002105 nanoparticle Substances 0.000 claims description 17
- 238000001816 cooling Methods 0.000 claims description 11
- 238000010304 firing Methods 0.000 claims description 10
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 5
- 238000009434 installation Methods 0.000 claims description 2
- 230000017525 heat dissipation Effects 0.000 abstract description 36
- 238000009413 insulation Methods 0.000 abstract description 7
- 230000001747 exhibiting effect Effects 0.000 abstract 2
- 238000001354 calcination Methods 0.000 abstract 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 24
- 239000010949 copper Substances 0.000 description 18
- 229910052802 copper Inorganic materials 0.000 description 16
- 239000000919 ceramic Substances 0.000 description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 229910052782 aluminium Inorganic materials 0.000 description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 8
- 239000011889 copper foil Substances 0.000 description 8
- 239000010953 base metal Substances 0.000 description 7
- 239000000463 material Substances 0.000 description 7
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 6
- 239000004642 Polyimide Substances 0.000 description 5
- 229920001721 polyimide Polymers 0.000 description 5
- 239000003507 refrigerant Substances 0.000 description 5
- 229910010271 silicon carbide Inorganic materials 0.000 description 5
- 235000012239 silicon dioxide Nutrition 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- 238000005507 spraying Methods 0.000 description 5
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000002994 raw material Substances 0.000 description 4
- 238000007650 screen-printing Methods 0.000 description 4
- 229910052709 silver Inorganic materials 0.000 description 4
- 239000004332 silver Substances 0.000 description 4
- 239000000498 cooling water Substances 0.000 description 3
- MTHSVFCYNBDYFN-UHFFFAOYSA-N diethylene glycol Chemical compound OCCOCCO MTHSVFCYNBDYFN-UHFFFAOYSA-N 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 239000011256 inorganic filler Substances 0.000 description 3
- 229910003475 inorganic filler Inorganic materials 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 239000002904 solvent Substances 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000004519 grease Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- DURPTKYDGMDSBL-UHFFFAOYSA-N 1-butoxybutane Chemical compound CCCCOCCCC DURPTKYDGMDSBL-UHFFFAOYSA-N 0.000 description 1
- 229910017083 AlN Inorganic materials 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 150000001412 amines Chemical class 0.000 description 1
- 238000009529 body temperature measurement Methods 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 230000009194 climbing Effects 0.000 description 1
- 239000011231 conductive filler Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000011812 mixed powder Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000003134 recirculating effect Effects 0.000 description 1
- 239000005871 repellent Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 229920006259 thermoplastic polyimide Polymers 0.000 description 1
- 230000008016 vaporization Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1301—Thyristor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
Abstract
Description
本発明は、放熱性及び電気的絶縁性に優れる絶縁回路基板並びに半導体モジュール及びその製造方法に関し、特に、パワー半導体装置等の発熱量が大きい装置にも適用できる技術に関する。 The present invention relates to an insulating circuit board, a semiconductor module, and a manufacturing method thereof that are excellent in heat dissipation and electrical insulation, and more particularly to a technique that can be applied to a device that generates a large amount of heat, such as a power semiconductor device.
従来、電源装置に使用される半導体モジュールは、家電製品などの民生機器から、インバータ、サーボコントローラなどの産業機器まで広く用いられている。特に、搭載したＩＧＢＴ（Insulated Gate Bipolar Transistor）などのパワー半導体素子を搭載したパワー半導体モジュールは、発熱量が大きいことから、放熱性に優れた金属板やセラミックス板を用いた絶縁回路基板が用いられている。この絶縁回路基板は、従来では数１００Ｖ程度の比較的低電圧が印加される用途に使用されていたが、省エネルギー化及び大容量化の要請により、近年では１ｋＶ以上の高電圧が印加されることもある。このため、絶縁回路基板の放熱性を高めるべく、有機材絶縁層に無機フィラーを充填すること、パワー半導体モジュールのフィン付金属ベースに直接冷却水を当てる構造（直接水冷構造）を設けることが提案されている。 2. Description of the Related Art Conventionally, semiconductor modules used for power supply devices are widely used from consumer equipment such as home appliances to industrial equipment such as inverters and servo controllers. In particular, a power semiconductor module equipped with a power semiconductor element such as an installed IGBT (Insulated Gate Bipolar Transistor) has a large amount of heat generation, and therefore an insulating circuit board using a metal plate or a ceramic plate having excellent heat dissipation is used. ing. This insulated circuit board has been used for applications where a relatively low voltage of about several hundred volts is applied in the past. However, in recent years, a high voltage of 1 kV or more has been applied due to a demand for energy saving and large capacity. There is also. For this reason, in order to improve the heat dissipation of the insulated circuit board, it is proposed to fill the organic insulating layer with an inorganic filler and to provide a structure (direct water cooling structure) that directly applies cooling water to the finned metal base of the power semiconductor module. Has been.
図９は、特許文献１の図３で説明される従来の金属ベース配線基板の断面構造を示す図である。金属ベース配線基板は、ベース金属１０１と、このベース金属１０１上に形成された絶縁層１０２と、この絶縁層１０２上に形成された回路パターン１０３との３層構造になっている。ベース金属１０１は、アルミニウム板または銅板などの放熱性に優れた金属が用いられている。絶縁層１０２は、ＳｉＯ２，Ａｌ２Ｏ３，ＡｌＮなどの無機フィラーを含有したエポキシ樹脂などの有機材料からなっている。回路パターン１０３は、銅箔などにより形成されている。 FIG. 9 is a diagram showing a cross-sectional structure of a conventional metal base wiring board described in FIG. The metal base wiring board has a three-layer structure including a base metal 101, an insulating layer 102 formed on the base metal 101, and a circuit pattern 103 formed on the insulating layer 102. As the base metal 101, a metal having excellent heat dissipation such as an aluminum plate or a copper plate is used. The insulating layer 102 is made of an organic material such as an epoxy resin containing an inorganic filler such as SiO 2 , Al 2 O 3 , or AlN. The circuit pattern 103 is formed of copper foil or the like.
図８は、特許文献１の図４で説明されるは従来のセラミックス配線基板の断面構造を示す図であって、（ａ）はセラミックス配線基板を示し、（ｂ）はベース金属が接合されたセラミックス配線基板を示している。このセラミックス配線基板は、セラミックス絶縁板１０４の両側に回路パターン１０３がろう材を介して貼り合わせられることによって構成され、例えば厚さ２〜３ｍｍ程度の銅板のベース金属１０１にはんだ層１０５を介して接合されている。
セラミックス絶縁板１０４は、その原料として、Ａｌ２Ｏ３，ＡｌＮ，Ｓｉ３Ｎ４などが用いられており、その熱伝導率は、原料がＡｌ２Ｏ３の場合は約２０Ｗ／ｍ・Ｋ、原料がＡｌＮの場合は１６０〜１８０Ｗ／ｍ・Ｋ、原料がＳｉ３Ｎ４の場合は８０Ｗ／ｍ・Ｋ程度であり、エポキシ樹脂に無機フィラーを配合した場合に比べて、１〜２桁高くなっているとされる。
FIGS. 8A and 8B are diagrams showing a cross-sectional structure of a conventional ceramic wiring board, which is described in FIG. 4 of Patent Document 1, wherein FIG. 8A shows a ceramic wiring board, and FIG. 8B shows a base metal bonded. A ceramic wiring board is shown. This ceramic wiring board is configured by bonding circuit patterns 103 to both sides of a ceramic insulating plate 104 via a brazing material. For example, the base metal 101 of a copper plate having a thickness of about 2 to 3 mm is interposed via a solder layer 105. It is joined.
The ceramic insulating plate 104 uses Al 2 O 3 , AlN, Si 3 N 4 or the like as its raw material, and its thermal conductivity is about 20 W / m · K when the raw material is Al 2 O 3 , When the raw material is AlN, it is 160 to 180 W / m · K, and when the raw material is Si 3 N 4 , it is about 80 W / m · K, which is 1 to 2 orders of magnitude higher than the case where an inorganic filler is added to the epoxy resin. It is supposed to be.
しかしながら、セラミックス配線基板の場合、セラミックス絶縁板を一度作製し、それに回路パターン層を接合し、エッチング加工し、このようにして作製されたセラミックス配線基板をベース金属にはんだで接合する、というように多くの工数が必要になっていることから、価格が高く、低価格化が困難であるという問題点があった。また、ヒートスプレッダ効果を高めるべく回路パターン用に厚い銅箔なし銅板を貼り付けるためには、約１０００℃以上の高温で銅板をセラミックス絶縁板に接合しなくてはならなかった。 However, in the case of a ceramic wiring board, a ceramic insulating board is produced once, a circuit pattern layer is joined thereto, etching is performed, and the ceramic wiring board thus produced is joined to a base metal by soldering. Since many man-hours are required, there is a problem that the price is high and it is difficult to reduce the price. Further, in order to attach a thick copper foil-free copper plate for a circuit pattern in order to enhance the heat spreader effect, the copper plate must be bonded to the ceramic insulating plate at a high temperature of about 1000 ° C. or higher.
図７は、特許文献２の図２で説明される従来のパワー半導体モジュールの直接水冷構造を示す図である。図７の構造では、フィン２０２をＩＧＢＴモジュール２００の金属ベース２０１に形製（フィン付ＩＧＢＴモジュール）し、アルミダイカスト製筐体２０５の開口部２０６より筐体２０５の外へ出し、直接冷却水を当てている。冷却用水路２０３は、アルミダイカスト製水路カバー２０４と金属ベース２０１で形製されている。 FIG. 7 is a diagram showing a direct water cooling structure of a conventional power semiconductor module described in FIG. In the structure of FIG. 7, the fin 202 is formed on the metal base 201 of the IGBT module 200 (an IGBT module with fins), is taken out of the housing 205 through the opening 206 of the aluminum die-cast housing 205, and the cooling water is directly supplied. I guess. The cooling water channel 203 is formed by an aluminum die-cast water channel cover 204 and a metal base 201.
ところで、近年、狭小空間においても実装ができるように、封入された冷媒の気化及び凝縮によって発熱体を冷却するヒートパイプが提案されている。特許文献３では、気化した冷媒を拡散する蒸気拡散路及び凝縮した冷媒を還流させる毛細管流路を内部に有する平板状の本体部と、本体部の少なくとも２箇所の温度差を測定する温度測定部と、温度差を所定の閾値と比較して比較結果を出力する比較部と、比較結果に基づいて本体部の動作状態をヒートパイプの冷却能力を基準として判定し、判定結果を出力する判定部を備え、蒸気拡散路が気化した冷媒を水平方向に拡散し、毛細管流路が凝縮した冷媒を垂直もしくは垂直・水平方向に還流させるヒートパイプが提案されている。 By the way, in recent years, a heat pipe that cools a heating element by vaporizing and condensing a sealed refrigerant has been proposed so that it can be mounted even in a narrow space. In Patent Document 3, a vapor diffusion path for diffusing the vaporized refrigerant, a flat plate-like main body section having a capillary channel for recirculating the condensed refrigerant, and a temperature measurement section for measuring a temperature difference between at least two positions of the main body section. A comparison unit that compares the temperature difference with a predetermined threshold and outputs a comparison result; and a determination unit that determines the operation state of the main body based on the comparison result based on the cooling capacity of the heat pipe and outputs the determination result There has been proposed a heat pipe that diffuses the refrigerant vaporized in the vapor diffusion path in the horizontal direction and recirculates the refrigerant condensed in the capillary channel in the vertical or vertical / horizontal direction.
従来の絶縁回路基板は、主にセラミックを用いているためコスト高という課題がある。また電気絶縁層が有機材料を主要な成分とする場合は、熱伝導性が悪いために、良好な放熱特性が得られないという課題がある。より詳細には、有機材料の放熱性は一般に０．３ｗ／ｍ・ｋ程度であり、無機材料（例えば、二酸化珪素（ＳｉＯ２）は１．５ｗ／ｍ・ｋ程度）と比べ、放熱性が劣っていた。
また、有機材料からなる絶縁層を有する配線基板は、耐熱性の問題や長時間の使用による劣化（耐久性）の問題がある。
本発明は、無機材料で且つ低コストで電気絶縁層を構成することを解決すべき課題とする。
The conventional insulated circuit board has a problem of high cost because it mainly uses ceramic. Further, when the electrical insulating layer contains an organic material as a main component, there is a problem that good heat dissipation characteristics cannot be obtained due to poor thermal conductivity. More specifically, the heat dissipation of organic materials is generally about 0.3 w / m · k, and the heat dissipation is less than that of inorganic materials (for example, silicon dioxide (SiO 2 ) is about 1.5 w / m · k). It was inferior.
Further, a wiring board having an insulating layer made of an organic material has a problem of heat resistance and a problem of deterioration (durability) due to long-term use.
This invention makes it the subject which should be solved to comprise an electrically insulating layer with an inorganic material and low cost.
特許文献２に開示される直接水冷構造は、個別の素子に対応した個別の水冷構造を設け、また、水路を塞ぐためのネジ締め等の工程が必要であり、製造コストが嵩むという問題がある。
汎用部品の利用を可能とし、さらには製造プロセスを簡易化することで、製造コストを低減することも本発明が解決すべき課題である。
The direct water cooling structure disclosed in Patent Document 2 is provided with individual water cooling structures corresponding to individual elements, and requires a process such as screw tightening to close the water channel, which increases manufacturing costs. .
It is also a problem to be solved by the present invention to reduce the manufacturing cost by making it possible to use general-purpose parts and simplifying the manufacturing process.
以上の課題を鑑み、本発明は、耐熱性、放熱性及び耐久性に優れた電気絶縁層を有し、しかもコスト性及びプロセス性に優れた絶縁回路基板並びに半導体モジュール及びその製造方法を提供することを目的とする。 In view of the above-described problems, the present invention provides an insulating circuit board, a semiconductor module, and a method for manufacturing the same that have an electrical insulating layer excellent in heat resistance, heat dissipation, and durability, and that are excellent in cost and processability. For the purpose.
発明者は、ナノ化された二酸化珪素（ＳｉＯ２）粒子とアルミナコートされた熱伝導率が１３０Ｗ／ｍ・Ｋ以上の導電粒子を含む液材（インク）を用いることにより、無機絶縁材料をインクジェット法やディスペンサー法あるいはスプレーコート法のインクとすることができ、任意のパターン形成や凹凸部への塗布を行うことを可能とした。また二酸化珪素（ＳｉＯ２）粒子がナノ化されたことにより、塗布対象の基板、例えば銅板などの微小な凹凸へのインクの周りこみが可能となり、密着性が大幅に向上し、無機材絶縁層と金属層の積層構造を形成することが可能となった。 The inventor made an inorganic insulating material by inkjet using a liquid material (ink) containing nano-sized silicon dioxide (SiO 2 ) particles and alumina-coated conductive particles having a thermal conductivity of 130 W / m · K or more. The ink can be made by a method, a dispenser method, or a spray coating method, and an arbitrary pattern can be formed or applied to an uneven portion. In addition, since the silicon dioxide (SiO 2 ) particles have been made nano-sized, it is possible to spill ink around minute irregularities such as a substrate to be coated, for example, a copper plate, and the adhesion is greatly improved. It became possible to form a laminated structure of metal layers.
すなわち、本発明は、以下の技術手段から構成される。
第１の発明は、有機材絶縁層及び有機材絶縁層上に形成された配線を有する基板、並びに、基板の表面に形成された無機材絶縁層を備え、半導体チップが搭載される絶縁回路基板であって、基板は少なくとも表面が金属であり、基板表面の少なくとも一部にナノ化されたＳｉＯ２粒子およびアルミナコートされた熱伝導率が１３０Ｗ／ｍ・Ｋ以上の導電粒子を含む液材を塗布し、焼成することにより無機材絶縁層を形成したことを特徴とする絶縁回路基板である。
第２の発明は、基板の表面に形成された無機材絶縁層及び無機材絶縁層上に形成された配線を備え、半導体チップが搭載される絶縁回路基板であって、基板は少なくとも表面が金属であり、基板表面の少なくとも一部にナノ化されたＳｉＯ２粒子およびアルミナコートされた熱伝導率が１３０Ｗ／ｍ・Ｋ以上の導電粒子を含む液材を塗布し、焼成することにより無機材絶縁層を形成したことを特徴とする絶縁回路基板である。
第１および第２の発明においては、「基板表面の少なくとも一部」とあることからも分かるように、例えば、基板表面のうち、チップ搭載部には無機材絶縁層が形成されない場合がある。また、配線の一部に乗り上げて無機材絶縁層を形成してもよく、この乗り上げ部分がソルダーレジストとなる場合もある。また、熱伝導率が１３０Ｗ／ｍ・Ｋ以上の導電粒子は、例えば、炭化珪素（ＳｉＣ）、高純度炭化珪素（ＳｉＣ３Ｎ）、銅（Ｃｕ）、アルミニウム（Ａｌ）、タングステン（Ｗ）、銀（Ａｇ）から選択された一または複数の導電粒子から構成される。第２の発明には、無機材絶縁層と配線の間にプライマー層が存在する態様も含まれる。
That is, the present invention comprises the following technical means.
A first invention is an insulating circuit board having an organic material insulating layer, a substrate having wiring formed on the organic material insulating layer, and an inorganic material insulating layer formed on the surface of the substrate, on which a semiconductor chip is mounted The substrate is made of a liquid material including at least a surface of a metal, nano-sized SiO 2 particles and alumina-coated conductive particles having a thermal conductivity of 130 W / m · K or more on at least a part of the substrate surface. An insulating circuit board characterized in that an inorganic insulating layer is formed by applying and baking.
A second invention is an insulating circuit board including an inorganic material insulating layer formed on the surface of the substrate and a wiring formed on the inorganic material insulating layer, on which a semiconductor chip is mounted, and the substrate has at least a metal surface Insulating inorganic material by applying and baking a liquid material containing nano-sized SiO 2 particles and alumina-coated conductive particles having a thermal conductivity of 130 W / m · K or more on at least a part of the substrate surface An insulating circuit board having a layer formed thereon.
In the first and second inventions, as can be seen from “at least a part of the substrate surface”, for example, the inorganic material insulating layer may not be formed on the chip mounting portion of the substrate surface. In addition, an inorganic material insulating layer may be formed on a part of the wiring, and this riding part may be a solder resist. Conductive particles having a thermal conductivity of 130 W / m · K or more include, for example, silicon carbide (SiC), high-purity silicon carbide (SiC3N), copper (Cu), aluminum (Al), tungsten (W), silver ( It is composed of one or a plurality of conductive particles selected from Ag). The second invention also includes a mode in which a primer layer exists between the inorganic insulating layer and the wiring.
第３の発明は、第１または２の発明において、前記焼成後の無機材絶縁層に含有されるＳｉＯ２粒子の割合が２０〜４０重量％であり、前記焼成後の無機材絶縁層に含有されるアルミナコートされた導電粒子の割合が６０〜８０重量％であることを特徴とする。
第４の発明は、第１ないし３のいずれかの発明において、前記ＳｉＯ２粒子の平均粒径が５０ｎｍ以下であることを特徴とする。
第５の発明は、第１ないし４のいずれかの発明において、前記基板が、閉じた流路を有する水冷構造を備える平板状基板であることを特徴とする。
The third invention is the invention of the first or second, the proportion of SiO 2 particles contained in the inorganic material insulating layer after the firing is 20 to 40 weight%, the inorganic material insulating layer after the firing The ratio of the conductive particles coated with alumina is 60 to 80% by weight.
According to a fourth invention, in any one of the first to third inventions, the average particle diameter of the SiO 2 particles is 50 nm or less.
According to a fifth invention, in any one of the first to fourth inventions, the substrate is a flat substrate having a water cooling structure having a closed flow path.
第６の発明は、第１ないし５のいずれかの発明に係る絶縁回路基板と、当該基板上に搭載された１または複数個の半導体チップと、を備える半導体モジュールである。
第７の発明は、第６の発明において、前記絶縁回路基板と対向して配置され、半導体チップの絶縁回路基板設置面と対向する面からの発熱を放熱する放熱基板を備えることを特徴とする。
第８の発明は、第６または７の発明において、前記半導体チップが、パワー半導体素子からなることを特徴とする。
A sixth invention is a semiconductor module comprising the insulating circuit board according to any one of the first to fifth inventions and one or a plurality of semiconductor chips mounted on the board.
According to a seventh invention, in the sixth invention, the semiconductor device further comprises a heat dissipation substrate that is disposed to face the insulating circuit substrate and dissipates heat generated from a surface of the semiconductor chip that faces the insulating circuit substrate installation surface. .
According to an eighth invention, in the sixth or seventh invention, the semiconductor chip comprises a power semiconductor element.
第９の発明は、半導体チップと、有機材絶縁層、有機材絶縁層上に形成された配線及び無機材絶縁層を有する絶縁回路基板を備える半導体モジュールの製造方法であって、前記基板の表面に、有機材絶縁層を介して金属層を形成し、金属層をエッチング加工することにより配線パターンを形成し、配線パターンをマスクとして有機材絶縁層をエッチング加工し、前記基板の少なくとも配線パターンの形成されていない部分を含む表面に、ナノ化されたＳｉＯ２粒子およびアルミナコートされた熱伝導率が１３０Ｗ／ｍ・Ｋ以上の導電粒子を含む液材を塗布し、焼成することにより、無機材絶縁層を形成し、基板上に半導体チップを搭載し、配線パターンに電気的に接続することを特徴とする半導体モジュールの製造方法である。
第１０の発明は、半導体チップと、無機材絶縁層及び無機材絶縁層上に形成された配線を有する絶縁回路基板を備える半導体モジュールの製造方法であって、前記基板の少なくとも表面の一部に、ナノ化されたＳｉＯ２粒子およびアルミナコートされた熱伝導率が１３０Ｗ／ｍ・Ｋ以上の導電粒子を含む液材を塗布し、焼成することにより、無機材絶縁層を形成し、導電性金属インクを塗布し、焼成することにより、無機材絶縁層上に配線を形成し、基板上に半導体チップを搭載し、配線パターンに電気的に接続することを特徴とする半導体モジュールの製造方法である。ここで、第１０の発明には、無機材絶縁層と配線の間にプライマー層が存在する態様も含まれる。
第１１の発明は、第９または１０の発明において、前記絶縁回路基板に、前記絶縁回路基板の表面が露出し半導体チップが載置される載置部を設けるように、前記配線パターン及び無機材絶縁層を形成することを特徴とする。
A ninth invention is a method of manufacturing a semiconductor module comprising a semiconductor chip, an organic material insulating layer, an insulating circuit substrate having a wiring formed on the organic material insulating layer and an inorganic material insulating layer, and the surface of the substrate In addition, a metal layer is formed via the organic material insulating layer, a wiring pattern is formed by etching the metal layer, the organic material insulating layer is etched using the wiring pattern as a mask, and at least the wiring pattern of the substrate is formed. An inorganic material is obtained by applying a liquid material containing nano-sized SiO 2 particles and alumina-coated conductive particles having a thermal conductivity of 130 W / m · K or more to a surface including a portion not formed and firing. An insulating layer is formed, a semiconductor chip is mounted on a substrate, and the semiconductor module is electrically connected to a wiring pattern.
A tenth invention is a method of manufacturing a semiconductor module comprising a semiconductor chip and an insulating circuit board having an inorganic material insulating layer and a wiring formed on the inorganic material insulating layer, and is provided on at least a part of the surface of the substrate. Applying and baking a liquid material containing nano-sized SiO 2 particles and alumina-coated conductive particles having a thermal conductivity of 130 W / m · K or more to form an inorganic material insulating layer, conductive metal A method of manufacturing a semiconductor module, comprising: applying an ink and baking to form a wiring on an inorganic insulating layer; mounting a semiconductor chip on a substrate; and electrically connecting to a wiring pattern . Here, the tenth invention includes an aspect in which a primer layer is present between the inorganic insulating layer and the wiring.
In an eleventh aspect of the invention according to the ninth or tenth aspect, the wiring pattern and the inorganic material are provided on the insulating circuit board so as to provide a mounting portion on which the surface of the insulating circuit board is exposed and a semiconductor chip is mounted. An insulating layer is formed.
本発明によれば、放熱に関する部分のほぼ全ての成分が無機材料からなる層を基板上に形成することができるので、耐熱性、放熱性及び耐久性に優れた電気絶縁層を有する絶縁回路基板及び半導体モジュールを提供することが可能となる。 According to the present invention, since a layer made of an inorganic material in which almost all components related to heat dissipation can be formed on a substrate, an insulated circuit board having an electrical insulating layer excellent in heat resistance, heat dissipation and durability In addition, a semiconductor module can be provided.
また、基板表面にナノ化されたＳｉＯ２粒子を含む液材を塗布し、焼成することにより、無機材絶縁層を形成するので、基板上の所望位置に所望の形状及び厚さの無機材絶縁層を構成することが可能である。 In addition, an inorganic material insulating layer is formed by applying a liquid material containing nano-sized SiO 2 particles to the substrate surface and baking it, so that the inorganic material insulation of a desired shape and thickness is formed at a desired position on the substrate. Layers can be constructed.
さらには、無機材絶縁層の形成は液材を塗布し、低温で焼成することにより行うので、製造プロセスを簡易であり、多様な市販部品を利用することが可能である。 Furthermore, since the inorganic insulating layer is formed by applying a liquid material and baking it at a low temperature, the manufacturing process is simple and various commercially available parts can be used.
以下、例示に基づき本発明を説明する。図１は、本発明を具体化するパワー半導体モジュールの第１の構成例を示す側面断面図である。図１のパワー半導体モジュール１は、市販の半導体チップ３と、有機材絶縁層１２、配線１３及び無機材絶縁層１４が形成された放熱基板２とを主要な構成要素とする。 Hereinafter, the present invention will be described based on examples. FIG. 1 is a side sectional view showing a first configuration example of a power semiconductor module embodying the present invention. The power semiconductor module 1 of FIG. 1 includes a commercially available semiconductor chip 3 and a heat dissipation substrate 2 on which an organic material insulating layer 12, a wiring 13, and an inorganic material insulating layer 14 are formed as main components.
（ａ）のパワー半導体モジュール１は、放熱基板２上に半導体チップ３が半田等の熱伝導性接着材により直接固定されている。半導体チップ３は、有機材絶縁層１２の上に設けられた配線１３の各々との間をワイヤボンド接続により電気的に接続されている。
（ｂ）のパワー半導体モジュール１は、放熱基板２上に形成された無機材絶縁層１４の上に半導体チップ３が熱伝導性接着材により固定されている。半導体チップ３は、（ａ）と同様に配線１３との間をワイヤボンド接続により電気的に接続されている。
なお、図１では、１個の半導体チップを配置する態様を図示しているが、複数個の半導体チップを設けることも当然可能である。
In the power semiconductor module 1 of (a), a semiconductor chip 3 is directly fixed on a heat dissipation substrate 2 by a heat conductive adhesive such as solder. The semiconductor chip 3 is electrically connected to each of the wirings 13 provided on the organic material insulating layer 12 by wire bond connection.
In the power semiconductor module 1 of (b), the semiconductor chip 3 is fixed on the inorganic material insulating layer 14 formed on the heat dissipation substrate 2 with a heat conductive adhesive. Similar to (a), the semiconductor chip 3 is electrically connected to the wiring 13 by wire bond connection.
Although FIG. 1 shows a mode in which one semiconductor chip is arranged, it is naturally possible to provide a plurality of semiconductor chips.
半導体チップ３は、パワー半導体モジュールに使用可能なものであればよく、例えば、ＧＴＯサイリスタ、ＩＧＢＴ、ダイオド、ＭＯＳ（Metal Oxide Semiconductor）等のパワー半導体素子を使用することができる。
図示の放熱基板２は、表面が平面で内部に水冷構造（例えば、複数の微小開口を持つ薄銅板を積層し、上下を銅板で密閉した液室内で毛細管現象による環流が生じるヒートパイプ（特許文献３参照））を有するものである。放熱基板２は、熱伝導性及び電気特性に優れる材料であれば水冷構造を有するものに限定されず、例えば、銅板またはアルミ板により構成してもよい。
放熱基板２の表面には、無機材絶縁層１４が設けられている。無機材絶縁層１４は、無機材絶縁層１４は、二酸化珪素（ＳｉＯ２）とアルミナコートされた熱伝導率が１３０Ｗ／ｍ・Ｋ以上の導電粒子を主要な成分とし、有機リン酸を含むジエチレングリコールモノブチルエーテルの溶剤でこれらを混ぜたインクを塗布、焼成して形成される。ここで、インクの塗布は、例えば、スクリーン印刷法、スプレーコート法、インクジェット法またはディスペンサー法により行われる。無機材絶縁層１４の膜厚は、直接的な耐電圧の要請は無いため、最も厚い部分の膜厚が有機材絶縁層１２と配線１３との合計膜厚以上となるように適宜設定する。放熱基板２の表面に接触する領域の全てが、有機材絶縁層１２と配線１３との合計膜厚以上である必要はなく、部分的に他の箇所よりも薄い部分があってもよい。
The semiconductor chip 3 only needs to be usable for a power semiconductor module. For example, a power semiconductor element such as a GTO thyristor, IGBT, diode, or MOS (Metal Oxide Semiconductor) can be used.
The illustrated heat radiating substrate 2 has a flat surface and a water-cooled structure inside (for example, a heat pipe in which a thin copper plate having a plurality of minute openings is stacked and the upper and lower sides are sealed with a copper plate to cause a recirculation due to capillary action (Patent Document) 3))). The heat radiating substrate 2 is not limited to a material having a water cooling structure as long as it is a material excellent in thermal conductivity and electrical characteristics, and may be composed of, for example, a copper plate or an aluminum plate.
An inorganic material insulating layer 14 is provided on the surface of the heat dissipation substrate 2. The inorganic insulating layer 14 is composed of silicon dioxide (SiO 2 ) and alumina-coated conductive particles having a thermal conductivity of 130 W / m · K or more as main components, and diethylene glycol containing organic phosphoric acid. It is formed by applying and baking ink mixed with monobutyl ether solvent. Here, the ink is applied by, for example, a screen printing method, a spray coating method, an ink jet method, or a dispenser method. The thickness of the inorganic insulating layer 14 is appropriately set so that the thickness of the thickest portion is not less than the total thickness of the organic insulating layer 12 and the wiring 13 because there is no direct voltage withstanding requirement. It is not necessary for the entire region in contact with the surface of the heat dissipation substrate 2 to be equal to or greater than the total film thickness of the organic insulating layer 12 and the wiring 13, and there may be a portion that is partially thinner than other portions.
本発明の無機材絶縁層１４の主要な特徴は、次のとおりである。
第１の特徴は、成膜された無機材絶縁層の９０重量％以上（好ましくは９５重量％以上）が無機材料で構成されているということである。例えば、９０重量％以上が無機材料で構成されているインクを塗布し、焼成すると、有機材料が殆ど存在しない絶縁層を形成することができる。成膜された無機材絶縁層の組成は、例えば、ＳｉＯ２を２０〜４０重量％、アルミナコート導電粒子を６０〜８０重量％とする。
The main features of the inorganic insulating layer 14 of the present invention are as follows.
The first characteristic is that 90% by weight or more (preferably 95% by weight or more) of the formed inorganic material insulating layer is made of an inorganic material. For example, when an ink composed of 90% by weight or more of an inorganic material is applied and baked, an insulating layer containing almost no organic material can be formed. The composition of the deposited inorganic material insulating layer is, for example, 20 to 40% by weight of SiO 2 and 60 to 80% by weight of alumina-coated conductive particles.
第２の特徴は、無機材料を構成する二酸化珪素（ＳｉＯ２）の粒子が、ナノ化されていることである。ナノ粒子化することにより、これまで困難であった８５重量％以上が無機材料で構成される液材（インク）を塗布することが可能となる。ここで、ナノ粒子とは、直径が数ｎｍ〜数百ｎｍの粒子をいう。ＳｉＯ２は、平均粒径は５０ｎｍ以下のものを用いることが好ましく、これに粒径が２０ｎｍ以下のものを含んでいることがより好ましく、粒径が１０ｎｍ以下のものを含んでいることがさらに好ましい。 The second feature is that the silicon dioxide (SiO 2 ) particles constituting the inorganic material are nano-sized. By forming nanoparticles, it is possible to apply a liquid material (ink) in which 85% by weight or more, which has been difficult until now, is composed of an inorganic material. Here, the nanoparticle means a particle having a diameter of several nm to several hundred nm. It is preferable to use SiO 2 having an average particle size of 50 nm or less, more preferably including a particle having a particle size of 20 nm or less, and further including a particle having a particle size of 10 nm or less. preferable.
第３の特徴は、アルミナ（Ａｌ２Ｏ３）でコートされた熱伝導率が１３０Ｗ／ｍ・Ｋ以上（好ましくは１６０Ｗ／ｍ・Ｋ以上、より好ましくは１９０Ｗ／ｍ・Ｋ以上）の導電粒子を用いていることである。熱伝導率が１３０Ｗ／ｍ・Ｋ以上の導電粒子としては、炭化珪素（１６０ｗ／ｍ・ｋ）、高純度炭化珪素（１４０ｗ／ｍ・ｋ）、銅（４００Ｗ／ｍ・Ｋ）、アルミニウム（２０４Ｗ／ｍＫ）、タングステン（１９８Ｗ／ｍＫ）、銀（４１８Ｗ／ｍＫ）が例示され、これらは高熱伝導フィラーとして機能する。導電粒子の平均粒径は、例えば１〜１０μｍであり、アルミナコート膜厚は２０〜５０ｎｍである。試作品では、中心が平均粒径は４μｍのＳｉＣ粒子でアルミナコートの膜厚は３０ｎｍのものを用いた。
上記で説明した導電粒子は、単独で、或いはこれらを組み合わせたものを用いることができるが、いずれのも導電粒子も絶縁性を確保するために表面をアルミナでコートすることが必要である。
The third feature is that the conductive particles coated with alumina (Al 2 O 3 ) have a thermal conductivity of 130 W / m · K or more (preferably 160 W / m · K or more, more preferably 190 W / m · K or more). It is using. Examples of conductive particles having a thermal conductivity of 130 W / m · K or more include silicon carbide (160 w / m · k), high-purity silicon carbide (140 w / m · k), copper (400 W / m · K), aluminum (204 W / MK), tungsten (198 W / mK), silver (418 W / mK) are exemplified, and these function as high thermal conductive fillers. The average particle diameter of the conductive particles is, for example, 1 to 10 μm, and the alumina coat film thickness is 20 to 50 nm. In the prototype, SiC particles having an average particle diameter of 4 μm at the center and an alumina coat film thickness of 30 nm were used.
The conductive particles described above can be used singly or in combination. However, any conductive particles must be coated with alumina in order to ensure insulation.
このような絶縁材料からなるインクを金属板上に塗布し、例えば、１６０〜２００℃で加熱することで、溶剤中に分散したナノサイズ絶縁粒子が基材表面の凹凸に倣って配列すると共に、溶剤が蒸発して緻密な無機材絶縁層（膜）が形成される。すなわち、ナノサイズ粒子の混合粉末を金属表面に直接接触させたまま大気圧下で加熱し、その場で焼結させ、ナノサイズ効果による拡散状態を利用して接合界面で金属表面接合し、無機材絶縁層と金属層の積層構造を形成する。このように、本発明では、無機材絶縁層を構成する絶縁材料をインク化することにより、基板上の所望位置に所望の形状及び厚さの無機材絶縁層を構成することを可能としている。本発明によれば、例えば、基板表面に凹所を形成した後、半導体チップ３の載置部を除く基板表面部分に、無機材絶縁層を塗布形成することも可能である。 By applying an ink made of such an insulating material on a metal plate and heating at 160 to 200 ° C., for example, the nano-sized insulating particles dispersed in the solvent are arranged following the unevenness of the substrate surface, The solvent evaporates to form a dense inorganic material insulating layer (film). In other words, the mixed powder of nano-sized particles is heated under atmospheric pressure while in direct contact with the metal surface, sintered in situ, and bonded to the metal surface at the bonding interface using the diffusion state due to the nano-size effect. A laminated structure of an equipment insulation layer and a metal layer is formed. As described above, in the present invention, the insulating material constituting the inorganic material insulating layer is converted into ink, whereby the inorganic material insulating layer having a desired shape and thickness can be formed at a desired position on the substrate. According to the present invention, for example, after forming a recess in the substrate surface, it is also possible to apply and form the inorganic material insulating layer on the substrate surface portion excluding the mounting portion of the semiconductor chip 3.
図２は、本発明を具体化するパワー半導体モジュールの第１の構成例（ａ）に使用する基板の製造工程を説明する側面断面図である。
まず、基板上に、有機材絶縁層（例えば、ポリイミド層）１２と銅箔層を形成する（ＳＴＥＰ１）。例えば金属板上に熱可塑性ポリイミド膜と銅箔を積層して、高温加圧（例えば３５０℃で２０分）して形成する。ポリイミドの耐電圧は２００〜５００Ｖ／μｍ程度であるので、厚さは少なくとも２０μｍ以上、好ましくは５０μｍ以上とする。配線１３の膜厚は大電流を可能とするため５０〜２００μｍの範囲で設定することが好ましいが、電流の少ない用途の場合はそれより薄くても構わない。
次に、貼り付けた銅箔の加工を行って、パターニング加工を行い、配線１３を形成する（ＳＴＥＰ２）。例えば、この加工のために、ホトリソグラフィ技術を用いる。銅箔の上にレジストを塗布し、パターンを露光、現像してさらにエッチングを行い、レジストを除去して、銅箔除去部を形成する。
次に、銅箔をマスクにして有機材絶縁層１２のエッチングを行う（ＳＴＥＰ３）。ポリイミドエッチング用の溶液としては例えばアミン系のものがよく使用される。
最後に、放熱基板２上の銅箔除去部を埋めるように、無機材を塗布し無機材絶縁層１４を形成する（ＳＴＥＰ４）。無機材の塗布法としては、スクリーン印刷法またはスプレーコート法が例示される。塗布された無機材を、大気圧下で１６０〜２００℃で焼成することにより、無機絶縁層を成膜する。放熱基板２の表面に接触する領域の無機材絶縁層１４の膜厚は、例えば７０〜３００μｍの範囲で設置する。半導体チップ３が載置される載置部１５には、無機絶縁層１４は形成しない。
なお、図２では、電気接続用の開口をのぞき、配線に一部乗り上げて無機材を塗布する態様を示したが、配線とほぼ同一面の高さまで無機材を塗布する態様としてもよい。
FIG. 2 is a side sectional view for explaining a manufacturing process of a substrate used in the first configuration example (a) of the power semiconductor module embodying the present invention.
First, an organic material insulating layer (for example, polyimide layer) 12 and a copper foil layer are formed on a substrate (STEP 1). For example, a thermoplastic polyimide film and a copper foil are laminated on a metal plate and formed by high-temperature pressurization (for example, at 350 ° C. for 20 minutes). Since the withstand voltage of polyimide is about 200 to 500 V / μm, the thickness is at least 20 μm or more, preferably 50 μm or more. The thickness of the wiring 13 is preferably set in the range of 50 to 200 μm in order to enable a large current, but may be thinner in the case of an application with a small current.
Next, the attached copper foil is processed and patterned to form the wiring 13 (STEP 2). For example, photolithography technology is used for this processing. A resist is applied on the copper foil, the pattern is exposed and developed, and etching is further performed to remove the resist, thereby forming a copper foil removing portion.
Next, the organic insulating layer 12 is etched using the copper foil as a mask (STEP 3). For example, amine-based solutions are often used as polyimide etching solutions.
Finally, an inorganic material is applied so as to fill the copper foil removal portion on the heat dissipation substrate 2 to form the inorganic material insulating layer 14 (STEP 4). Examples of the inorganic material coating method include a screen printing method and a spray coating method. An inorganic insulating layer is formed by baking the applied inorganic material at 160 to 200 ° C. under atmospheric pressure. The film thickness of the inorganic insulating layer 14 in the region in contact with the surface of the heat dissipation substrate 2 is set in the range of 70 to 300 μm, for example. The inorganic insulating layer 14 is not formed on the placement portion 15 on which the semiconductor chip 3 is placed.
In FIG. 2, an embodiment in which the inorganic material is applied by partially climbing on the wiring except for the opening for electrical connection is shown. However, an aspect in which the inorganic material is applied to a height almost the same as the wiring may be used.
以上に説明した本発明の絶縁回路基板は、有機材絶縁層（ポリイミド層）以外は無機材料で絶縁層を構成しているので、ポリイミド層の耐熱性能（例えば３５０℃）を有する基板を提供することが可能である。
また、ＳｉＯ２とアルミナコートされた導電粒子で構成される液材（インク）の焼成は２００℃以下の低温プロセスで行うことができるので、基板製造コストを削減することが可能である。そして、低温プロセスが可能であることから、水冷構造を有する市販の放熱基板（例えば、日本モレックス社のＦＧＨＰ（特許文献３参照））を利用することも可能となる。
また、ＳｉＯ２とアルミナコートされた導電粒子で構成される無機材絶縁層は熱膨張率が小さいため、半導体チップとの接合性も良好である。
さらに、無機材絶縁層は、ＳｉＯ２とアルミナコートされた導電粒子Ｃｕで構成されるので、高熱伝導性を有する。表１及び表２は、下記式１に示すＢｒｕｇｇｅｍａｎの式により算出した熱伝導率の一例である。
Since the insulating circuit board of the present invention described above has an insulating layer made of an inorganic material other than the organic insulating layer (polyimide layer), a substrate having a heat resistance (for example, 350 ° C.) of the polyimide layer is provided. It is possible.
In addition, baking of a liquid material (ink) composed of conductive particles coated with SiO 2 and alumina can be performed by a low-temperature process of 200 ° C. or lower, so that the substrate manufacturing cost can be reduced. And since a low-temperature process is possible, it becomes possible to utilize the commercially available heat dissipation board | substrate (For example, FGHP (refer patent document 3) of Nihon Molex) which has a water cooling structure.
In addition, since the inorganic insulating layer composed of the conductive particles coated with SiO 2 and alumina has a low coefficient of thermal expansion, the bonding property with the semiconductor chip is also good.
Furthermore, since the inorganic insulating layer is composed of SiO 2 and alumina-coated conductive particles Cu, it has high thermal conductivity. Tables 1 and 2 are examples of the thermal conductivity calculated by the Bruggeman formula shown in the following formula 1.
［式１］
[Formula 1]
ここで、λｃは求める値、λｆはフィラーの熱伝導率、λｍはベース機材（ＳｉＯ２）の熱伝導率、Φは充填率である。 Here, λ c is a desired value, λ f is the thermal conductivity of the filler, λ m is the thermal conductivity of the base material (SiO 2 ), and Φ is the filling rate.
図３は、本発明を具体化するパワー半導体モジュールの第２の構成例を示す側面断面図である。第２の構成例では、第１の構成例（ａ）に、無機材絶縁層１６、無機材絶縁層１７及び放熱基板２０が付加されており、半導体チップ３の両面から放熱が行われる。
図３（ａ）に示すように、半導体チップ３周囲の空間に、無機絶縁層１６を例えばディスペンサー法により充填する。また、半導体チップ３の上面に無機材絶縁層１７を例えばディスペンサー法により形成する。無機材絶縁層１７に代え、ワイヤと干渉しない高熱伝導性の絶縁放熱板を用いてもよい。
続いて図３（ｂ）に示すように、無機材絶縁層２４と放熱基板２０とを、高熱伝導性接着材または放熱グリースにより接着する。このとき無機絶縁層２４を無くして直接半導体チップ上に放熱グリースを接着しても良い。放熱基板２０は、放熱基板２と同じ水冷構造を有するもの（特許文献３参照）であるが、これに限定されず、熱伝導性及び電気特性に優れる材料からなる板材（例えば、銅板またはアルミ板）により構成してもよい。
最後に図３（ｃ）に示すように、複数の固定部材１８により放熱基板２及び２０を固定する。固定部材１８には、ネジ留め等の簡易な固定手段を採用することが好ましい。なお、放熱基板２及び２０には、予め固定部材１８を挿通するための挿通孔（図示せず）が設けられている。
FIG. 3 is a side sectional view showing a second configuration example of the power semiconductor module embodying the present invention. In the second configuration example, the inorganic material insulating layer 16, the inorganic material insulating layer 17, and the heat dissipation substrate 20 are added to the first configuration example (a), and heat is radiated from both surfaces of the semiconductor chip 3.
As shown in FIG. 3A, the space around the semiconductor chip 3 is filled with an inorganic insulating layer 16 by, for example, a dispenser method. Further, the inorganic material insulating layer 17 is formed on the upper surface of the semiconductor chip 3 by, for example, a dispenser method. Instead of the inorganic material insulating layer 17, an insulating heat radiating plate having high thermal conductivity that does not interfere with the wire may be used.
Subsequently, as shown in FIG. 3B, the inorganic insulating layer 24 and the heat dissipation substrate 20 are bonded to each other with a high thermal conductive adhesive or heat dissipation grease. At this time, the inorganic insulating layer 24 may be eliminated and the heat dissipating grease may be directly bonded onto the semiconductor chip. The heat dissipation board 20 has the same water cooling structure as the heat dissipation board 2 (see Patent Document 3), but is not limited to this, and is a plate material (for example, a copper plate or an aluminum plate) made of a material having excellent thermal conductivity and electrical characteristics. ).
Finally, as shown in FIG. 3C, the heat dissipation substrates 2 and 20 are fixed by a plurality of fixing members 18. The fixing member 18 preferably employs simple fixing means such as screwing. In addition, the heat dissipation substrates 2 and 20 are provided with insertion holes (not shown) for inserting the fixing member 18 in advance.
このように構成された第２の構成例では、半導体チップ３からの発熱が、無機絶縁層１６、無機材絶縁層１７及び放熱基板２０からも放熱されるため、第１の構成例と比べより高い放熱性能を得ることができる。
なお、図３では第１の構成例（ａ）に、無機材絶縁層１６、無機材絶縁層１７及び放熱基板２０を付加する態様を説明したが、第１の構成例（ｂ）にもこれらの構成を適用できることは言うまでもない。
In the second configuration example configured as described above, the heat generated from the semiconductor chip 3 is also radiated from the inorganic insulating layer 16, the inorganic material insulating layer 17, and the heat dissipation substrate 20, and therefore, compared with the first configuration example. High heat dissipation performance can be obtained.
In addition, although the aspect which adds the inorganic material insulating layer 16, the inorganic material insulating layer 17, and the thermal radiation board | substrate 20 to the 1st structural example (a) was demonstrated in FIG. 3, these are also shown in the 1st structural example (b). Needless to say, this configuration can be applied.
図４は、本発明を具体化するパワー半導体モジュールの第３の構成例を示す側面断面図である。第２の構成例では、第２の構成例に、ケース部材１９及びモールド樹脂２１が付加されている。
図４（ａ）に示すように、半導体チップ３周囲の空間に、無機絶縁層１６を例えばディスペンサー法により充填する。また、半導体チップ３の上面に無機材絶縁層１７を例えばディスペンサー法により形成する。そして、環状のケース部材１９を無機材絶縁層１４を介して放熱基板２に設置する。なお、ケース部材１９を、放熱基板２に直接固定するようにしてもよい。
続いて図４（ｂ）に示すように、ケース部材１９で囲まれた領域に、例えばエポキシ樹脂またはシリコーンゲルで充填する。無機材絶縁層１７の上面（放熱基板２０との当接面）は、熱伝導性を損なわないためにモールドしないようにする。
最後に図４（ｃ）に示すように、複数の固定部材１８により放熱基板２及び２０を固定する。
FIG. 4 is a side sectional view showing a third configuration example of the power semiconductor module embodying the present invention. In the second configuration example, a case member 19 and a mold resin 21 are added to the second configuration example.
As shown in FIG. 4A, the space around the semiconductor chip 3 is filled with an inorganic insulating layer 16 by, for example, a dispenser method. Further, the inorganic material insulating layer 17 is formed on the upper surface of the semiconductor chip 3 by, for example, a dispenser method. Then, the annular case member 19 is installed on the heat dissipation substrate 2 through the inorganic material insulating layer 14. Note that the case member 19 may be directly fixed to the heat dissipation board 2.
Subsequently, as shown in FIG. 4B, the region surrounded by the case member 19 is filled with, for example, epoxy resin or silicone gel. The upper surface of the inorganic material insulating layer 17 (contact surface with the heat dissipation substrate 20) is not molded so as not to impair the thermal conductivity.
Finally, as shown in FIG. 4C, the heat dissipation substrates 2 and 20 are fixed by a plurality of fixing members 18.
図５は、本発明を具体化するパワー半導体モジュールの第４の構成例を説明する側面断面図である。図５のパワー半導体モジュール１は、市販の半導体チップ３と、配線１３及び無機材絶縁層１４が形成された放熱基板２とを主要な構成要素とする。半導体チップ３と、配線１３及び無機材絶縁層１４の構成については、これまで述べた構成例と同様であるのでここでは説明を省略する。 FIG. 5 is a side sectional view for explaining a fourth configuration example of the power semiconductor module embodying the present invention. The power semiconductor module 1 in FIG. 5 includes a commercially available semiconductor chip 3 and a heat dissipation substrate 2 on which wirings 13 and an inorganic material insulating layer 14 are formed as main components. Since the configuration of the semiconductor chip 3, the wiring 13, and the inorganic material insulating layer 14 is the same as the configuration example described so far, the description thereof is omitted here.
図６は、本発明を具体化するパワー半導体モジュールの第４の構成例に使用する基板の製造工程を説明する側面断面図である。
まず、放熱基板２上に、上述したナノ化されたＳｉＯ２粒子およびアルミナコートされた熱伝導率が１３０Ｗ／ｍ・Ｋ以上の導電粒子を含む液材を塗布し無機材絶縁層１４を形成する（ＳＴＥＰ１）。放熱基板２は、表面が平面で内部に水冷構造（例えば、複数の微小開口を持つ薄銅板を積層し、上下を銅板で密閉した液室内で毛細管現象による環流が生じるヒートパイプ（特許文献３参照））を有するもの、銅板またはアルミ板から適宜選択される。無機材の塗布法としては、スクリーン印刷法またはスプレーコート法が例示される。塗布された無機材を、大気圧下で１６０〜２００℃で焼成することにより、無機絶縁層を成膜する。なお、半導体チップ３が載置される載置部１５には、無機絶縁層１４を形成しないようにしてもよい。
FIG. 6 is a side cross-sectional view illustrating a manufacturing process of a substrate used in the fourth configuration example of the power semiconductor module embodying the present invention.
First, the inorganic material insulating layer 14 is formed on the heat dissipation substrate 2 by applying the above-described nano-sized SiO 2 particles and alumina-coated liquid material containing conductive particles having a thermal conductivity of 130 W / m · K or more. (STEP 1). The heat radiating substrate 2 has a flat surface and a water-cooled structure inside (for example, a heat pipe in which a thin copper plate having a plurality of minute openings is laminated and the upper and lower sides are sealed with a copper plate to generate a recirculation due to capillary action (see Patent Document 3) )), A copper plate or an aluminum plate. Examples of the inorganic material coating method include a screen printing method and a spray coating method. An inorganic insulating layer is formed by baking the applied inorganic material at 160 to 200 ° C. under atmospheric pressure. Note that the inorganic insulating layer 14 may not be formed on the placement portion 15 on which the semiconductor chip 3 is placed.
次に、無機材絶縁層１４の表面の撥水性などにより配線１３の形成が困難である場合は、必要に応じて、プラズマ処理等で撥水性残渣を除去し表面活性化を行うと共に、素材間の密着性を向上させるプライマー（例えばエポキシプライマー）を塗布しプライマー層２２を形成する（ＳＴＥＰ２）。プライマーの塗布法としては、スピンコーティング法またはスプレーコート法が例示される。
最後に、無機材絶縁層１４の上に導電性金属インク（例えば、銀インクや銀と銅を混合したハイブリッドインク）をスクリーン印刷法、インクジェット法またはディスペンサー法により必要箇所に描画塗布した後、焼成して金属化させることにより配線１３を形成する。
Next, when it is difficult to form the wiring 13 due to the water repellency of the surface of the inorganic insulating layer 14, the surface of the inorganic material insulating layer 14 is activated by removing the water-repellent residue by plasma treatment or the like. A primer layer 22 is formed by applying a primer (for example, an epoxy primer) that improves the adhesion of the primer (STEP 2). Examples of the primer application method include spin coating and spray coating.
Finally, a conductive metal ink (for example, silver ink or a hybrid ink in which silver and copper are mixed) is drawn and applied on the inorganic insulating layer 14 by a screen printing method, an inkjet method or a dispenser method, and then fired. Then, the wiring 13 is formed by metallization.
以上、本開示にて幾つかの実施の形態を単に例示として詳細に説明したが、本発明の新規な教示及び有利な効果から実質的に逸脱せずに、その実施の形態には多くの改変例が可能である。 Although several embodiments have been described in detail in the present disclosure by way of example only, many modifications may be made to the embodiments without substantially departing from the novel teachings and advantages of the present invention. Examples are possible.
１ パワー半導体モジュール
２ 放熱基板
３ 半導体チップ
４ 熱伝導性接着材
１２ 有機材絶縁層
１３ 配線
１４ 無機材絶縁層
１５ 載置部
１６ 無機材絶縁層
１７ 無機材絶縁層
１８ 固定部材
１９ ケース部材
２０ 放熱基板
２１ モールド樹脂
２２ プライマー層
DESCRIPTION OF SYMBOLS 1 Power semiconductor module 2 Thermal radiation board 3 Semiconductor chip 4 Thermally conductive adhesive material 12 Organic material insulating layer 13 Wiring 14 Inorganic material insulating layer 15 Mounting part 16 Inorganic material insulating layer 17 Inorganic material insulating layer 18 Fixing member 19 Case member 20 Heat dissipation Substrate 21 Mold resin 22 Primer layer
Claims (11)
基板は少なくとも表面が金属であり、基板表面の少なくとも一部にナノ化されたＳｉＯ２粒子およびアルミナコートされた熱伝導率が１３０Ｗ／ｍ・Ｋ以上の導電粒子を含む液材を塗布し、焼成することにより無機材絶縁層を形成したことを特徴とする絶縁回路基板。 A substrate having an organic material insulating layer and a wiring formed on the organic material insulating layer, and an insulating circuit substrate provided with an inorganic material insulating layer formed on the surface of the substrate, on which a semiconductor chip is mounted,
At least the surface of the substrate is a metal, and a liquid material containing nano-sized SiO 2 particles and alumina-coated conductive particles having a thermal conductivity of 130 W / m · K or more is applied to at least a part of the substrate surface, followed by firing. An insulating circuit board characterized in that an inorganic insulating layer is formed.
基板は少なくとも表面が金属であり、基板表面の少なくとも一部にナノ化されたＳｉＯ２粒子およびアルミナコートされた熱伝導率が１３０Ｗ／ｍ・Ｋ以上の導電粒子を含む液材を塗布し、焼成することにより無機材絶縁層を形成したことを特徴とする絶縁回路基板。 An insulating circuit board comprising an inorganic material insulating layer formed on the surface of the substrate and wiring formed on the inorganic material insulating layer, on which a semiconductor chip is mounted,
At least the surface of the substrate is a metal, and a liquid material containing nano-sized SiO 2 particles and alumina-coated conductive particles having a thermal conductivity of 130 W / m · K or more is applied to at least a part of the substrate surface, followed by firing. An insulating circuit board characterized in that an inorganic insulating layer is formed.
前記基板の表面に、有機材絶縁層を介して金属層を形成し、金属層をエッチング加工することにより配線パターンを形成し、配線パターンをマスクとして有機材絶縁層をエッチング加工し、
前記基板の少なくとも配線パターンの形成されていない部分を含む表面に、ナノ化されたＳｉＯ２粒子およびアルミナコートされた熱伝導率が１３０Ｗ／ｍ・Ｋ以上の導電粒子を含む液材を塗布し、焼成することにより、無機材絶縁層を形成し、
基板上に半導体チップを搭載し、配線パターンに電気的に接続することを特徴とする半導体モジュールの製造方法。 A method for manufacturing a semiconductor module comprising a semiconductor chip, an organic material insulating layer, an insulating circuit board having an inorganic material insulating layer and wiring formed on the organic material insulating layer,
A metal layer is formed on the surface of the substrate via an organic material insulating layer, a wiring pattern is formed by etching the metal layer, and the organic material insulating layer is etched using the wiring pattern as a mask,
Applying a liquid material containing nano-sized SiO 2 particles and alumina-coated conductive particles having a thermal conductivity of 130 W / m · K or more to the surface including at least a portion of the substrate where the wiring pattern is not formed, By firing, an inorganic material insulating layer is formed,
A method for manufacturing a semiconductor module, comprising mounting a semiconductor chip on a substrate and electrically connecting to a wiring pattern.
前記基板の少なくとも表面の一部に、ナノ化されたＳｉＯ２粒子およびアルミナコートされた熱伝導率が１３０Ｗ／ｍ・Ｋ以上の導電粒子を含む液材を塗布し、焼成することにより、無機材絶縁層を形成し、
導電性金属インクを塗布し、焼成することにより、無機材絶縁層上に配線を形成し、
基板上に半導体チップを搭載し、配線パターンに電気的に接続することを特徴とする半導体モジュールの製造方法。 A method of manufacturing a semiconductor module comprising a semiconductor chip and an insulating circuit board having an inorganic material insulating layer and a wiring formed on the inorganic material insulating layer,
An inorganic material is obtained by applying a liquid material containing nano-sized SiO 2 particles and alumina-coated conductive particles having a thermal conductivity of 130 W / m · K or more to at least a part of the surface of the substrate, followed by firing. Forming an insulating layer,
By applying conductive metal ink and firing, wiring is formed on the inorganic insulating layer,
A method for manufacturing a semiconductor module, comprising mounting a semiconductor chip on a substrate and electrically connecting to a wiring pattern.
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| KR101870153B1 (en) * | 2016-11-28 | 2018-06-25 | 주식회사 네패스 | Semiconductor Package of using Insulating Frame and Method of fabricating the same |
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