JP4961314B2 - Power semiconductor device - Google Patents

Power semiconductor device Download PDF

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JP4961314B2
JP4961314B2 JP2007252967A JP2007252967A JP4961314B2 JP 4961314 B2 JP4961314 B2 JP 4961314B2 JP 2007252967 A JP2007252967 A JP 2007252967A JP 2007252967 A JP2007252967 A JP 2007252967A JP 4961314 B2 JP4961314 B2 JP 4961314B2
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power semiconductor
semiconductor device
electrode
wiring
semiconductor element
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JP2009088046A (en
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心哉 河喜多
円丈 露野
英人 吉成
裕二朗 金子
裕之 宝蔵寺
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Hitachi Astemo Ltd
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Hitachi Automotive Systems Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a power semiconductor device which is superior in reliability and which can be made thin, small in size and high in heat dissipation. <P>SOLUTION: In a power semiconductor device in which a power semiconductor element with a first electrode and a second electrode provided on one surface thereof is mounted on a wiring substrate, a polymeric material which is electrically insulative and has a thixotropy of 1.2 or larger and a viscosity of 400 Pa s or smaller is prepared between a wiring, on which the first electrode of the power semiconductor element is mounted, a wiring on which the second electrode of the power semiconductor element is mounted in the wiring substrate; and the thickness of the polymeric material is larger than the thickness of the wiring. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

本発明は、パワー半導体素子が搭載されたパワー半導体装置に関する。   The present invention relates to a power semiconductor device on which a power semiconductor element is mounted.

大電流をスイッチング制御するＭＯＳＦＥＴやＩＧＢＴのパワーデバイスとスイッチング時に発生する逆電圧を開放するダイオードから構成されるパワー半導体装置は、電力変換器用インバータ装置の主要構成部品として家電から車両用等の幅広い分野で用いられている。近年、自動車分野のモータ制御化が急速に進められる中、その電流制御機器であるパワー半導体装置が使用される環境が厳しくなってきており、設置場所が冷却を十分行えない高温雰囲気下であったり、制御する電流容量が増大する方向にある。このため、パワー半導体モジュールの性能として、温度変化の大きい使用環境で長期間に渡り正常動作を確保できる高い信頼性や、大電流通電に伴う素子からの発熱量増大によるデバイスの高温化に耐える高耐熱性が求められている。また、このようなパワー半導体装置では、実装面積の低減、回路上の寄生インダクタンスや寄生抵抗成分の低減を図るため、複数のパワー半導体チップを一つのパッケージに封入される。複数のパワー半導体チップを一つのパッケージ化したパワー半導体装置では放熱性が減少するため、放熱性に優れた実装構造とする必要がある。これに対し、大電流用半導体装置の小型化，低浮遊容量化，高放熱化，配線用ワイヤレス化を目標に半導体装置全体を樹脂で封止する形の半導体装置が知られている。また、複数のパワー半導体チップの電極間を板状のリード部材で接続し、リード部材が露出した状態で樹脂封止することで、パワー半導体装置の両面から放熱するパッケージ構造が知られている（特許文献１）。   Power semiconductor devices composed of MOSFET and IGBT power devices that control switching of large currents and diodes that release the reverse voltage generated during switching are a wide range of fields from home appliances to vehicles as the main components of inverter devices for power converters. It is used in. In recent years, as motor control in the automotive field has been rapidly advanced, the environment in which the power semiconductor device that is the current control device is used has become severe, and the installation location is under a high-temperature atmosphere where cooling cannot be performed sufficiently. The current capacity to be controlled tends to increase. For this reason, the power semiconductor module has high reliability that can ensure normal operation over a long period of time in an environment where temperature changes are large, and that can withstand high temperatures due to an increase in the amount of heat generated from the elements caused by energization of a large current. Heat resistance is required. Also, in such a power semiconductor device, a plurality of power semiconductor chips are enclosed in one package in order to reduce the mounting area and the parasitic inductance and parasitic resistance components on the circuit. In a power semiconductor device in which a plurality of power semiconductor chips are packaged in one package, heat dissipation is reduced. Therefore, a mounting structure having excellent heat dissipation is required. On the other hand, there is known a semiconductor device in which the entire semiconductor device is sealed with resin for the purpose of downsizing, low stray capacitance, high heat dissipation, and wireless wiring for high-current semiconductor devices. In addition, a package structure is known in which electrodes of a plurality of power semiconductor chips are connected by plate-like lead members and resin-sealed in a state where the lead members are exposed, thereby radiating heat from both sides of the power semiconductor device ( Patent Document 1).

特開２００６−１３０８０号公報JP 2006-13080 A

特許文献１のように両面放熱型の半導体装置とすることで、半導体装置の小型化とともに放熱性に優れるという利点がある。しかし、特許文献１で提案された半導体装置は非絶縁型であり、配線基板等の電極に実装され使用されることになる。その際、放熱経路は、半導体装置の電極から配線基板等の電極へ放熱する経路であり、熱を広い領域へ拡散させながら放熱することは難しい。高温雰囲気下や、制御する電流容量が増大に対応し、より放熱性を向上させるために、金属板上の配線基板にパワー半導体素子を搭載し、これらを樹脂封止した絶縁型の半導体装置とすることが挙げられる。   By using a double-sided heat dissipation type semiconductor device as in Patent Document 1, there is an advantage that the semiconductor device is miniaturized and excellent in heat dissipation. However, the semiconductor device proposed in Patent Document 1 is a non-insulating type, and is mounted and used on an electrode such as a wiring board. In this case, the heat dissipation path is a path for dissipating heat from the electrode of the semiconductor device to an electrode such as a wiring board, and it is difficult to dissipate heat while diffusing heat over a wide area. In order to cope with an increase in the current capacity to be controlled in a high-temperature atmosphere or to improve heat dissipation, an insulating semiconductor device in which a power semiconductor element is mounted on a wiring board on a metal plate and these are sealed with a resin To do.

一方、パワー半導体装置としては、小型化，高放熱化の要求とともに、製造工程における工数の低減による低コスト化の要求がある。工程数の低減のために、パワー半導体素子の配線基板への実装と、複数のパワー半導体素子間の電気的接続を一括接合することが考えられる。パワー半導体素子を実装する際に、金バンプや銀ペーストなど、複数の種類の接合材を用いて半導体素子やその他の部材を接続する構造では、接続を確立するために接続部材の種類と同数以上の工程が必要とされ、製造工程が複雑化する。そのため、一括接合を実現するためには、ペースト状または板状の同種のはんだを用いて接合する。パワー半導体素子の一つの面に第一の電極と第二の電極が設けられた面と配線基板の配線との接続に、ペースト状または板状のはんだを用いた場合、はんだリフロー時に、はんだが飛んだり、濡れ広がってしまい、第一の電極と第二の電極が短絡するという問題がある。   On the other hand, as a power semiconductor device, there is a demand for cost reduction by reducing man-hours in the manufacturing process as well as demand for miniaturization and high heat dissipation. In order to reduce the number of processes, it can be considered that the power semiconductor element is mounted on the wiring board and the electrical connection between the plurality of power semiconductor elements is collectively bonded. When a power semiconductor element is mounted, in the structure in which semiconductor elements and other members are connected using multiple types of bonding materials such as gold bumps and silver paste, the same number or more of the types of connection members is required to establish the connection. This process is required and the manufacturing process becomes complicated. Therefore, in order to realize collective bonding, bonding is performed using the same kind of solder in the form of paste or plate. When paste or plate-like solder is used to connect the surface of the power semiconductor element with the first electrode and the second electrode provided on one surface and the wiring of the wiring board, the solder will be removed during solder reflow. There is a problem that the first electrode and the second electrode are short-circuited by flying or spreading.

一方、半導体素子の両面に金属板を配置して両面から放熱する半導体装置では、パワー半導体素子の厚さ方向の寸法誤差や、はんだ等の接合材の厚さばらつきにより、電気絶縁性樹脂にて封止する工程において、金属板上に封止樹脂の一部が進入するという問題がある。この進入した封止樹脂を除去せずに半導体装置を動作させた場合、この封止樹脂進入領域では、金属板露出領域に比べ放熱性が低下するため、所定の放熱性が得られず、半導体装置の誤動作や故障に繋がるという問題がある。そのため、樹脂封止工程後、放熱板上に進入した封止樹脂の除去工程が加わる分、製造工程における工数増加という問題がある。更に、前記の除去工程は何れも半導体装置に損傷を与える危険性もある。   On the other hand, in a semiconductor device in which metal plates are arranged on both sides of a semiconductor element to dissipate heat from both sides, due to dimensional errors in the thickness direction of the power semiconductor element and variations in the thickness of bonding materials such as solder, an electrically insulating resin is used. In the sealing step, there is a problem that a part of the sealing resin enters the metal plate. When the semiconductor device is operated without removing the entering sealing resin, the heat dissipation performance is reduced in the sealing resin entrance area as compared to the exposed area of the metal plate. There is a problem that it leads to malfunction or failure of the device. Therefore, after the resin sealing process, there is a problem that the number of steps in the manufacturing process increases due to the additional process of removing the sealing resin that has entered the heat sink. Furthermore, any of the above-described removal processes may cause damage to the semiconductor device.

本発明は、上述のような問題を踏まえ、信頼性に優れ、薄型化，小型化，高放熱性が可能なパワー半導体装置を提供することを目的とする。   In view of the above-described problems, an object of the present invention is to provide a power semiconductor device that is excellent in reliability and can be reduced in thickness, size, and heat dissipation.

上記課題を解決するため、本発明は次のような手段を用いる。   In order to solve the above problems, the present invention uses the following means.

本発明のパワー半導体装置は、一つ面に第一の電極と第二の電極が設けられたパワー半導体素子が配線基板に実装されたパワー半導体装置において、前記配線基板の、前記パワー半導体素子の第一の電極が実装される配線と、前記パワー半導体素子の第二の電極が実装される配線との間に、電気絶縁性で且つチクソ性１.２以上，粘度４００Ｐａ・ｓ以下の高分子材料が設けられ、前記高分子材料の厚さが前記配線の厚さよりも厚いことを特徴とする。このように、配線間に高分子材料を設けたことにより、はんだリフロー時のはんだの飛散や、濡れ広がることに起因する、前記第一の電極と第二の電極の短絡を防止できる。   The power semiconductor device of the present invention is a power semiconductor device in which a power semiconductor element having a first electrode and a second electrode provided on one surface is mounted on a wiring board. Between the wiring on which the first electrode is mounted and the wiring on which the second electrode of the power semiconductor element is mounted, a polymer that is electrically insulative and has a thixotropy of 1.2 or more and a viscosity of 400 Pa · s or less. A material is provided, and the polymer material is thicker than the wiring. As described above, by providing the polymer material between the wirings, it is possible to prevent the first electrode and the second electrode from being short-circuited due to the scattering of the solder during the solder reflow and the spreading of the wet.

また、本発明のパワー半導体装置は、絶縁基板の一方の面に配線が形成され、他方の面に金属板を有する配線基板と、一方の面にゲート電極とソース電極、他方の面にドレイン電極を有し、前記ドレイン電極がはんだにより前記配線と接続された第１のパワー半導体素子と、一方の面にゲート電極とソース電極、他方の面にドレイン電極を有し、前記ゲート電極とソース電極がはんだにより前記配線と接続された第２のパワー半導体素子と、前記第１のパワー半導体素子のソース電極と、前記第２のパワー半導体素子のドレイン電極とを電気的に接続するための導体平板と、前記配線基板と電気的に接続された外部接続用端子と、前記配線基板、第１，第２のパワー半導体素子、導体平板、及び、外部接続用端子を封止する封止樹脂とを備え、前記金属板と前記導体平板の表面が、前記封止樹脂の表面に露出していることを特徴とする。絶縁基板の一方の面に配線が形成され、他方の面に金属板を有する配線基板に複数のパワー半導体素子を実装し、この際、第１，第２のパワー半導体素子を反対向きに実装し、パワー半導体素子の電極間の接続を導体平板により行い、導体平板、金属板が露出するように樹脂封止した構造により、装置の薄型化，小型化と放熱性の向上が図れる。   The power semiconductor device according to the present invention includes a wiring substrate having a wiring formed on one surface of an insulating substrate and a metal plate on the other surface, a gate electrode and a source electrode on one surface, and a drain electrode on the other surface. A first power semiconductor element in which the drain electrode is connected to the wiring by solder, a gate electrode and a source electrode on one surface, and a drain electrode on the other surface, the gate electrode and the source electrode Is a conductor flat plate for electrically connecting the second power semiconductor element connected to the wiring by solder, the source electrode of the first power semiconductor element, and the drain electrode of the second power semiconductor element And an external connection terminal electrically connected to the wiring board, and a sealing resin for sealing the wiring board, the first and second power semiconductor elements, the conductive flat plate, and the external connection terminal. Preparation Surface of the conductor flat plate and the metal plate, and wherein the exposed on the surface of the sealing resin. A plurality of power semiconductor elements are mounted on a wiring board having a wiring formed on one surface of the insulating substrate and a metal plate on the other surface. At this time, the first and second power semiconductor elements are mounted in opposite directions. The structure of the power semiconductor element connected between the electrodes by a conductive flat plate and resin-sealed so that the conductive flat plate and the metal plate are exposed can reduce the thickness and size of the device and improve the heat dissipation.

本発明により、信頼性に優れ、薄型化，小型化，高放熱性が可能なパワー半導体装置を提供することができる。   According to the present invention, it is possible to provide a power semiconductor device that is excellent in reliability and can be thinned, miniaturized, and highly radiated.

本発明の実施形態について説明する。本発明のパワー半導体装置は、一つ面に第一の電極と第二の電極が設けられ、他の面に第三の電極が設けられたパワー半導体素子が配線基板に実装された構造を有する。配線基板に設けられた配線のうち、パワー半導体素子の第一の電極が実装される配線と、パワー半導体素子の第二の電極が実装される配線との間に、電気絶縁性で且つチクソ性１.２以上，粘度４００Ｐａ・ｓ以下の高分子材料が設けられ、前記高分子材料の厚さが前記配線の厚さよりも厚いことを特徴とする。また、配線間に設けられる高分子材料の高さは、パワー半導体素子と前記配線とを接続するはんだの厚さの半分以上、はんだ厚さ以下とすることが好ましい。   An embodiment of the present invention will be described. The power semiconductor device of the present invention has a structure in which a power semiconductor element in which a first electrode and a second electrode are provided on one surface and a third electrode is provided on the other surface is mounted on a wiring board. . Of the wiring provided on the wiring board, between the wiring on which the first electrode of the power semiconductor element is mounted and the wiring on which the second electrode of the power semiconductor element is mounted is electrically insulating and thixotropic. A polymer material having a viscosity of 1.2 or more and a viscosity of 400 Pa · s or less is provided, and the thickness of the polymer material is larger than the thickness of the wiring. The height of the polymer material provided between the wirings is preferably not less than half the thickness of the solder connecting the power semiconductor element and the wiring and not more than the solder thickness.

このように電気絶縁性で且つチクソ性１.２以上，粘度４００Ｐａ・ｓ以下の高分子材料が、はんだ厚さの半分以上の厚さに設けられることで、はんだリフロー時のはんだの飛散や、濡れ広がることに起因する、前記第一の電極と第二の電極の短絡を防止できる。また、はんだ厚さ以下の高さに前記電気絶縁性で且つチクソ性１.２以上，粘度４００Ｐａ・ｓ以下の高分子材料に設けることで、はんだ厚さのばらつきが低減できることを見出した。かかる結果、パワー半導体素子の接続を一回の工程で達成でき、且つ耐圧信頼性も公知の接続方法と同等、または同等以上となることを見出した。また前記チクソ性１.２以上，粘度４００Ｐａ・ｓ以下の高分子材料を、はんだ厚さ以下の高さに設けることで、はんだ厚さのばらつきが低減できることを見出した。   As described above, the polymer material having an electrical insulation and thixotropy of 1.2 or more and a viscosity of 400 Pa · s or less is provided with a thickness of half or more of the solder thickness. A short circuit between the first electrode and the second electrode due to spreading by wetting can be prevented. Further, it has been found that the variation in the solder thickness can be reduced by providing the polymer material with the electrical insulation property and the thixotropy of 1.2 or more and the viscosity of 400 Pa · s or less at the height of the solder thickness or less. As a result, it has been found that the connection of the power semiconductor element can be achieved in a single process, and the withstand voltage reliability is equal to or greater than that of a known connection method. Further, it has been found that variation in solder thickness can be reduced by providing a polymer material having a thixotropy of 1.2 or more and a viscosity of 400 Pa · s or less at a height of the solder thickness or less.

第一の電極が実装される配線と、第二の電極が実装される配線の間に設ける高分子材料のチクソ性が１.２より小さいとディスペンサーで塗布する際、前記高分子材料が電極面など意図しない部位まで広がってしまう可能性があり、前記高分子材料の粘度が４００Ｐａ・ｓより大きいとディスペンサーで塗布する際に流れにくく作業性が悪くなる。   When the thixotropy of the polymer material provided between the wiring on which the first electrode is mounted and the wiring on which the second electrode is mounted is smaller than 1.2, the polymer material is applied to the electrode surface when applied with a dispenser. If the viscosity of the polymer material is higher than 400 Pa · s, it is difficult to flow when applied with a dispenser, and workability is deteriorated.

ここで、チクソ性とは、２５℃におけるずり速度１（１／ｓ）の粘度を、２５℃におけるずり速度１０（１／ｓ）の粘度で割った値であり、粘度とは２５℃におけるずり速度１０（１／ｓ）の時の粘度である。   Here, the thixotropy is a value obtained by dividing the viscosity at a shear rate of 1 (1 / s) at 25 ° C. by the viscosity at a shear rate of 10 (1 / s) at 25 ° C., and the viscosity is a shear at 25 ° C. The viscosity at a speed of 10 (1 / s).

電気絶縁性を有する高分子材料は、２５℃の体積抵抗率が１×１０10Ω・cm以上の材料であることを指す。 The polymer material having electrical insulation indicates that the volume resistivity at 25 ° C. is 1 × 10 10 Ω · cm or more.

配線基板とは、金属ベースと絶縁層と配線からなるものであればよい。絶縁層は、厚さ１.０mm以下、好ましくは０.１mm以下の樹脂や無機物が添加された樹脂、又は厚さ１.０mm以下、好ましくは０.５mm以下のセラミクスであればよい。セラミクスとしては、Ａｌ2Ｏ3（酸化アルミニウム），Ｓｉ3Ｎ4（窒化珪素），ＡｌＮ（窒化アルミニウム），ＡｌＳｉＣ（アルミニウムシリコンカーバイト）などを用いることができる。 The wiring board only needs to be composed of a metal base, an insulating layer, and wiring. The insulating layer may be a resin with a thickness of 1.0 mm or less, preferably 0.1 mm or less or a resin to which an inorganic substance is added, or a ceramic with a thickness of 1.0 mm or less, preferably 0.5 mm or less. As ceramics, Al 2 O 3 (aluminum oxide), Si 3 N 4 (silicon nitride), AlN (aluminum nitride), AlSiC (aluminum silicon carbide), or the like can be used.

パワー半導体素子とは、交流を直流に変換したり、電圧を降圧するなどによりモータを駆動したり、バッテリを充電したり、マイコンやＬＳＩを動作させるなど、電源あるいは電力の制御や供給を行う半導体素子を指す。第一の電極，第二の電極，第三の電極とは、パワー半導体素子の動作の基準となる電圧、又は／且つ電流が与えられる部分のことであり、例えば電界効果型トランジスタ（ＭＯＳＦＥＴ）では、ゲート電極，ソース電極，ドレイン電極のことを指す。   A power semiconductor element is a semiconductor that controls or supplies power or power, such as driving a motor by converting AC to DC, reducing the voltage, charging a battery, or operating a microcomputer or LSI. Refers to an element. The first electrode, the second electrode, and the third electrode are portions to which a voltage or / and a current serving as a reference for the operation of the power semiconductor element are applied. For example, in a field effect transistor (MOSFET) , Gate electrode, source electrode, and drain electrode.

上記のパワー半導体装置として、配線基板が金属板に搭載され、少なくとも配線基板，パワー半導体素子が樹脂により封止されていることが好ましい。封止に用いる電気絶縁性樹脂としては、熱硬化性樹脂組成物であればよく、特に望ましくはエポキシ樹脂，硬化剤，硬化促進剤並びに無機質充填材を有する、エポキシ樹脂組成物が望ましい。エポキシ樹脂は、１分子中にエポキシ基を２個以上有するものであれば特に限定されない。硬化剤は、フェノール性水酸基，アミノ基，カルボキシ基，酸無水物基等エポキシ樹脂を硬化する官能基を有するものであれば特に限定されない。無機質充填材には、ＳｉＯ2（二酸化珪素），Ａｌ2Ｏ3（酸化アルミニウム），ＢＮ（窒化ホウ素），ＭｇＯＨ（水酸化マグネシウム）等が用いられ、粒子形状については、球，角，燐片状のどの形状でもよい。硬化促進剤は、エポキシ樹脂との場合には硬化反応を促進させるものならば種類は限定されない。 As said power semiconductor device, it is preferable that a wiring board is mounted in a metal plate and at least a wiring board and a power semiconductor element are sealed with resin. The electrically insulating resin used for sealing may be a thermosetting resin composition, and an epoxy resin composition having an epoxy resin, a curing agent, a curing accelerator and an inorganic filler is particularly desirable. The epoxy resin is not particularly limited as long as it has two or more epoxy groups in one molecule. The curing agent is not particularly limited as long as it has a functional group that cures the epoxy resin, such as a phenolic hydroxyl group, an amino group, a carboxy group, and an acid anhydride group. For the inorganic filler, SiO 2 (silicon dioxide), Al 2 O 3 (aluminum oxide), BN (boron nitride), MgOH (magnesium hydroxide), etc. are used. Any shape can be used. The type of the curing accelerator is not limited as long as it accelerates the curing reaction in the case of an epoxy resin.

上記のパワー半導体装置として、配線基板上に複数のパワー半導体素子が搭載し、複数のパワー半導体素子の電極間を導体平板により接続し、金属板と導体平板が露出するように樹脂封止した構成とする。また、はんだにより、配線と前記複数のパワー半導体素子、及び、前記パワー半導体素子と前記導体平板を接続することで、配線基板とパワー半導体素子の実装、パワー半導体素子同士の電気的接続を同一工程で行うことが可能となる。これにより、工程数の低減を図ることができる。   As the above power semiconductor device, a structure in which a plurality of power semiconductor elements are mounted on a wiring board, electrodes of the plurality of power semiconductor elements are connected by a conductive flat plate, and resin sealing is performed so that the metal plate and the conductive flat plate are exposed. And Also, by connecting the wiring and the plurality of power semiconductor elements, and the power semiconductor element and the conductor flat plate with solder, the mounting of the wiring substrate and the power semiconductor element and the electrical connection between the power semiconductor elements are performed in the same process. Can be performed. Thereby, reduction of the number of processes can be aimed at.

パワー半導体素子等の接続に用いるはんだは、融点が１３０℃以上４００℃以下であればよく、好ましくはＳｎ（錫）−Ｃｕ（銅）はんだ，Ｓｎ（錫）−Ａｇ（銀）−Ｃｕ（銅）はんだ、Ｓｎ（錫）−Ａｇ（銀）−Ｃｕ（銅）−Ｂｉ（ビスマス）はんだなどのＰｂ（鉛）フリーはんだがよい。   The solder used for the connection of the power semiconductor element or the like may have a melting point of 130 ° C. or higher and 400 ° C. or lower, preferably Sn (tin) -Cu (copper) solder, Sn (tin) -Ag (silver) -Cu (copper ) Solder, Pb (lead) -free solder such as Sn (tin) -Ag (silver) -Cu (copper) -Bi (bismuth) solder is preferable.

また、導体平板としては、前記導体平板が、銅，銅合金，アルミニウム，アルミニム合金，炭素繊維複合体のいずれか、または２種類以上の積層板を用いることができる。炭素繊維複合体は、炭素繊維と銅，炭素繊維と銅合金，炭素繊維とアルミ，炭素繊維とアルミ合金などから成るものがよい。また、炭素繊維と金属の複合体で繊維方向の熱伝導率が４００Ｗ／ｍＫ以上、好ましくは６００Ｗ／ｍＫ以上で、前記繊維と垂直方向に１０Ｗ／ｍＫ以上、好ましくは１００Ｗ／ｍＫ以上がよい。   As the conductor flat plate, the conductor flat plate may be copper, copper alloy, aluminum, aluminum alloy, carbon fiber composite, or two or more kinds of laminated plates. The carbon fiber composite is preferably composed of carbon fiber and copper, carbon fiber and copper alloy, carbon fiber and aluminum, carbon fiber and aluminum alloy, and the like. Further, the thermal conductivity in the fiber direction of the composite of carbon fiber and metal is 400 W / mK or more, preferably 600 W / mK or more, and 10 W / mK or more, preferably 100 W / mK or more in the direction perpendicular to the fiber.

上記のパワー半導体装置において、複数のパワー半導体素子同士を接続する導体平板のパワー半導体素子が実装された面と反対の面に、熱伝導率０.５Ｗ／ｍＫ以上であり電気絶縁性を有する高分子材料を設け、高分子材料を露出させた状態で封止樹脂することを特徴とする。導体平板に積層する高分子材料は、厚さ０.１mm以上１０mm以下で、縦弾性係数０.５ＭＰａ以上１.０ＧＰａ以下であることが好ましい。   In the power semiconductor device described above, the surface opposite to the surface on which the power semiconductor element of the conductive plate connecting the plurality of power semiconductor elements is mounted has a thermal conductivity of 0.5 W / mK or more and high electrical insulation. It is characterized by providing a molecular material and encapsulating resin in a state where the polymer material is exposed. The polymer material laminated on the conductor flat plate preferably has a thickness of 0.1 mm or more and 10 mm or less and a longitudinal elastic modulus of 0.5 MPa or more and 1.0 GPa or less.

このように、電気絶縁性と高熱伝導性を有する高分子材料が設けられた導体平板を用いて、パワー半導体素子同士を電気的に接続することにより、前記導体平板上に被った封止樹脂を機械的方法にて除去する場合に発生する衝撃，応力を低減し、パワー半導体素子の損傷を低減することができる。   Thus, by using a conductor flat plate provided with a polymer material having electrical insulation and high thermal conductivity, the power semiconductor elements are electrically connected to each other so that the sealing resin covered on the conductor flat plate is It is possible to reduce the impact and stress that occur when removing by a mechanical method, and to reduce the damage of the power semiconductor element.

また、パワー半導体素子同士を電気的に接続する導体平板上に積層された高分子材料は、厚さがはんだの厚さばらつきの最大値以上か、製造工程における取り扱い性の悪化を防止できる０.１mm以上の、どちらか大きい方とすることで、前記導体平板を露出させて、樹脂封止した場合でも、該導体平板上に樹脂が浸入することを防止できる効果を見出した。更に、前記パワー半導体素子同士を電気的に接続する導体平板上に積層された高分子材料の厚さが１０mm以下、好ましくは５.０mm以下で、且つ熱伝導率０.５Ｗ／ｍＫ以上とすることで、複数個の半導体素子を直列、または並列に接続し通電した場合でも、公知のアーチ形状の金属板を用いて接続したパワー半導体装置に通電した場合と同等、または同等以下の接合温度の上昇となり、パワー半導体装置が高放熱化されることを見出した。一方、前記導体平板に積層する高分子材料の縦弾性係数が０.５ＭＰａ以上とすることで、製造工程における取り扱い性が良くなることを見出した。また、前記縦弾性係数を１.０ＧＰａ以下とすることで、はんだが予測値より厚くなった場合でも、前記導体平板に積層した高分子材料が変形し、前記導体平板を露出させた状態で樹脂封止できることを見出した。   In addition, the polymer material laminated on the conductor flat plate that electrically connects the power semiconductor elements is equal to or greater than the maximum value of the solder thickness variation, or can prevent deterioration in handleability in the manufacturing process. It has been found that an effect of preventing the resin from entering the conductive flat plate even when the conductive flat plate is exposed and resin-sealed by using the larger one of 1 mm or more. Furthermore, the thickness of the polymer material laminated on the conductor flat plate for electrically connecting the power semiconductor elements is 10 mm or less, preferably 5.0 mm or less, and the thermal conductivity is 0.5 W / mK or more. Thus, even when a plurality of semiconductor elements are connected in series or in parallel and energized, the junction temperature is equal to or lower than that when a power semiconductor device connected using a known arch-shaped metal plate is energized. As a result, the power semiconductor device was found to increase heat dissipation. On the other hand, it has been found that when the longitudinal elastic modulus of the polymer material laminated on the conductor flat plate is 0.5 MPa or more, the handleability in the production process is improved. Further, by setting the longitudinal elastic modulus to 1.0 GPa or less, even when the solder becomes thicker than the predicted value, the polymer material laminated on the conductor flat plate is deformed and the resin flat plate is exposed. It discovered that it could seal.

また、導体平板より熱伝導率が低い電気絶縁層をパワー半導体装置の最も外側に配置することで、パワー半導体素子の発熱量を拡散し易い構造となり、パワー半導体素子の接合温度上昇を抑制できることを見出した。   In addition, by disposing an electrical insulating layer having a lower thermal conductivity than the conductive flat plate on the outermost side of the power semiconductor device, it becomes a structure in which the amount of heat generated by the power semiconductor element can be easily diffused, and an increase in the junction temperature of the power semiconductor element can be suppressed. I found it.

以上で説明したパワー半導体装置は、筒内直噴エンジン制御用パワー半導体装置，電動パワーステアリング用モータ制御向けパワー半導体装置，電動ブレーキ制御用パワー半導体装置等のパワー半導体装置、及びインバータ装置等に適用することができる。   The power semiconductor device described above is applied to a power semiconductor device for in-cylinder direct injection engine control, a power semiconductor device for motor control for electric power steering, a power semiconductor device for electric brake control, and an inverter device. can do.

以下に本発明を具体化した、第一の実施例を図面に従って説明する。図１は、本実施の形態におけるパワー半導体装置の一例を示したものである。   A first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an example of a power semiconductor device in the present embodiment.

第一のパワー半導体素子（パワーＭＯＳＦＥＴ）１は、第一の電極（ゲート電極）３と第二の電極（ソース電極）１３（図示せず）が設けられた面が上向きに、第三の電極（ドレイン電極）１４（図示せず）が設けられた面が下向きに、はんだ７（図示せず）を介して、配線基板の配線５上に実装されている。第二のパワー半導体素子（パワーＭＯＳＦＥＴ）２は、第三の電極（ドレイン電極）１４（図示せず）が設けられた面が上向きに、第一の電極（ゲート電極）３（図示せず）と第二の電極（ソース電極）１３（図示せず）が設けられた面が下向きに、はんだ７（図示せず）を介して、配線基板の配線５上に実装されている。２個のパワー半導体素子（パワーＭＯＳＦＥＴ）１および２の上面には、導体平板６が実装され、２個のパワー半導体素子（パワーＭＯＳＦＥＴ）１および２を電気的に直列接続している。前記パワー半導体素子（パワーＭＯＳＦＥＴ）１および２、導体平板６等の部材が実装された後、電気絶縁性の封止樹脂１０（図示せず）にて、全体が封止されている。   The first power semiconductor element (power MOSFET) 1 has a surface on which a first electrode (gate electrode) 3 and a second electrode (source electrode) 13 (not shown) are provided with the third electrode The surface on which the (drain electrode) 14 (not shown) is provided is mounted downward on the wiring 5 of the wiring board via the solder 7 (not shown). The second power semiconductor element (power MOSFET) 2 has a surface on which a third electrode (drain electrode) 14 (not shown) is provided facing upward, and a first electrode (gate electrode) 3 (not shown). The surface on which the second electrode (source electrode) 13 (not shown) is provided is mounted downward on the wiring 5 of the wiring board via the solder 7 (not shown). A conductive flat plate 6 is mounted on the upper surfaces of the two power semiconductor elements (power MOSFETs) 1 and 2, and the two power semiconductor elements (power MOSFETs) 1 and 2 are electrically connected in series. After the members such as the power semiconductor elements (power MOSFETs) 1 and 2 and the conductive flat plate 6 are mounted, the whole is sealed with an electrically insulating sealing resin 10 (not shown).

導体平板６のパワー半導体素子側の面には、はんだレジスト１６（図示せず）が印刷されている。また配線５上のパワー半導体素子（パワーＭＯＳＦＥＴ）１および２の実装位置の周囲にも、はんだレジスト１６（図示せず）が印刷されている。はんだレジスト１６により、はんだ溶融に伴う、導体平板６とパワー半導体素子（パワーＭＯＳＦＥＴ）１および２の位置ずれが抑制される。   A solder resist 16 (not shown) is printed on the surface of the conductor flat plate 6 on the power semiconductor element side. A solder resist 16 (not shown) is also printed around the mounting positions of the power semiconductor elements (power MOSFETs) 1 and 2 on the wiring 5. The solder resist 16 suppresses misalignment between the conductor flat plate 6 and the power semiconductor elements (power MOSFETs) 1 and 2 due to solder melting.

使用するフラックスが異なると、フラックスの気化温度などの条件が異なることに起因し、導体平板６とパワー半導体素子（パワーＭＯＳＦＥＴ）１および２の位置がずれる場合もある。位置ずれのため、ゲート電極３と導体平板６が短絡する危険性が懸念される場合は、前記の通り、はんだレジスト１６により、はんだ７が濡れ広がる領域を必要最小限とすることが良い。また、図２のごとく、導体平板６上の第一の電極（ゲート電極）３の近傍に切り欠きを設けてもよい。   If the flux to be used is different, the positions of the conductor flat plate 6 and the power semiconductor elements (power MOSFETs) 1 and 2 may be shifted due to different conditions such as the vaporization temperature of the flux. If there is a risk of short-circuit between the gate electrode 3 and the conductor flat plate 6 due to misalignment, it is preferable to minimize the area where the solder 7 is spread by the solder resist 16 as described above. Further, as shown in FIG. 2, a notch may be provided in the vicinity of the first electrode (gate electrode) 3 on the conductor flat plate 6.

図３は、図１のＡ−Ａ線に沿って断面にしたパワー半導体装置を示したものである。２個のパワー半導体素子（パワーＭＯＳＦＥＴ）１および２と配線５との間、２個のパワー半導体素子（パワーＭＯＳＦＥＴ）１および２と、導体平板６との間は、はんだ７で接続されている。また、外部入出力端子８と配線５との接続にも、はんだ７が用いられている。   FIG. 3 shows a power semiconductor device having a cross section taken along line AA of FIG. Between the two power semiconductor elements (power MOSFETs) 1 and 2 and the wiring 5, the two power semiconductor elements (power MOSFETs) 1 and 2 and the conductor flat plate 6 are connected by solder 7. . Also, the solder 7 is used for the connection between the external input / output terminal 8 and the wiring 5.

前記のごとく、パワー半導体装置内で使用するはんだ７が統一されていることにより、一工程のみで、全接続を達成できる。かかる結果、工程数の低減化が実現される。   As described above, since the solders 7 used in the power semiconductor device are unified, all connections can be achieved in one step. As a result, the number of processes can be reduced.

なお、第一の電極（ゲート電極）のはんだ接続面積は、第二の電極（ソース電極）や第三の電極（ドレイン電極）などのはんだ接続面積に比べて狭い。そのため、第一の電極（ゲート電極）に印刷、または供給されたはんだの溶融時間は、第二の電極（ソース電極）や第三の電極（ドレイン電極）に印刷、または供給されたはんだの溶融時間より短い。はんだ溶融時間を同等にしたい場合、第二の電極（ソース電極）や第三の電極（ドレイン電極）に図４のごとく、板状はんだを設置するか、又は模様をつけてペースト状はんだを印刷、または、ディスペンサーにより供給すればよい。なお、図４は模様の一例であり、模様を設ける意図を逸脱しないものであれば、図４に示した以外の模様でもよい。ただし、第二の電極（ソース電極）が複数のパッドに分割されている場合は、全てのパッドが電気的に接続される模様となることが好ましい。   Note that the solder connection area of the first electrode (gate electrode) is narrower than the solder connection area of the second electrode (source electrode), the third electrode (drain electrode), or the like. Therefore, the melting time of the solder printed or supplied to the first electrode (gate electrode) is the melting time of the solder printed or supplied to the second electrode (source electrode) or the third electrode (drain electrode). Shorter than time. If you want the solder melting time to be equal, place the plate-like solder on the second electrode (source electrode) or the third electrode (drain electrode) as shown in Fig. 4, or print the paste solder with a pattern. Or may be supplied by a dispenser. Note that FIG. 4 is an example of a pattern, and a pattern other than that shown in FIG. 4 may be used as long as it does not depart from the intention of providing the pattern. However, when the second electrode (source electrode) is divided into a plurality of pads, it is preferable that all the pads are electrically connected.

図５は、図１のＢ−Ｂ線に沿った断面のうち、パワー半導体素子（パワーＭＯＳＦＥＴ）２と配線５との接続部分の要部縦断面図である。本実施の形態で用いたパワー半導体装置の第二の電極（ソース電極）１３は複数に分割されている。   FIG. 5 is a longitudinal sectional view of an essential part of a connection portion between the power semiconductor element (power MOSFET) 2 and the wiring 5 in the cross section taken along the line BB in FIG. The second electrode (source electrode) 13 of the power semiconductor device used in the present embodiment is divided into a plurality of parts.

第一の電極（ゲート電極）３が実装される配線５ａと、第二の電極（ソース電極）１３が実装される配線５ｂには、はんだレジスト１６が設けられている。図５に示す縦断面部位においては、配線５ａと５ｂの間から、第二の電極（ソース電極）１３の分割された電極の一つである電極パッド１３ａの下面まで、はんだレジスト１６が印刷されている。かかる結果、はんだフィレットが配線５側から電極側へ広がる形状となり、前記第一の電極（ゲート電極）３と第二の電極（ソース電極）１３の短絡を防止できる効果がある。   A solder resist 16 is provided on the wiring 5 a on which the first electrode (gate electrode) 3 is mounted and the wiring 5 b on which the second electrode (source electrode) 13 is mounted. In the longitudinal section shown in FIG. 5, the solder resist 16 is printed from between the wirings 5 a and 5 b to the lower surface of the electrode pad 13 a that is one of the divided electrodes of the second electrode (source electrode) 13. ing. As a result, the solder fillet expands from the wiring 5 side to the electrode side, and there is an effect that the first electrode (gate electrode) 3 and the second electrode (source electrode) 13 can be prevented from being short-circuited.

図６に、本実施例で用いた配線基板６を示す。図６に示すごとく、配線５ａ，５ｂを曲線形状とすることにより、図５の断面部位では、はんだが濡れていない第二の電極（ソース電極）１３の電極パッド１３ａにも、はんだ７が濡れる構造になる。かかる結果、第一の電極（ゲート電極）３と第二の電極（ソース電極）１３の短絡を防止でき、且つ第二の電極（ソース電極）１３の全ての電極パッドに通電可能となる構造を見出した。   FIG. 6 shows the wiring board 6 used in this example. As shown in FIG. 6, by forming the wirings 5 a and 5 b in a curved shape, the solder 7 is also wetted on the electrode pad 13 a of the second electrode (source electrode) 13 where the solder is not wetted in the cross-sectional portion of FIG. 5. Become a structure. As a result, the first electrode (gate electrode) 3 and the second electrode (source electrode) 13 can be prevented from being short-circuited, and all electrode pads of the second electrode (source electrode) 13 can be energized. I found it.

本実施例のパワー半導体装置は、図７に示す手順にて作製した。まず、絶縁層９の一方の面に金属ベース９、他方の面に配線５が設けられた配線基板１２を準備する。配線基板１２の配線５の上に接続材料を供給する。次に、配線基板に搭載するパワー半導体素子１，２、その他の部品や外部入出力端子８を配線５の上に搭載する。次に、パワー半導体素子１，２の電極上に接続材料を供給する。この接続材料の上に導体平板６を搭載する。この状態で、加熱により、パワー半導体素子１，２と配線５及び導体平板６との接続，その他部品や外部入出力端子８と配線５との接続を一括で行う。一括接続の際、加熱のほかに加圧等を加えてもよい。接続後、洗浄により不要な接合材等を除去した後、装置全体を樹脂封止する。その後、めっき等の後工程を経て本実施例のパワー半導体装置を得た。   The power semiconductor device of this example was manufactured according to the procedure shown in FIG. First, a wiring substrate 12 having a metal base 9 on one surface of the insulating layer 9 and wiring 5 on the other surface is prepared. A connection material is supplied onto the wiring 5 of the wiring board 12. Next, the power semiconductor elements 1 and 2 to be mounted on the wiring board, other components, and the external input / output terminal 8 are mounted on the wiring 5. Next, a connection material is supplied onto the electrodes of the power semiconductor elements 1 and 2. A conductor flat plate 6 is mounted on this connecting material. In this state, the connection between the power semiconductor elements 1 and 2 and the wiring 5 and the conductor flat plate 6 and the connection between other components and the external input / output terminal 8 and the wiring 5 are performed by heating. In addition to heating, pressurization or the like may be applied during batch connection. After the connection, unnecessary bonding materials and the like are removed by washing, and then the entire apparatus is sealed with resin. Thereafter, a power semiconductor device of this example was obtained through a post-process such as plating.

本実施例では、２個のパワー半導体素子をそれぞれ上下逆向きに配線上に実装することで、前記２個のパワー半導体素子を直列に接続したが、図７に示す手順にて、２個のパワー半導体素子を上下同方向に配線上に実装することで、該２個の半導体素子を並列に接続することも可能である。   In the present embodiment, the two power semiconductor elements are connected in series by mounting the two power semiconductor elements on the wiring in the upside down direction, but in the procedure shown in FIG. It is also possible to connect the two semiconductor elements in parallel by mounting the power semiconductor elements on the wiring in the same vertical direction.

更に、本実施例では２個の半導体素子を１つの半導体装置として樹脂で封止したが、本実施例に限らず、２個の半導体装置の組み合わせを複数個纏めて、１つの半導体装置として樹脂封止してもよい。   Furthermore, in this embodiment, two semiconductor elements are sealed with resin as one semiconductor device. However, the present invention is not limited to this embodiment, and a plurality of combinations of two semiconductor devices are grouped together as one semiconductor device. It may be sealed.

以下に本発明を具体化した、第二の実施例を図面に従って説明する。図８は、本実施の形態におけるパワー半導体装置のパワー半導体素子（パワーＭＯＳＦＥＴ）２と配線５との接続部分の縦断面である。   A second embodiment of the present invention will be described below with reference to the drawings. FIG. 8 is a longitudinal section of a connection portion between the power semiconductor element (power MOSFET) 2 and the wiring 5 of the power semiconductor device according to the present embodiment.

本実施の形態では、パワー半導体素子（パワーＭＯＳＦＥＴ）２の片面に第一の電極（ゲート電極）３と第二の電極（ソース電極）１３が設けられた面が実装される配線基板上の配線５において、前記パワー半導体素子（パワーＭＯＳＦＥＴ）２の第一の電極（ゲート電極）３が実装される配線５ａと、前記パワー半導体素子（パワーＭＯＳＦＥＴ）２の第二の電極（ソース電極）１３が実装される配線５ｂの間に、電気絶縁性で且つチクソ性１.２以上，粘度４００Ｐａ・ｓ以下の高分子材料１５が、はんだ７の厚さの半分以上、はんだ７の厚さ以下の高さに設けられている。   In the present embodiment, the wiring on the wiring board on which the surface provided with the first electrode (gate electrode) 3 and the second electrode (source electrode) 13 is mounted on one surface of the power semiconductor element (power MOSFET) 2. 5, the wiring 5a on which the first electrode (gate electrode) 3 of the power semiconductor element (power MOSFET) 2 is mounted and the second electrode (source electrode) 13 of the power semiconductor element (power MOSFET) 2 are Between the wirings 5b to be mounted, the polymer material 15 that is electrically insulative and has a thixotropy of 1.2 or more and a viscosity of 400 Pa · s or less is not less than half the thickness of the solder 7 and not more than the thickness of the solder 7. Is provided.

以上のごとく、電気絶縁性で且つチクソ性１.２以上，粘度４００Ｐａ・ｓ以下の高分子材料１５を、配線５ａと５ｂの間に塗布しておくことで、前記配線５ａと５ｂの間に壁が形成させる。かかる結果、はんだによる電極間の短絡を防止できる。なお、前記電気絶縁性で且つチクソ性１.２以上，粘度４００Ｐａ・ｓ以下の高分子材料を塗布した後、加熱や吸湿など所定の硬化条件で、硬化させておく必要がある。   As described above, by applying the polymer material 15 that is electrically insulating and thixotropic 1.2 or more and having a viscosity of 400 Pa · s or less between the wirings 5a and 5b, between the wirings 5a and 5b. A wall is formed. As a result, a short circuit between the electrodes due to solder can be prevented. In addition, it is necessary to harden under the predetermined curing conditions such as heating and moisture absorption after applying the polymer material having electrical insulation and thixotropy of 1.2 or more and viscosity of 400 Pa · s or less.

また、電気絶縁性で且つチクソ性１.２以上，粘度４００Ｐａ・ｓ以下の高分子材料１５を、はんだ７の厚さ以下の高さに設けることで、前記はんだ７厚さのばらつきが低減できることを見出した。   Moreover, by providing the polymer material 15 that is electrically insulating and thixotropic 1.2 or more and having a viscosity of 400 Pa · s or less at a height equal to or less than the thickness of the solder 7, variation in the thickness of the solder 7 can be reduced. I found.

図９に第二の実施の形態における配線基板１２の上面図を示す。図９に示すごとく、前記電気絶縁性で、且つチクソ性１.２以上，粘度４００Ｐａ・ｓ以下の高分子材料１５を塗布する位置は、前記第一の電極（ゲート電極）と第二の電極（ソース電極）の間であればよく、望ましくは、配線５ａと５ｂの間全面である。   FIG. 9 shows a top view of the wiring board 12 in the second embodiment. As shown in FIG. 9, the first electrode (gate electrode) and the second electrode are disposed at the position where the polymer material 15 having electrical insulation, thixotropy 1.2 or more and viscosity 400 Pa · s or less is applied. It may be between (source electrodes), and preferably the entire surface between the wirings 5a and 5b.

以下に本発明を具体化した、第三の実施例を図面に従って説明する。図１０は、本実施の形態におけるパワー半導体装置の要部縦断面図である。   A third embodiment of the present invention will be described below with reference to the drawings. FIG. 10 is a longitudinal sectional view of a main part of the power semiconductor device according to the present embodiment.

本実施例では、２個のパワー半導体素子（パワーＭＯＳＦＥＴ）１および２と、該パワー半導体素子（パワーＭＯＳＦＥＴ）同士を電気的に接続する、電気絶縁性と高熱伝導性を有する高分子材料３１が積層された導体平板６、及び前記パワー半導体素子（パワーＭＯＳＦＥＴ）が実装される配線基板１２とを有するパワー半導体装置において、電気絶縁性と高熱伝導性を有する高分子材料３１が積層された導体平板６が、パワー半導体装置を封止している電気絶縁性の封止樹脂１０の表面に露出している。   In the present embodiment, two power semiconductor elements (power MOSFETs) 1 and 2 and a polymer material 31 having electrical insulation and high thermal conductivity, which electrically connect the power semiconductor elements (power MOSFETs) to each other, are provided. In a power semiconductor device having a laminated conductive flat plate 6 and a wiring substrate 12 on which the power semiconductor element (power MOSFET) is mounted, a conductive flat plate in which a polymer material 31 having electrical insulation and high thermal conductivity is laminated. 6 is exposed on the surface of the electrically insulating sealing resin 10 sealing the power semiconductor device.

電気絶縁性と高熱伝導性を有する高分子材料３１として、厚さ０.５mm，熱伝導率が２Ｗ／ｍＫ，体積抵抗率１×１０12Ω・cmの高分子材料が用いられている。また導体平板６として厚さ０.５mmの銅板が用いられている。 As the polymer material 31 having electrical insulation and high thermal conductivity, a polymer material having a thickness of 0.5 mm, a thermal conductivity of 2 W / mK, and a volume resistivity of 1 × 10 12 Ω · cm is used. A copper plate having a thickness of 0.5 mm is used as the conductor flat plate 6.

図１０において、各はんだ７の厚さは０.１mmを想定して作製された。しかし、実測のはんだ厚さは、０.１±０.０８mmであった。そのため、前記導体平板６の下、つまり配線基板１２側には、はんだ７が２層あるため、前記導体平板６上の高さ方向の誤差は０.１６mmであった。   In FIG. 10, the thickness of each solder 7 was assumed to be 0.1 mm. However, the measured solder thickness was 0.1 ± 0.08 mm. Therefore, since there are two layers of solder 7 below the conductor flat plate 6, that is, on the wiring board 12 side, the height error on the conductor flat plate 6 was 0.16 mm.

本実施例のごとく、パワー半導体装置の厚さに誤差がある状態でも、前記導体平板６上に積層された高分子材料３１が封止用金型によって圧縮され、金型と前記高分子材料３１の間に、封止樹脂１０が進入可能な間隔がなくなる。かかく結果、前記導体平板上に封止樹脂が進入せず、パワー半導体装置を小型化，薄型化，高放熱化できる効果を見出した。   As in this embodiment, even when there is an error in the thickness of the power semiconductor device, the polymer material 31 laminated on the conductor flat plate 6 is compressed by the sealing mold, and the mold and the polymer material 31 are compressed. In the meantime, there is no interval at which the sealing resin 10 can enter. As a result, it has been found that the sealing resin does not enter the conductor flat plate, and that the power semiconductor device can be reduced in size, thickness, and heat dissipation.

なお、図１０に示した断面は、本実施の形態の一例であり、樹脂封止用金型外した後、前記電気絶縁性と高熱伝導性を有する高分子材料３１が、封止樹脂１０の表面より盛り上がっていてもよい。   The cross section shown in FIG. 10 is an example of the present embodiment, and after removing the resin sealing mold, the polymer material 31 having the electrical insulation and high thermal conductivity is formed of the sealing resin 10. It may be raised from the surface.

また、導体平板としては銅のほか、銅合金，アルミニウム，アルミニウム合金，炭素複合材料を用いてもよいが、配線基板，封止樹脂との熱膨張差等で、封止樹脂が各部材からはく離しないように、前記導体平板の熱膨張係数，メッキ等を調整する必要がある。   In addition to copper, copper alloy, aluminum, aluminum alloy, and carbon composite material may be used as the conductor flat plate. However, the sealing resin is peeled off from each member due to the difference in thermal expansion from the wiring board and sealing resin. Therefore, it is necessary to adjust the coefficient of thermal expansion, plating, etc. of the conductor flat plate.

一方、前記導体平板に積層する高分子材料は、製造工程における取り扱い性の悪化を防止できる０.１mm以上か、はんだ厚さのばらつき値以上の、どちらか大きな値以上であればよい。また、前記導体平板に積層する高分子材料の熱抵抗が、封止樹脂より大きくなると、放熱性が低下するため、１０mm以下、好ましくは５.０mm以下で熱伝導率０.５ Ｗ／ｍＫ以上であればよい。更に、縦弾性係数は、製造工程における取り扱い性の悪化を防止できる０.５ＭＰａ以上であればよく、樹脂封止時に金型で圧縮されることで、前記導体平板上に封止樹脂が進入する空間を除去するため、封止樹脂の縦弾性係数より小さく、好ましくは１.０ＧＰａ以下であればよい。   On the other hand, the polymer material to be laminated on the conductor flat plate may be 0.1 mm or more that can prevent deterioration in handleability in the manufacturing process, or a larger value than the variation value of the solder thickness. Further, if the thermal resistance of the polymer material laminated on the conductor flat plate becomes larger than that of the sealing resin, the heat dissipation is reduced. Therefore, the thermal conductivity is 0.5 W / mK or more at 10 mm or less, preferably 5.0 mm or less. If it is. Furthermore, the longitudinal elastic modulus may be 0.5 MPa or more that can prevent deterioration in handleability in the manufacturing process, and the sealing resin enters the conductor flat plate by being compressed with a mold during resin sealing. In order to remove the space, it may be smaller than the longitudinal elastic modulus of the sealing resin, preferably 1.0 GPa or less.

以下に本発明を具体化した、第四の実施例を図面に従って説明する。図１１は、本実施の形態におけるパワー半導体装置の一例の上面図を示したものである。   Hereinafter, a fourth embodiment of the present invention will be described with reference to the drawings. FIG. 11 shows a top view of an example of the power semiconductor device according to the present embodiment.

図１１において、第一のパワー半導体素子（パワーＭＯＳＦＥＴ）１は、第一の電極（ゲート電極）３と第二の電極（ソース電極）１３（図示せず）が設けられた面が上向きに、第三の電極（ドレイン電極）１４（図示せず）が設けられた面が下向きに、はんだ７（図示せず）を介して配線５上に実装されている。第二のパワー半導体素子（パワーＭＯＳＦＥＴ）２は、第三の電極（ドレイン電極）１４（図示せず）が設けられた面が上向きに、第一の電極（ゲート電極）３と第二の電極（ソース電極）１３が設けられた面が下向きに、はんだ７（図示せず）を介して配線５上に実装されている。第三のパワー半導体素子（パワーＭＯＳＦＥＴ）１９（図示せず）と第五のパワー半導体素子（パワーＭＯＳＦＥＴ）２１（図示せず）は、第一のパワー半導体素子（パワーＭＯＳＦＥＴ）１と同じ向きに配線５に実装されている。また第四のパワー半導体素子（パワーＭＯＳＦＥＴ）２０（図示せず）と第六のパワー半導体素子（パワーＭＯＳＦＥＴ）２２（図示せず）は、第二のパワー半導体素子（パワーＭＯＳＦＥＴ）２と同じ向きに配線５に実装され、電気絶縁性の封止樹脂１０（図示せず）にて、全体が封止されている。前記パワー半導体素子（パワーＭＯＳＦＥＴ）１および２の上面、パワー半導体素子（パワーＭＯＳＦＥＴ）１９および２０の上面、パワー半導体素子（パワーＭＯＳＦＥＴ）２１および２２の上面にはそれぞれ、電気絶縁性と高熱伝導性を有する高分子材料３１が積層された導体平板６が実装され、該２個のパワー半導体素子（パワーＭＯＳＦＥＴ）を電気的に直列接続している。また前記パワー半導体素子（パワーＭＯＳＦＥＴ）１と３と５、および前記パワー半導体素子（パワーＭＯＳＦＥＴ）２と４と６はそれぞれ、並列に接続されている。   In FIG. 11, the first power semiconductor element (power MOSFET) 1 has a surface on which a first electrode (gate electrode) 3 and a second electrode (source electrode) 13 (not shown) are provided facing upward. The surface on which the third electrode (drain electrode) 14 (not shown) is provided is mounted on the wiring 5 via the solder 7 (not shown) in a downward direction. The second power semiconductor element (power MOSFET) 2 has a surface on which a third electrode (drain electrode) 14 (not shown) is provided facing upward, the first electrode (gate electrode) 3 and the second electrode. The surface on which the (source electrode) 13 is provided is mounted on the wiring 5 via the solder 7 (not shown) in a downward direction. The third power semiconductor element (power MOSFET) 19 (not shown) and the fifth power semiconductor element (power MOSFET) 21 (not shown) are oriented in the same direction as the first power semiconductor element (power MOSFET) 1. It is mounted on the wiring 5. The fourth power semiconductor element (power MOSFET) 20 (not shown) and the sixth power semiconductor element (power MOSFET) 22 (not shown) are oriented in the same direction as the second power semiconductor element (power MOSFET) 2. The whole is mounted on the wiring 5 and is sealed with an electrically insulating sealing resin 10 (not shown). The upper surfaces of the power semiconductor elements (power MOSFETs) 1 and 2, the upper surfaces of the power semiconductor elements (power MOSFETs) 19 and 20, and the upper surfaces of the power semiconductor elements (power MOSFETs) 21 and 22 are electrically insulative and highly thermally conductive, respectively. The conductive flat plate 6 on which the polymer material 31 having the above is stacked is mounted, and the two power semiconductor elements (power MOSFETs) are electrically connected in series. The power semiconductor elements (power MOSFETs) 1, 3 and 5 and the power semiconductor elements (power MOSFETs) 2, 4 and 6 are connected in parallel.

前記パワー半導体装置から外部へ、第一の電極（ゲート電極）３に接続されている信号端子２３が、導体平板６に接続させている出力端子２４，２５，２６が、また配線５に接続させている主電流の入出力端子８が出ている。   From the power semiconductor device to the outside, signal terminals 23 connected to the first electrode (gate electrode) 3 are connected to the output terminals 24, 25, 26 connected to the conductor flat plate 6 and also to the wiring 5. The main current input / output terminal 8 is output.

図１２に、図１１のＣ−Ｃ線に沿って断面にしたパワー半導体装置の斜視図を示す。本実施の形態に示したように、６個のパワー半導体素子（パワーＭＯＳＦＥＴ）を１個のパワー半導体装置として電気絶縁性の樹脂１０で封止することで、複数個のパワー半導体素子を用いるパワー半導体装置を用いた小型化，薄型化，高放熱化できることを見出した。   FIG. 12 is a perspective view of the power semiconductor device taken along a line CC in FIG. As shown in the present embodiment, six power semiconductor elements (power MOSFETs) are sealed with an electrically insulating resin 10 as one power semiconductor device, thereby using a plurality of power semiconductor elements. We found that semiconductor devices can be made smaller, thinner, and higher heat dissipation.

本実施の形態におけるパワー半導体装置をモータ制御に用いた際の等価回路を図１３に示す。図１３において、点線で囲った部分が本実施の形態におけるパワー半導体装置である。前記パワー半導体素子（パワーＭＯＳＦＥＴ）１と２を接続する導体平板６から伸びた端子２４、前記パワー半導体素子（パワーＭＯＳＦＥＴ）１９と２０を接続する導体平板６から伸びた端子２５、前記パワー半導体素子（パワーＭＯＳＦＥＴ）２１と２２を接続する導体平板６から伸びた端子２６にそれぞれ、Ｕ相シャント抵抗２７，Ｖ相シャント抵抗２８，Ｗ相シャント抵抗２９が接続され、モータ３０に接続されている。   FIG. 13 shows an equivalent circuit when the power semiconductor device according to the present embodiment is used for motor control. In FIG. 13, the portion surrounded by a dotted line is the power semiconductor device in the present embodiment. A terminal 24 extending from the conductor flat plate 6 connecting the power semiconductor elements (power MOSFETs) 1 and 2; a terminal 25 extending from the conductor flat plate 6 connecting the power semiconductor elements (power MOSFETs) 19 and 20; (Power MOSFET) A U-phase shunt resistor 27, a V-phase shunt resistor 28, and a W-phase shunt resistor 29 are connected to a terminal 26 extending from the conductor flat plate 6 connecting the power resistors 21 and 22, and connected to the motor 30.

本実施例の形態は、図１３の点線で示すように、パワー半導体素子（パワーＭＯＳＦＥＴ）６個を１個の半導体装置としたが、実施例１などで示すようにパワー半導体素子（パワーＭＯＳＦＥＴ）２個を１つのパワー半導体装置とし、該パワー半導体装置を３個用いて、モータ制御に用いてもいい。   In the present embodiment, six power semiconductor elements (power MOSFETs) are formed as one semiconductor device as shown by the dotted line in FIG. 13, but as shown in the first embodiment, the power semiconductor elements (power MOSFET) are used. Two power semiconductor devices may be used, and three power semiconductor devices may be used for motor control.

以下に本発明を具体化した、第五の実施例を図面に従って用いて説明する。図１４は、本実施の形態におねるパワー半導体装置の要部縦断面図である。   Hereinafter, a fifth embodiment of the present invention will be described with reference to the drawings. FIG. 14 is a longitudinal sectional view of a main part of the power semiconductor device according to the present embodiment.

通電によりパワー半導体素子（パワーＭＯＳＦＥＴ）１および２から生じた熱量は、金属ベース１８方向に伝導されるほか、該パワー半導体素子（パワーＭＯＳＦＥＴ）１と２を電気的に接続している、電気絶縁性と高熱伝導性を有する高分子材料３１が積層された導体平板６を介して、放熱フィン１７に熱が伝導され、周囲へ伝達，放射される。   The amount of heat generated from the power semiconductor elements (power MOSFETs) 1 and 2 by energization is conducted in the direction of the metal base 18 and also electrically connects the power semiconductor elements (power MOSFETs) 1 and 2. Heat is conducted to the heat radiating fins 17 through the conductor flat plate 6 on which the polymer material 31 having high heat conductivity and heat conductivity is laminated, and is transmitted and radiated to the surroundings.

本実施の形態に示したとおり、パワー半導体装置を前記放熱フィン１７に固定することにより、前記導体平板６に積層された電気絶縁性と高熱伝導性を有する高分子材料３１が圧縮される。かかる結果、パワー半導体装置と前記放熱フィン１７の間の接触熱抵抗が低減され、従来必要とされた放熱グリスや熱伝導性接着剤、放熱シートなど放熱部材を用いずに放熱できることを見出した。   As shown in the present embodiment, by fixing the power semiconductor device to the heat radiating fins 17, the polymer material 31 having electrical insulation and high thermal conductivity laminated on the conductor flat plate 6 is compressed. As a result, it has been found that the contact thermal resistance between the power semiconductor device and the heat radiating fins 17 is reduced, and heat can be radiated without using heat radiating members such as heat radiating grease, a heat conductive adhesive, and a heat radiating sheet that have been conventionally required.

本実施例では、放熱フィンとして銅からなる直線フィンを用いたが、円柱や円錐，多角錐などの突起フィンを用いてもよい。また材質は銅のほか、銅合金，アルミ，アルミ合金，銅とアルミからなる合金でもよい。   In this embodiment, a straight fin made of copper is used as the heat radiating fin, but a protruding fin such as a cylinder, a cone, or a polygonal pyramid may be used. The material may be copper, copper alloy, aluminum, aluminum alloy, or an alloy made of copper and aluminum.

また、同じ電流，電圧を負荷した場合でも、パワー半導体素子の種類や、近接する発熱体との距離等の環境条件の違いにより、パワー半導体素子の温度は異なる。パワー半導体装置の中で発熱量にばらつきが出る場合、特に放熱が必要な場所には、ヒートパイプを内蔵した放熱フィンを用いることもできる。前記ヒートパイプが内蔵された放熱フィンを用いる形態では、発熱量が高い場所の熱がヒートパイプを介して発熱量の少ない場所に熱を伝導され、前記放熱フィンを介して伝達される。   Even when the same current and voltage are applied, the temperature of the power semiconductor element varies depending on the type of the power semiconductor element and the environmental conditions such as the distance from the adjacent heating element. When the amount of heat generated varies among the power semiconductor devices, a heat radiating fin with a built-in heat pipe can be used particularly in a place where heat radiation is required. In the embodiment using the heat radiating fin in which the heat pipe is built, heat in a place where the heat generation amount is high is conducted to the place where the heat generation amount is small via the heat pipe, and is transmitted through the heat radiating fin.

以下に本発明を具体化した、第六の実施例を図面に従って説明する。図１５は、本実施の形態におけるパワー半導体装置の一例を示したものである。   The sixth embodiment of the present invention will be described below with reference to the drawings. FIG. 15 shows an example of a power semiconductor device in the present embodiment.

第一のパワー半導体素子（パワーＭＯＳＦＥＴ）１は、第一の電極（ゲート電極）３と第二の電極（ソース電極）１３（図示せず）が設けられた面が上向きに、第三の電極（ドレイン電極）１４（図示せず）が設けられた面が下向きに、はんだ７（図示せず）を介して配線５上に実装されている。第二のパワー半導体素子（パワーＭＯＳＦＥＴ）２は、第三の電極（ドレイン電極）１４（図示せず）が設けられた面が上向きに、第一の電極（ゲート電極）３（図示せず）と第二の電極（ソース電極）１３（図示せず）が設けられた面が下向きに、はんだ７（図示せず）を介して配線５上に実装されている。前記２個のパワー半導体素子（パワーＭＯＳＦＥＴ）１および２を電気的に接続するため、前記上面に、はんだ７（図示せず）を介してリード３２が実装されている。   The first power semiconductor element (power MOSFET) 1 has a surface on which a first electrode (gate electrode) 3 and a second electrode (source electrode) 13 (not shown) are provided with the third electrode The surface on which the (drain electrode) 14 (not shown) is provided is mounted on the wiring 5 via the solder 7 (not shown) in a downward direction. The second power semiconductor element (power MOSFET) 2 has a surface on which a third electrode (drain electrode) 14 (not shown) is provided facing upward, and a first electrode (gate electrode) 3 (not shown). The surface on which the second electrode (source electrode) 13 (not shown) is provided is mounted on the wiring 5 via the solder 7 (not shown). In order to electrically connect the two power semiconductor elements (power MOSFETs) 1 and 2, leads 32 are mounted on the upper surface via solder 7 (not shown).

パワー半導体素子（パワーＭＯＳＦＥＴ）の実装、はんだ７の供給，リフロー，洗浄，電気絶縁性樹脂１０（図示せず）による全体封止、樹脂の後硬化の工程後、図１６に示すごとく、リード３２の不要部分は切断し、メッキ等の後工程を経て、パワー半導体装置となる。   After mounting the power semiconductor element (power MOSFET), supplying the solder 7, reflowing, cleaning, sealing with the electrically insulating resin 10 (not shown), and post-curing of the resin, as shown in FIG. The unnecessary portion is cut, and after a subsequent process such as plating, a power semiconductor device is obtained.

なお、２個のパワー半導体素子（パワーＭＯＳＦＥＴ）を接続する部位から伸びた端子は、外部に接続してもいい。   In addition, you may connect the terminal extended from the site | part which connects two power semiconductor elements (power MOSFET) outside.

本実施の形態においては、前記リード３２として銅を用いた。該リード３２を用いることで接続部材７が溶融した場合でも、外部出力端子、パワー半導体素子（パワーＭＯＳＦＥＴ）同士を接続する導体等が枠と一体となっているため位置ずれしない。また、配線基板１２に設けられた固定用の穴１１に、リード３２の位置合わせ用端子３２ａを合わせることで、配線基板１２とリード３２の位置が決まる。かかる結果、各部材の位置ずれが極めて小さい構造となることを見出した。更に、リード部３２を用いることにより、配線基板１２に実装する部品点数を削減できるため、製造工程の低減化が実現できる。   In the present embodiment, copper is used as the lead 32. Even when the connecting member 7 is melted by using the leads 32, the external output terminal, the conductor connecting the power semiconductor elements (power MOSFETs) and the like are integrated with the frame, so that the position does not shift. The positions of the wiring board 12 and the leads 32 are determined by aligning the positioning terminals 32 a of the leads 32 with the fixing holes 11 provided in the wiring board 12. As a result, it has been found that the position shift of each member is extremely small. Furthermore, since the number of components to be mounted on the wiring board 12 can be reduced by using the lead part 32, the manufacturing process can be reduced.

リード３２のパワー半導体素子（パワーＭＯＳＦＥＴ）を接続する部分から伸びた端子３２ｃは他の部分に接続してもいい。   The terminal 32c extending from the portion where the power semiconductor element (power MOSFET) of the lead 32 is connected may be connected to another portion.

図１６は、図１５のＤ−Ｄ線に沿った断面を示している。外部入出力部３２ｂは、リード３２の一部であるため、前記外部入出力部３２ｂと配線５の間は、パワー半導体素子（パワーＭＯＳＦＥＴ）と配線５の間隔、パワー半導体素子（パワーＭＯＳＦＥＴ）とリード３２の間隔より厚くなるため、前記外部入出力部３２ｂと配線５の間にスペーサを設けるなどして、前記外部入出力部３２ｂと配線５を接続するはんだ７の体積を低減してもよい。   FIG. 16 shows a cross section taken along the line DD of FIG. Since the external input / output unit 32b is a part of the lead 32, the space between the external input / output unit 32b and the wiring 5 is a distance between the power semiconductor element (power MOSFET) and the wiring 5, and the power semiconductor element (power MOSFET). Since it is thicker than the distance between the leads 32, the volume of the solder 7 connecting the external input / output unit 32 b and the wiring 5 may be reduced by providing a spacer between the external input / output unit 32 b and the wiring 5. .

本発明は、前記の実施例に限定されるものではなく、特許請求の範囲に記載された本発明の精神を逸脱しない範囲で、種々の設計変更を行うことができるものである。   The present invention is not limited to the embodiments described above, and various design changes can be made without departing from the spirit of the present invention described in the claims.

第一の実施の形態におけるパワー半導体装置の一例。An example of the power semiconductor device in 1st embodiment. 切り欠きのある導体平板を用いた、第一の実施の形態におけるパワー半導体装置の一例。An example of the power semiconductor device in 1st embodiment using the conductor flat plate with a notch. 図１のＡ−Ａ線に沿った縦断面図。The longitudinal cross-sectional view along the AA line of FIG. はんだ印刷または供給模様の一例。An example of solder printing or supply pattern. 図１のＢ−Ｂ線に沿った縦断面図のうち、パワー半導体素子（パワーＭＯＳＦＥＴ）２と配線５との接続部分の要部縦断面拡大図。The principal part longitudinal cross-sectional enlarged view of the connection part of the power semiconductor element (power MOSFET) 2 and the wiring 5 among the longitudinal cross-sectional views along the BB line of FIG. 第一の実施の形態における配線基板１２の上面図。The top view of the wiring board 12 in 1st embodiment. 第一の実施の形態におけるパワー半導体装置の組立手順。The assembly procedure of the power semiconductor device in 1st embodiment. 第二の実施の形態におけるパワー半導体素子（パワーＭＯＳＦＥＴ）２と配線５との接続部分の要部縦断面拡大図である。It is a principal part longitudinal cross-sectional enlarged view of the connection part of the power semiconductor element (power MOSFET) 2 and wiring 5 in 2nd embodiment. 第二の実施の形態における配線基板１２の上面図。The top view of the wiring board 12 in 2nd embodiment. 第三の実施の形態におけるパワー半導体装置の要部縦断面図。The principal part longitudinal cross-sectional view of the power semiconductor device in 3rd embodiment. 第四の実施の形態におけるパワー半導体装置の一例の上面図。The top view of an example of the power semiconductor device in 4th Embodiment. 図１１のＣ−Ｃ線に沿って断面にしたパワー半導体装置の斜視図。The perspective view of the power semiconductor device made into the cross section along CC line of FIG. 第四の実施の形態におけるパワー半導体装置をモータ制御に用いた際の等価回路。The equivalent circuit at the time of using the power semiconductor device in 4th Embodiment for motor control. 第五の実施の形態におねるパワー半導体装置の要部縦断面図。The principal part longitudinal cross-sectional view of the power semiconductor device concerning 5th embodiment. 第六の実施の形態におけるパワー半導体装置の一例の上面図。The top view of an example of the power semiconductor device in 6th Embodiment. 図１５のＤ−Ｄ線に沿った縦断面図の要部縦断面図。The principal part longitudinal cross-sectional view of the longitudinal cross-sectional view along the DD line of FIG.

符号の説明Explanation of symbols

１ 第一のパワー半導体素子（パワーＭＯＳＦＥＴ）
２ 第二のパワー半導体素子（パワーＭＯＳＦＥＴ）
３ 第一の電極（デート電極）
４ アルミワイヤ
５ 配線
５ａ 第一の電極（デート電極）３が実装される配線
５ｂ 第二の電極（ソース電極）１３が実装される配線
６ 電気絶縁性と高熱伝導性を具備する高分子材料が積層された導体平板
７ はんだ
８ 外部入出力端子
９ 絶縁層
１０ 封止樹脂
１１ 締結用ボルト穴
１２ 配線基板
１３ 第二の電極（ソース電極）
１４ 第三の電極（ドレイン電極）
１５ 高チクソ性高分子材料
１６ はんだレジスト
１７ 放熱フィン
１８ 金属ベース
１９ 第三のパワー半導体素子（パワーＭＯＳＦＥＴ）
２０ 第四のパワー半導体素子（パワーＭＯＳＦＥＴ）
２１ 第五のパワー半導体素子（パワーＭＯＳＦＥＴ）
２２ 第六のパワー半導体素子（パワーＭＯＳＦＥＴ）
２３ 第一の電極（デート電極）に接続された信号端子
２４ 第一のパワー半導体素子（パワーＭＯＳＦＥＴ）と第二のパワー半導体素子（パワーＭＯＳＦＥＴ）を接続する導体平板６から伸びる出力端子
２５ 第三のパワー半導体素子（パワーＭＯＳＦＥＴ）と第四のパワー半導体素子（パワーＭＯＳＦＥＴ）を接続する導体平板６から伸びる出力端子
２６ 第五のパワー半導体素子（パワーＭＯＳＦＥＴ）と第六のパワー半導体素子（パワーＭＯＳＦＥＴ）を接続する導体平板６から伸びる出力端子
２７ Ｕ相シャント抵抗
２８ Ｖ相シャント抵抗
２９ Ｗ相シャント抵抗
３０ モータ
３１ 電気絶縁性と高熱伝導性を有する高分子材料
３２ リード
３２ａ リード３２の位置合わせ用端子
３２ｂ リード３２の外部入出力部
３２ｃ リード３２のパワー半導体素子（パワーＭＯＳＦＥＴ）を接続する部分から伸びた端子 1 First power semiconductor element (power MOSFET)
2 Second power semiconductor device (power MOSFET)
3 First electrode (date electrode)
4 Aluminum wire 5 Wiring 5a Wiring 5b on which the first electrode (date electrode) 3 is mounted Wiring 5 on which the second electrode (source electrode) 13 is mounted 6 A polymer material having electrical insulation and high thermal conductivity Laminated conductor flat plate 7 Solder 8 External input / output terminal 9 Insulating layer 10 Sealing resin 11 Fastening bolt hole 12 Wiring board 13 Second electrode (source electrode)
14 Third electrode (drain electrode)
15 High thixotropic polymer material 16 Solder resist 17 Radiation fin 18 Metal base 19 Third power semiconductor element (power MOSFET)
20 Fourth power semiconductor element (power MOSFET)
21 Fifth power semiconductor element (power MOSFET)
22 Sixth power semiconductor device (power MOSFET)
23 A signal terminal 24 connected to the first electrode (date electrode) 24 An output terminal 25 extending from the conductor plate 6 connecting the first power semiconductor element (power MOSFET) and the second power semiconductor element (power MOSFET) Output terminal 26 extending from the conductive plate 6 connecting the power semiconductor element (power MOSFET) and the fourth power semiconductor element (power MOSFET) to the fifth power semiconductor element (power MOSFET) and the sixth power semiconductor element (power MOSFET) Output terminal 27 extending from the conductor flat plate 6 to which is connected) U-phase shunt resistor 28 V-phase shunt resistor 29 W-phase shunt resistor 30 Motor 31 Polymer material 32 having electrical insulation and high thermal conductivity 32 Lead 32a For alignment of lead 32 Terminal 32b External input / output part 32c of lead 32 Power half of lead 32 A terminal extending from a portion where a conductive element (power MOSFET) is connected

Claims (12)

一つの面に第一の電極と第二の電極が設けられたパワー半導体素子が配線基板に実装されたパワー半導体装置において、
前記配線基板の、前記パワー半導体素子の第一の電極が実装される配線と、前記パワー半導体素子の第二の電極が実装される配線との間に、電気絶縁性で且つチクソ性１.２以上，粘度４００Ｐａ・ｓ以下の高分子材料が設けられ、
前記高分子材料の厚さが前記配線の厚さよりも厚いことを特徴とするパワー半導体装置。 In one power semiconductor device in which the power semiconductor element is mounted on a wiring substrate on which the first electrode and the second electrode is provided on the surface of,
Between the wiring on which the first electrode of the power semiconductor element is mounted and the wiring on which the second electrode of the power semiconductor element is mounted on the wiring board, 1.2 is electrically insulating and thixotropic. As described above, a polymer material having a viscosity of 400 Pa · s or less is provided,
A power semiconductor device, wherein the polymer material is thicker than the wiring. 請求項１に記載のパワー半導体装置において、
前記高分子材料の高さが、前記パワー半導体素子と前記配線とを接続するはんだの厚さの半分以上、はんだ厚さ以下であることを特徴とするパワー半導体装置。 The power semiconductor device according to claim 1,
A power semiconductor device characterized in that a height of the polymer material is not less than half of a thickness of solder connecting the power semiconductor element and the wiring and not more than a solder thickness. 請求項１に記載のパワー半導体装置において、
前記配線基板が金属板に搭載され、少なくとも前記配線基板、前記パワー半導体素子が樹脂により封止されていることを特徴とするパワー半導体装置。 The power semiconductor device according to claim 1,
A power semiconductor device, wherein the wiring board is mounted on a metal plate, and at least the wiring board and the power semiconductor element are sealed with resin. 請求項３に記載のパワー半導体装置において、
前記配線基板上に複数のパワー半導体素子が搭載され、
前記複数のパワー半導体素子の電極間が導体平板により接続され、
前記金属板と導体平板が露出するように樹脂封止されていることを特徴とするパワー半導体装置。 The power semiconductor device according to claim 3,
A plurality of power semiconductor elements are mounted on the wiring board,
The electrodes of the plurality of power semiconductor elements are connected by a conductive flat plate,
A power semiconductor device, wherein the metal plate and the conductor flat plate are resin-sealed so as to be exposed. 請求項４に記載のパワー半導体装置において、
はんだにより、前記配線と前記複数のパワー半導体素子、及び、前記パワー半導体素子と前記導体平板が接続されていることを特徴とするパワー半導体装置。 The power semiconductor device according to claim 4,
The power semiconductor device, wherein the wiring and the plurality of power semiconductor elements, and the power semiconductor element and the conductor flat plate are connected by solder. 請求項４に記載のパワー半導体装置において、
前記導体平板のパワー半導体素子が実装された面と反対の面に、熱伝導率０.５Ｗ／ｍＫ以上であり電気絶縁性を有する高分子材料が設けられていることを特徴とするパワー半導体装置。 The power semiconductor device according to claim 4,
A power semiconductor device characterized in that a polymer material having a thermal conductivity of 0.5 W / mK or more and an electrical insulating property is provided on a surface opposite to the surface on which the power semiconductor element of the conductive plate is mounted. . 請求項６に記載のパワー半導体装置において、
前記導体平板に設けられた高分子材料は、厚さ０.１mm以上１０mm以下で、縦弾性係数０.５ＭＰａ以上１.０ＧＰａ以下であることを特徴とするパワー半導体装置。 The power semiconductor device according to claim 6,
The power semiconductor device, wherein the polymer material provided on the conductor flat plate has a thickness of 0.1 mm or more and 10 mm or less and a longitudinal elastic modulus of 0.5 MPa or more and 1.0 GPa or less. 請求項４に記載のパワー半導体装置において、
前記導体平板が、銅，銅合金，アルミニウム，アルミニウム合金，炭素繊維複合体のいずれか、または２種類以上の積層板であることを特徴とするパワー半導体装置。 The power semiconductor device according to claim 4,
The power semiconductor device, wherein the conductor flat plate is one of copper, copper alloy, aluminum, aluminum alloy, carbon fiber composite, or two or more kinds of laminated plates. 請求項６に記載のパワー半導体装置において、
前記導体平板に設けられた高分子材料上に放熱板が搭載されていることを特徴とするパワー半導体装置。 The power semiconductor device according to claim 6,
A power semiconductor device, wherein a heat sink is mounted on a polymer material provided on the conductor flat plate. 絶縁基板の一方の面に配線が形成され、他方の面に金属板を有する配線基板と、
一方の面にゲート電極とソース電極、他方の面にドレイン電極を有し、前記ドレイン電極がはんだにより前記配線と接続された第１のパワー半導体素子と、
一方の面にゲート電極とソース電極、他方の面にドレイン電極を有し、前記ゲート電極とソース電極がはんだにより前記配線と接続された第２のパワー半導体素子と、
前記第１のパワー半導体素子のソース電極と、前記第２のパワー半導体素子のドレイン電極とを電気的に接続するための導体平板と、
前記配線基板と電気的に接続された外部接続用端子と、
前記配線基板、第１，第２のパワー半導体素子，導体平板、及び、外部接続用端子を封止する封止樹脂とを備え、
前記配線基板の、前記第２のパワー半導体素子のゲート電極と接続された配線と、前記第２のパワー半導体素子のソース電極と接続された配線との間に、電気絶縁性で且つチクソ性１.２以上，粘度４００Ｐａ・ｓ以下の高分子材料が設けられ、前記高分子材料の厚さが前記配線の厚さよりも厚く、
前記金属板と前記導体平板の表面が、前記封止樹脂の表面に露出していることを特徴とするパワー半導体装置。 A wiring board having wiring formed on one surface of the insulating substrate and a metal plate on the other surface;
A first power semiconductor element having a gate electrode and a source electrode on one side and a drain electrode on the other side, wherein the drain electrode is connected to the wiring by solder;
A second power semiconductor element having a gate electrode and a source electrode on one surface and a drain electrode on the other surface, wherein the gate electrode and the source electrode are connected to the wiring by solder;
A conductive plate for electrically connecting the source electrode of the first power semiconductor element and the drain electrode of the second power semiconductor element;
An external connection terminal electrically connected to the wiring board;
The wiring board, the first and second power semiconductor elements, the conductor flat plate, and a sealing resin for sealing the external connection terminal,
Between the wiring connected to the gate electrode of the second power semiconductor element of the wiring board and the wiring connected to the source electrode of the second power semiconductor element, an electrically insulating and thixotropic 1 .2 or more and a viscosity of 400 Pa · s or less is provided, and the thickness of the polymer material is larger than the thickness of the wiring,
The power semiconductor device, wherein the surfaces of the metal plate and the conductive flat plate are exposed on the surface of the sealing resin. 請求項１０に記載のパワー半導体装置において、
前記導体平板のパワー半導体素子と接続された面と反対の面に、熱伝導率０.５Ｗ／ｍＫ以上であり電気絶縁性を有する高分子材料が設けられていることを特徴とするパワー半導体装置。 The power semiconductor device according to claim 10,
A power semiconductor device characterized in that a polymer material having a thermal conductivity of 0.5 W / mK or more and an electrical insulation property is provided on a surface opposite to the surface connected to the power semiconductor element of the conductive plate. . 請求項１０に記載のパワー半導体装置において、
前記導体平板の前記第１のパワー半導体素子のゲート電極と隣接する箇所に切り欠け部が設けられていることを特徴とするパワー半導体装置。 The power semiconductor device according to claim 10,
A power semiconductor device, wherein a notch is provided at a location adjacent to the gate electrode of the first power semiconductor element of the conductive flat plate.
JP2007252967A 2007-09-28 2007-09-28 Power semiconductor device Expired - Fee Related JP4961314B2 (en)

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