JP5141005B2 - Semiconductor memory - Google Patents

Description

  The present invention relates to a semiconductor memory such as a flash memory, and more particularly to a semiconductor memory suitable for use in making a memory having a double capacity by using a plurality of, particularly two, memories.

For the past several years, non-volatile flash memory has been increasingly used in portable electronic devices such as digital cameras, portable audio and mobile phones. In addition, with the advancement of functions, there is an increasing demand for an increase in memory capacity (size that can be stored), and it is not uncommon for the capacity to be doubled using two memory chips.
By doing so, for example, in the case of a NOR flash memory, a new development may be omitted when a double 32 MB is required for a NOR flash memory having a memory capacity of about 16 MB (megabytes). It becomes possible. As for a large-capacity NOR flash memory having a memory capacity of 256 MB, a 512-MB NOR flash memory having a double memory capacity can be prepared without changing the system.
As described above, when a large capacity is realized by using two flash memory chips, if one chip enable signal is controlled for two chips, there is a concern about an access delay or a command timing shift. Therefore, it is general to individually control each chip enable terminal (pad) of a plurality of chips.

  FIG. 5 shows a memory card system using two flash memory chips. FIG. 6 shows a memory card system using a plurality of chips. In FIG. 5, reference numerals 51-1 and 51-2 denote memory chips, and reference numeral 52 denotes a memory controller that controls these memory chips. Each memory chip 51-1, 51-2 is provided with chip enable terminals CE 1, CE 2, and each chip enable terminal CE 1, CE 2 is connected to the memory controller 52 via individual wiring. FIG. 7 is a block diagram showing a configuration of an input address control unit which is a main part of the memory chips 51-1 and 51-2, where CEB is a chip enable terminal, A <m>, A <m−. 1>,... Are address terminals to which memory addresses are supplied, and 54, 55, 55 are input buffers. Here, when receiving the chip enable signal CEINa from the input buffer 54, the input buffer 55 becomes active and inputs the addresses of the memory address terminals A <m>, A <m−1>.

  However, if the chip enable terminals of the two chips are individually controlled as described above, it is naturally necessary for the user to control the controller on the assumption that two chips are used. Therefore, in order to save such trouble, it is ideal to control the two chip enable terminals with a single chip enable signal and an address signal for chip selection. FIG. 8 is a block diagram showing a memory card system when two memory chips are controlled by a single chip enable signal. FIG. 9 shows an example in which three or more memory chips are controlled. In FIG. 8, reference numerals 57-1 and 57-2 denote memory chips configured similarly to the memory chip shown in FIG. However, the memory chips 57-1 and 57-2 are provided with a chip selection address terminal AD, which is different from that shown in FIG. A memory controller 58 outputs a single chip enable signal and a chip selection address to each of the memory chips 57-1 and 57-2.

  FIG. 10 is a block diagram showing the configuration of the main parts of the memory chips 57-1 and 57-2. In this figure, CEB is a chip enable terminal, AD is a terminal to which the above-described chip selection address is supplied, and A <m >, A <m−1>,... Are address terminals to which memory addresses are supplied, and 54, 55, 55 and 56 are input buffers. Here, the input buffer 56 outputs the chip enable signal CEINb2 to the input buffers 55 and 55 when the chip selection address matches the address of its own chip set inside.

By the way, if it is attempted to control the chip enable for two memory chips with a single signal as described above, problems of access delay and command timing shift occur as described below.
That is, regarding the access delay, when a chip enable signal is prepared for each chip (FIG. 5 or FIG. 6), after the chip enable signal of the selected chip becomes valid, the enable signal CEINa in the chip is established. Access is started (FIG. 7). On the other hand, when the chip enable is controlled by one (FIG. 8 or FIG. 9), the chip is selected by the address signal CEINb2 (FIG. 10), but the access to the selected chip is started by the input buffer 54 ( After the chip enable signal CEINb output from FIG. 10) becomes effective and the address for determining the chip selection is determined, the enable signal CEINb2 in the chip is established and access is started. Therefore, as compared with the case where a chip enable signal is output for each of a plurality of chips, as shown in FIG. 11, an extra access time is required for the time Δt for determining an address for determining chip selection. .

Further, regarding the command timing shift (see FIG. 12), similarly, it is necessary to care for the input timing of the write enable signal WEB by the delay of the chip enable signal CEINb2 in the chip. In addition, there is a risk of command input to the non-selected chip. There is no restriction on the change of the address as long as the setup time and hold time of the address specified in the specifications are satisfied when the command is input. However, when the chip enable signal is controlled by one, the selected chip is chipped. Since it is determined by the selected address, if the address is changed carelessly, the selection of the chip changes, and there is a possibility that the command may be established even for the non-selected chip (see FIG. 13). For the above reasons, conventionally, a chip enable signal has been individually output for each memory chip.
JP 2004-110849 A

The present invention has been made in consideration of the above circumstances, and its purpose is to control one chip enable signal even when two are connected, that is, in the same way as when only one chip exists in the user. It is another object of the present invention to provide a semiconductor memory that can perform the above-described problems of access delay and command timing shift.
Another object of the present invention is to provide a semiconductor memory in which the number of control signals is reduced and the problem of access delay does not occur when a plurality of chips are controlled.

The present invention has been made to solve the above-described problems, and the invention according to claim 1 can perform data writing / reading of a memory array provided therein based on a command supplied from an external circuit. In the semiconductor memory to be executed, a command control means for receiving a command supplied from the external circuit and outputting a command control signal corresponding to the command, and an active state according to a selection signal supplied from the external circuit, and the selection A first input buffer unit that receives a chip selection address supplied from an external circuit and outputs a chip selection signal when in an active state according to a signal; an address set therein; and the chip selection address; matches, if both that match, the state of the chip select signal, the provided memory array is selected A data matching unit to indicate a condition, when the chip selection signal indicating a state in which the provided memory array is selected is not outputted, for a command control signal corresponding to the command is output comprising a gate means for outputting a control signal for inhibiting to the front SL command control means, wherein the data matching unit is a semiconductor memory which is characterized in that provided in the first input buffer portion.

According to a second aspect of the present invention, in the above-mentioned invention , when the memory array is activated, a signal supplied from an external circuit is activated in response to the selection signal and in an active state in response to the selection signal. And a second input buffer unit that outputs an internal signal for controlling the processing .

According to a third aspect of the present invention, in the above-mentioned invention , an output buffer unit is further provided which receives an output instruction signal and becomes active, and outputs data read as information stored in the memory array to a data terminal. And when the second input buffer unit is in an active state in response to the selection signal, the memory array address based on an address supplied from an external circuit is a part of the internal signal. The output instruction signal based on an output instruction supplied from an external circuit is output as a part of the internal signal when the address buffer unit is output in the active state according to the selection signal. And an output terminal activation signal buffer unit .

According to a fourth aspect of the present invention, in the above invention , the first input buffer unit is a signal supplied from an external circuit, and determines whether to set the multi-chip usage mode or the single-chip usage mode. When it is determined to set to the multiple chip use mode by a multiple / single use selection signal, the output chip selection signal is a signal indicating a state in which the provided memory array is selected. It is characterized by that.

The invention according to claim 5 comprises a plurality of chips each having the semiconductor memory of the invention as a chip, and the plurality of chips each have the plurality / single use selection signal set to the plurality chip use mode, The semiconductor memory is characterized in that an address set in a chip is set to be different for each chip .

  According to the present invention, even when two are used, it is possible to control with one chip enable signal without causing a problem of a shift in access timing or command timing. This has the advantage that the user can control under the same conditions as when only one chip is present.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a main part of a semiconductor memory (flash memory) according to an embodiment of the present invention, and FIG. 2 is a block diagram showing write and erase operations of the semiconductor memory. In FIG. 2, 1 is an interface circuit to which commands, data, and addresses are input from an external circuit, and 2 is a command user interface (hereinafter referred to as CUI) for decoding the commands input to the interface circuit 1. A control circuit 3 controls writing, reading, and erasing of the memory array 4. Reference numeral 5 denotes a power supply circuit that supplies DC power to each unit. Further, a high voltage (+) is generated during writing to the memory array 4, a medium voltage (+) is generated during reading, and a negative voltage (−) is generated during erasing, and is output to the memory array 4.

  A decoder 6 receives a control signal output from the control circuit 3 and an address from the interface circuit 1 and outputs a signal designating a write / read mode to the memory array 4. In addition, an address and data are output to the memory array 4 at the time of writing and an address is output to the memory array 4 at the time of reading to select a designated memory cell. Further, the data read from the memory array 4 is output to the control circuit 3 via the sense amplifier 8. As shown in the figure, the memory array 4 has storage blocks BLK0 to BLK15 and redundant blocks BRD0 and BRD1. Here, the storage blocks BLK0 to BLK15 are original storage areas, and the redundant blocks BRD0 and BRD1 are storage areas used instead when any of the storage blocks BLK0 to BLK15 becomes defective. The BRD information storage memory 9 is a memory in which data relating to the use state of redundant blocks and other control data are stored.

  In FIG. 1, CEB is a terminal (pad) to which a chip enable signal is applied from an external memory controller, WEB is a terminal to which a write enable signal is applied, and A <m> to A <0> are write / read addresses. A terminal to be added, AD is a terminal to which a chip selection address is added, OEB is a terminal to which an output enable signal is added, D <n> to D <0> are added with write data, and are read from the memory array 4 This is a data terminal to output the data.

  The input buffer 11 outputs a chip enable signal applied to the terminal CEB as a chip enable signal CEIN. The input buffer 12 becomes active upon receiving the chip enable signal CEIN, and outputs a write enable signal applied to the terminal WEB as the write enable signal WEIN. When the chip enable signal CEIN is not input, a cut-off state is established. The input buffers 13-m to 13-0 are activated upon receiving the chip enable signal CEIN, and output addresses obtained at the terminals A <m> to A <0> to the memory array 4. The input buffer 14 becomes active upon receiving the chip enable signal CEIN, and outputs the chip enable signal CEIN2 when the chip selection address applied to the terminal AD matches the address of its own chip set inside. The plural / single unit specification selection signal ROMEN for designating whether the number of chips used is plural or single unit is a signal generated inside the chip. Here, when plural chips are used, the plural / single unit selection signal ROMEN is used. In the case of = H and a single chip, explanation will be made assuming that plural / single specification selection signal ROMEN = L. The setting of the multiple / single specification selection signal ROMEN signal can be freely changed by the user by using a flash ROM in which setting information is written in a dedicated flash memory cell, as will be described later with reference to FIG. It becomes possible to do.

The input buffer 15 becomes active upon receiving the chip enable signal CEIN2, and outputs the output enable signal obtained at the terminal OEB as the output enable signal OEIN. The input buffers 16-n to 16-0 become active upon receiving the chip enable signal CEIN, and output data obtained at the terminals D <n> to D <0> to the memory array 4. The output buffers 17-n to 17-0 receive the output enable signal OEIN output from the input buffer 15 and become active, read out data read from the memory array 4 and output through the sense amplifier 8 to the terminals. Output to D <n> to D <0>.
Each terminal and input / output buffer described above are provided in the interface circuit 1 of FIG.

  The command decoder 21 (FIG. 1) decodes the write command output from the CUI • 2 and outputs a write signal WS. When the write enable signal WEIN is output from the input buffer 12, the latch 22 reads the chip enable signal CEIN 2 and outputs it to the AND gate 23. When the output of the latch 22 is “0”, the AND gate 23 outputs the signal WS to the CUI 2 as the reset signal RST. As a result, CUI.2 is reset in the final command cycle, and the output of the write signal WS to the memory array 4 is prohibited. On the other hand, when the output of the latch 22 is “1”, the AND gate 23 does not output the reset signal RST, and the write signal WS is output to the memory array 4.

Next, the operation of the above-described semiconductor memory will be described. As shown in FIG. 8, it is assumed that two semiconductor memories described above are connected to the memory controller to form a memory circuit having a double capacity.
(1) Data read In the case of data read, the chip enable signal from the memory controller to the terminal CEB, the chip selection address to the terminal AD, the read address to the terminals A <m> to A <0>, and the output enable signal to the terminal Added to OEB. When the chip enable signal is applied to the terminal CEB, the chip enable signal CEIN is output from the input buffer 11 and supplied to the input buffers 13-m to 13-0. As a result, the input buffers 13-m to 13-0 become active, and the read address applied to the terminals A <m> to A <0> is added to the memory array 4. That is, the read operation is performed in both chips regardless of the selected and non-selected chips. As described above, data is read from the memory array 4 and supplied to the input terminals of the output buffers 17-n to 17-0.

On the other hand, when the chip selection address is supplied to the terminal AD, the input buffer 14 collates the address of its own chip set inside with the address applied to the terminal AD. If they do not match, the chip enable signal CEIN2 is not output. In this case, the input buffer 15 is not active, and therefore the output buffers 17-n to 17-1 are not active and data is output from the data terminals D <n> to D <0>. Absent.
On the other hand, the input buffer 14 compares the address of its own chip set inside with the address applied to the terminal AD, and if they match, the chip enable signal CEIN2 is output. When the chip enable signal CEIN2 is output, the input buffer 15 becomes active and outputs the output enable signal OEIN. As a result, the output buffers 17-n to 17-1 are activated, and data read from the memory array 4 is output from the data terminals D <n> to D <0>. That is, it is determined by AD whether or not the data read by both chips is finally output to the outside.

(2) Data Write In the case of data write, the chip enable signal is to the terminal CEB, the chip selection address is to the terminal AD, the write address is to the terminals A <m> to A <0>, and the write data is to the data terminal D <n>. A write enable signal is applied to the terminal WEB to .about.D <0>.
When the chip selection address is added to the terminal AD, the input buffer 14 collates the address of the own chip set inside and the address added to the terminal AD. If they do not match, the chip enable signal CEIN2 is not output (“0” signal is output). If they match, the chip enable signal CEIN2 (“1” signal) is output.

  When the chip enable signal is applied to the terminal CEB, the chip enable signal CEIN is output from the input buffer 11 and supplied to the input buffer 12, the input buffers 13-m to 13-0, and the input buffers 16-n to 16-0. Is done. When the chip enable signal CEIN is supplied to the input buffers 13-m to 13-0, the input buffers 13-m to 13-0 become active, and the read applied to the terminals A <m> to A <0>. An address is applied to the memory array 4. Also, the input buffers 16-n to 16-0 become active, and write data applied to the terminals D <n> to D <0> is added to the memory array 4 via the buffers 16-n to 16-0. It is done.

  When the chip enable signal CEIN is supplied to the input buffer 12, the input buffer 12 becomes active, and the write enable signal supplied to the terminal WEB is supplied to the CUI.2 and the latch 22 as the write enable signal WEIN. The When the write enable signal WEIN is supplied to CUI · 2, CUI · 2 outputs a write command to the command decoder 21, and the write signal WS is output from the command decoder 21 to the AND gate 23. When the write enable signal WEIN is supplied to the latch 22, the chip enable signal CEIN output from the input buffer 14 at this time is read into the latch 22 and supplied to the AND gate 23.

If the chip selection address supplied to the terminal AD does not match the address set in the input buffer 14, a “0” signal is output as the chip enable signal CEIN and read into the latch 22. As a result, the AND gate 23 is opened, and the signal WS output from the command decoder 21 is returned to the CUI 2 as the reset signal RST via the AND gate 23. As a result, CUI.2 is reset in the final command cycle, and the output of the write signal WS to the memory array 4 is prohibited. On the other hand, if the chip selection address supplied to the terminal AD matches the address set in the input buffer 14, a “1” signal is output as the chip enable signal CEIN and read into the latch 22. As a result, the latch 22 is closed, the reset signal RST is not output from the AND gate 23, and the write signal WS is output to the memory array 4.
When the write signal WS is output to the memory array 4, the data output from the input buffers 16-n to 16-0 to the memory array 4 is specified by the addresses output from the input buffers 13-m to 13-0. To the storage location of the memory array 4.

  Here, the data collating means (comparing circuit) for outputting the chip selection signal of the input buffer 14 will be described in detail. FIG. 3 shows an example in which a system is composed of two chips. ROMCS is a chip selection signal and is set in the chip. For the setting, for example, a flash ROM described later with reference to FIG. 14 is used. The plural / single specification selection signal ROMEN is a signal for setting whether to use a plurality of chips or a single chip. Here, since two chips are used, the plural / single specification selection signal ROMEN = H is used. The number is set as multiple. 61-1 is a comparison circuit that receives a chip selection signal ROMCS for setting chip selection and an external address AD and performs exclusive OR to determine whether a chip is selected. And a plural / single unit specification selection signal ROMEN indicating a plurality of chip modes, and outputs an internal chip selection signal CEIN2-1 as an output. The basic configuration of the comparison circuit 61-1 and the coincidence circuit 62-1 constitutes an input buffer 63-1 for generating the chip selection signal CEIN2-1. 64-1 indicates the first memory chip, and 64-2 indicates the second memory chip. A flash ROM as shown in FIG. 14 for setting the chip selection signal ROMCS or the plural / single specification selection signal ROMEN is built in this chip. The chip is the other memory chip, and the circuit configuration is the same as that of the chip. In the case of the two-chip configuration, the chip is set to the chip selection signal ROMCS = L, and the chip is set to the chip selection signal ROMCS = H.

  FIG. 4 shows an example using four chips. To select four chips, two chip selection signals ROMCS are required. To select a chip, chip selection signal ROMCS1 = L, chip selection signal ROMCS2 = L, and to select a chip, chip selection. The signal ROMCS1 = L, the chip selection signal ROMCS2 = H,... Are set. Also, two selection addresses, AD1 and AD2, are required. Chip selection is determined by the exclusive OR circuit 71-1 and 72-1 and the AND circuit 73-1. 74-1 is an AND circuit for determining the state of the ROM. As in FIG. 3, the internal selection signal CEIN2-1 for selecting a chip is generated by 71-1, 72-1, 73-1, and 74-1. The chip 76-2 to the chip 76-4 have the same configuration.

  The operation of the flash ROM for setting the plural / single unit specification selection signal ROMEN signal or the chip selection signal ROMCS1 and the chip selection signal ROMCS2 will be described with reference to FIG. The flash memory cell 81 is a cell for storing setting information and is equivalent to the cell of the flash memory. A selection signal WL is connected to the gate, and 5 V (volts) is applied during reading and 10 V is applied during writing. The transistor 82 is an N-type transistor having a threshold value of approximately zero volts, and a bias voltage BIAS is input to a gate. This is for the purpose of setting so that a high voltage is not applied to the drain of the memory cell at the time of reading due to a problem in reliability, and the BIAS voltage is set to about 1V. The transistor 83 is a P-type transistor serving as a load for the memory cell 81, the transistor 84 is turned on when setting data is read from the memory cell, and is turned off when not selected, and 85 is a value for reading data from the memory cell. A latch circuit 86 for latching is a write circuit for writing setting information to the memory cell. As a power source for the writing circuit 86, a high voltage for writing generated in the chip is supplied.

Next, the operation of this flash ROM will be described. In the initial state, the memory cell 81 is in the erased state, and the threshold value is as low as about 3V. At this time, in the setting data read mode, the selection voltage 5V is applied to the gate signal WL of the memory cell and the threshold value is 3V. Therefore, the memory cell 81 is turned on, and the sense and latch circuit 85 has the “L” level. Is input and the output ROM becomes “L” at the same time that “L” is latched. Here, when setting data is changed, an operation of writing information to the memory cell 81 is performed. At the time of writing, a high voltage of 10V is applied to the gate WL of the memory cell 81, and about 5V is applied to the drain via the write circuit 86. In this state, an excessive current flows through the memory cell 81, electrons are injected into the floating gate of the memory cell by the hot electron effect, and the threshold value becomes as high as 6V. This completes the write operation. Next, in order to read out the written data, when 5 V is applied to WL in the read mode, the threshold value of the memory cell is 6 V, so that the memory cell 81 is turned off and the latch circuit 85 has “H”. The data is latched and the output ROM becomes “H”. In this way, the setting of the plural / unit specification selection signal ROMEN is determined within the chip. Although the erasing circuit is not shown in FIG. 14, if the setting data is to be changed several times, the setting data can be changed by adding the erasing circuit as in the flash memory.
Further, the chip selection signal ROMCS1, the chip selection signal ROMCS2, and the like are also configured by the same circuit as that in FIG.

  The above is the details of the embodiment shown in FIGS. In this embodiment, as a countermeasure against an access delay which has been a problem in the past, since an extra access is required for the time required for determining an address for selecting a chip, two chips are used as one chip enable regardless of the chip selection. Let it be accessed. As a result, the access operation is performed on both chips. In the case of data reading, only the selection of whether to output or not is determined by the chip selection address that determines the chip selection, thereby preventing an access delay. This countermeasure eliminates the command timing shift described with reference to FIG. Similarly, regarding the risk of establishment of command input to the non-selected chip, similarly, the command is intentionally established for the non-selected chip and, as described in the write operation, the non-selected chip at the last command cycle A command is reset to establish a command only for the selected chip.

The present invention is not limited to two chips and can be used by using a plurality of chips. However, a read operation is performed on all chips regardless of selection or non-selection. Therefore, since the read current increases in proportion to the number of chips, this is a problem.
However, since the chip enable signal is not required for each increase in the number of chips, there is an advantage of reducing the wiring on the printed circuit board.

  The present invention is used for a nonvolatile memory such as a flash memory.

It is a block diagram which shows the structure of the principal part of the semiconductor memory by one Embodiment of this invention. It is a block diagram which shows the structure of the same semiconductor memory. FIG. 2 is a detailed configuration diagram of an input buffer that outputs CEIN2 when using two chips in the block diagram shown in FIG. FIG. 2 is a detailed configuration diagram of an input buffer that outputs CEIN2 when 3 chips or 4 chips are used in the block diagram shown in FIG. It is a block diagram which shows the structural example of the memory system using two conventional semiconductor memories. It is a block diagram which shows the structural example of the memory system using two or more conventional semiconductor memories. FIG. 6 is a block diagram illustrating a partial configuration of a command input unit of the semiconductor memory illustrated in FIG. 5. It is a block diagram which shows the other structural example of the memory system using two semiconductor memories. It is a block diagram which shows the other structural example of the memory system using two or more semiconductor memories. It is a block diagram which shows a partial structure of the command input part of the semiconductor memory shown in FIG. FIG. 11 is a timing chart for explaining problems of the semiconductor memory shown in FIGS. 8 and 10. FIG. FIG. 11 is a timing chart for explaining problems of the semiconductor memory shown in FIGS. 8 and 10. FIG. FIG. 11 is a timing chart for explaining problems of the semiconductor memory shown in FIGS. 8 and 10. FIG. In the block diagram shown in FIG. 1, the circuit configuration of the flash ROM for setting the signal ROMEN or the chip selection setting signal ROMCS shown in FIGS. 3 to 4 is shown.

Explanation of symbols

1 ... Interface circuit 2 ... CUI
DESCRIPTION OF SYMBOLS 3 ... Control circuit 4 ... Memory array 6 ... Decoder 8 ... Sense amplifier 9 ... BRD information storage memory 11, 12, 13-m-13-0, 14, 15, 16-n-16-0 ... Input buffer 17-n ... 17-0 ... Output buffer 21 ... Command decoder 22 ... Latch 23 ... AND gates CEB, WEB, A <m> to A <0>, AD, OEB, D <n> to D <0>.

Claims (5)

In a semiconductor memory that performs data writing / reading of a memory array provided inside based on a command supplied from an external circuit,
Command control means for receiving a command supplied from the external circuit and outputting a command control signal corresponding to the command;
A first input buffer that is in an active state in response to a selection signal supplied from an external circuit and receives a chip selection address supplied from the external circuit and outputs a chip selection signal when in an active state in response to the selection signal And
The address set therein, collates the said chip select address, if both that match, the state of the chip select signals, to indicate the state of the provided by which the memory array is selected and data collation means to,
When the chip select signal indicating a state in which the provided memory array is selected is not output, before Symbol command control means a control signal for prohibiting the command control signal corresponding to the command is output Gating means for outputting to ,
Comprising
The data collating means includes
A semiconductor memory provided in the first input buffer section . A second input buffer unit that is in an active state in response to the selection signal and outputs a signal supplied from an external circuit as an internal signal for controlling processing on the memory array when the active signal is in response to the selection signal The semiconductor memory according to claim 1, comprising: An output buffer unit that receives an output instruction signal and is in an active state, and outputs data read as information stored in the memory array to a data terminal;
The second input buffer unit includes:
An address buffer unit that outputs an address of the memory array based on an address supplied from an external circuit as a part of the internal signal when in an active state according to the selection signal;
An output terminal activation signal buffer unit that outputs the output instruction signal based on an output instruction supplied from an external circuit as a part of the internal signal when in an active state according to the selection signal; ,
The semiconductor memory according to claim 2, comprising: The first input buffer unit includes:
A signal supplied from an external circuit, is defined to be set to the plurality of chips used modes by multiple / single use selection signal or shall be determined to be set to either a single chip using mode is set to a plurality of chips using modes If you are a semiconductor memory according to any one of claims 1 to 3, characterized in that a chip select signal to the output, the provided memory array is a signal indicating the state of being selected . A plurality of chips each including the semiconductor memory according to claim 4 as a chip.
Comprising
The plurality of chips are:
The multiple / single use selection signal is set to the multiple chip use mode,
An address set in the chip is set so that each chip has a different address .

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