JP2009043110A - Semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To dispense with special signal wiring and control for write protection by an external system. <P>SOLUTION: This semiconductor storage device has: a memory part storing data, having a write protect terminal, and forbidding writing of data when a control signal to the write protect terminal becomes active; and a memory controller controlling access to the memory part. The memory part is accessed from the outside through the memory controller. The memory controller generates and outputs the control signal to the write protect terminal of the memory part. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device including a memory unit that stores data and a memory controller that performs read / write control thereof.

  NAND flash memory is known as one of electrically rewritable nonvolatile semiconductor memories (EEPROM). The NAND flash memory has a smaller unit cell area than the NOR type and can easily be increased in capacity. The read / write speed per cell is slower than that of the NOR type, but by increasing the cell range (physical page length) in which reading / writing is simultaneously performed between the cell array and the page buffer, In particular, high-speed reading / writing is possible.

  Taking advantage of these features, NAND flash memories are used as various recording media including file memories and memory cards.

  In a memory card or the like, a nonvolatile memory and a memory controller are packaged, and reading / writing of the nonvolatile memory is controlled by a command and a logical address supplied from a host. For example, it has been proposed to read data of a plurality of sectors by giving a logical address and the number of sectors from a host (see Patent Document 1).

By the way, in the conventional NAND flash memory, when it is used alone, a write protect (/ WP) pin for instructing permission / prohibition of writing is provided as an external terminal, so that erroneous writing is likely to occur. In a situation, for example, in a predetermined period immediately after power-on, it is necessary to control from the outside that the / WP pin is controlled to a low level, which is an active level, and maintained at a high level during device operation. However, such control causes an increase in signal wiring in the external system and requires a special control by the external system.
JP 2006-155335 A

  It is an object of the present invention to provide a semiconductor memory device that does not require special signal wiring and control for write protection by an external system.

  A semiconductor memory device according to an aspect of the present invention includes a memory unit that stores data and has a write protect terminal, and prohibits data writing when a control signal to the write protect terminal becomes active, and the memory unit And a memory controller for controlling access to the memory unit, wherein the memory controller generates a control signal to the write protect terminal of the memory unit. It is characterized by outputting.

  According to the present invention, special signal wiring and control for write protection by an external system can be eliminated.

  Embodiments of the present invention will be described below with reference to the drawings.

[Configuration of semiconductor memory]
FIG. 1 is a block diagram showing a semiconductor memory according to the present embodiment.

  The semiconductor memory of this embodiment constitutes a memory module integrally packaged by, for example, one or a plurality of NAND flash memories 21 and a memory controller 22 that controls reading / writing. Since all the mounted flash memories 21 are controlled as a logical memory by a single memory controller 22, this is hereinafter referred to as a logical block address NAND flash memory (hereinafter abbreviated as an LBA-NAND memory). That's it.

  The NAND flash memory 21 mounted on the LBA-NAND memory 20 is composed of one or a plurality of memory chips. In FIG. 1, two memory chips chip 1 and chip 2 are shown, but in this case as well, they are controlled by one memory controller 22. The maximum number of memory chips is determined by the current capacity of the regulator and other factors.

  The memory controller 22 includes a NAND flash interface 23 for transferring data to and from the flash memory 21, a host interface 25 for transferring data to and from the host device, and a buffer RAM 26 for temporarily storing read / write data and the like. This is a one-chip controller having a hardware sequencer 27 that is used for MPU 24 that performs data transfer control, firmware / FW sequence control of firmware (FW) in the NAND flash memory 21, and the like.

  Whether the NAND flash memory 21 and the memory controller 22 are one chip or different chips is not essential for the LBA-NAND memory 20.

  FIG. 2 shows a cell array configuration of the memory core portion of the NAND flash memory 21 of FIG.

  The memory cell array 1 is a NAND cell unit in which a plurality of electrically rewritable nonvolatile memory cells (32 memory cells in the illustrated example) M0 to M31 are connected in series, and selection transistors S1 and S2 are connected to both ends thereof. (NAND string) NU is arranged.

  One end of the NAND cell unit NU is connected to the bit lines BLo and BLe via the selection gate transistor S1, and the other end is connected to the common source line CELSRC via the selection gate transistor S2. Control gates of memory cells M0-M31 are connected to word lines WL0-WL31, respectively, and gates of select gate transistors S1, S2 are connected to select gate lines SGD, SGS.

  A set of NAND cell units arranged in the word line direction constitutes a block serving as a minimum unit of data erasure, and a plurality of blocks BLK0 to BLKn-1 are arranged in the bit line direction as shown in the figure.

  A sense amplifier circuit 3 used for reading and writing cell data is arranged on one end side of the bit lines BLe and BLo, and a row decoder 2 for selecting and driving the word line and the selection gate line is arranged on one end side of the word line. The The figure shows a case where adjacent even-numbered bit lines BLe and odd-numbered bit lines BLo are selectively connected to each sense amplifier SA of the sense amplifier circuit 3 by a bit line selection circuit.

  In the LBA-NAND memory 20 configured as described above, commands, addresses (logical addresses) and data, chip enable signal / CE, write enable signal / WE, read enable signal / RE, command latch enable signal CLE, etc. The control signal is input / output between an external host system (not shown) and the host I / F 25. In the host I / F 25, commands and control signals are distributed to the MPU 24 and the hardware sequencer 27, and addresses and data are stored in the buffer RAM 26.

  A logical address input from the outside is converted into a physical address of the NAND flash memory 21 by the NAND flash I / F 23. Further, under the control of the hardware sequencer 27 based on various control signals, data transfer control and write / erase / read sequence control are executed. The converted physical address is transferred to the row decoder 2 and the column decoder (not shown) via the address register in the NAND flash memory 21. Write data is loaded into the sense amplifier circuit 3 via an I / O control circuit or the like, and read data is output to the outside via an I / O control circuit or the like.

  In addition, control signals such as a chip enable signal / CE, a write enable signal / WE, a read enable signal / RE, and a command latch enable signal CLE are internally input / output between the NAND flash I / F 23 and the NAND flash memory 21. Has been. Further, the NAND flash memory 21 is provided with a write protect (/ WP) pin, and a / WP signal is supplied from the NAND flash I / F 23 via this pin. The / WP signal is generated by, for example, the NAND flash I / F 23 as an internal operation of the memory controller 22.

  As such an internal operation, for example, as shown in FIG. 3, after the power is turned on, the / WP signal is maintained at a low level for a certain period until the memory 20 is booted. In the LBA-NAND memory 20 with the built-in controller 22, there is a possibility that the Busy period of the power-on reset becomes long, and the write permission to the NAND flash memory 21 cannot be given until the Busy period ends. For this reason, in the present embodiment, the NAND flash I / F 23 includes hardware for forcibly setting the / WP signal to the low level during the boot period. Thereby, it is possible to prevent the NAND flash memory 21 from erroneously writing.

  In addition, since / WP is not provided outside the LBA-NAND memory 20, special wiring and control for / WP control by an external host system can be eliminated.

  In addition, this invention is not limited to embodiment mentioned above. For example, in the above embodiment, the NAND type is used as the flash memory, but a NOR type other type of memory may be used.

1 is a diagram showing a configuration of an LBA-NAND memory system according to an embodiment of the present invention. It is a figure which shows the memory cell array structure of the same LBA-NAND memory. 4 is a timing chart when the LBA-NAND memory is powered on.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Memory cell array, 2 ... Row decoder, 3 ... Sense amplifier circuit, 20 ... LBA-NAND memory, 21 ... NAND flash memory, 22 ... Memory controller, 23 ... NAND flash interface, 24 ... MPU, 25 ... Host interface, 26 ... buffer RAM, 27 ... hardware sequencer.

Claims (3)

A memory unit that stores data and has a write protect terminal, and prohibits data writing when a control signal to the write protect terminal becomes active;
A memory controller that controls access to the memory unit; and a semiconductor memory device that accesses the memory unit from the outside via the memory controller,
The semiconductor memory device, wherein the memory controller generates and outputs a control signal to a write protect terminal of the memory unit. The semiconductor memory device according to claim 1, wherein the memory controller activates a control signal to the write protect terminal of the memory unit for a predetermined period immediately after power-on. The semiconductor memory device according to claim 1, wherein the memory controller does not have an externally accessible write protect terminal.

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