JP2002343090A - Non-volatile memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a non-volatile memory in which stable information holding operation is realized with simple constitution. SOLUTION: This memory is a non-volatile memory performing electrically write-in operation and erasure operation of storage information, when write-in operation is performed for a threshold value of first distribution being adjacent to threshold voltage of an erasure state, first voltage is given to a selection word line, second voltage is given to a selection bit line and first write-in operation is performed, when such write-in operation is performed that the operation has threshold voltage being higher than threshold voltage of the first distribution basing threshold voltage of the erasure state as a reference, third voltage being higher than the first voltage is given to a selection word line, potential difference for a bit line is made larger than potential difference at write-in operation of threshold voltage of the first distribution, second write-in operation is performed, while a potential of a non-selection bit line at the time of the first write-in operation is made lower than that of the second write-in operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile memory, and more particularly to a technique which is effectively used as a writing technique in a flash memory or the like which can be electrically written and erased.

[0002]

2. Description of the Related Art A nonvolatile memory cell such as a flash EEPROM (hereinafter simply referred to as a flash memory) has a diffusion layer composed of a source and a drain and a gate insulating film on a semiconductor substrate between the source and the drain. The floating gate and the control gate have a stacked structure, the control gate is connected to a word line, and the drain is a bit line (or data line).
And the source is commonly connected to the source line. Then, in the write operation, 18 to
There is an FN tunnel writing type in which a high voltage such as 15 V is applied, and an FN tunnel current of electrons flows from a channel through the gate insulating film to a floating gate (hereinafter referred to as FG) to accumulate charges.

[0003]

FIG. 6 shows voltage conditions in a write state of a memory cell as described above. A write voltage Vww (about 18 V) is applied to the write selected word line. At this time, 0 V is applied to the bit line of the selected memory cell, and writing is performed by FN tunnel (electron injection into FG).
I do. On the other hand, Vwd (about 5 V) is applied to the bit line of the non-selected memory cell. Further, by turning off the selection MOSFET on the source line side, the source line is brought into a floating state (open state), and the channel potential of the non-selected memory cell to be written is raised to Vwd to prevent writing.

By applying the above-mentioned voltage Vwd to the bit lines of the non-selected memory cells, the memory cells connected to the non-selected word lines and the non-selected bit lines are disturbed. Disturb is a phenomenon in which the memory Vth of a memory cell in a non-selected state fluctuates. As shown in FIG. 6, there are particularly three disturbances that cause a problem during the write operation.

(1) Write word disturb (in FIG. 6, memory cell A is subject to disturbance) (2) Write drain disturb 1 (in FIG. 6,
(3) Write drain disturb 2 (memory cell B is disturbed in FIG. 6)
(The memory cell C is a disturbance target.)

The write drain disturbs 1 and 2 in (2) and (3) are generated because a voltage Vus is applied to a write non-selected word line. The voltage Vus is, as shown in FIG. 7A, when 0 V is applied to a non-selected word line.
The voltage Vwd applied to the non-selected write bit line is applied in order to prevent electrons from being emitted by the high electric field on the drain side due to the drain-side high electric field and to prevent the memory Vth from falling down (Vth drop).

Although the memory Vth is prevented from falling down by the application of the voltage Vus, as shown in FIG. 7B, while the current is flowing through the memory cell, the memory Vth is in an electron injection state by hot electrons. Rise. In the multi-valued memory, when the memory Vth rises beyond the read voltage one level higher, a read failure occurs. In the write state, since all the source-side selection MOSFETs are in the off state, the current flows through the memory cell and disturb becomes a problem as shown in FIG. Probable transient current. This transient current can be prevented by providing a MOSFET that short-circuits between the local source line and the bit line. That is, by flowing the transient current through the short-circuit MOSFET, the current flowing through the memory cell can be used to prevent or reduce the generation of the hot electrons.

However, the short-circuit MOSF as described above
It has been found that even when ET is provided, the memory Vth increases due to the electron injection by the hot electrons. As a result of investigating this phenomenon, as shown in FIG. 8B, it was found that there was a cause of a leak current (DC mode) caused by a leak path between the local source line and the substrate. That is, as a countermeasure against transient current due to local source line charging, the short-circuit MOSF
The provision of ET alone has no effect on the hot electrons caused by the leak current as described above, and does not provide a measure against the leak current which is a main current component. Therefore, it cannot be said that this is a sufficient countermeasure against the write drain disturbance 2.

An object of the present invention is to provide a nonvolatile memory which realizes stabilization of an information holding operation with a simple configuration. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. A non-volatile memory electrically performing a write operation and an erase operation of the storage information, wherein a write operation is performed on a selected word line during a write operation to a first distribution threshold value adjacent to a threshold voltage in an erased state; A first voltage is applied, a second voltage is applied to a selected bit line, and a first write operation is performed, and a threshold voltage higher than the threshold voltage of the first distribution with reference to the threshold voltage in the erased state. In a write operation having a value voltage, the first word is applied to the selected word line.
The second write operation is performed by applying a third voltage larger than the voltage and making the potential difference between the bit line and the bit line larger than that in the write operation of the threshold voltage of the first distribution, and compared with the second write operation. Thus, the potential of the non-selected bit line at the time of the first write operation is reduced.

[0011]

FIG. 1 is a block diagram showing one embodiment of a nonvolatile memory according to the present invention. Each circuit block in FIG. 1 is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

In this embodiment, in order to reduce the number of external terminals, a command designating an operation mode and an X (row) address signal are taken in via data terminals I / O (0-7). That is, the input signal input via the input / output buffer 39 is transmitted to the command decoder 31, the data conversion circuit 20, and the address counter ACNT of the rescue circuit 40 through the internal signal lines. The data conversion circuit 20 has a multiplexer function. In addition to the original data conversion operation, the X address signal is transmitted through a signal line (not shown) to the X decoder (X-DEC) 1 of the memory array.
3a and 13b.

The address counter ACNT is mainly used for bit line relief. The address counter ACNT compares the defective address stored in the redundant fuse circuit with the Y address formed by the address counter ACNT. The circuit switches to a spare bit line. The address counter ACNT is an address generation circuit for that purpose. The head address may be input to the address counter ACNT from an external terminal. However, when reading / writing in word line units (sectors) as in a hard disk memory as described above, the above Y
It doesn't make sense to enter the first value of the address.

In FIG. 1, the signal path through which the Y address signal is transmitted is also omitted as in the case of the X address signal, and is transmitted to a Y decoder (Y-DEC) 11 to form a Y selection signal. The control operation including the distribution of the input signals as described above includes the control signals supplied to the control signal input buffer & input / output control circuit 38 (for example, the chip enable signal CE,
Write enable signal WE, output enable signal OE, command enable signal CCDW) and clock signal SC. A reset signal RES is provided, and when this signal is at a low level, a low power consumption mode is set in which no operation is performed. The ready / busy circuit R / B informs an external access device of the status of use of the multi-level flash memory.

The X address (sector address) signal is decoded by X decoders (X-DEC) 13a and 13b, and one word line of the memory mat MAT-U (upper side) or MAT-D (down side). Select WL. Although not particularly limited, in this embodiment, a sense latch circuit SL including the Y gate is provided in common at the center so as to sandwich the two memory mats MAT-U and MAT-D. The memory mat includes the sense latch circuit S
L is centered on the upper memory mat MAT-U and the lower memory mat MAT-D.

Word line drivers (W-DRIVER) 14a, 14b which receive a main word line selection signal and a gate selection signal formed by an X decoder (X-DEC) and select a word line to which a memory cell is connected are provided. Write operation,
In each of the erasing operation and the reading operation, the potential of the main word line connected to the gate of the selection MOSFET and the potential of the word line connected to the control gate of the storage transistor, which will be described later, are different according to the respective modes. For this reason, it has an output circuit that outputs a selection / non-selection level of a voltage corresponding to each operation mode. The voltages necessary for these operation modes are formed by an internal power supply including a reference power supply, a charge pump booster circuit, a step-down circuit, etc., a voltage switching circuit, and an internal voltage generation circuit 37 including a voltage control circuit 371 for controlling them.

Memory array mats MAT-U and MAT
In -D, a storage transistor (memory cell) is provided at the intersection of a word line and a bit line as shown in FIG. Although not particularly limited, the bit line is a hierarchy composed of local bit lines (hereinafter simply referred to as bit lines) to which drains of a plurality of storage transistors are commonly connected to a global bit line (not shown) via a drain selection MOSFET. Structure. One block is constituted by bit lines to which the drains of the storage transistors are commonly connected, and the sources of the storage transistors in such blocks are connected to a common source line via a source selection MOSFET.

Although one block is not particularly limited,
Word lines W1 to W128, in other words, sector 1
1 or 128 (128 word lines) such as the sector 128, and the memory mat MAT shown in FIG.
-U and MAT-D as a whole, although not particularly limited, have 16384 sectors (word lines) as a normal memory area.
Is provided. Although not particularly limited, each of the memory mats MAT-U and MAT-D is provided with 245 word lines (sectors) used as management areas.

For example, a redundant word line (sector) is further added to relieve a word line for a defect. Therefore, an X address signal for selecting a word line is composed of 9 bits X0 to X8. In the method of inputting the X address signal from the data terminals DQ0 to DQ7 as described above, two cycles are required to capture the address signals X0 to X8.

In the Y direction, although not particularly limited, 512 × 8 = 4096 bit lines are provided as a normal array, and a plurality of redundant lines are separately provided as described above. Each of the memory mats MAT-U and MAT-D is provided with about 4M storage transistors, and each of about 8M storage transistors stores quaternary (2-bit) storage information in each of them. A total of about 16 Mbytes (128 Mbits) of information can be stored.

In FIG. 1, one end of the global bit line is connected to a sense latch SL. The sense latch SL has a function of reading and sensing the high level and the low level of the global bit line, and has a function of latching it. This sense latch S
The L circuit has a function as a register.
Although not particularly limited, as the sense latch SL, a circuit similar to a CMOS sense amplifier used in a known dynamic RAM is used. That is, the sense latch SL includes a pair of CMOs whose inputs and outputs are cross-connected.
It comprises an S inverter circuit and a power switch for supplying an operating voltage and a circuit ground voltage to a plurality of CMOS inverter circuits. A data latch DL provided at the other end of the global bit line is used for reading and writing in four values.

The column selection operation of the column decoder (Y-DEC) 11 is performed by decoding the address signal generated by the address counter ACNT and setting the input / output node of the sense latch circuit SL to the input / output line by the selection signal formed. Connect. The redundant circuit 41 and the rescue circuit 41 switch the defective bit line of the normal array of the memory mat to the spare bit line provided in the redundant array. The address counter ACNT counts the serial clock signal SC supplied from an external terminal and generates the Y address signal. The serially input write data is input in synchronization with the serial clock SC,
The read data output serially is output in synchronization with the serial clock SC. The clock generation circuit 34 forms various internal clock signals including the serial clock SC.

In this embodiment, when erasing, writing, and reading are performed in units of one word line as one sector, control by a normal mass storage controller such as an HDC (hard disk controller) becomes easy. Therefore, the construction of the memory system is simplified. Then, compatibility with a file memory such as a hard disk memory is obtained, and replacement with the file memory becomes easy.

A write operation, a read operation and an erase operation for a memory cell include a command decoder 31, a control circuit (sequencer) 32 and a status & test system circuit 35.
And write verify, erase verify write,
This is performed by the erase determination circuit 33.

In this embodiment, the data latches DL for storing the same number of write data and read data as the sense latches SL are provided in the upper and lower memory mats MAT-U and MAT-U.
D, the data latch DL and the sense latch S
L is connected via a bit line. Then, it is used for a buffer memory or multi-value determination at the time of a read operation. A signal path is provided such that data transferred from the sense latch SL to the data latch DL is supplied to the main amplifier (MA) 36. This signal path includes a column switch provided in the sense latch SL, and performs serial data transfer to the main amplifier MA.

The memory cell of this embodiment has a quaternary threshold voltage distribution like LEVEL0 to LEVEL3 as shown in FIG. The LEVEL0 distribution is in an erased state and corresponds to the storage information of the logic 11. LEVEL1 distribution adjacent to such an erased state (LEVEL0) is
The LEVEL2 distribution corresponds to the storage information of logic 00, and the LEVEL3 distribution corresponds to the storage information of logic 01 hereinafter. In the flash memory, the threshold voltage distribution LEVEL in the erased state is used.
Based on 0, the LEVEL 1
Or the distribution is changed to the threshold distribution of LEVEL3. The voltages Vrw1 to Vrw3 in the drawing are read voltages applied to the word lines to identify the above four-valued threshold voltage distribution.

FIG. 4 is a waveform chart for explaining one embodiment of the write operation of the nonvolatile memory according to the present invention. FIG. 3 shows the voltage Vww of the selected word line,
The voltage Vwd of the unselected bit line is shown. In this embodiment, the word line voltage Vww is set in three stages in accordance with the difference between the threshold voltage and the erased state (LEVEL0) in order to increase the efficiency of the write operation. That is, LEVEL that maximizes the difference between the threshold voltage and the erased state
3, the word line selection voltage Vww at the time of the write operation of LEVEL 2 is increased to 18 V, and the word line selection voltage Vww at the time of the write operation of LEVEL 2 is set to an intermediate voltage such as 17 V. And the word line selection voltage Vww at the time of the write operation of LEVEL1 having the smallest difference in threshold voltage, such as 16V, is set to the smallest such as 16V. At the time of the write operation, the voltage of the selected bit line is 0 V, and the voltage Vus of the non-selected word line is 5 V, as described above.

In this embodiment, the mechanism of the write drain disturb 2 (disturb of the memory cell C in FIG. 6) uses the Vsu ( ~ 58V)
Is generated by applying. This is because while applying current to the memory cell by applying the voltage Vsu, hot electrons are generated on the drain side of the memory cell C in FIG. 6, electrons are injected, and the memory Vth fluctuates.

In order to reduce the generation of hot electrons, the write blocking voltage Vwd must be lowered. However, simply lowering Vwd increases the potential difference between the word line and the bit line, so that the word disturb in the memory cell (A) in FIG. 6 becomes a problem this time. Therefore, in this embodiment, as shown in FIG. 4, the drain disturb 2 is relaxed by lowering the voltage Vwd of the non-selected bit line only in the write operation of the logic 10 in which the voltage of the selected word line Vww is the smallest.

For example, in the conventional 512M flash memory, Vwd is all 6V. The drain disturb 2 can be reduced by lowering the voltage by 1 V to 5 V only when writing the logic 10. The reduction in the voltage Vwd causes word disturb, but the difference between the voltage Vww of the selected word line and the voltage 16 V is only 10 V, and the word disturb is over-cared when the logic 10 is written. There is no problem if you let them.

FIG. 5 shows a word disturb characteristic diagram of the nonvolatile memory according to the present invention. Logic 10
By reducing the voltage Vwd of the non-selected bit line from 6 V to 5 V at the time of the write operation, word disturb free is possible only by delaying 1 V. That is, as for the word disturb characteristic, the logic 00 and the logic 10 have the same word disturb characteristic by applying the present invention, and the drain disturb 2 can be improved without impairing the word disturb.

The functions and effects obtained from the above embodiment are as follows. (1) A nonvolatile memory that electrically performs a write operation and an erase operation of the above-mentioned storage information, and is selected when a write operation to a first distribution threshold value adjacent to a threshold voltage in an erased state is performed. A first voltage is applied to a word line and a second voltage is applied to a selected bit line to perform a first write operation, and the threshold voltage in the erased state is set higher than the threshold voltage in the first distribution. At the time of a write operation having a large threshold voltage, a third voltage higher than the first voltage is applied to the selected word line so that the potential difference between the selected word line and the bit line has the first distribution. The second write operation is performed with a larger voltage than that of the above-mentioned case, and the potential of the non-selected bit line during the first write operation is made smaller than that of the second write operation. Realization The effect is that it can be realized.

(2) In addition to the above, the memory cell has a quaternary threshold voltage including an erased state, and the distribution of the threshold voltage higher than the threshold voltage of the first distribution is The selected word line at the time of the second threshold distribution as the second threshold distribution and the third threshold distribution is set to the third voltage, and the selected word line at the time of the third threshold distribution larger than that is selected. By setting the fourth voltage to a fourth voltage higher than the third voltage, an effect can be obtained that an efficient writing operation can be performed.

(3) In addition to the above, by setting the voltage of the unselected word line at the time of the first write operation and the second write operation to a predetermined voltage close to the potential of the unselected bit line, word disturb can be achieved. And drain disturb can be minimized.

The invention made by the present inventor has been specifically described based on the embodiments. However, the invention of the present application is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, the memory cell may have any storage information having three or more values.
The memory array and its specific circuit may be any as long as they perform the above-described erasing, writing and reading operations. Further, the storage state may be reversed from that of the above embodiment. For example, the distribution of the threshold voltage of LEVEL 3 in FIG. 3 may be set to an erased state, and the threshold voltage may be lowered in a write operation to create a storage state of the remaining three values. The present invention can be widely used for nonvolatile memories.

[0036]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. A non-volatile memory electrically performing a write operation and an erase operation of the storage information, wherein a write operation is performed on a selected word line during a write operation to a first distribution threshold value adjacent to a threshold voltage in an erased state; A first voltage is applied, a second voltage is applied to a selected bit line, and a first write operation is performed, and a threshold voltage higher than the threshold voltage of the first distribution with reference to the threshold voltage in the erased state. In a write operation having a value voltage, the first word is applied to the selected word line.
The second write operation is performed by applying a third voltage larger than the voltage and making the potential difference between the bit line and the bit line larger than that in the write operation of the threshold voltage of the first distribution, and compared with the second write operation. Thus, the information holding operation can be stabilized with a simple configuration in which the potential of the non-selected bit line in the first writing operation is reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a nonvolatile memory according to the present invention.

FIG. 2 is a schematic circuit diagram showing one embodiment of a memory array mat of FIG. 1;

FIG. 3 is a threshold voltage distribution diagram of a memory cell in a nonvolatile memory to which the present invention is applied;

FIG. 4 is a waveform chart for explaining one embodiment of a write operation of the nonvolatile memory according to the present invention.

FIG. 5 is a word disturb characteristic diagram of the nonvolatile memory according to the present invention.

FIG. 6 is a circuit diagram showing a voltage condition in a write state of a conventional memory cell.

FIG. 7 is an explanatory diagram of disturbance in an unselected memory cell;

FIG. 8 is an explanatory diagram of disturbance in an unselected memory cell.

[Explanation of symbols]

W1 to W128: word line, 10: memory array, 11
... Sense latch & Y decoder, 12a, 12b ... Data latch, 13a, 13b ... X decoder, 14a, 14b
... word line driver, 20 ... data conversion circuit, 31 ... command decoder, 32 ... control circuit, 33 ... erase judgment circuit, 34 ... clock generation circuit, 35 ... status & test system circuit, 36 ... main amplifier, 37 ... internal voltage Generating circuit, 38: input / output control circuit, 39: input / output buffer,
40: redundancy circuit, 41: relief circuit,

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kenjun Takase 3-16-6 Shinmachi, Ome-shi, Tokyo F-term in the Hitachi, Ltd. Device Development Center Co., Ltd. 5B025 AA01 AC01 AC04 AD04 AD08 AD09 AD14 AD15 AE08

Claims (3)

[Claims] A plurality of word lines and a plurality of bit lines;
At the intersection of the plurality of word lines and the plurality of bit lines, there are a plurality of memory cells having a threshold voltage of three or more values corresponding to the amount of charge stored in the floating gate, and electrically stores the memory information. A nonvolatile memory for performing a write operation and an erase operation, wherein a first voltage is applied to a selected word line during a write operation to a first distribution threshold value adjacent to a threshold voltage in an erased state. A second voltage is applied to the bit line, and a first write operation of injecting electrons from the selected bit line into the floating gate of the selected memory cell according to the potential difference is performed. In a write operation having a threshold voltage higher than the threshold voltage of the first distribution on the basis of a reference, a third voltage higher than the first voltage is applied to a selected word line, and a selected bit line is applied to a selected bit line. The second voltage The second write operation is performed by injecting electrons from the selected bit line into the floating gate of the selected memory cell by the voltage difference whose potential difference is made larger than the write operation of the threshold voltage of the first distribution. A non-volatile memory, wherein the potential of an unselected bit line at the time of the first write operation is lower than that of the operation. 2. The memory cell according to claim 1, wherein the memory cell has a quaternary threshold voltage including an erased state, and has a threshold voltage distribution higher than the first distribution threshold voltage. Is composed of a second threshold distribution and a third threshold distribution. The selected word line in the second threshold distribution is a third voltage, and the selected word line in the third threshold distribution is larger than the third voltage. A nonvolatile memory, wherein the voltage of the selected word line is a fourth voltage higher than the third voltage. 3. The voltage according to claim 1, wherein the voltage of the non-selected word line in the first write operation and the second write operation is set to a predetermined voltage close to the potential of the non-selected bit line. Non-volatile memory characterized by the above-mentioned.