JP5110164B2 - Component built-in module and manufacturing method thereof - Google Patents

Component built-in module and manufacturing method thereof Download PDF

Info

Publication number
JP5110164B2
JP5110164B2 JP2010520749A JP2010520749A JP5110164B2 JP 5110164 B2 JP5110164 B2 JP 5110164B2 JP 2010520749 A JP2010520749 A JP 2010520749A JP 2010520749 A JP2010520749 A JP 2010520749A JP 5110164 B2 JP5110164 B2 JP 5110164B2
Authority
JP
Japan
Prior art keywords
resin
circuit component
component
module
resin layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2010520749A
Other languages
Japanese (ja)
Other versions
JPWO2010007736A1 (en
Inventor
俊介 千阪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP2010520749A priority Critical patent/JP5110164B2/en
Publication of JPWO2010007736A1 publication Critical patent/JPWO2010007736A1/en
Application granted granted Critical
Publication of JP5110164B2 publication Critical patent/JP5110164B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/186Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0237High frequency adaptations
    • H05K1/0239Signal transmission by AC coupling
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10674Flip chip
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Combinations Of Printed Boards (AREA)

Description

本発明は部品内蔵モジュール及びその製造方法に関し、詳しくは、樹脂基板内に回路部品を内蔵する部品内蔵モジュール及びその製造方法に関する。   The present invention relates to a component built-in module and a manufacturing method thereof, and more particularly to a component built-in module in which a circuit component is built in a resin substrate and a manufacturing method thereof.

従来、樹脂基板内に回路部品を内蔵する部品内蔵モジュールが種々提案されている。   Conventionally, various component built-in modules in which circuit components are built in a resin substrate have been proposed.

例えば図6の断面図に示すように、回路部品204を、導電性接着剤205を介して銅箔203に実装し、その上に、貫通孔201に導電性樹脂202が充填された、熱硬化性樹脂を含む板状部材200と、銅箔206とを重ねて加熱し、板状部材200を軟化させて電気絶縁性基板207内に回路部品204を内蔵した後、配線パターン209,210を形成する(例えば、特許文献1参照)。   For example, as shown in the cross-sectional view of FIG. 6, the circuit component 204 is mounted on the copper foil 203 via the conductive adhesive 205, and the through hole 201 is filled with the conductive resin 202. After the plate-like member 200 containing the conductive resin and the copper foil 206 are overlaid and heated to soften the plate-like member 200 and incorporate the circuit component 204 in the electrically insulating substrate 207, the wiring patterns 209 and 210 are formed. (For example, refer to Patent Document 1).

特開平11−220262号公報Japanese Patent Laid-Open No. 11-220262

しかしながら、半田等の導電材料を用いて実装された回路部品を樹脂に埋設するため樹脂を加熱すると、半田等の導電材料が再溶融し、ショートが発生するおそれがある。そのため、回路部品の端子電極間のピッチが狭い場合や、樹脂内に埋設する回路部品の隙間が小さい場合には、部品内蔵モジュールを製造することが困難になる。   However, if the resin is heated in order to embed a circuit component mounted using a conductive material such as solder in the resin, the conductive material such as solder may be remelted and a short circuit may occur. Therefore, when the pitch between the terminal electrodes of the circuit component is narrow, or when the gap between the circuit components embedded in the resin is small, it is difficult to manufacture the component built-in module.

本発明は、かかる実情に鑑み、導電材料の溶融等によるショートが発生することがない、部品内蔵モジュール及びその製造方法を提供しようとするものである。   In view of such circumstances, the present invention intends to provide a component built-in module and a method for manufacturing the same, in which a short circuit due to melting of a conductive material or the like does not occur.

本発明は、上記課題を解決するために、以下のように構成した部品内蔵モジュールを提供する。   In order to solve the above problems, the present invention provides a component built-in module configured as follows.

部品内蔵モジュールは、(a)複数の樹脂層が接合された基板本体と、(b)端子電極と前記端子電極を覆う誘電体層とを有し、前記基板本体の内部に配置された回路部品と、(c)少なくとも1層の前記樹脂層の主面に接して配置された配線パターンとを備える。前記回路部品の前記端子電極と前記配線パターンとが、前記誘電体層を介して容量結合している。 The component built-in module includes (a) a substrate body to which a plurality of resin layers are joined, and (b) a circuit component disposed inside the substrate body , the terminal electrode and a dielectric layer covering the terminal electrode. And (c) a wiring pattern disposed in contact with the main surface of at least one of the resin layers. And the terminal electrodes of the circuit component and the wiring pattern are capacitively coupled via the dielectric layer.

上記構成によれば、半田等の導電材料を用いて回路部品を配線パターンに実装する必要がないので、樹脂層を接合する際の加熱によって導電材料が溶融する等によりショートが発生することがない。   According to the above configuration, since it is not necessary to mount circuit components on the wiring pattern using a conductive material such as solder, a short circuit does not occur due to melting of the conductive material due to heating when the resin layer is bonded. .

好ましくは、前記樹脂層の主面に接して配置された配線パターンをさらに備える。前記樹脂層の前記主面に垂直な方向から透視すると、前記配線パターンは前記回路部品を含む。   Preferably, a wiring pattern arranged in contact with the main surface of the resin layer is further provided. When seen through from a direction perpendicular to the main surface of the resin layer, the wiring pattern includes the circuit component.

この場合、回路部品の上側および/または下側に配線パターンが設けられており、配線パターンは、これを平面視したとき、その投影面が回路部品の投影面を含むように形成されている。   In this case, a wiring pattern is provided on the upper side and / or the lower side of the circuit component, and the wiring pattern is formed so that its projection plane includes the projection plane of the circuit component when viewed in plan.

樹脂シートを積層してなる樹脂基板が特に可撓性を有している場合、樹脂基板に衝撃が加わって樹脂基板が変形すると、埋設された回路部品がダメージを受ける可能性がある。そこで、回路部品を包み込むように配線パターンを設けることで、回路部品が受けるダメージを最小限に抑えることができる。また、樹脂基板が変形すると、回路部品の端子電極と配線パターンとの間に形成された容量値が変動する可能性があるが、その変動を最小限に抑えることもできる。   When the resin substrate formed by laminating the resin sheets is particularly flexible, if the resin substrate is deformed by an impact applied to the resin substrate, the embedded circuit component may be damaged. Therefore, by providing a wiring pattern so as to enclose the circuit component, damage to the circuit component can be minimized. Further, when the resin substrate is deformed, there is a possibility that the capacitance value formed between the terminal electrode of the circuit component and the wiring pattern may fluctuate, but the fluctuation can be minimized.

好ましくは、対向する一対の前記配線パターンと、該一対の前記配線パターン間を接続するビアホール導体とを備える。前記回路部品は、該一対の前記配線パターン間に配置されている。 Preferably, a pair of the wiring patterns facing each other and a via-hole conductor connecting the pair of wiring patterns are provided. The circuit component is disposed between the pair of wiring patterns.

この場合、回路部品の上側および下側に配線パターンが設けられており、配線パターン同士は互いにビアホール導体で接続されている。ビアホール導体は、回路部品の上下の配線パターン間の支柱として機能するため、回路部品が受けるダメージをより効果的に抑制できるとともに、容量値の安定化を図ることができる。   In this case, wiring patterns are provided on the upper and lower sides of the circuit component, and the wiring patterns are connected to each other by via-hole conductors. Since the via-hole conductor functions as a support between the upper and lower wiring patterns of the circuit component, damage to the circuit component can be more effectively suppressed and the capacitance value can be stabilized.

また、本発明は、上記課題を解決するために、以下のように構成した部品内蔵モジュールの製造方法を提供する。   In order to solve the above-mentioned problems, the present invention provides a method for manufacturing a component built-in module configured as follows.

部品内蔵モジュールの製造方法は、複数の樹脂層が接合された基板本体の内部に回路部品が配置された部品内蔵モジュールの製造方法である。部品内蔵モジュールの製造方法は、(i)前記樹脂層の間に、端子電極と前記端子電極を覆う誘電体層とを有する回路部品を配置した状態で、前記樹脂層を積層する第1の工程と、(ii)積層された前記樹脂層を加熱・圧着する第2の工程とを備える。前記第1の工程において、前記樹脂層の間に配線パターンを配置し、該配線パターンに前記回路部品の前記誘電体層が接する状態で、前記樹脂層を積層する。 The method for manufacturing a component built-in module is a method for manufacturing a component built-in module in which circuit components are arranged inside a substrate body to which a plurality of resin layers are bonded. In the component built-in module manufacturing method, (i) a first step of laminating the resin layer with a circuit component having a terminal electrode and a dielectric layer covering the terminal electrode disposed between the resin layers. And (ii) a second step of heating and pressure-bonding the laminated resin layers. In the first step, a wiring pattern between the resin layer is disposed, in the state where the dielectric layer is in contact before Symbol circuit components wiring pattern, laminating the resin layer.

上記方法によれば、配線パターンと回路部品の端子電極とを容量結合させることができる。容量結合させると、半田等の導電材料を用いて回路部品を配線パターンに実装する必要がないので、樹脂層の加熱によって導電材料が溶融する等によりショートが発生することがない。   According to the above method, the wiring pattern and the terminal electrode of the circuit component can be capacitively coupled. When capacitively coupled, there is no need to mount circuit components on the wiring pattern using a conductive material such as solder, so that a short circuit does not occur due to melting of the conductive material due to heating of the resin layer.

好ましくは、前記第1の工程において、固定材を用いて、前記樹脂層の一方主面に前記回路部品を固定した後、前記回路部品が固定された前記樹脂層の前記一方主面に少なくとも1層の他の前記樹脂層を積層する。前記固定材は、前記第2の工程において積層された前記樹脂層を加熱・圧着する前に、消失する。   Preferably, in the first step, after fixing the circuit component to one main surface of the resin layer using a fixing material, at least 1 is applied to the one main surface of the resin layer to which the circuit component is fixed. The other resin layer of the layer is laminated. The fixing material disappears before the resin layer laminated in the second step is heated and pressure-bonded.

この場合、固定材により、回路部品が固定された樹脂層の一方主面に他の樹脂層を積層したときに、回路部品が動かないように固定することができる。樹脂層を積層した後、固定材が消失してから、積層された樹脂層を加熱・圧着するため、固定材は、部品内蔵モジュールの内部に残らない。そのため、固定材は、樹脂層の間に閉じ込められてクラック発生の原因になる等の悪影響を及ぼすことがない。   In this case, when the other resin layer is laminated on the one main surface of the resin layer to which the circuit component is fixed, the circuit component can be fixed so as not to move. Since the fixing material disappears after the resin layers are laminated, the laminated resin layer is heated and pressure-bonded, so that the fixing material does not remain inside the component built-in module. For this reason, the fixing material does not have an adverse effect such as being confined between the resin layers and causing cracks.

好ましくは、前記固定材が有機溶剤である。   Preferably, the fixing material is an organic solvent.

有機溶剤は気化しやすく、消失しやすいため、作業が容易になる。   Since the organic solvent is easily vaporized and easily lost, the operation is facilitated.

本発明によれば、導電材料の溶融等によるショートが発生することがない。そのため、部品内蔵モジュールに内蔵する回路部品の端子の狭ピッチ化に容易に対応することができる。   According to the present invention, a short circuit due to melting of the conductive material does not occur. Therefore, it is possible to easily cope with the narrowing of the pitch of the terminals of the circuit components incorporated in the component built-in module.

部品内蔵モジュールの断面図である。(実施例1)It is sectional drawing of a component built-in module. Example 1 部品内蔵モジュールの断面図である。(実施例2)It is sectional drawing of a component built-in module. (Example 2) 部品内蔵モジュールの断面図である。(実施例3)It is sectional drawing of a component built-in module. (Example 3) 部品内蔵モジュールの接合前の断面図である。(実施例4)It is sectional drawing before joining of a component built-in module. Example 4 部品内蔵モジュールの断面図である。(実施例4)It is sectional drawing of a component built-in module. Example 4 部品内蔵モジュールの製造工程を示す断面図である。(従来例)It is sectional drawing which shows the manufacturing process of a component built-in module. (Conventional example)

以下、本発明の実施の形態について、図1〜図5を参照しながら説明する。   Hereinafter, embodiments of the present invention will be described with reference to FIGS.

<実施例1> 実施例1の部品内蔵モジュール30について、図1を参照しながら説明する。図1(a)は、接合前の部品内蔵モジュール30の断面図である。図1(b)は、接合後の部品内蔵モジュール30の断面図である。   <Example 1> The component built-in module 30 of Example 1 is demonstrated, referring FIG. FIG. 1A is a cross-sectional view of the component built-in module 30 before joining. FIG. 1B is a cross-sectional view of the component built-in module 30 after joining.

図1に示すように、部品内蔵モジュール30は、熱可塑性樹脂の樹脂層11,13,15,17,19が接合された基板本体32の内部や表面に、配線パターン10a,12a,12b,14a,14b,14c,16a,16b,18aや貫通導体11a,11b,13a,13b,15a,15b,17a,17b,19a,19bが形成され、基板本体32の内部には、ICチップやコンデンサ等の回路部品2が内蔵されている。回路部品2の端子電極6a,6bは、樹脂層13を介して、配線パターン14a,14bと容量結合している。   As shown in FIG. 1, the component built-in module 30 includes wiring patterns 10a, 12a, 12b, and 14a on the inside and the surface of a substrate body 32 to which resin layers 11, 13, 15, 17, and 19 of thermoplastic resin are bonded. , 14b, 14c, 16a, 16b, 18a and through conductors 11a, 11b, 13a, 13b, 15a, 15b, 17a, 17b, 19a, 19b are formed inside the substrate body 32, such as an IC chip or a capacitor. The circuit component 2 is incorporated. The terminal electrodes 6 a and 6 b of the circuit component 2 are capacitively coupled to the wiring patterns 14 a and 14 b through the resin layer 13.

回路部品2の端子電極6a,6bと配線パターン14a,14bとが容量結合していると、回路部品2の端子電極6a,6bは、導電材料を介して配線パターンに接続しなくても、回路部品2と配線パターンとを電気的に接続することができる。よって、導電材料の溶融等によるショート等の危険性はない。また、回路部品2の端子電極6a,6bが狭くなっても、容易に対応することができる。また、複数の回路部品を、隙間を小さくして内蔵することもできる。   When the terminal electrodes 6a and 6b of the circuit component 2 and the wiring patterns 14a and 14b are capacitively coupled, the terminal electrodes 6a and 6b of the circuit component 2 can be connected to the wiring pattern via a conductive material without being connected to the wiring pattern. The component 2 and the wiring pattern can be electrically connected. Therefore, there is no danger of a short circuit due to melting of the conductive material. Moreover, even if the terminal electrodes 6a and 6b of the circuit component 2 become narrow, it can be easily handled. Also, a plurality of circuit components can be incorporated with a small gap.

回路部品2の端子電極6a,6bと配線パターン14a,14bとの間に形成された容量は、部品内蔵モジュール30の内部に回路部品2と同様に設けられた他の回路素子(図示せず)とともに、部品内蔵モジュール30を構成する回路の一素子として利用することができる。たとえば、インピーダンスマッチング用のキャパシタンス素子として利用することもできる。内蔵されたインダクタンス素子とあわせて、LC共振回路のキャパシタンス素子として利用することもできる。また、サージ電圧が加わった時、直流電圧が回路部品に加わらないようにするための直流成分カット用素子としても利用される。   The capacitance formed between the terminal electrodes 6a, 6b of the circuit component 2 and the wiring patterns 14a, 14b is another circuit element (not shown) provided in the component built-in module 30 in the same manner as the circuit component 2. In addition, it can be used as one element of a circuit constituting the component built-in module 30. For example, it can be used as a capacitance element for impedance matching. Together with the built-in inductance element, it can also be used as a capacitance element of the LC resonance circuit. It is also used as a DC component cutting element for preventing a DC voltage from being applied to circuit components when a surge voltage is applied.

埋設された回路部品2の上側の配線パターン10aおよび下側の配線パターン16bは、これらを平面視したとき、その投影面が回路部品2の投影面を含むように形成されている。すなわち、配線パターン10aが配置されている樹脂層11の主面に垂直な方向から透視すると、配線パターン10aは回路部品2を含む。また、配線パターン16bが配置されている樹脂層17の主面に垂直な方向から透視すると、配線パターン16bは回路部品2を含む。   The upper wiring pattern 10a and the lower wiring pattern 16b of the embedded circuit component 2 are formed such that their projection plane includes the projection plane of the circuit component 2 when viewed in plan. That is, when seen through from a direction perpendicular to the main surface of the resin layer 11 on which the wiring pattern 10 a is arranged, the wiring pattern 10 a includes the circuit component 2. Further, when seen through from the direction perpendicular to the main surface of the resin layer 17 on which the wiring pattern 16 b is disposed, the wiring pattern 16 b includes the circuit component 2.

さらに、回路部品2の上側に設けられた配線パターン10aと、回路部品2の下側に設けられた配線パターン16bは、ビアホール導体11b,13b,15bにより接続されている。これらのビアホール導体11b,13b,15bは、配線パターン10aおよび配線パターン16bの支柱として機能するため、回路部品2が受けるダメージをより効果的に抑制できるとともに、回路部品2の端子電極6a,6bと配線パターン14a,14bとの間の容量値の安定化を図ることができる。   Furthermore, the wiring pattern 10a provided on the upper side of the circuit component 2 and the wiring pattern 16b provided on the lower side of the circuit component 2 are connected by via-hole conductors 11b, 13b, and 15b. These via-hole conductors 11b, 13b, and 15b function as pillars of the wiring pattern 10a and the wiring pattern 16b, so that damage to the circuit component 2 can be more effectively suppressed, and the terminal electrodes 6a and 6b of the circuit component 2 The capacitance value between the wiring patterns 14a and 14b can be stabilized.

なお、このことから、回路部品の上下に設けられた配線パターン同士は、複数個所に設けられたビアホール導体を介して接続されていること(すなわち、回路部品の上下に配線パターンがあり、回路部品の周囲に複数のビアホール導体がある構造)が好ましい。   Because of this, the wiring patterns provided above and below the circuit components are connected via via-hole conductors provided at a plurality of locations (that is, there are wiring patterns above and below the circuit components. And a structure having a plurality of via-hole conductors around the periphery of the substrate.

次に、部品内蔵モジュール30の製造方法について説明する。   Next, a method for manufacturing the component built-in module 30 will be described.

(1)まず、図1(a)の断面図に示すように、所定の配線パターン10a,12a,12b,14a,14b,14c,16a,16b,18aを有する樹脂基板10,12,14,16,18を作製する。   (1) First, as shown in the sectional view of FIG. 1A, resin substrates 10, 12, 14, 16 having predetermined wiring patterns 10a, 12a, 12b, 14a, 14b, 14c, 16a, 16b, 18a. , 18 are produced.

樹脂基板10,12,14,16,18は、例えば、片面に金属箔を有する樹脂シートを用いて作製する。すなわち、樹脂シートの金属箔上に感光性レジストを塗布し、露光、現像を行い、所定のマスクパターンを形成し、マスクパターンを介して金属箔のエッチングを行った後、マスクパターンを除去することにより、樹脂シートの樹脂層11,13,15,17,19上に、金属箔を用いて所定形状の配線パターン10a,12a,12b,14a,14b,14c,16a,16b,18aを形成する。樹脂シート上に、インクジェットやメッキによって、配線パターンを形成してもよい。   The resin substrates 10, 12, 14, 16, and 18 are produced using, for example, a resin sheet having a metal foil on one side. That is, a photosensitive resist is applied on the metal foil of the resin sheet, exposed and developed, a predetermined mask pattern is formed, the metal foil is etched through the mask pattern, and then the mask pattern is removed. Thus, the wiring patterns 10a, 12a, 12b, 14a, 14b, 14c, 16a, 16b, and 18a having a predetermined shape are formed on the resin layers 11, 13, 15, 17, and 19 of the resin sheet using a metal foil. A wiring pattern may be formed on the resin sheet by inkjet or plating.

また、樹脂シートにレーザー加工やドリル加工により貫通孔を形成した後、印刷等により導電性材料を貫通孔に充填して、貫通導体11a,11b,13a,13b,15a,15b,17a,17b,19a,19bを形成する。   Further, after forming a through hole in the resin sheet by laser processing or drilling, the conductive material is filled into the through hole by printing or the like, and the through conductors 11a, 11b, 13a, 13b, 15a, 15b, 17a, 17b, 19a and 19b are formed.

樹脂シートは、樹脂層11,13,15,17,19となる。樹脂シートには、加工が簡単で、加工後の変形が少ない材料が適しており、可撓性を有することが好ましい。例えば、液晶ポリマー(LCP)、ポリイミド、フッ素樹脂等の熱可塑性樹脂を用いる。特に、液晶ポリマー(LCP)は、吸水性が低く、エッチング後の変形が極めて小さいため、特に好ましい。樹脂シート上の金属箔には、所定形状の配線パターンの形成が容易な材料、例えば、銅を用いる。   The resin sheet becomes the resin layers 11, 13, 15, 17, and 19. For the resin sheet, a material that is easy to process and less deformed after processing is suitable, and preferably has flexibility. For example, a thermoplastic resin such as liquid crystal polymer (LCP), polyimide, or fluorine resin is used. In particular, a liquid crystal polymer (LCP) is particularly preferable because of its low water absorption and extremely small deformation after etching. For the metal foil on the resin sheet, a material that can easily form a wiring pattern having a predetermined shape, such as copper, is used.

(2)次いで、ICチップやコンデンサ等の内蔵すべき回路部品2を、所定の樹脂基板12の所定位置に搭載し、固定材80を用いて固定する。   (2) Next, the circuit component 2 to be incorporated, such as an IC chip or a capacitor, is mounted at a predetermined position on a predetermined resin substrate 12 and fixed using a fixing material 80.

固定材80は、内蔵する回路部品2側に塗布しても、樹脂基板12側に塗布しても、それらの両方に塗布してもよい。樹脂基板12側に塗布する場合、回路部品2を搭載する領域よりも広い一定範囲の領域に、あるいは樹脂基板12の全面に塗布すると、塗布作業が容易になる。固定材80は、回路部品2の端子電極6a,6bに塗布してもよい。固定材80は、回路部品2の本体4のみに塗布し、端子電極6a,6bには塗布しないようにしてもよい。   The fixing member 80 may be applied to the built-in circuit component 2 side, the resin substrate 12 side, or both of them. In the case of applying to the resin substrate 12 side, the application work is facilitated by applying to a certain range wider than the area where the circuit component 2 is mounted or to the entire surface of the resin substrate 12. The fixing member 80 may be applied to the terminal electrodes 6a and 6b of the circuit component 2. The fixing member 80 may be applied only to the main body 4 of the circuit component 2 and may not be applied to the terminal electrodes 6a and 6b.

固定材80は、樹脂基板12に対して位置がずれないように回路部品2を固定することができればよく、一般的なエポキシ系やアクリル系の接着材を用いることもできる。   The fixing member 80 only needs to be able to fix the circuit component 2 so that the position thereof does not shift with respect to the resin substrate 12, and a general epoxy or acrylic adhesive can also be used.

固定材80には、固定時に粘性が高い液体を用いてもよい。   For the fixing member 80, a liquid having a high viscosity at the time of fixing may be used.

あるいは、回路部品2を樹脂基板12に配置するときには粘性が高くないが、配置後に温度を下げると、粘性が高くなり、あるいは固化して、回路部品2を固定できるものでもよい。この場合には、固定材80を塗布して回路部品2を樹脂基板12の所定位置に配置した後、温度を下げて回路部品2を樹脂基板12に固定した状態で、後の積層工程を行う。例えば、凝固点が60℃前後の固定材80を用い、常温よりも高い温度(例えば80℃)で、液状の固定材80を樹脂基板12に塗布して回路部品2を搭載した後、常温に戻して固定材80を固化させて部品2を固定した状態で、樹脂基板10,12,14,16,18を積層して積層体を形成する。   Alternatively, the viscosity is not high when the circuit component 2 is arranged on the resin substrate 12, but the viscosity may be increased or solidified to fix the circuit component 2 when the temperature is lowered after the arrangement. In this case, after applying the fixing material 80 and arranging the circuit component 2 at a predetermined position on the resin substrate 12, the subsequent lamination process is performed in a state where the temperature is lowered and the circuit component 2 is fixed to the resin substrate 12. . For example, using a fixing material 80 having a freezing point of around 60 ° C., applying the liquid fixing material 80 to the resin substrate 12 at a temperature higher than normal temperature (for example, 80 ° C.) and mounting the circuit component 2, then returning to normal temperature. In a state where the fixing member 80 is solidified and the component 2 is fixed, the resin substrates 10, 12, 14, 16, and 18 are stacked to form a stacked body.

固定材80は、部品内蔵モジュール30の内部に残るとクラック発生等の不具合の原因となる可能性があるので、後工程で樹脂基板10,12,14,16,18を積層した後、加熱・圧着する前に消失するものが好ましい。例えば、水よりも粘性が高く、加熱圧着工程での加熱温度(例えば、約300℃)よりも低い温度(例えば、約200℃)で消失する、エチレングリコール、グリセリン、オリゴマ等の有機溶剤を、固定材80に用いることができる。有機溶剤は、気化しやくす、消失しやすいため、作業が容易になる。   If the fixing material 80 remains inside the component built-in module 30, there is a possibility of causing problems such as cracks. Therefore, after the resin substrates 10, 12, 14, 16, 18 are laminated in a subsequent process, Those that disappear before the pressure bonding are preferred. For example, an organic solvent such as ethylene glycol, glycerin, oligomer, etc., which has a higher viscosity than water and disappears at a temperature (for example, about 200 ° C.) lower than the heating temperature (for example, about 300 ° C.) in the thermocompression bonding process, The fixing material 80 can be used. Since the organic solvent is easily vaporized and easily disappears, the operation becomes easy.

(3)次いで、樹脂基板10,12,14,16,18を所定の順序で積み重ねて積層体を形成し、積層体を積層方向に押圧し、真空引きした状態で、樹脂基板10,12,14,16,18の樹脂層11,13,15,17,19のガラス転移温度を超えない温度(例えば、300℃)まで加熱し、樹脂層11,13,15,17,19の熱可塑性樹脂を軟化させ、樹脂層11,13,15,17,19を圧着する。このとき、回路部品2に重ねられる樹脂層11は、軟化して、回路部品2を包み込むように変形する。   (3) Next, the resin substrates 10, 12, 14, 16 and 18 are stacked in a predetermined order to form a laminate, and the laminate is pressed in the stacking direction and evacuated, and then the resin substrates 10, 12, The thermoplastic resin of the resin layers 11, 13, 15, 17, 19 is heated to a temperature not exceeding the glass transition temperature of the resin layers 11, 13, 15, 17, 19 of the 14, 16, 18 (eg, 300 ° C.). Is softened and the resin layers 11, 13, 15, 17, 19 are pressure-bonded. At this time, the resin layer 11 superimposed on the circuit component 2 is softened and deformed so as to wrap around the circuit component 2.

前述したように、固定材80は、積層体を加熱・圧着する前に気化し、消失していることが好ましい。   As described above, it is preferable that the fixing material 80 is vaporized and disappears before the laminated body is heated and pressed.

また、図1(a)に示すように、回路部品2を包み込む樹脂層11には、回路部品2の形状に相当する開口部11kが形成されていることが好ましい。開口部11kを設けておき、積層時に回路部品2を開口部11k内に収容することにより、開口部11kを有していない場合に比べて、積層時に回路部品2の体積排除効果による樹脂層11の変形を抑えることができる。   Further, as illustrated in FIG. 1A, it is preferable that an opening 11 k corresponding to the shape of the circuit component 2 is formed in the resin layer 11 that wraps the circuit component 2. By providing the opening part 11k and accommodating the circuit component 2 in the opening part 11k at the time of stacking, the resin layer 11 due to the volume exclusion effect of the circuit part 2 at the time of stacking compared to the case where the opening part 11k is not provided. Can be prevented from being deformed.

(4)次いで、加熱・圧着後、必要に応じて、配線パターン10a,18aのエッチングやめっき等を行って、部品内蔵モジュール30が完成する。例えば、部品内蔵モジュール30の配線パターン10aに表面実装型部品を搭載してもよい。   (4) Next, after heating and pressure bonding, if necessary, the wiring patterns 10a and 18a are etched or plated to complete the component built-in module 30. For example, a surface mount type component may be mounted on the wiring pattern 10 a of the component built-in module 30.

以上の工程により、樹脂層11,13,15,17,19が熱可塑性樹脂である樹脂基板10,12,14,16,18を用いて、部品内蔵モジュール30を製造することができる。   Through the above steps, the component built-in module 30 can be manufactured using the resin substrates 10, 12, 14, 16, and 18 in which the resin layers 11, 13, 15, 17, and 19 are thermoplastic resins.

<実施例2> 実施例2の部品内蔵モジュール30aについて、図2を参照しながら説明する。図2(a)は、接合前の部品内蔵モジュール30aの断面図である。図2(b)は、接合後の部品内蔵モジュール30aの断面図である。   Second Embodiment A component built-in module 30a according to a second embodiment will be described with reference to FIG. FIG. 2A is a cross-sectional view of the component built-in module 30a before joining. FIG. 2B is a cross-sectional view of the component built-in module 30a after joining.

実施例2の部品内蔵モジュール30aは、実施例1の部品内蔵モジュール30と略同様に構成され、略同様の工程で製造することができる。以下では、実施例1と同様の構成部分には同じ符号を用い、実施例1との相違点を中心に説明する。   The component built-in module 30a according to the second embodiment is configured in substantially the same manner as the component built-in module 30 according to the first embodiment, and can be manufactured through substantially the same process. In the following description, the same reference numerals are used for the same components as in the first embodiment, and differences from the first embodiment will be mainly described.

図2に示すように、実施例2の部品内蔵モジュール30aは、基板本体32a内に内蔵される回路部品2の端子電極6a,6bが電極パターン12s,12tに接合されている。この電極パターン12s,12tは、樹脂層13を介して、配線パターン14a,14bと容量結合している。   As shown in FIG. 2, in the component built-in module 30a according to the second embodiment, the terminal electrodes 6a and 6b of the circuit component 2 built in the substrate body 32a are joined to the electrode patterns 12s and 12t. The electrode patterns 12 s and 12 t are capacitively coupled to the wiring patterns 14 a and 14 b through the resin layer 13.

回路部品2の端子電極6a,6bが接合される電極パターン12s,12tは、それぞれ、別個独立に形成され、配線パターン10a,12a,12b,14a,14b,14c,16a,16b,18aから離れている。すなわち、電極パターン12s,12tと配線パターン10a,12a,12b,14a,14b,14c,16a,16b,18aとの間には、直流電流が流れない。   The electrode patterns 12s and 12t to which the terminal electrodes 6a and 6b of the circuit component 2 are joined are formed separately and separately from the wiring patterns 10a, 12a, 12b, 14a, 14b, 14c, 16a, 16b, and 18a. Yes. That is, no direct current flows between the electrode patterns 12s and 12t and the wiring patterns 10a, 12a, 12b, 14a, 14b, 14c, 16a, 16b, and 18a.

回路部品2の端子電極6a,6bに接合された電極パターン12s,12tと配線パターン14a,14bとを容量結合すると、対向面積が増え、確実に容量結合させることができる。   When the electrode patterns 12s and 12t joined to the terminal electrodes 6a and 6b of the circuit component 2 and the wiring patterns 14a and 14b are capacitively coupled, the facing area is increased and the capacitive coupling can be reliably performed.

また、実施例1と同様に、回路部品2の端子電極6a,6bは、導電材料を介して配線パターンに接続する必要がないため、導電材料の溶融等によるショート等の危険性はない。また、回路部品2の端子電極6a,6bが狭くなっても、容易に対応することができる。また、複数の回路部品を、隙間を小さくして内蔵することもできる。   Similarly to the first embodiment, since the terminal electrodes 6a and 6b of the circuit component 2 do not need to be connected to the wiring pattern through the conductive material, there is no danger of short-circuiting due to melting of the conductive material. Moreover, even if the terminal electrodes 6a and 6b of the circuit component 2 become narrow, it can be easily handled. Also, a plurality of circuit components can be incorporated with a small gap.

次に、部品内蔵モジュール30aの製造方法について説明する。   Next, a manufacturing method of the component built-in module 30a will be described.

(1)実施例1と同様に、まず、図2(a)の断面図に示すように、所定の配線パターン10a,12a,12b,14a,14b,14c,16a,16b,18aと電極パターン12s,12tと貫通導体11a,11b,13a,13b,15a,15b,17a,17b,19a,19bとを有する樹脂基板10,12,14,16,18を作製する。樹脂基板10,12,14,16,18は、例えば片面に金属箔を有する熱可塑性樹脂の樹脂シートを用いて形成する。本実施例では金属箔として銅箔を使用し、配線パターン10a,12a,12b,14a,14b,14c,16a,16b,18aと電極パターン12s,12tがCuよりなる場合について、記載する。   (1) As in the first embodiment, first, as shown in the sectional view of FIG. 2A, predetermined wiring patterns 10a, 12a, 12b, 14a, 14b, 14c, 16a, 16b, 18a and an electrode pattern 12s. , 12t and the through conductors 11a, 11b, 13a, 13b, 15a, 15b, 17a, 17b, 19a, 19b are produced. The resin substrates 10, 12, 14, 16, and 18 are formed using, for example, a thermoplastic resin sheet having a metal foil on one side. In this embodiment, a case where copper foil is used as the metal foil and the wiring patterns 10a, 12a, 12b, 14a, 14b, 14c, 16a, 16b, 18a and the electrode patterns 12s, 12t are made of Cu will be described.

回路部品2の端子電極6a,6bを接合する電極パターン12s,12tは、配線パターン10a,12a,12b,14a,14b,14c,16a,16b,18aと同じ方法で形成された後、電極パターン12s,12t上にスパッタリングやメッキ等により、例えばAu又はSnの薄膜12p,12qを形成して、電極パターン12s,12tを被覆される。   The electrode patterns 12s and 12t for joining the terminal electrodes 6a and 6b of the circuit component 2 are formed by the same method as the wiring patterns 10a, 12a, 12b, 14a, 14b, 14c, 16a, 16b, and 18a, and then the electrode pattern 12s. , 12t, for example, Au or Sn thin films 12p, 12q are formed by sputtering, plating, or the like to cover the electrode patterns 12s, 12t.

(2)次いで、ICチップ等の内蔵すべき回路部品2を、実施例1と同様に固定材82を用いて、固定する。このとき、回路部品2の端子電極6a,6bが電極パターン12s,12t上の薄膜12p,12qに対向し、好ましくは接するように、回路部品2を固定する。   (2) Next, the circuit component 2 to be built in such as an IC chip is fixed using the fixing material 82 as in the first embodiment. At this time, the circuit component 2 is fixed so that the terminal electrodes 6a and 6b of the circuit component 2 are opposed to and preferably in contact with the thin films 12p and 12q on the electrode patterns 12s and 12t.

(3)次いで、樹脂基板10,12,14,16,18を所定の順序で積み重ねて積層体を形成し、積層体を積層方向に分離しない程度に軽く押圧し、真空引きした状態で、樹脂基板10,12,14,16,18の樹脂層11,13,15,17,19の熱可塑性樹脂のガラス転移温度を超えない温度(例えば、300℃)まで加熱し、樹脂層11,13,15,17,19の熱可塑性樹脂を軟化させ、樹脂層11,13,15,17,19同士を圧着する。   (3) Next, the resin substrates 10, 12, 14, 16, and 18 are stacked in a predetermined order to form a laminated body, lightly pressed to such an extent that the laminated body is not separated in the laminating direction, and the resin is evacuated. The resin layers 11, 13, 15, 19 of the substrates 10, 12, 14, 16, 18 are heated to a temperature that does not exceed the glass transition temperature of the thermoplastic resin (for example, 300 ° C.). The thermoplastic resins 15, 17, and 19 are softened, and the resin layers 11, 13, 15, 17, and 19 are pressed together.

固定材82は、積層体を加熱・圧着する前に気化し、消失していることが好ましい。   It is preferable that the fixing material 82 is vaporized and disappears before the laminated body is heated and pressed.

接触している回路部品2の端子電極6a,6bの表面の金属(例えば、Au)と樹脂基板12の電極パターン12s,12t上の薄膜12p,12qの金属(例えば、Au又はSn)とは、加熱により、固相拡散接合し、回路部品2の端子電極6a,6bと電極パターン12s,12tとが固着する。固相拡散接合により形成された合金層は、樹脂基板10,12,14,16,18の加熱温度では溶融しないので、樹脂基板10,12,14,16,18の加熱時にショート等が発生することはない。   The metal (for example, Au) on the surface of the terminal electrodes 6a and 6b of the circuit component 2 that is in contact and the metal (for example, Au or Sn) of the thin films 12p and 12q on the electrode patterns 12s and 12t of the resin substrate 12 are: By heating, solid phase diffusion bonding is performed, and the terminal electrodes 6a and 6b of the circuit component 2 and the electrode patterns 12s and 12t are fixed. Since the alloy layer formed by solid phase diffusion bonding does not melt at the heating temperature of the resin substrates 10, 12, 14, 16, 18, a short circuit occurs when the resin substrates 10, 12, 14, 16, 18 are heated. There is nothing.

(4)次いで、加熱・圧着後に、必要に応じて、配線パターン10a,18aのエッチングやめっき等を行って、部品内蔵モジュール30aが完成する。   (4) Next, after heating and pressure bonding, the wiring patterns 10a and 18a are etched or plated as necessary to complete the component built-in module 30a.

以上の工程により、樹脂層11,13,15,17,19が熱可塑性樹脂である樹脂基板10,12,14,16,18を用いて、部品内蔵モジュール30aを製造することができる。   Through the above steps, the component built-in module 30a can be manufactured using the resin substrates 10, 12, 14, 16, and 18 in which the resin layers 11, 13, 15, 17, and 19 are thermoplastic resins.

なお、本実施例において電極パターン12s,12t上に薄膜12p,12qを形成しなくても良い。すなわち、Cuよりなる電極パターン12s,12tと回路部品2の端子電極6a,6bとを直接、固相拡散接合させても良い。   In this embodiment, the thin films 12p and 12q may not be formed on the electrode patterns 12s and 12t. That is, the electrode patterns 12s and 12t made of Cu and the terminal electrodes 6a and 6b of the circuit component 2 may be directly solid-phase diffusion bonded.

<実施例3> 実施例3の部品内蔵モジュール30bについて、図3を参照しながら説明する。図3(a)は、接合前の部品内蔵モジュール30bの断面図である。図3(b)は、接合後の部品内蔵モジュール30bの断面図である。   <Example 3> The component built-in module 30b of Example 3 is demonstrated referring FIG. FIG. 3A is a cross-sectional view of the component built-in module 30b before joining. FIG. 3B is a cross-sectional view of the component built-in module 30b after joining.

実施例3の部品内蔵モジュール30bは、実施例1、2の部品内蔵モジュールと略同様に構成され、略同様の工程で製造することができる。以下では、実施例1、2と同様の構成部分には同じ符号を用い、実施例1、2との相違点を中心に説明する。   The component built-in module 30b according to the third embodiment is configured in substantially the same manner as the component built-in module according to the first and second embodiments, and can be manufactured through substantially the same process. Below, the same code | symbol is used for the component similar to Example 1, 2, and it demonstrates centering around difference with Example 1,2.

回路基板40は、半導体基板41の最上層配線42の周囲にパッシベーション膜44が形成され、最上層配線42とその周囲のパッシベーション膜44上に端子電極46が形成され、端子電極46は誘電体層48で覆われている。回路部品40の端子電極46は、実施例1、2と異なり、誘電体層48を介して、電極パターン12s,12tと容量結合している。電極パターン12s,12tは樹脂層13を介して配線パターン14a,14bと容量結合を形成していても良いし、他の電極パターン(例えば12a,21b)と直流電流が流れるように接続されていても良い。   In the circuit board 40, a passivation film 44 is formed around the uppermost layer wiring 42 of the semiconductor substrate 41, a terminal electrode 46 is formed on the uppermost layer wiring 42 and the surrounding passivation film 44, and the terminal electrode 46 is a dielectric layer. 48. Unlike the first and second embodiments, the terminal electrode 46 of the circuit component 40 is capacitively coupled to the electrode patterns 12 s and 12 t through the dielectric layer 48. The electrode patterns 12s and 12t may form capacitive coupling with the wiring patterns 14a and 14b via the resin layer 13, and are connected to other electrode patterns (for example, 12a and 21b) so that a direct current flows. Also good.

半導体基板41の最上層配線42がパッシベーション膜44を介してパッシベーション膜44上に引き出されており、最上層配線42の面積に比べて端子電極46の面積を大きくすることができ、しかも、厚み1μm〜50μm程度の薄膜の誘電体層48を介して配線パターン12s,12tを容量結合しているので、その容量値を大きくすることができる。   The uppermost layer wiring 42 of the semiconductor substrate 41 is drawn on the passivation film 44 through the passivation film 44, and the area of the terminal electrode 46 can be made larger than the area of the uppermost layer wiring 42, and the thickness is 1 μm. Since the wiring patterns 12s and 12t are capacitively coupled via the thin dielectric layer 48 of about ˜50 μm, the capacitance value can be increased.

次に、部品内蔵モジュール30bの製造方法について説明する。   Next, a manufacturing method of the component built-in module 30b will be described.

(1)図3(a)の断面図に示すように、まず、所定の配線パターン10a,12a,12b,14a,14b,14c,16a,16b,18aと電極パターン12s,12tと貫通導体11a,11b,13a,13b,15a,15b,17a,17b,19a,19bとを有する樹脂基板10,12,14,16,18を用意する。樹脂基板10,12,14,16,18は、例えば片面に金属箔を有する熱可塑性樹脂の樹脂シートを用いて形成する。   (1) As shown in the sectional view of FIG. 3A, first, predetermined wiring patterns 10a, 12a, 12b, 14a, 14b, 14c, 16a, 16b, 18a, electrode patterns 12s, 12t, and through conductors 11a, Resin substrates 10, 12, 14, 16, 18 having 11b, 13a, 13b, 15a, 15b, 17a, 17b, 19a, 19b are prepared. The resin substrates 10, 12, 14, 16, and 18 are formed using, for example, a thermoplastic resin sheet having a metal foil on one side.

(2)次いで、端子電極46が誘電体層48で覆われた回路部品40を、樹脂基板12の電極パターン12s,12tに搭載し、固定材84を用いて固定する。   (2) Next, the circuit component 40 in which the terminal electrode 46 is covered with the dielectric layer 48 is mounted on the electrode patterns 12 s and 12 t of the resin substrate 12 and fixed using the fixing material 84.

固定材84は、回路部品40を、樹脂基板12の樹脂層13に固定しなくてもかまわない。たとえば、回路部品40の最上層配線42付近のできるスペース(くぼみ)に接着剤を充填しておき、この接着剤を利用して、回路部品40を樹脂基板12の配線パターン12s,12tにのみ固定してもよい。   The fixing member 84 does not need to fix the circuit component 40 to the resin layer 13 of the resin substrate 12. For example, an adhesive is filled in a space (indentation) in the vicinity of the uppermost layer wiring 42 of the circuit component 40, and the circuit component 40 is fixed only to the wiring patterns 12s and 12t of the resin substrate 12 by using this adhesive. May be.

(3)次いで、樹脂基板10,12,14,16,18を所定の順序で積み重ねて積層体を形成し、積層体を積層方向に分離しない程度に軽く押圧し、真空引きした状態で、樹脂基板10,12,14,16,18の樹脂層11,13,15,17,19の熱可塑性樹脂のガラス転移温度を超えない温度(例えば、300℃)まで加熱し、樹脂層11,13,15,17,19の熱可塑性樹脂を軟化させ、樹脂層11,13,15,17,19同士を接合する。   (3) Next, the resin substrates 10, 12, 14, 16, and 18 are stacked in a predetermined order to form a laminated body, lightly pressed to such an extent that the laminated body is not separated in the laminating direction, and the resin is evacuated. The resin layers 11, 13, 15, 19 of the substrates 10, 12, 14, 16, 18 are heated to a temperature that does not exceed the glass transition temperature of the thermoplastic resin (for example, 300 ° C.). The thermoplastic resins 15, 17, and 19 are softened, and the resin layers 11, 13, 15, 17, and 19 are joined to each other.

固定材84は、積層体を加熱・圧着する前に気化し、消失してもよい。   The fixing member 84 may vaporize and disappear before the laminated body is heated and pressure-bonded.

(4)次いで、加熱・圧着後、必要に応じて、配線パターン10a,18aのめっき等を行って、部品内蔵モジュール30bが完成する。   (4) Next, after heating and pressure bonding, the wiring patterns 10a and 18a are plated as necessary to complete the component built-in module 30b.

以上の工程により、樹脂層11,13,15,17,19が熱可塑性樹脂である樹脂基板10,12,14,16,18を用いて、部品内蔵モジュール30bを製造することができる。   Through the above steps, the component built-in module 30b can be manufactured using the resin substrates 10, 12, 14, 16, and 18 in which the resin layers 11, 13, 15, 17, and 19 are thermoplastic resins.

<実施例4> 実施例4の部品内蔵モジュール70について、図4及び図5を参照しながら説明する。図4は、接合前の部品内蔵モジュール70の断面図である。図5は、接合後の部品内蔵モジュール70の断面図である。   <Example 4> The component built-in module 70 of Example 4 is demonstrated referring FIG.4 and FIG.5. FIG. 4 is a cross-sectional view of the component built-in module 70 before joining. FIG. 5 is a cross-sectional view of the component built-in module 70 after joining.

実施例4の部品内蔵モジュールは、実施例1〜3とは異なり、樹脂層51,53,55,57,59,61,63が熱硬化性樹脂である樹脂基板50,52,54,56,58,60,62を用いる。   In the component built-in module according to the fourth embodiment, unlike the first to third embodiments, the resin layers 51, 53, 55, 57, 59, 61, 63 are resin substrates 50, 52, 54, 56, which are thermosetting resins. 58, 60, 62 are used.

図5の断面図に示すように、部品内蔵モジュール70は、熱硬化性樹脂の樹脂層51,53,55,57,59,61,63が接合された基板本体72の内部や表面に、配線パターン50a,56a,56b,58a,58b,58c,60a,60b,62a、電極パターン56s,56t、貫通導体51a,51b,59a,59b,61a,61b,63a,63bが形成され、基板本体72の内部にICチップやコンデンサ等の回路部品2が配置されている。   As shown in the cross-sectional view of FIG. 5, the component built-in module 70 is connected to the inside or the surface of the substrate body 72 to which the thermosetting resin layers 51, 53, 55, 57, 59, 61, 63 are bonded. Patterns 50a, 56a, 56b, 58a, 58b, 58c, 60a, 60b, 62a, electrode patterns 56s, 56t, through conductors 51a, 51b, 59a, 59b, 61a, 61b, 63a, 63b are formed. A circuit component 2 such as an IC chip or a capacitor is disposed inside.

部品内蔵モジュール70に内蔵される回路部品2の端子電極6a,6bは、電極パターン56s,56tに接合され、この電極パターン56s,56tが、樹脂層57を介して、配線パターン58a,58bと容量結合している。   The terminal electrodes 6a and 6b of the circuit component 2 built in the component built-in module 70 are joined to the electrode patterns 56s and 56t, and the electrode patterns 56s and 56t are connected to the wiring patterns 58a and 58b and the capacitance via the resin layer 57. Are connected.

回路部品2の端子電極6a,6bが接合される電極パターン56s,56tは、それぞれ、別個独立に形成され、配線パターン50a,56a,56b,58a,58b,58c,60a,60b,62aから離れている。すなわち、電極パターン56s,56tと配線パターン50a,56a,56b,58a,58b,58c,60a,60b,62aとの間には、直流電流が流れない。   The electrode patterns 56s and 56t to which the terminal electrodes 6a and 6b of the circuit component 2 are joined are formed separately and independently from the wiring patterns 50a, 56a, 56b, 58a, 58b, 58c, 60a, 60b, and 62a. Yes. That is, no direct current flows between the electrode patterns 56s and 56t and the wiring patterns 50a, 56a, 56b, 58a, 58b, 58c, 60a, 60b, and 62a.

このように回路部品2の端子電極6a,6bに接合された電極パターン56s,56tと配線パターン58a,58bとが容量結合していると、回路部品2の端子電極は、貫通導体を介して配線パターンに接続する必要がないため、導電材料の溶融等によるショート等の危険性はない。また、回路部品2の端子電極6a,6bが狭くなっても、容易に対応することができる。また、複数の回路部品を、隙間を小さくして内蔵することもできる。   When the electrode patterns 56s and 56t joined to the terminal electrodes 6a and 6b of the circuit component 2 and the wiring patterns 58a and 58b are capacitively coupled as described above, the terminal electrodes of the circuit component 2 are wired via the through conductors. Since there is no need to connect to the pattern, there is no danger of a short circuit due to melting of the conductive material. Moreover, even if the terminal electrodes 6a and 6b of the circuit component 2 become narrow, it can be easily handled. Also, a plurality of circuit components can be incorporated with a small gap.

次に、部品内蔵モジュール70の製造方法について説明する。   Next, a method for manufacturing the component built-in module 70 will be described.

(1)図4の断面図に示すように、所定の配線パターン50a,56a,56b,58a,58b,58c,60a,60b,62aと、電極パターン56s,56tと、貫通導体51a,51b,59a,59b,61a,61b,63a,63bとを有する樹脂基板50,52,54,56,58,60,62を作製する。   (1) As shown in the sectional view of FIG. 4, predetermined wiring patterns 50a, 56a, 56b, 58a, 58b, 58c, 60a, 60b, 62a, electrode patterns 56s, 56t, and through conductors 51a, 51b, 59a , 59b, 61a, 61b, 63a, 63b, resin substrates 50, 52, 54, 56, 58, 60, 62 are produced.

配線パターン50a,56a,56b,58a,58b,58c,60a,60b,62aや電極パターン56s,56tは、例えば片面に銅等の金属箔を有する樹脂シートを準備し、金属箔上に感光性レジストを塗布し、露光、現像を行い、所定のマスクパターンを形成し、マスクパターンを介してエッチングを行った後、マスクパターンを除去することにより形成する。樹脂シート上に、インクジェットやメッキによって、配線パターンを形成してもよい。   For the wiring patterns 50a, 56a, 56b, 58a, 58b, 58c, 60a, 60b, 62a and the electrode patterns 56s, 56t, for example, a resin sheet having a metal foil such as copper on one side is prepared, and a photosensitive resist is formed on the metal foil. Is applied, exposed and developed to form a predetermined mask pattern, etched through the mask pattern, and then removed by removing the mask pattern. A wiring pattern may be formed on the resin sheet by inkjet or plating.

貫通導体51a,51b,59a,59b,61a,61b,63a,63bは、樹脂シートにレーザー加工やドリル加工により貫通孔を形成し、印刷等により導電性材料を充填することにより形成する。   The through conductors 51a, 51b, 59a, 59b, 61a, 61b, 63a, and 63b are formed by forming a through hole in a resin sheet by laser processing or drilling and filling a conductive material by printing or the like.

貫通孔53s,55sは、金型を用いた打ち抜き加工やレーザー加工によって形成する。   The through holes 53s and 55s are formed by punching using a mold or laser processing.

樹脂シートは、樹脂層51,53,55,57,59,61,63になる。樹脂シートには、加工が簡単で、加工後の変形が少ない材料が適しており、例えば、エポキシ等の熱硬化性樹脂を用いる。必要に応じて、樹脂シートにフィラーを添加してもよい。   The resin sheet becomes the resin layers 51, 53, 55, 57, 59, 61, 63. For the resin sheet, a material that is easy to process and has little deformation after processing is suitable. For example, a thermosetting resin such as epoxy is used. You may add a filler to a resin sheet as needed.

回路部品2を搭載する樹脂基板56の電極パターン56s,56t上には、スパッタリングやメッキにより、Au又はSnの薄膜56p,56qを形成する。   Au or Sn thin films 56p and 56q are formed on the electrode patterns 56s and 56t of the resin substrate 56 on which the circuit component 2 is mounted by sputtering or plating.

(2)次いで、ICチップやコンデンサ等の内蔵すべき回路部品2を、樹脂基板56の電極パターン56s,56tに配置し、固定材86を用いて固定する。このとき、回路部品2の端子電極6a,6bと樹脂基板56の電極パターン56s,56t上の薄膜56p、56qとが対向し、好ましくは接するようにする。   (2) Next, the circuit component 2 to be built in such as an IC chip or a capacitor is disposed on the electrode patterns 56 s and 56 t of the resin substrate 56 and fixed using a fixing material 86. At this time, the terminal electrodes 6a and 6b of the circuit component 2 and the thin films 56p and 56q on the electrode patterns 56s and 56t of the resin substrate 56 face each other, and preferably contact each other.

固定材86は、樹脂基板に対して位置がずれないように部品を固定することができればよく、一般的なエポキシ系やアクリル系の接着材を用いることができる。固定材86は、後述する積層工程の後、加熱・圧着工程の前に消失するものでもよい。   The fixing material 86 only needs to be able to fix components so that the position thereof does not shift with respect to the resin substrate, and a general epoxy or acrylic adhesive can be used. The fixing material 86 may disappear after the laminating process described later and before the heating / crimping process.

(3)次いで、樹脂基板52,54,56,58,60,62を所定の順序で積み重ねて積層体を形成し、積層体を積層方向に加圧し、真空引きした状態で、樹脂基板50,52,54,56,58,60,62の熱硬化性樹脂の硬化温度(例えば、200℃)まで加熱し、樹脂層51,53,55,57,59,61,63が互いに圧着した状態で熱硬化性樹脂を硬化させる。   (3) Next, the resin substrates 52, 54, 56, 58, 60, 62 are stacked in a predetermined order to form a laminate, and the laminate is pressurized in the stacking direction and evacuated, In the state where the resin layers 51, 53, 55, 57, 59, 61, 63 are pressure-bonded to each other by heating to the curing temperature (for example, 200 ° C.) of the thermosetting resin of 52, 54, 56, 58, 60, 62. The thermosetting resin is cured.

このとき、貫通孔53s,55sを形成した樹脂基板52,54の樹脂層53,55は、回路部品2の周りに流れ込み、回路部品2の周囲を取り囲む。   At this time, the resin layers 53 and 55 of the resin substrates 52 and 54 in which the through holes 53 s and 55 s are formed flow around the circuit component 2 and surround the circuit component 2.

また、回路部品2の端子電極6a,6bの表面の金属(例えば、Au)と樹脂基板12の電極パターン12s,12t上の薄膜12p,12qの金属(例えば、Au又はSn)とが接触し、加熱により、界面近傍領域において溶融し、回路部品2の端子電極6a,6bと電極パターン12s,12tとが固着する。   Further, the metal (for example, Au) on the surface of the terminal electrodes 6a, 6b of the circuit component 2 and the metal (for example, Au or Sn) of the thin films 12p, 12q on the electrode patterns 12s, 12t of the resin substrate 12 come into contact. By heating, it melts in the vicinity of the interface, and the terminal electrodes 6a and 6b of the circuit component 2 and the electrode patterns 12s and 12t are fixed.

(4)次いで、加熱・圧着後、必要に応じて配線パターン50a,62aにエッチングやめっき等を行って、部品内蔵モジュール70が完成する。   (4) Next, after heating and pressure bonding, the wiring patterns 50a and 62a are etched or plated as necessary to complete the component built-in module 70.

以上の工程により、樹脂層51,53,55,57,59,61,63が熱硬化性樹脂である樹脂基板50,52,54,56,58,60,62を用いて、部品内蔵モジュール70を製造することができる。   Through the above steps, the component built-in module 70 is formed by using the resin substrates 50, 52, 54, 56, 58, 60, 62 in which the resin layers 51, 53, 55, 57, 59, 61, 63 are thermosetting resins. Can be manufactured.

<まとめ> 以上のように、回路部品の端子電極と配線パターンとの間を容量結合することにより、回路部品の端子電極は、加熱により再溶融する半田等の導電材料を介して配線パターンに接続する必要がなくなるため、導電材料の溶融等によるショート等の危険性はなく、電極の狭ピッチ化にも容易に対応できる。   <Summary> As described above, the terminal electrode of the circuit component is connected to the wiring pattern through a conductive material such as solder that is remelted by heating by capacitively coupling the terminal electrode of the circuit component and the wiring pattern. Therefore, there is no danger of a short circuit due to melting of the conductive material, and it is possible to easily cope with the narrow pitch of the electrodes.

なお、本発明は、上記実施の形態に限定されるものではなく、種々変更を加えて実施することが可能である。   The present invention is not limited to the above embodiment, and can be implemented with various modifications.

例えば、基板本体に内蔵される回路部品の端子電極と容量結合する配線パターンが、基板本体に内蔵されずに外部に露出してもよい。   For example, a wiring pattern that capacitively couples with a terminal electrode of a circuit component built in the board body may be exposed to the outside without being built in the board body.

また、複数の樹脂基板を圧着した積層体に、さらに他の樹脂基板や積層体を接合して、部品内蔵モジュールを作製してもよい。   Further, a component built-in module may be manufactured by further bonding another resin substrate or a laminate to a laminate obtained by pressure bonding a plurality of resin substrates.

また、回路部品(半導体基板等)を樹脂層に固定するための固定材は、回路部品の端子電極が設けられている側ではなく、端子電極が設けられていない側(半導体基板であれば、最上層配線が設けられている側ではなく、半導体基板の天面側)で固定してもよい。このように、回路部品を上下反転させて樹脂層表面に固定し、さらにこの上に、容量結合するための配線パターンを有する樹脂層を積み重ねていくことにより、回路部品の端子電極と前記配線パターンとを容量結合させることも可能である。   Further, the fixing material for fixing the circuit component (semiconductor substrate or the like) to the resin layer is not the side where the terminal electrode of the circuit component is provided, but the side where the terminal electrode is not provided (if it is a semiconductor substrate, It may be fixed not on the side where the uppermost layer wiring is provided but on the top surface side of the semiconductor substrate. In this way, the circuit component is turned upside down and fixed to the surface of the resin layer, and further, a resin layer having a wiring pattern for capacitive coupling is stacked thereon, whereby the terminal electrode of the circuit component and the wiring pattern are stacked. Can also be capacitively coupled.

また、回路部品を包み込む樹脂層に、回路部品の形状に相当する開口部が形成されている場合、まず、樹脂層中の開口部(キャビティ部)の底面および/または側面に固定材を設けておき、ここに回路部品を収容した後、順次、他の樹脂層と積層、圧着してもよい。特に、この場合、回路部品の端子電極が設けられていない側(半導体基板であれば、最上層配線が設けられている側ではなく、半導体基板の天面側)で固定することが好ましい。   Further, when an opening corresponding to the shape of the circuit component is formed in the resin layer that wraps the circuit component, first, a fixing material is provided on the bottom surface and / or the side surface of the opening (cavity portion) in the resin layer. Alternatively, after the circuit component is accommodated here, it may be sequentially laminated and pressure-bonded with another resin layer. In particular, in this case, it is preferable to fix the circuit component on the side where the terminal electrodes are not provided (in the case of a semiconductor substrate, not on the side where the uppermost layer wiring is provided, but on the top surface side of the semiconductor substrate).

2 回路部品
4 本体
6a,6b 端子電極
10,12,14,16,18 樹脂基板
12s,12t 電極パターン(電極)
12p,12q 薄膜
14a,14b 配線パターン
11,13,15,17,19 樹脂層
30,30a,30b 部品内蔵モジュール
32,32a,32b 基板本体
40 回路部品
46 端子電極
50,52,54,56,58,60,62 樹脂基板
56s,56t 電極パターン(電極)
56p,56q 薄膜
58a,58b 配線パターン
51,53,55,57,59,61,63 樹脂層
70 部品内蔵モジュール
72 基板本体
80,82,84,86 固定材
2 Circuit parts 4 Body 6a, 6b Terminal electrode 10, 12, 14, 16, 18 Resin substrate 12s, 12t Electrode pattern (electrode)
12p, 12q thin film 14a, 14b wiring pattern 11, 13, 15, 17, 19 resin layer 30, 30a, 30b component built-in module 32, 32a, 32b substrate body 40 circuit component 46 terminal electrode 50, 52, 54, 56, 58 , 60, 62 Resin substrate 56s, 56t Electrode pattern (electrode)
56p, 56q thin film 58a, 58b wiring pattern 51, 53, 55, 57, 59, 61, 63 resin layer 70 component built-in module 72 substrate main body 80, 82, 84, 86 fixing material

Claims (6)

複数の樹脂層が接合された基板本体と、
端子電極と前記端子電極を覆う誘電体層とを有し、前記基板本体の内部に配置された回路部品と、
少なくとも1層の前記樹脂層の主面に接して配置された配線パターンと、
を備え、
前記回路部品の前記端子電極と前記配線パターンとが、前記誘電体層を介して容量結合していることを特徴とする、部品内蔵モジュール。
A substrate body to which a plurality of resin layers are bonded;
A circuit component having a terminal electrode and a dielectric layer covering the terminal electrode, and disposed inside the substrate body;
A wiring pattern disposed in contact with the main surface of at least one resin layer;
With
The component built-in module, wherein the terminal electrode of the circuit component and the wiring pattern are capacitively coupled via the dielectric layer .
前記樹脂層の主面に接して配置された配線パターンをさらに備え、
前記樹脂層の前記主面に垂直な方向から透視すると、前記配線パターンは前記回路部品を含むことを特徴とする、請求項1に記載の部品内蔵モジュール。
A wiring pattern disposed in contact with the main surface of the resin layer;
The component built-in module according to claim 1, wherein the wiring pattern includes the circuit component when seen through from a direction perpendicular to the main surface of the resin layer.
対向する一対の前記配線パターンと、
該一対の前記配線パターン間を接続するビアホール導体と、
を備え、
前記回路部品は、該一対の前記配線パターン間に配置されていることを特徴とする、請求項に記載の部品内蔵モジュール。
A pair of opposing wiring patterns;
Via-hole conductors connecting the pair of wiring patterns;
With
The component built-in module according to claim 2 , wherein the circuit component is disposed between the pair of wiring patterns.
複数の樹脂層が接合された基板本体の内部に回路部品が配置された部品内蔵モジュールの製造方法であって、
前記樹脂層の間に、端子電極と前記端子電極を覆う誘電体層とを有する回路部品を配置した状態で、前記樹脂層を積層する第1の工程と、
積層された前記樹脂層を加熱・圧着する第2の工程と、
を備え、
前記第1の工程において、前記樹脂層の間に配線パターンを配置し、該配線パターンに前記回路部品の前記誘電体層が接する状態で、前記樹脂層を積層することを特徴とする、部品内蔵モジュールの製造方法。
A method of manufacturing a component built-in module in which circuit components are arranged inside a substrate body to which a plurality of resin layers are bonded,
A first step of laminating the resin layer with a circuit component having a terminal electrode and a dielectric layer covering the terminal electrode disposed between the resin layers;
A second step of heating and pressure-bonding the laminated resin layers;
With
Wherein in the first step, a wiring pattern between the resin layer is disposed, in the state where the dielectric layer is in contact before Symbol circuit components wiring pattern, characterized by laminating the resin layer, parts Manufacturing method of built-in module.
前記第1の工程において、固定材を用いて、前記樹脂層の一方主面に前記回路部品を固定した後、前記回路部品が固定された前記樹脂層の前記一方主面に少なくとも1層の他の前記樹脂層を積層し、
前記固定材は、前記第2の工程において積層された前記樹脂層を加熱・圧着する前に、消失することを特徴とする、請求項に記載の部品内蔵モジュールの製造方法。
In the first step, after fixing the circuit component to one main surface of the resin layer using a fixing material, at least one other layer on the one main surface of the resin layer to which the circuit component is fixed Of the resin layer,
5. The method of manufacturing a component built-in module according to claim 4 , wherein the fixing material disappears before the resin layer laminated in the second step is heated and pressure-bonded.
前記固定材が有機溶剤であることを特徴とする、請求項に記載の部品内蔵モジュールの製造方法。The method of manufacturing a component built-in module according to claim 5 , wherein the fixing material is an organic solvent.
JP2010520749A 2008-07-17 2009-07-03 Component built-in module and manufacturing method thereof Active JP5110164B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2010520749A JP5110164B2 (en) 2008-07-17 2009-07-03 Component built-in module and manufacturing method thereof

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2008186389 2008-07-17
JP2008186389 2008-07-17
PCT/JP2009/003091 WO2010007736A1 (en) 2008-07-17 2009-07-03 Module with built-in component and method for manufacturing the module
JP2010520749A JP5110164B2 (en) 2008-07-17 2009-07-03 Component built-in module and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPWO2010007736A1 JPWO2010007736A1 (en) 2012-01-05
JP5110164B2 true JP5110164B2 (en) 2012-12-26

Family

ID=41550148

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010520749A Active JP5110164B2 (en) 2008-07-17 2009-07-03 Component built-in module and manufacturing method thereof

Country Status (3)

Country Link
JP (1) JP5110164B2 (en)
CN (1) CN102100131A (en)
WO (1) WO2010007736A1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010007715A1 (en) * 2008-07-17 2010-01-21 株式会社 村田製作所 Manufacturing method of a parts installation module
WO2018037628A1 (en) * 2016-08-23 2018-03-01 株式会社村田製作所 Resin multilayer substrate
CN109844935B (en) * 2016-10-28 2023-01-06 株式会社村田制作所 Electronic component device
WO2020129808A1 (en) * 2018-12-21 2020-06-25 株式会社村田製作所 Method for producing electronic component module, and electronic component module

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0758447A (en) * 1993-08-18 1995-03-03 Nippon Signal Co Ltd:The Packaging method for electronic component
JP2002246503A (en) * 2001-02-16 2002-08-30 Philips Japan Ltd Electronic component and its manufacturing method
JP2002344146A (en) * 2001-05-15 2002-11-29 Tdk Corp High frequency module and its manufacturing method

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63278399A (en) * 1987-05-11 1988-11-16 Japan Radio Co Ltd Composing method for mixed thick film circuit
JP3375555B2 (en) * 1997-11-25 2003-02-10 松下電器産業株式会社 Circuit component built-in module and method of manufacturing the same
JP4238843B2 (en) * 2005-06-21 2009-03-18 セイコーエプソン株式会社 Semiconductor chip, semiconductor chip manufacturing method, and electronic device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0758447A (en) * 1993-08-18 1995-03-03 Nippon Signal Co Ltd:The Packaging method for electronic component
JP2002246503A (en) * 2001-02-16 2002-08-30 Philips Japan Ltd Electronic component and its manufacturing method
JP2002344146A (en) * 2001-05-15 2002-11-29 Tdk Corp High frequency module and its manufacturing method

Also Published As

Publication number Publication date
JPWO2010007736A1 (en) 2012-01-05
WO2010007736A1 (en) 2010-01-21
CN102100131A (en) 2011-06-15

Similar Documents

Publication Publication Date Title
JP5195422B2 (en) Wiring board, mounting board, and electronic device
JP4424351B2 (en) Manufacturing method of three-dimensional electronic circuit device
US10083887B2 (en) Chip component-embedded resin multilayer substrate and manufacturing method thereof
US20110241203A1 (en) Semiconductor module, method for manufacturing semiconductor module, and portable apparatus
JP2006108211A (en) Wiring board, multilayered wiring circuit board using the board, and method of manufacturing the multilayered wiring circuit board
CN102789991A (en) Packaging structure and manufacturing method thereof
JP2014045026A (en) Wiring board and wiring board manufacturing method
JP2006324568A (en) Multilayer module and its manufacturing method
JP5110163B2 (en) Manufacturing method of module with built-in components
JP2009289802A (en) Module having electronic part built-in and production method thereof
JP5110164B2 (en) Component built-in module and manufacturing method thereof
US9750134B2 (en) Method for producing a printed circuit board with multilayer sub-areas in sections
JP2001230515A (en) Mounting member of electronic component, method of manufacturing mounting member of electronic component, and secondary mounting structure of mounting member
JP4276740B2 (en) Multilayer wiring board
JP2008182039A (en) Multilayer wiring board and its manufacturing method
WO2019230524A1 (en) Resin multilayer substrate and electronic device
WO2013129154A1 (en) Manufacturing method of component-internal substrate
JP2010040721A (en) Semiconductor module, semiconductor device, portable apparatus, and manufacturing method of semiconductor module, and manufacturing method of semiconductor device
JP2012089568A (en) Organic multilayer substrate and manufacturing method therefor
US9854681B2 (en) Component-embedded substrate
JP2006049536A (en) Multilayer circuit board
US9913379B2 (en) Component-embedded substrate
WO2010125858A1 (en) Multilayered resin circuit board, and manufacturing method of multilayered resin circuit board
JP2010141029A (en) Printed wiring board and method of manufacturing the same
JP5585035B2 (en) Circuit board manufacturing method

Legal Events

Date Code Title Description
A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120403

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120529

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20120911

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20120924

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20151019

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Ref document number: 5110164

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150