JP5092431B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device in which a transistor having a MOS structure such as a power MOSFET (MOS field effect transistor) is mounted on a semiconductor substrate.

  Conventionally, as this type of semiconductor device, for example, a semiconductor device in which a lateral MOS (LDMOS: Lateral Diffused Metal Oxide Semiconductor) is mounted on a semiconductor substrate, as shown in FIG. Yes. The outline of this semiconductor device will be described below with reference to FIG.

  As shown in FIG. 26, this semiconductor device is configured to have a plurality of impurity regions formed in a manner in which appropriate conductivity type impurities are added to the semiconductor substrate 100. That is, this semiconductor device basically includes a drain region 101 made of an N-type diffusion layer constituting most of the semiconductor substrate 100 and a P-type diffusion layer (near the upper surface of the semiconductor substrate 100). The channel region 102 is formed of a P well.

Here, the channel region 102 has a substrate contact portion 103 made of a P-type diffusion layer (P ⁺ ) formed with a higher concentration than the channel region 102 and an N-type formed with a higher concentration than the drain region 101. And a source region 104 made of a diffusion layer (N ⁺ ). In the drain region 101, a drain contact portion 105 made of a diffusion layer (N ⁺ ) having a concentration higher than that of the drain region 101 is formed.

  On the other hand, in the vicinity of the channel region 102 of the substrate 100, a field oxide film (LOCOS oxide film) 106 having a LOCOS structure is formed so as to isolate the channel region 102 and the drain contact portion 105 from each other. Yes. Then, a gate electrode made of, for example, polycrystalline silicon is formed on the channel region 102 so as to partially overlap the LOCOS oxide film 106 through a gate insulating film GI made of, for example, silicon oxide. 107 is formed.

  As shown in FIG. 26, the gate electrode 107 is usually covered with an insulating film ILD made of, for example, BPSG (Boron Phosphorous Silicate Glass) and insulated from the periphery thereof, and is formed on the insulating film ILD. The drive voltage input terminal Vin is electrically connected through a contact hole (not shown). Similarly, an insulating film ILD is also formed on the substrate contact portion 103 and the source region 104, and the substrate contact portion 103 and the source region 104 have contact holes (not shown) formed in the insulating film ILD. For example, the potential is grounded (GND). Further, an insulating film ILD is also formed on the drain contact portion 105, and the drain contact portion 105 is electrically connected to, for example, a circuit power supply Vc through a contact hole (not shown) formed in the insulating film ILD. Connected. In this case, normally, a load to be driven by the semiconductor device (transistor) is connected between the drain contact portion 105 and the circuit power supply Vc.

  In the semiconductor device configured as described above, a driving voltage is applied to the gate electrode 107 from the driving voltage input terminal Vin, so that the channel between the drain region 101 and the source region 104 is more accurately applied. An inversion layer is formed in the region 102 immediately below the gate electrode 107, and a current flows in the inversion layer. The amount of current flowing between the drain region 101 and the source region 104 can be made variable by adjusting the drive voltage applied to the gate electrode 107 from the drive voltage input terminal Vin.

  By the way, when manufacturing such a semiconductor device, the amount of current flowing through the channel region 102 is usually taken into consideration, for example, in consideration of an assumed size of a driving load connected to the drain region 101 (more precisely, the drain contact portion 105). The required values for the corresponding on-resistance value and switching time are obtained. Then, the total layout including the size and impurity concentration of each of the impurity regions as the semiconductor device is determined so that these required values are satisfied. However, even if the semiconductor device can be manufactured based on the layout determined in this way, the on-resistance value and the switching are changed due to a change in the connected driving load or a problem such as heat generation. It may be necessary to readjust the time. However, since the conventional semiconductor device configured as a lateral MOS has a very low degree of freedom to change such a required value, the layout size is eventually changed to meet the required value. The design was forced to change. That is, the semiconductor device itself is recreated from scratch in accordance with a change in the connected driving load.

  Note that this situation is generally common not only to semiconductor devices having the above-described lateral MOS structure but also to semiconductor devices configured as transistors having a general MOS structure.

  The present invention has been made in view of the above circumstances, and its purpose is to adjust these required values with a high degree of freedom even when readjustment of various required values is required due to, for example, a load change. An object of the present invention is to provide a semiconductor device that can cope with the change.

In order to achieve such an object, according to the first aspect of the present invention, the first and second electrodes connected so as to be interposed in the current flow path, and the first and second electrodes depending on the applied voltage. Transistors having a MOS structure having a gate electrode for controlling the current flowing between the electrodes are arranged on a semiconductor substrate in such a manner that the transistors are divided into a plurality of transistors electrically connected in parallel to the current flow path. In addition, when the plurality of divided transistors are regarded as a single transistor according to the number of transistors selectively activated based on driving information of the plurality of transistors variably set in the nonvolatile memory, as semiconductor devices, such channel width is variable in a semiconductor substrate, drive information is variably set in the nonvolatile memory, said plurality of transistors Information indicating whether or not a drive voltage can be applied to each gate electrode is information configured to have the same number of bits as the number of the plurality of transistors, and the drive information is variably set. Functions as a plurality of switching elements that are switched on / off according to the logic level of each bit constituting the same information, and the plurality of switching elements drive the driving voltages for the gate electrodes of the plurality of transistors. The lines connecting the gate electrodes and the switching elements are grounded via the pull-down resistors so as to correspond to the switching elements in the on state. A transistor for applying a driving voltage to the gate electrode is selectively activated, and the divided And a configuration in which the effective channel width when regarded the number of transistors and a single transistor is variable within a semiconductor substrate.

  According to such a configuration as the semiconductor device, even when the semiconductor device is manufactured, when the plurality of divided transistors are regarded as a single transistor through operation of drive information variably set in the nonvolatile memory The on-resistance value and switching time can be adjusted. Accordingly, for example, even when readjustment of various required values is required in accordance with a change in load, the required values can be adjusted and changed with a high degree of freedom.

In addition, the on-resistance value, switching time, and the like when the plurality of divided transistors are regarded as a single transistor can be arbitrarily adjusted through the application mode of the driving voltage to the gate electrodes of the plurality of transistors. It becomes like this.

In particular, according to the above configuration, the application mode of the drive voltage to the gate electrodes of the plurality of transistors described above can be accurately varied with a simple configuration. In this case, the plurality of divided transistors are driven by a divided value (divided voltage) between the ON resistance and the pull-down resistor of the switching element corresponding to each of the driving voltages. In that sense, the gate resistance of the plurality of divided transistors is set as a value depending on the on-resistance of each switching element.

In particular, in the configuration according to claim 1 , the nonvolatile memory is formed on the same semiconductor substrate as the semiconductor substrate on which the plurality of divided transistors are formed, for example, according to the invention according to claim 2. As a result, it becomes possible to rationalize the manufacturing in accordance with the miniaturization of the semiconductor device. That is, since the plurality of divided transistors and the non-volatile memory have many common semiconductor manufacturing processes, the number of manufacturing steps as the semiconductor device is naturally reduced.

In the configuration according to claim 1 or 2 , the structure of the divided transistor is, for example, according to the invention according to claim 3 ,
(A1) Each first electrode and each second electrode constituting the transistors are electrically connected through diffusion layers formed in the semiconductor substrate, and only each gate electrode constituting the transistor is electrically connected. Isolated structure,
Alternatively, as in the invention according to claim 4 ,
(A2) The transistors are separated from each other and arrayed or formed in a matrix on a semiconductor substrate, and the first electrodes and the second electrodes constituting the transistors are electrically connected by wirings. Structure,
Etc. can be adopted.

By the way, according to the structure (A1) (Claim 3 ), it is not necessary to lay a metal wiring or the like for electrically connecting the divided transistors to the current flow path in parallel. Therefore, it is possible to simplify the structure and the manufacturing process. In addition, since a concern such as disconnection is eliminated compared to the case of laying metal wiring or the like, a more reliable semiconductor device can be realized. On the other hand, the (A2) structure (claim 4), although the structure and manufacturing steps compared to the above (A1) is increased, in stabilizing the divided plurality of transistors each characteristic desired structure It becomes. In addition, the degree of freedom related to the arrangement of the plurality of transistors can be increased.

In addition, for the transistors arranged and formed on the semiconductor substrate in the form of being divided as described in claims 1 to 4 , for example, according to the invention described in claim 5 ,
(D1) a transistor having an LDMOS structure in which each drain electrode and each source electrode which are the first and second electrodes are connected so as to be interposed in the current flow path of the drive load;
Alternatively, as in the invention according to claim 6 ,
(D2) a transistor having a VDMOS structure in which each drain electrode and each source electrode which are the first and second electrodes are connected so as to be interposed in the current flow path of the drive load;
Or, according to the invention of claim 7 ,
(D3) a transistor having an IGBT structure in which the collector electrode and the emitter electrode, which are the first and second electrodes, are connected so as to be interposed in the current flow path of the drive load;
It is particularly effective when used as a load driving transistor for a transistor used in a so-called power stage.

(First embodiment)
A semiconductor device according to a first embodiment of the present invention will be described below with reference to FIGS.

  In this embodiment, as will be described in detail below, the following configuration is basically adopted. That is, a transistor having an LDMOS structure including a drain-source electrode connected so as to be interposed in a current flow path and a gate electrode for controlling a current flowing between the drain-source electrode in accordance with an applied voltage. An array is formed on the semiconductor substrate in such a manner that it is divided into a plurality of transistors electrically connected in parallel to the current flow path. Drive information indicating whether or not a drive voltage can be applied to each gate electrode of a plurality of transistors constituting the LDMOS region can be variably set on a plurality of memory cells constituting the nonvolatile memory region on the same semiconductor substrate. The plurality of transistors are selectively activated based on the set drive information. As a result, when these multiple transistors are regarded as a single transistor, the required values such as the on-resistance value and switching time can be made variable, and the required values need to be readjusted when the load is changed, for example. Even so, it is possible to cope with the adjustment and change of the required value with a high degree of freedom.

  FIG. 1 shows an entire equivalent circuit including a driving load centering on a semiconductor substrate on which such a semiconductor device is mounted. FIG. 2 shows a plan view of an LDMOS region formed in the semiconductor substrate. The structure is schematically shown.

  First, as shown in FIG. 1, the semiconductor substrate C1 on which the semiconductor device of this embodiment is mounted is interposed in a current flow path from the circuit power supply Vc to the ground (GND) through the driving load Ld. Is provided. Here, the driving load Ld is a load constituted by a resistance such as a heater or a coil (inductance) such as a motor. The semiconductor substrate C1 basically includes an LDMOS region 10 that is a transistor region having the LDMOS structure and a nonvolatile memory region 11 that is a region in which the drive information is variably set.

  Among these, in the LDMOS region 10, as described above, the transistor having the LDMOS structure is divided into, for example, five transistors L11 to L15 that are electrically connected in parallel to the current flow path. An array is formed. Each of these transistors L11 to L15 has a structure according to the LDMOS structure illustrated in FIG. 26, and the drain electrode (first electrode) D and the source electrode (second electrode) S are respectively the above-described ones. A gate electrode G, which is connected to the current flow path and controls the current flowing between the drain electrode D and the source electrode S, is connected to each memory cell constituting the nonvolatile memory region 11.

  Further, five memory cells M11 to M15 having the same number as the transistors L11 to L15 are formed in the nonvolatile memory area 11 formed of an electrically rewritable nonvolatile memory (for example, EPROM). These memory cells M11 to M15 also basically have a MOS structure. As shown in FIG. 1, these memory cells M11 to M15 are based on the drain electrode D and the source electrode S and the voltages applied according to the drive information. A control gate electrode CG for controlling whether or not a current flows between the drain electrode D and the source electrode S is provided. The drain electrodes D of the memory cells M11 to M15 are electrically connected in parallel to a drive voltage input terminal Vin to which a drive voltage consisting of a constant voltage or a rectangular wave voltage is input, and the memory cell M11. To M15 are connected to the gate electrodes G of the transistors L11 to L15, respectively. That is, the memory cells M11 to M15 constituting the nonvolatile memory region 11 are switched (on / off) by being interposed in the drive voltage application lines to the gate electrodes G of the transistors L11 to L15 constituting the LDMOS region 10. ) Function as a switching element.

  The control gate electrodes CG of the memory cells M11 to M15 are connected to a voltage control circuit (not shown), and drive information of the transistors L11 to L15 is connected to the control gate electrodes CG through the voltage control circuit. A predetermined voltage corresponding to each logic level of the rewritable 5-bit information constituting the is applied. Specifically, among the bits constituting the drive information, for example, the corresponding memory cell is turned on for the control gate electrode CG of the memory cell corresponding to the bit at the logic H (high) level. Is applied. On the other hand, of the bits constituting the drive information, for example, the magnitude of the corresponding memory cell being turned off for the control gate electrode CG of the memory cell corresponding to the bit at the logic L (low) level. Is applied. As a result, the lines connecting the source electrodes S of the memory cells M11 to M15 and the gate electrodes G of the transistors L11 to L15, that is, the drive voltage application lines are switched on / off.

  On the other hand, as shown in FIG. 1, pull-down resistors R11 to R15 each having the other end grounded (GND) are connected to the drive voltage application line. Therefore, in these lines, the ON resistances of the memory cells M11 to M15 and the divided values (divided voltages) of the drive voltages by the corresponding pull-down resistors R11 to R15 correspond to the transistors L11 to L15, respectively. A transistor applied to the gate electrode G and applied with the divided voltage is selectively activated. Conversely, the line corresponding to the off cell of the memory cells M11 to M15 is fixed to the ground (GND) potential by the corresponding pull-down resistor. That is, among the transistors L11 to L15, the transistor whose gate electrode G is connected to the line has its gate potential fixed to the ground (GND) potential, and no channel is formed there.

Here, in this embodiment, each drain electrode (region) D is actually a semiconductor substrate, as shown in FIG. 2 in the planar structure of the transistors L11 to L15 constituting the LDMOS region 10. They are electrically connected to each other through a drain contact portion Dc formed of an N type diffusion layer and a high concentration (N ⁺ ) diffusion layer formed in C1. The other end of the drive load Ld connected to the circuit power supply Vc is connected to the drain contact portion Dc via an appropriate wiring. Similarly, the source electrodes (regions) S of the transistors L11 to L15 are also electrically connected to each other through a high concentration (N ⁺ ) diffusion layer provided in the P well. The source electrode (region) S is grounded (GND) potential through an appropriate wiring together with the substrate contact portion Bc formed as a high concentration (P ⁺ ) diffusion layer in the P well. . In this way, the transistors L11 to L15 constituting the LDMOS region 10 are connected so as to be interposed in the current flow path of the drive load Ld.

  On the other hand, only the gate electrodes G of the transistors L11 to L15 are formed so as to be electrically isolated from each other in the LDMOS region 10, as shown in FIG. The source electrodes S (FIG. 1) of the memory cells M11 to M15 to be configured are electrically connected to each other through appropriate wirings. As described above, when a drive voltage is selectively applied to these gate electrodes G, a channel length ChL is formed in a portion immediately below the gate electrode to which the drive voltage is applied among the gate electrodes G11 to G15. A channel layer (inversion layer) is formed, and the transistor in which the channel layer is formed among the transistors L11 to L15 is selectively activated. That is, current flows through the formed channel layer. In other words, the effective channel width ChW when the transistors L11 to L15 are regarded as a single transistor is made variable in the LDMOS region 10 according to the number of these activated transistors. Become.

  Next, a method for adjusting the effective channel width ChW when the LDMOS region 10 is regarded as a single transistor in the semiconductor device configured as described above will be described. This adjustment can be performed arbitrarily even after the semiconductor device is manufactured.

  In this adjustment, first, drive information indicating whether or not the drive voltage can be applied to the gate electrodes G (G11 to G15) of the transistors L11 to L15 (FIG. 1) is set in the nonvolatile memory region 11. The setting mode of the drive information can be freely changed through a well-known memory operation. In this way, a predetermined voltage corresponding to the logic level of each bit constituting the drive information is applied to each control gate electrode CG of the memory cells M11 to M15, and this is selectively turned on. Thus, the drain electrode D of the memory cell (switching element) that is turned on based on the drive voltage applied to the drain electrode D of each of the memory cells M11 to M15 from the drive voltage input terminal Vin shown in FIG. A current flows through a pull-down resistor connected between the source electrode S and a line following the source electrode S, and reaches a ground (GND). In the line through which the current flows in this way, the on-resistance of the memory cell turned on and the divided voltage of the drive voltage by the pull-down resistor corresponding thereto are applied to each gate electrode G of the corresponding transistor among the transistors L11 to L15. The transistor to which the divided voltage is applied is activated. That is, the current supplied from the circuit power supply Vc to the drive load Ld flows only through the activated transistors, and the transistors L11 to L15 are regarded as a single transistor according to the number of the activated transistors. The effective channel width ChW at this time is made variable in the semiconductor substrate C1.

As described above, according to the semiconductor device according to the first embodiment, the effects listed below can be obtained.
(1) The drive information indicating whether or not the drive voltage can be applied to the gate electrodes G (G11 to G15) of the transistors L11 to L15 constituting the LDMOS region 10 is variably set in the nonvolatile memory region 11 and Based on this, the transistors L11 to L15 are selectively activated. Thereby, even after the semiconductor device is manufactured, the required values such as the on-resistance value and switching time when the transistors L11 to L15 are regarded as a single transistor can be set to the driving voltages for the gate electrodes G (G11 to G15). It becomes possible to adjust through the application mode. Therefore, for example, even when readjustment of the required value is required due to a change in load, the required value can be adjusted and changed with a high degree of freedom.

  (2) The LDMOS region 10 and the nonvolatile memory region 11 are formed on the same semiconductor substrate C1. As a result, the semiconductor device can be miniaturized. Since many of the semiconductor manufacturing processes are common to the transistors L11 to L15 constituting the LDMOS region 10 and the memory cells M11 to M15 constituting the nonvolatile memory region 11, the number of manufacturing steps as the semiconductor device is reduced. Reduction can also be achieved.

  (3) The drain electrodes (regions) D and the source electrodes (regions) S of the transistors L11 to L15 are electrically connected through the diffusion layers. This eliminates the need for laying metal wiring or the like for electrically connecting these transistors L11 to L15 in parallel to the current flow path from the circuit power supply Vc to the ground (GND), and simplifies the structure. The manufacturing process can be simplified. In addition, since the fear of disconnection is eliminated as compared with the case of laying metal wiring or the like, a more reliable semiconductor device can be realized.

( First reference example )
Next, a first reference example will be described with reference to FIGS. 3 and 4 focusing on differences from the first embodiment.

The semiconductor device of this reference example is basically configured in accordance with the first embodiment shown in FIGS. 1 and 2, that is, the drive voltage applied to each gate electrode of a plurality of transistors constituting the LDMOS region. Drive information indicating whether or not application is possible is configured to be variably set in a plurality of memory cells in the non-volatile memory area on the same semiconductor substrate. However, in this reference example , a plurality of MOS transistors are connected in the form of a drive voltage application line to each gate electrode of the plurality of transistors, and the above-described through the driving of the plurality of MOS transistors based on the driving information. A plurality of transistors are selectively activated.

  FIG. 3 shows an entire equivalent circuit including a driving load centered on a semiconductor substrate on which such a semiconductor device is mounted. FIG. 4 is a plan view of an LDMOS region formed in the semiconductor substrate. The structure is schematically shown. Note that, in these drawings, the same elements as those shown in FIGS. 1 and 2 are denoted by the same reference numerals, and overlapping descriptions of these elements are omitted.

First, as shown in FIG. 3, the semiconductor substrate C2 on which the semiconductor device of this reference example is mounted is also grounded (GND) from the circuit power supply Vc via the drive load Ld, as in the first embodiment. ) In the form of an intervening current flow path. The semiconductor substrate C2 basically includes an LDMOS region 20 which is a transistor region having an LDMOS structure, a non-volatile memory region 21 which is a region where the drive information is variably set, and a drive voltage application line. An N channel MOS region 22 to be connected is provided.

  Among these, in the LDMOS region 20, as in the first embodiment, for example, five transistors L21 to L25 in which transistors having an LDMOS structure are electrically connected in parallel to the current flow path are provided. An array is formed on the semiconductor substrate C2 in a divided form. Each of these transistors L21 to L25 also has a structure according to the LDMOS structure illustrated in FIG. However, here, the drain electrode D and the source electrode S are each connected to the flow path of the current, and the gate electrode G for controlling the current flowing between the drain electrode D and the source electrode S is the N channel MOS region. 22 is connected to each MOS transistor constituting the circuit 22.

  In addition, the nonvolatile memory area 21 composed of an electrically rewritable nonvolatile memory (for example, EPROM) has the same number as the transistors L21 to L25 as in the first embodiment. Thus, five memory cells M21 to M25 are formed. These memory cells M21 to M25 also basically have a MOS structure. As shown in FIG. 3, these memory cells M21 to M25 are based on the drain electrode D and the source electrode S and the voltages applied according to the drive information. A control gate electrode CG for controlling whether or not a current flows between the drain electrode D and the source electrode S is provided. The drain electrodes D of the memory cells M21 to M25 are electrically connected in parallel to the memory power supply Vm to which a memory voltage consisting of a constant voltage is applied, and the source electrodes of the memory cells M21 to M25 are connected. S is connected to each MOS transistor constituting the N-channel MOS region 22.

  The control gate electrodes CG of the memory cells M21 to M25 are also connected to a voltage control circuit (not shown) as in the first embodiment. A predetermined voltage corresponding to each logic level of rewritable 5-bit information constituting the driving information of the transistors L21 to L25 is applied to each control gate electrode CG through this voltage control circuit. Specifically, among the bits constituting the drive information, for example, the corresponding memory cell is turned on for the control gate electrode CG of the memory cell corresponding to the bit at the logic H (high) level. Is applied. On the other hand, of the bits constituting the drive information, for example, the magnitude of the corresponding memory cell being turned off for the control gate electrode CG of the memory cell corresponding to the bit at the logic L (low) level. Is applied.

  In the N-channel MOS region 22, five MOS transistors N21 to N25, which are the same number as the transistors L21 to L25, are formed. As shown in FIG. 3, these MOS transistors N21 to N25 have their drain electrodes D electrically connected in parallel to a drive voltage input terminal Vin which is a terminal to which the drive voltage is input. The source electrodes S of the MOS transistors N21 to N25 are connected to the transistors L21 to L25 constituting the LDMOS region 20, respectively.

  On the other hand, as shown in FIG. 3, pull-down resistors R211 to R215 whose other ends are grounded (GND) are applied to the drive voltage application lines to the gate electrodes G of the transistors L21 to L25 constituting the LDMOS region 20, respectively. Is connected. Therefore, in these lines, the ON resistances of the MOS transistors N21 to N25 and the divided values (divided voltages) of the drive voltages by the pull-down resistors R211 to R215 corresponding thereto correspond to the respective ones of the transistors L21 to L25. A transistor applied to the gate electrode G and applied with the divided voltage is selectively activated. Conversely, the line corresponding to the cell in the off state among the MOS transistors N21 to N25 is fixed to the ground (GND) potential by the corresponding pull-down resistor. That is, among the transistors L21 to L25, the transistor whose gate electrode G is connected to the line has its gate potential fixed to the ground (GND) potential, and no channel is formed there.

  Further, as shown in FIG. 3, a pull-down resistor whose other end is grounded (GND) is applied to the memory voltage application line to each gate electrode G of the MOS transistors N21 to N25 constituting the N-channel MOS region 22. R221 to R225 are connected. Therefore, in these lines, the ON resistances of the memory cells M21 to M25 and the divided values (divided voltages) of the memory voltages by the corresponding pull-down resistors R221 to R225 correspond to the corresponding ones of the MOS transistors N21 to N25. The MOS transistor to which the divided voltage is applied is selectively activated. Conversely, the line corresponding to the off cell of the memory cells M21 to M25 is fixed to the ground (GND) potential by the corresponding pull-down resistor.

As described above, in this reference example , the memory cells M21 to M25 constituting the nonvolatile memory region 21 function as switching elements that perform switching in the form of being interposed in the memory voltage application line. The drive voltage application lines (transistors L21 to L25) are switched on / off through the active / inactive operation of the memory voltage application lines (MOS transistors N21 to N25).

Here, even in this reference example , the drain electrodes (regions) D are actually formed on the semiconductor substrate C2 as shown in FIG. They are electrically connected to each other through a drain contact portion Dc formed of an N-type diffusion layer and a high concentration (N ⁺ ) diffusion layer. The other end of the drive load Ld connected to the circuit power supply Vc is connected to the drain contact portion Dc via an appropriate wiring. Similarly, the source electrodes (regions) S of the transistors L21 to L25 are also electrically connected to each other through a high concentration (N ⁺ ) diffusion layer provided in the P well. The source electrode (region) S is set to the ground (GND) potential through an appropriate wiring together with the substrate contact portion Bc similarly formed as a high concentration (P ⁺ ) diffusion layer in the P well. . In this way, the transistors L21 to L25 constituting the LDMOS region 20 are connected so as to be interposed in the current flow path of the drive load Ld.

  On the other hand, also here, only the gate electrodes G of the transistors L21 to L25 are formed so as to be electrically isolated from each other in the LDMOS region 20, as shown in FIG. 22 are electrically connected to the source electrodes S (FIG. 3) of the MOS transistors N21 to N25 constituting the circuit 22 via appropriate wirings. As described above, by selectively applying a driving voltage to these gate electrodes G, a channel length ChL is formed in a portion immediately below the gate electrode to which the driving voltage is applied among the gate electrodes G21 to G25. A channel layer (inversion layer) is formed, and the transistor in which the channel layer is formed among the transistors L21 to L25 is selectively activated. That is, current flows through the formed channel layer. In other words, the effective channel width ChW when the transistors L21 to L25 are regarded as a single transistor is made variable in the LDMOS region 20 according to the number of these activated transistors. Become.

  Next, a method for adjusting the effective channel width ChW when the LDMOS region 20 is regarded as a single transistor in the semiconductor device configured as described above will be described. Note that this adjustment can also be arbitrarily performed even after the semiconductor device is manufactured, as in the first embodiment.

  In this adjustment, first, drive information indicating whether or not the drive voltage can be applied to the gate electrodes G (G21 to G25) of the transistors L21 to L25 (FIG. 3) is set in the nonvolatile memory region 21. The setting of the drive information can be freely changed through a well-known memory operation. Thus, a predetermined voltage corresponding to the logic level of each bit constituting the drive information is applied to each control gate electrode CG of the memory cells M21 to M25, and this is selectively turned on. Accordingly, the drain electrode D and the source of the memory cell (switching element) that is turned on based on the memory voltage applied to the drain electrode D of each of the memory cells M21 to M25 from the memory power supply Vm shown in FIG. A current flows through a pull-down resistor connected between the electrodes S and a line following the subsequent stage, and each reaches a ground (GND). In the line through which the current flows in this way, the divided voltage of the memory voltage by the ON resistance of the memory cell turned ON and the pull-down resistor corresponding thereto is the gate electrode G of each corresponding MOS transistor of the MOS transistors N21 to N25. The MOS transistor to which the divided voltage is applied is made active.

  In this way, when the MOS transistors N21 to N25 are selectively activated based on the drive information, the drive voltage applied to the drain electrodes D of the MOS transistors N21 to N25 from the drive voltage input terminal Vin is set. Based on this, a current flows between the drain electrode D and the source electrode S of the activated MOS transistor. This current flows through a pull-down resistor connected to a line following the subsequent stage, and reaches each ground (GND). In the line through which current flows in this way, the divided voltage of the drive voltage by the on-resistance of the activated MOS transistor and the corresponding pull-down resistor is applied to each gate electrode G of the corresponding transistor among the transistors L21 to L25. The transistor to which the divided voltage is applied is activated. That is, the current supplied from the circuit power supply Vc to the drive load Ld flows only through the activated transistors, and the effective channel width when the activated transistors L21 to L25 are regarded as a single transistor. ChW becomes variable in the semiconductor substrate C2.

As described above, according to the semiconductor device according to the first reference example , the effects listed below can be obtained.
(1) The drive information indicating whether or not the drive voltage can be applied to the gate electrodes G (G21 to G25) of the transistors L21 to L25 constituting the LDMOS region 20 is variably set in the memory cells M21 to M25. Then, the transistors L21 to L25 are selectively selected based on the driving information through the driving of the MOS transistors N21 to N25 connected to the gate electrodes G of the transistors L21 to L25. To be active. Thereby, even after the semiconductor device is manufactured, the required values such as the on-resistance value and the switching time when the transistors L21 to L25 are regarded as a single transistor can be set to the driving voltages for the gate electrodes G (G21 to G25). It becomes possible to adjust through the application mode. Therefore, for example, even when readjustment of the required value is required due to a change in load, the required value can be adjusted and changed with a high degree of freedom. In this case, the MOS transistors N21 to N25 are interposed, so that unlike the first embodiment, the gate resistances of the transistors L21 to L25 and the on resistances of the memory cells M21 to M25 constituting the switching elements are Can also be set independently.

  (2) The LDMOS region 20 and the nonvolatile memory region 21 are formed on the same semiconductor substrate C2. As a result, the semiconductor device can be miniaturized. In addition, for the transistors L21 to L25 constituting the LDMOS region 20, the memory cells M21 to M25 constituting the nonvolatile memory region 21, and the MOS transistors N21 to N25 constituting the N channel MOS region 22, many of the semiconductor manufacturing processes are performed. Since they are common, the number of manufacturing steps as the semiconductor device can be reduced.

  (3) The drain electrodes (regions) D and the source electrodes (regions) S of the transistors L21 to L25 are electrically connected through the diffusion layers. This eliminates the need for laying metal wiring or the like for electrically connecting these transistors L21 to L25 in parallel to the current flow path from the circuit power supply Vc to the ground (GND), and simplifies the structure. The manufacturing process can be simplified. In addition, since the fear of disconnection is eliminated as compared with the case of laying metal wiring or the like, a more reliable semiconductor device can be realized.

In addition, regarding the first embodiment and the first reference example described above, for example, the following embodiment can be appropriately changed and implemented.
In the first embodiment and the first reference example , the drain electrodes D and the source electrodes S of the transistors L11 to L15 or the transistors L21 to L25 are respectively passed through diffusion layers formed on the semiconductor substrate C1 or C2. An electrically connected structure was adopted. However, the present invention is not limited to this structure, and each drain electrode D and each source electrode S as well as each gate electrode G are separated from each other by a semiconductor substrate and electrically connected through appropriate wiring. It may be adopted.

In the first embodiment and the first reference example , the nonvolatile memory region 11 or 21 or the N-channel MOS region 22 is collectively put on one semiconductor substrate C1 or C2 on which the LDMOS region 10 or 20 is formed. However, the present invention is not limited to this configuration. In addition, for example, the memory cells M11 to M15 or M21 to M25 constituting the nonvolatile memory region 11 or 21 and the MOS transistors N21 to N25 constituting the N channel MOS region 22 are formed on another semiconductor substrate, and appropriate wirings are formed. Through the transistors L11 to L15 or L21 to L25 constituting the LDMOS region 10 or 20 formed in the semiconductor substrate C1 or C2. In short, the structure that realizes the equivalent circuit shown in FIGS. 1 and 3 above, that is, the drive information indicating whether or not the drive voltage can be applied to each gate electrode of the transistor is variably set in the nonvolatile memory region. As long as the transistor in which the drive voltage is applied to the gate electrode is selectively activated based on the drive information, the implementation mode is arbitrary.

( Second reference example )
Next, a second reference example will be described with reference to FIGS. 5 and 6 focusing on differences from the first embodiment.

The semiconductor device of this reference example is also basically configured in accordance with the first embodiment shown in FIGS. 1 and 2, that is, a transistor having an LDMOS structure is electrically connected to a current flow path. The semiconductor substrate is configured to be divided into a plurality of transistors connected in parallel. However, in this reference example , drive information indicating whether or not current can be supplied to a plurality of transistors constituting the LDMOS region can be variably set in a plurality of memory cells constituting the nonvolatile memory region on the same semiconductor substrate. To do. Based on the set drive information, a current is selectively allowed to flow to a transistor that can be supplied with a current among the plurality of transistors.

  FIG. 5 shows an entire equivalent circuit including a driving load centered on a semiconductor substrate on which such a semiconductor device is mounted. FIG. 6 shows a plan view of an LDMOS region formed in the semiconductor substrate. The structure is schematically shown. Also in these drawings, the same elements as those shown in FIGS. 1 and 2 are denoted by the same reference numerals, and overlapping descriptions of these elements are omitted.

First, as shown in FIG. 5, the semiconductor substrate C3 on which the semiconductor device of this reference example is mounted is grounded (GND) from the circuit power supply Vc via the drive load Ld, as in the first embodiment. ) In the form of an intervening current flow path. The semiconductor substrate C3 basically includes an LDMOS region 30 which is a transistor region having an LDMOS structure and a nonvolatile memory region 31 which is a region where the drive information is variably set.

  Among these, in the LDMOS region 30, as in the first embodiment, for example, five transistors L31 to L35 in which transistors having an LDMOS structure are electrically connected in parallel to the current flow path are provided. The semiconductor substrate C3 is arrayed in a divided form. Each of these transistors L31 to L35 also has a structure according to the LDMOS structure illustrated in FIG. 26, and controls the drain electrode D and source electrode S and the current flowing between the drain electrode D and source electrode S. And a gate electrode G to be configured. However, in these transistors L31 to L35, each drain electrode D is connected to each memory cell M31 to M35 constituting the nonvolatile memory region 31, and a drive voltage is input to the gate electrode G. The drive voltage input terminal Vin is directly and electrically connected in parallel.

  Further, the nonvolatile memory area 31 composed of an electrically rewritable nonvolatile memory (for example, EPROM) is also provided with the same number as the transistors L31 to L35, as in the first embodiment. Thus, five memory cells M31 to M35 are formed. These memory cells M31 to M35 also basically have a MOS structure, and as shown in FIG. 5, the drain electrode D and source electrode S connected to the current flow path, and the drive information A control gate electrode CG for controlling whether or not a current flows between the drain electrode D and the source electrode S based on a voltage applied accordingly is provided. The drain electrodes D of the memory cells M31 to M35 are electrically connected in parallel to the other end of the drive load Ld connected to the circuit power source Vc via appropriate wiring, The source electrodes S of the memory cells M31 to M35 are connected to the drain electrodes D of the transistors L31 to L35, respectively.

  The control gate electrodes CG of the memory cells M31 to M35 are connected to a voltage control circuit (not shown) as in the first embodiment. A predetermined voltage corresponding to each logic level of rewritable 5-bit information constituting the driving information of the transistors L31 to L35 is applied to each control gate electrode CG through this voltage control circuit. Specifically, among the bits constituting the drive information, for example, the corresponding memory cell is turned on for the control gate electrode CG of the memory cell corresponding to the bit at the logic H (high) level. Is applied. Thereby, current supply to a transistor connected to the subsequent stage of the memory cell is allowed. On the other hand, of the bits constituting the drive information, for example, the magnitude of the corresponding memory cell being turned off for the control gate electrode CG of the memory cell corresponding to the bit at the logic L (low) level. Is applied. As a result, current supply to the transistor connected to the subsequent stage of the memory cell is prohibited. In this way, the memory cells M31 to M35 constituting the nonvolatile memory region 31 are connected to the source electrodes S and the drain electrodes D of the transistors L31 to L35 constituting the LDMOS region 30, that is, currents. It functions as a switching element that performs switching (on / off) in the form of being interposed in the supply path.

Here, in the reference example , as shown in the planar structure of the transistors L31 to L35 in FIG. 6, each gate electrode G is actually formed in the LDMOS region 30 in the entire channel region of the transistors L31 to L35. Are formed as a single gate electrode G3. On the other hand, each drain electrode (region) D of the transistors L31 to L35 is actually a drain contact portion Dc composed of an N type diffusion layer and a high concentration (N ⁺ ) diffusion layer formed in the semiconductor substrate C3. Are separated from each other by the element isolation layer Is. The source electrodes S of the memory cells M31 to M35 are electrically connected to the drain contact portions Dc thus separated through appropriate wirings. On the other hand, the source electrodes (regions) S of the transistors L31 to L35 are actually electrically connected to each other through a high concentration (N ⁺ ) diffusion layer provided in the P well. The source electrode (region) S is grounded (GND) potential through an appropriate wiring together with the substrate contact portion Bc similarly formed as a high concentration (P ⁺ ) diffusion layer in the P well. . In this way, the transistors L31 to L35 constituting the LDMOS region 30 are connected so as to be interposed in the current flow path of the drive load Ld.

  A drive voltage is commonly applied from the drive voltage input terminal Vin to the gate electrodes G of the transistors L31 to L35, that is, the single gate electrode G3, so that the channel length is directly below the gate electrode G3. A channel layer (inversion layer) of ChL is formed. However, even if the channel layers are formed in all of the transistors L31 to L35 in this way, when the memory cells M31 to M35 are selectively turned on, only the transistor corresponding to the selected memory cell is actually used. The current supplied from the circuit power supply Vc does not flow. In this way, only the transistors in which current actually flows in the channel layer among the transistors L31 to L35 are selectively activated. That is, also in this case, the effective channel width ChW when the transistors L31 to L35 are regarded as a single transistor is made variable in the LDMOS region 30 according to the number of these activated transistors. become.

  Next, a method for adjusting the effective channel width ChW when the LDMOS region 30 is regarded as a single transistor in the semiconductor device configured as described above will be described. Note that this adjustment can also be performed arbitrarily even after the semiconductor device is manufactured, as in the first embodiment.

  In this adjustment, first, a driving voltage is applied in common from the driving voltage input terminal Vin to each gate electrode G (single gate electrode G3) of the transistors L31 to L35 (FIG. 5), and immediately below the gate electrode G3. A channel layer (inversion layer) is formed in this part. On the other hand, drive information indicating whether or not current can be supplied to the transistors L31 to L35 (FIG. 5) is set in the nonvolatile memory region 31. As described above, the setting of the drive information can be freely changed through a well-known memory operation. Thus, a predetermined voltage corresponding to the logic level of each bit constituting the drive information is applied to each control gate electrode CG of the memory cells M31 to M35, and this is selectively turned on. As a result, the current supplied from the circuit power source Vc shown in FIG. 5 to the drive load Ld flows between the drain electrode D and the source electrode S of the memory cell (switching element) that is turned on, and the line following the subsequent stage. Only the connected transistor flows, and this is activated, and each reaches the ground (GND). The effective channel width ChW when the transistors L31 to L35 are regarded as a single transistor is made variable in the semiconductor substrate C3 according to the number of activated transistors.

As described above, according to the semiconductor device of the second reference example , the effects listed below can be obtained.
(1) Drive information indicating whether or not current can be supplied to the transistors L31 to L35 constituting the LDMOS region 30 is variably set in the memory cells M31 to M35 constituting the nonvolatile memory region 31, and the transistor is based on the drive information. A current is selectively supplied to the transistors among L31 to L35 that can be supplied with current. Thereby, even after the manufacturing of the semiconductor device, the required values such as the on-resistance value and the switching time when the transistors L31 to L35 are regarded as a single transistor are adjusted through a current supply mode to the transistors L31 to L35. Will be able to. Therefore, for example, even when readjustment of the required value is required due to a change in load, the required value can be adjusted and changed with a high degree of freedom.

  (2) The LDMOS region 30 and the nonvolatile memory region 31 are formed on the same semiconductor substrate C3. As a result, the semiconductor device can be miniaturized. Since the transistors L31 to L35 constituting the LDMOS region 30 and the memory cells M31 to M35 constituting the nonvolatile memory region 31 have many common semiconductor manufacturing processes, the number of manufacturing steps as the semiconductor device is reduced. Reduction can be achieved.

  (3) The gate electrodes G of the transistors L31 to L35 are formed as a single gate electrode G3 corresponding to all channel regions of the transistors L31 to L35. This eliminates the need for laying a metal wiring or the like for commonly applying a driving voltage to the gate electrodes G of the transistors L31 to L35, thereby simplifying the structure and simplifying the manufacture. Will be able to. In addition, since a concern such as disconnection is eliminated as compared with the case where metal wiring or the like is laid, a more reliable semiconductor device can be realized. This also applies to each source electrode S electrically connected through a diffusion layer in the transistors L31 to L35.

( Third reference example )
Next, a third reference example will be described with reference to FIGS. 7 and 8 focusing on differences from the first embodiment or the second reference example .

The semiconductor device of this reference example is also basically configured in accordance with the first embodiment shown in FIGS. 1 and 2, that is, a transistor having an LDMOS structure is electrically connected to a current flow path. In this configuration, the semiconductor substrate is arrayed and divided into a plurality of transistors connected in parallel. Also in this reference example , basically, as in the second reference example , drive information indicating whether or not current can be supplied to the plurality of transistors constituting the LDMOS region is stored in the non-volatile memory region on the same semiconductor substrate. Can be variably set in a plurality of memory cells. However, here, based on the set drive information, the current supply of the plurality of transistors can be supplied through the drive of the plurality of MOS transistors connected to each of the current supply paths to the plurality of transistors. A current is selectively supplied to a transistor to be selected.

  FIG. 7 shows an entire equivalent circuit including a driving load centered on a semiconductor substrate on which such a semiconductor device is mounted. FIG. 8 shows a plan view of an LDMOS region formed in the semiconductor substrate. The structure is schematically shown. Also in these drawings, the same elements as those shown in FIGS. 1 and 2 are denoted by the same reference numerals, and overlapping descriptions of these elements are omitted.

First, as shown in FIG. 7, the semiconductor substrate C4 on which the semiconductor device of this reference example is mounted is grounded (GND) from the circuit power supply Vc via the drive load Ld, as in the first embodiment. ) In the form of an intervening current flow path. The semiconductor substrate C4 basically includes an LDMOS region 40 which is a transistor region having an LDMOS structure, a non-volatile memory region 41 which is a region where the drive information is variably set, and a current supply path to the LDMOS region 40. The N channel MOS region 42 is connected in such a manner.

  Among these, in the LDMOS region 40, as in the first embodiment, for example, five transistors L41 to L45 in which transistors having an LDMOS structure are electrically connected in parallel to the current flow path. Are arranged on the semiconductor substrate C4. Each of these transistors L41 to L45 has a structure according to the LDMOS structure illustrated in FIG. 26, and controls the drain electrode D and the source electrode S and the current flowing between the drain electrode D and the source electrode S. And a gate electrode G to be configured. In these transistors L41 to L45, each drain electrode D is connected to each MOS transistor constituting the N-channel MOS region 42, and the gate electrode G is a drive voltage input to which a drive voltage is input. Directly and in parallel with the terminal Vin.

  In the nonvolatile memory area 41, five memory cells M41 to M45 having the same number as the transistors L41 to L45 are formed. These memory cells M41 to M45 also basically have a MOS structure, and as shown in FIG. 7, these are based on the drain electrode D and the source electrode S and the voltages applied in accordance with the drive information. A control gate electrode CG for controlling whether or not a current flows between the drain electrode D and the source electrode S is provided. The drain electrodes D of the memory cells M41 to M45 are electrically connected in parallel to the memory power supply Vm, and the source electrodes S of the memory cells M41 to M45 constitute the N channel MOS region. The MOS transistors N41 to N45 are connected to the gate electrodes G, respectively.

  Note that the control gate electrodes CG of the memory cells M41 to M45 are also connected to a voltage control circuit (not shown), as in the first embodiment. A predetermined voltage corresponding to each logic level of rewritable 5-bit information constituting the driving information of the transistors L41 to L45 is applied to each control gate electrode CG through this voltage control circuit. Specifically, among the bits constituting the drive information, for example, the corresponding memory cell is turned on for the control gate electrode CG of the memory cell corresponding to the bit at the logic H (high) level. Is applied. On the other hand, of the bits constituting the drive information, for example, the magnitude of the corresponding memory cell being turned off with respect to the control gate electrode CG of the memory cell corresponding to the bit at the logic L (low) level. Is applied.

  In the N channel MOS region 42, five MOS transistors N41 to N45, which are the same number as the transistors L41 to L45, are formed. These MOS transistors N41 to N45 are electrically connected in parallel via appropriate wiring to the other end of the drive load Ld whose drain electrodes D are connected to the circuit power supply Vc. The source electrodes S of the transistors N41 to N45 are connected to the drain electrodes D of the transistors L41 to L45, respectively.

  On the other hand, as shown in FIG. 7, memory voltage application lines to the gate electrodes G of the MOS transistors N41 to N45 constituting the N-channel MOS region 42, that is, the memory cells M41 to M41 constituting the nonvolatile memory region 41, respectively. Pull-down resistors R41 to R45 each having the other end grounded (GND) are connected to a common connection portion of each M45 with each source electrode S. For this reason, in these lines, the ON resistances of the memory cells M41 to M45 and the divided values (divided voltages) of the memory voltages by the corresponding pull-down resistors R41 to R45 correspond to the corresponding ones of the MOS transistors N41 to N45. The MOS transistor to which the divided voltage is applied is selectively activated. Conversely, the line corresponding to the off cell of the memory cells M41 to M45 is fixed to the ground (GND) potential by the corresponding pull-down resistor.

  As described above, the memory cells M41 to M45 constituting the nonvolatile memory region 41 function as switching elements that perform switching in the form of being interposed in the memory voltage application line. That is, these switching elements execute on / off of the memory voltage application line, and thus active / inactive switching of the MOS transistors N41 to N45. Then, through the active / inactive operation of the MOS transistors N41 to N45, the current supply path to the transistors L41 to L45 connected to the subsequent stage is switched on / off.

Here, in this reference example , as shown in the planar structure of the transistors L41 to L45 in FIG. 8, the gate electrodes G are actually all channels of the transistors L41 to L45 in the LDMOS region 40. A single gate electrode G4 corresponding to the region is formed. On the other hand, each drain electrode (region) D of the transistors L41 to L45 is actually a drain contact portion Dc composed of an N type diffusion layer and a high concentration (N ⁺ ) diffusion layer formed in the semiconductor substrate C4. Are separated from each other by the element isolation layer Is. The source electrodes S of the MOS transistors N41 to N45 are electrically connected in series to the drain contact portions Dc separated from each other through appropriate wirings. On the other hand, the source electrodes (regions) S of the transistors L41 to L45 are actually electrically connected to each other through a high concentration (N ⁺ ) diffusion layer provided in the P well. The source electrode (region) S is grounded (GND) potential through an appropriate wiring together with the substrate contact portion Bc similarly formed as a high concentration (P ⁺ ) diffusion layer in the P well. . In this way, the transistors L41 to L45 constituting the LDMOS region 40 are connected so as to be interposed in the current flow path of the drive load Ld.

  A drive voltage is commonly applied from the drive voltage input terminal Vin to the gate electrodes G of the transistors L41 to L45, that is, the single gate electrode G4, so that the channel length is directly below the gate electrode G4. A channel layer (inversion layer) of ChL is formed. However, even if the channel layers are formed in all of the transistors L41 to L45 in this way, when the MOS transistors N41 to N45 are selectively turned on (active), the transistors actually correspond to the selected MOS transistors. The current supplied from the circuit power supply Vc flows only to the transistors (L41 to L45). In this way, only the transistors in which current actually flows in the channel layer among the transistors L41 to L45 are selectively activated. That is, also in this case, the effective channel width ChW when the transistors L41 to L45 are regarded as a single transistor is made variable in the LDMOS region 40 according to the number of these activated transistors. become.

  Next, a method for adjusting the effective channel width ChW when the LDMOS region 40 is regarded as a single transistor in the semiconductor device configured as described above will be described. Note that this adjustment can also be performed arbitrarily even after the semiconductor device is manufactured, as in the first embodiment.

  In this adjustment, first, a drive voltage is applied in common from the drive voltage input terminal Vin to each gate electrode G (single gate electrode G4) of the transistors L41 to L45 (FIG. 7), and immediately below the gate electrode G4. A channel layer (inversion layer) is formed in this part. On the other hand, drive information indicating whether or not current can be supplied to the transistors L41 to L45 (FIG. 5) is set in the nonvolatile memory area 41. The setting of the drive information can be freely changed through a well-known memory operation. Thus, a predetermined voltage corresponding to the logic level of each bit constituting the drive information is applied to each control gate electrode CG of the memory cells M41 to M45, and this is selectively turned on. Accordingly, the drain electrode D and the source of the memory cell (switching element) that is turned on based on the memory voltage applied to the drain electrode D of each of the memory cells M41 to M45 from the memory power supply Vm shown in FIG. A current flows through a pull-down resistor connected between the electrodes S and a line following the subsequent stage, and each reaches a ground (GND). In the line through which current flows in this way, the divided voltage of the memory voltage by the on-resistance of the memory cell turned on and the pull-down resistor corresponding thereto is the gate electrode G of each corresponding MOS transistor among the MOS transistors N41 to N45. The MOS transistor to which the divided voltage is applied is made active. The current supplied to the drive load Ld from the circuit power supply Vc shown in FIG. 7 is only the transistor connected between the drain electrode D and source electrode S of the MOS transistor turned on and the line following the subsequent stage. Each of these leads to grounding (GND) while making this active. The effective channel width ChW when the transistors L41 to L45 are regarded as a single transistor is made variable in the semiconductor substrate C4 in accordance with the number of activated transistors.

As described above, according to the semiconductor device of the third reference example , the effects listed below can be obtained.
(1) Drive information indicating whether or not current can be supplied to the transistors L41 to L45 constituting the LDMOS region 40 is variably set in the memory cells M41 to M45 constituting the nonvolatile memory region 41. Then, through the driving of the MOS transistors N41 to N45 that are connected to each of the current supply paths to the transistors L41 to L45, the transistors that can be supplied with current among the transistors L41 to L45 based on the driving information. A current was selectively supplied to the. Thereby, even after manufacturing the semiconductor device, the required values such as the on-resistance value and the switching time when the transistors L41 to L45 are regarded as a single transistor are adjusted through the current supply mode to the transistors L41 to L45. Will be able to. Therefore, for example, even when readjustment of the required value is required due to a change in load, the required value can be adjusted and changed with a high degree of freedom. In addition, in this case, by interposing the MOS transistors N41 to N45, the gate resistance of the transistors L41 to L45 and the on-resistance of the memory cells M41 to M45 constituting the switching elements are made independent from those of the second reference example. Can be set.

  (2) The LDMOS region 40 and the nonvolatile memory region 41 are formed on the same semiconductor substrate C4. As a result, the semiconductor device can be miniaturized. In addition, for the transistors L41 to L45 constituting the LDMOS region 40, the memory cells M41 to M45 constituting the nonvolatile memory region 41, and the MOS transistors N41 to N45 constituting the N channel MOS region 42, many of the semiconductor manufacturing processes are performed. Since they are common, it is possible to reduce the number of manufacturing steps as the semiconductor device.

( Fourth reference example )
Next, a fourth reference example will be described with reference to FIG.

The semiconductor device of this reference example is basically configured according to the second reference example shown in FIGS. However, in this reference example , the memory cells M31 to M35 constituting the nonvolatile memory region 31 are respectively incorporated in the transistors L31 to L35 constituting the LDMOS region 30.

  FIG. 9 schematically shows an example of a side sectional structure of an LDMOS transistor incorporating such a nonvolatile memory. Also in this figure, the same elements as those shown in FIG. 26 or FIG. 5 and FIG. 6 are denoted by the same reference numerals, and the respective elements are duplicated. I will omit the explanation.

In this reference example , an electrically rewritable EPROM is adopted as the non-volatile memory, and the memory built-in transistor 32 basically has the same structure as the semiconductor substrate 100 as shown in FIG. And
A gate electrode 321 connected to the drive voltage input terminal Vin by appropriate wiring
A floating gate electrode 322 formed adjacent to the gate electrode 321
A tunnel film 324 formed on the floating gate electrode 322
A control gate electrode 323 formed on the tunnel film 324 and connected to a voltage control circuit (not shown) by appropriate wiring.
And so on.

  Here, the memory built-in transistor 32 corresponds to a set of memory cells and transistors connected to each other by appropriate wirings among the memory cells M31 to M35 and the transistors L31 to L35 in FIG. is there. The gate electrode 321 corresponds to each gate electrode G of the transistors L31 to L35, and the control gate electrode 323 corresponds to each gate electrode G of the memory cells M31 to M35.

  For such a memory-embedded transistor 32, drive information indicating whether or not current can be supplied to the transistor is set through driving of the voltage control circuit. That is, the voltage control circuit causes a voltage having a predetermined magnitude higher than the ground (GND) corresponding to the bit (current supply is possible) at the logic H (high) level among the bits constituting the drive information to the memory. The voltage is applied to the control gate electrode 323 of the built-in transistor 32. As a result, electrons existing in the floating gate electrode 322 are extracted toward the control gate electrode 323 via the tunnel film 324, and the memory built-in transistor 32 is turned on. On the other hand, a voltage of a predetermined magnitude lower than the ground (GND) corresponding to a bit (current supply is not possible) corresponding to a bit at a logic L (low) level among the bits constituting drive information by the voltage control circuit The voltage is applied to the control gate electrode 323 of the built-in transistor 32. As a result, electrons are injected from the control gate electrode 323 to the floating gate electrode 322 via the tunnel film 324, and the memory built-in transistor 32 is turned off. Thus, the memory built-in transistor 32 functions as a switching element that can be switched on / off in accordance with the logic level of each bit constituting the drive information.

  Next, a method for adjusting the effective channel width when the LDMOS region is regarded as a single transistor in the semiconductor device configured as described above will be described. As described above, this adjustment can also be performed arbitrarily even after the semiconductor device is manufactured.

  In this adjustment, first, a predetermined driving voltage is applied to each gate electrode 321 of the transistor from the driving voltage input terminal Vin, and a channel layer (inversion layer) is formed in a portion of the channel region 102 immediately below the gate electrode 321. The channel layer formed in this manner is electrically connected because it is in contact with the source region 104, while it is not in contact with the drain region 101 and is not electrically connected.

  On the other hand, by driving the voltage control circuit, electrons can be exchanged between the control gate electrode 323 and the floating gate electrode 322 via the tunnel film 324 according to the potential applied to the control gate electrode 323. Based on this, on / off for each bit of the drive information is set. At this time, when the memory built-in transistor 32 is turned on, a channel layer (inversion layer) is formed in the channel region 102 immediately below the floating gate electrode 322. The channel layer thus formed is electrically connected to be in contact with the channel layer and drain region 101 formed in the portion immediately below the gate electrode 321 described above.

  As described above, when a predetermined voltage is applied selectively to the control gate electrode 323 of the transistor 32 with built-in memory and commonly to the gate electrode 321 of the transistor, the circuit power supply Vc supplies it. The current flows only between the drain region 101 and the source region 104 of the memory built-in transistor 32 that is turned on, and reaches the ground (GND). In this way, the effective channel width when a transistor is regarded as a single transistor is determined according to the number of transistors selectively activated based on transistor drive information set in the nonvolatile memory region. It is variable within the semiconductor substrate.

Also by the semiconductor device according to the fourth reference example described above, the same effect as that of the second reference example can be obtained.
In addition, regarding the fourth reference example , for example, the following embodiment can be appropriately changed and implemented.
In the fourth reference example , a channel layer is formed in a portion of the channel region 102 immediately below the floating gate electrode 322 based on transfer of electrons between the control gate electrode 323 and the floating gate electrode 322 via the tunnel film 324. However, the method for forming the channel layer is not limited to this. As shown in FIG. 10 corresponding to FIG. 9, the control gate electrode 323a of the memory built-in transistor 32a is laminated on the floating gate electrode 322a so as to cover the corner portion of the floating gate electrode 322a. Then, using the electric field concentration at the corner of the floating gate electrode 322a corresponding to the potential applied to the control gate electrode 323a through the driving of the voltage control circuit, on / off for each bit of the drive information is set. It is good. This also provides the same effects as those of the fourth reference example , that is, the second reference example .

( Fifth reference example )
Next, a fifth reference example will be described with reference to FIG.

The semiconductor device of this reference example basically has a configuration according to the third reference example shown in FIGS. However, in this reference example , the transistors L41 to L45 constituting the LDMOS region 40 are replaced with the MOS transistors N constituting the N-channel MOS region 42.
41 to N45 are respectively incorporated.

  FIG. 11 schematically shows an example of a side cross-sectional structure of such a transistor. Also in this figure, the same elements as those shown in FIG. 26 or FIG. 7 and FIG. 8 are denoted by the same reference numerals, and the respective elements are duplicated. I will omit the explanation.

As shown in FIG. 11, the transistor 43 incorporating such a MOS transistor basically has
A gate electrode 431 connected to the drive voltage input terminal Vin by appropriate wiring
A gate electrode 433 formed adjacent to the gate electrode 431 and connected to the memory region 41 (not shown) by appropriate wiring.
And so on.

  Here, transistor 43 corresponds to a pair of MOS transistors and transistors connected to each other by appropriate wirings among MOS transistors N41 to N45 and transistors L41 to L45 in FIG. The gate electrode 431 corresponds to each gate electrode G of the transistors L41 to L45, and the gate electrode 433 corresponds to each gate electrode G of the MOS transistors N41 to N45. In this way, the transistor 43 is formed as a transistor sharing the channel region as the transistors L41 to L45 and the channel region as the MOS transistors N41 to N45.

  Next, a method for adjusting the effective channel width when the LDMOS region is regarded as a single transistor in the semiconductor device configured as described above will be described. This adjustment can also be performed arbitrarily even after the semiconductor device is manufactured.

  In this adjustment, first, a predetermined drive voltage is applied to the gate electrode 431 of the transistor 43 from the drive voltage input terminal Vin, and a channel layer (inversion layer) is formed in a portion of the channel region 102 immediately below the gate electrode 431. Note that the channel layer thus formed is electrically connected to be in contact with the source region 104, but is not electrically connected to the drain region 101. However, when the memory cells M41 to M45 (FIG. 7) constituting the nonvolatile memory region 41 are turned on, a channel layer (inversion layer) is formed in a portion immediately below the gate electrode 432 of the channel region 102. Are connected to the channel layer formed in the portion immediately below the gate electrode 431. That is, the drain region 101 and the source region 104 are electrically connected via the channel layer formed.

  As described above, when a predetermined voltage is applied to the memory cells constituting the nonvolatile memory region 41 selectively and in common to the gate electrodes 431 of the transistors, the power is supplied from the circuit power supply Vc. The current flows only between the drain region 101 and the source region 104 of the transistor 43 that is turned on, and reaches the ground (GND). Thus, the effective channel width when a transistor is regarded as a single transistor according to the number of transistors selectively activated based on transistor drive information variably set in the nonvolatile memory area. Is variable in the semiconductor substrate.

The semiconductor device according to the fifth reference example described above can achieve the same effects as those of the third reference example .
In the semiconductor device according to the fifth reference example , after the second gate electrode 433 is formed, the first gate electrode 431 is formed so as to partially overlap the second gate electrode 433. An increase in threshold value and on-resistance can be suppressed.

That is, in this reference example, it is necessary to supply different voltages to the first gate electrode 431 and the second gate electrode 433 formed adjacent to each other. For this reason, the gate electrodes 431 and 433 need to be electrically opened. As a method of separating the gate electrodes 431 and 433, for example, a method of dividing the gate electrode 107 shown in FIG. 26 into a first gate electrode and a second gate electrode by a method such as etching can be considered. However, in this method, if the first gate electrode and the second gate electrode are too far apart, the channel layer formed in the P well 102 is not connected by both gate electrodes, and the transistor is difficult to turn on. For this reason, when the first gate electrode and the second gate electrode are formed by such a method, and the first gate electrode and the second gate electrode are separated too much, a substantial gap between the two gate electrodes. High voltage must be applied depending on This is equivalent to driving a transistor in which a thick gate insulating film is formed, and causes an increase in threshold value and on-resistance.

In this respect, in the reference example , since the first gate electrode 431 is formed so that a part thereof overlaps the second gate electrode 433, the interval between the first gate electrode 431 and the second gate electrode 433 is the insulating film ILD. And becomes narrower than the interval between the gate electrodes formed by the above method. For this reason, even if the voltage applied to each gate electrode 431,433 is low, since the channel layer formed by both gate electrodes 431,433 is connected, an increase in threshold voltage and on-resistance can be suppressed.

Note that the fifth reference example can be implemented with appropriate modifications in the following forms, for example.
In the fifth reference example , the first gate electrode 431 is partially overlapped with the second gate electrode 433. However, as shown in FIG. 12, the first gate electrode 431a is replaced with the second gate electrode 433b. You may form so that a part may overlap. This also achieves the same effect as the fifth reference example , that is, the third reference example, and can suppress an increase in the threshold value and on-resistance of the transistor 43a.

In the fifth reference example , the first gate electrode 431 and the second gate electrode 433 are formed so that a part of them overlaps with another gate electrode. However, as shown in FIG. If the distance between the first gate electrode 431b and the second gate electrode 433b can be formed sufficiently short, the gate electrodes 431b and 433b may be formed so as not to overlap each other. According to this, since the gate electrodes 431b and 433b can be formed in one layer, that is, they can be formed simultaneously, the number of steps can be reduced and the steps can be simplified.

Further, in addition to the configuration of FIG. 13, as shown in FIG. 14, an N type diffusion layer 434 may be formed in the P well 102 corresponding to the gap between the first gate electrode 431b and the second gate electrode 433b. Good. The impurity concentration of the diffusion layer 434 is set to the same concentration (N ⁺ ) as that of the source region 104, for example. With this configuration, even if the distance between the first gate electrode 431b and the second gate electrode 433b is not sufficiently short, the channel layers respectively formed by the first and second gate electrodes 431b and 433b are diffusion layers. Since the transistor 434 is connected to the transistor 434, the transistor 43c can be turned on with a low gate voltage, and an increase in threshold voltage and on-resistance can be suppressed.

In the fifth reference example and the modified example, the first gate electrode 431 and the like are connected to the drive voltage input terminal Vin, and the second gate electrode 433 and the like are connected to the memory region 41, but the first gate electrode 431 and the like are connected. The second gate electrode 433 and the like may be connected to the drive voltage input terminal Vin in connection with the memory region 41. Further, similarly to the fourth reference example , it may be connected to a power supply circuit (voltage control circuit) formed on a substrate on which these transistors are formed. It is clear that the same effects as those of the fifth reference example can be obtained by these configurations.

( Sixth reference example )
Next, a sixth reference example will be described with reference to FIG.

FIG. 15A schematically shows an example of a side cross-sectional structure of the transistor 45 formed in the semiconductor device of this reference example . This transistor 45 is applied to the transistors L11 to L15, L21 to L25, L31 to L35, and L41 to L45 constituting the LDMOS regions 10 to 40 of the first embodiment and the first to third reference examples. .

In this figure, the same elements as those shown in the conventional example (FIG. 26) or the fifth reference example and the modified examples (FIGS. 11 to 14) are denoted by the same reference numerals. The redundant explanation of each element is omitted.

As shown in FIG. 15A, the transistor 45 basically has the above-described semiconductor substrate 100,
A gate electrode 451 as a first control electrode connected to the drive voltage input terminal Vin by appropriate wiring
A control electrode 452 as a second control electrode formed adjacent to the gate electrode 451 and connected to a voltage control circuit (not shown) by appropriate wiring.
It has. That is, in the transistor 45 of this reference example, the gate electrode formed from the source region 104 to the field oxide film 106 is divided into the gate electrode 451 and the control electrode 452. The gate electrode 451 is formed so that a part thereof overlaps the control electrode 452.

The channel region 102 is formed so that the length of the current path direction between the source region 104 and the drain region 101 (drain contact portion 105) is shorter than that in the fifth reference example . The gate electrode 451 is formed so as to cover a region from the source region 104 to the drain region 101, and the control electrode 452 is formed so as to cover the drain region 101.

Next, the operation of the transistor 45 configured as described above will be described.
The gate electrode 451 covering the channel region 102a forms a channel layer (inversion layer) in the channel region 102a by a predetermined driving voltage applied from the driving voltage input terminal Vin. Note that the channel layer thus formed electrically connects the source region 104 and the drain region 101. Therefore, the gate electrode 451 formed so as to cover the channel region 102 a constitutes an N-type MOS transistor together with the source region 104 and the drain region 101. This MOS transistor is turned on / off by a predetermined drive voltage applied to the gate electrode 451 from the drive voltage input terminal Vin.

  The control electrode 452 covering the drain region 101 is opposed to the insulating film ILD and functions as a capacitor. Therefore, when a positive voltage is applied to the control electrode 452, a charge storage layer in which electrons are stored is formed in the drain region 101 facing the control electrode 452.

Since the drain region 101 usually has a low impurity concentration and a high resistance to ensure a breakdown voltage, the current mainly flows through this charge storage layer. The amount of electrons stored in the charge storage layer corresponds to the voltage applied to the control electrode 452, and a current corresponding to the amount of stored electrons flows. Therefore, the ease of current flow, that is, the resistance value can be controlled by the voltage applied to the control electrode 452. The resistance value of the charge storage layer acts when the MOS transistor controlled by the gate electrode 451 is turned on. That is, the transistor 45 functions as a MOS transistor and a variable resistor connected in series to the transistor as shown in FIG. Then, the on-resistance of the transistor 45 can be changed by a voltage applied to the control electrode 452. For this reason, the on-resistance value is precisely controlled by adopting the transistor 45 in this reference example as compared with an example in which a plurality of MOS transistors are connected in parallel and the on-resistance value is adjusted by the number of transistors to be turned on / off. Will be able to.

  Note that as a potential applied to the control electrode 452, a potential applied to the source region 104 (a ground (GND) potential in FIG. 15A) or a positive constant potential can be employed. Since the charge storage layer is not formed at the source potential and the ground potential, the resistance value is high (high resistance). When a positive voltage is applied, the charge storage layer is formed and the resistance value is low (low resistance). Become.

As described above, according to the semiconductor device of the sixth reference example , the effects listed below can be obtained.
(1) In the transistor 45, a gate electrode formed from the source region 104 to the field oxide film 106, a gate electrode 451 that covers a region from the source region 104 to the drain region 101, and a control electrode that covers the drain region 101. Divided into 452. This transistor is equivalent to a structure in which a MOS transistor and a variable resistor are connected in series. Accordingly, by applying a predetermined drive voltage applied from the drive voltage input terminal Vin to the gate electrode 451 and applying a predetermined voltage to the control electrode 452, the on-resistance between the source region 104 and the drain contact portion 105 is increased. The value can be controlled precisely.

  (2) Since the control electrode 452 does not directly participate in the on / off operation of the transistor 45, the transistor 45 is substantially turned on / off by the voltage applied to the gate electrode 451. Since the opposing area between the first gate electrode 451 and the drain region is smaller than that of the conventional transistor, the parasitic capacitance can be reduced.

(3) The gate electrode 451 is formed so that a part thereof overlaps with the control electrode 452. Therefore, as in the fifth reference example , an increase in on-resistance of the transistor 45 can be suppressed. That is, it is necessary to electrically separate (open state) the gate electrode 451 and the control electrode 452. For this reason, if the gate electrode 451 and the control electrode 452 are too far apart, a portion having high resistance is formed between the channel layer formed by the gate electrode 451 and the charge storage layer formed by the control electrode 452. Therefore, the on-resistance value controlled by the control electrode 452 is less likely to contribute to the operation of the transistor 45, leading to an increase in on-resistance.

In this respect, in this reference example , since the gate electrode 451 is formed so that a part thereof overlaps the control electrode 452, the distance between the gate electrode 451 and the control electrode 452 becomes the film thickness of the insulating film ILD, and etching, etc. It becomes narrower than the interval formed by this method. For this reason, since a high resistance part is not formed or becomes small, an increase in on-resistance can be suppressed.

In addition, regarding the sixth reference example , for example, the following embodiment can be appropriately changed and implemented.
In the sixth reference example , the control electrode 452 is formed so that part of the gate electrode 451 overlaps, but as shown in FIG. 16, the gate electrode 451a is formed so that part of the control electrode 452b overlaps. May be. Also by this, the same effect as the sixth reference example can be obtained and an increase in the on-resistance of the transistor 45a can be suppressed.

In the sixth reference example , the gate electrode 451 and the control electrode 452 are formed so that part of them overlaps with another gate electrode. However, as shown in FIG. 17, the gate electrode 451b of the transistor 45b If the distance from the control electrode 452b can be formed sufficiently short, the gate electrode 451b and the control electrode 452b may be formed so as not to overlap each other. According to this, since the gate electrode 451b and the control electrode 452b can be formed in one layer, that is, they can be formed at the same time, the number of steps can be reduced and the steps can be simplified.

Further, in addition to the configuration of FIG. 17, an N type diffusion layer 434 may be formed in the P well 102 corresponding to the gap between the gate electrode 451b and the control electrode 452b, as shown in FIG. The impurity concentration of the diffusion layer 434 is set to the same concentration (N ⁺ ) as that of the source region 104, for example. With this configuration, even if the distance between the gate electrode 451b and the control electrode 452b is not sufficiently short, the channel layer formed by the gate electrode 451 and the charge accumulation layer formed by the control electrode 452 are formed as a diffusion layer. Since the connection is made by 434, an increase in on-resistance can be suppressed.

In addition, regarding said embodiment and a reference example , it can also change suitably with the following forms, for example , and can also implement it.
In the second to sixth reference examples , the drain electrodes D of the transistors L31 to L35 or L41 to L45 are formed in an electrically isolated form, and the source electrodes of the transistors L31 to L35 or L41 to L45 are formed. S is formed so as to be electrically connected through a diffusion layer S (N ⁺ ) formed in the semiconductor substrate C3 or C4. Conversely, the source electrodes S of the transistors L31 to L35 or L41 to L45 are formed in an electrically isolated form, and the drain electrodes D of the transistors L31 to L35 or L41 to L45 are formed in the semiconductor substrate C3 or C4. You may form in the form electrically connected through the formed diffusion layer Dc (N ^<+> ). In short, after forming each gate electrode G as a single electrode, one of each drain electrode D and each source electrode S is formed in an electrically isolated manner, and the other is formed in the semiconductor substrate. If it is formed in such a manner that it is electrically connected through the formed diffusion layer, the effect (3) of the second reference example can be obtained.

  Further, the transistors Ln1 to Ln5 are separated from each other in, for example, an array as shown in FIG. 19 and arranged on the semiconductor substrate C5, and each gate electrode and each drain constituting the transistors Ln1 to Ln5 are arranged. Either one of the electrode and each source electrode may be electrically connected by wiring. Alternatively, the transistors L1 to L9 are separated from each other in a matrix as shown in FIG. 20, for example, and arranged on the semiconductor substrate C6, and each gate electrode and each drain electrode constituting the transistors L1 to L9 are arranged. Any one of the source electrodes may be electrically connected by wiring. Since such a structure is complicated, the number of manufacturing steps is increased, but the structure is desirable in order to stabilize the characteristics of each of the divided transistors. Furthermore, in this case, the degree of freedom related to the arrangement of the plurality of transistors is increased.

In the second to sixth reference examples , the nonvolatile memory region 31 is formed on the semiconductor substrate C3 in which the LDMOS region 30 is formed, or the semiconductor substrate C4 in which the LDMOS region 40 and the N-channel MOS region 42 are formed. Although the nonvolatile memory area 41 is formed, the present invention is not limited to this configuration. The memory cells M31 to M35 constituting the nonvolatile memory region 31 are formed on a separate semiconductor substrate and connected to the transistors L31 to L35 constituting the LDMOS region 30 formed on the semiconductor substrate C3 by, for example, metal wiring. Also good. Alternatively, the memory cells M41 to M45 constituting the nonvolatile memory region 41 and the MOS transistors N41 to N45 constituting the N channel MOS region 42 are formed on a separate semiconductor substrate, and formed on the semiconductor substrate C4 by, for example, metal wiring. The transistors may be connected to the transistors L41 to L45 constituting the LDMOS region 40, respectively.
In short, a structure in which the equivalent circuit shown in FIGS. 5 and 7 is realized, that is, a drive voltage is commonly applied to each gate electrode of a plurality of transistors connected in parallel to a current flow path, and If the drive information indicating whether or not current supply to each transistor is possible is variably set in the non-volatile memory, and the transistor for which current supply is enabled is selectively activated based on the information, the specific information The realization mode is arbitrary.

Moreover, regarding the first embodiment and the first to sixth reference examples , for example, the following embodiments can be appropriately changed and implemented.
In each of the above-described embodiments and reference examples , each drain electrode D and each source electrode S is a current flow of the drive load Ld as a transistor that is formed on a semiconductor substrate by being divided into a plurality of transistors connected in parallel. Although a transistor having an LDMOS structure connected so as to be interposed in the path is employed, the present invention is not limited to this configuration. In addition, as shown in FIG. 21 as a diagram corresponding to FIG. 9, a floating gate electrode 522 formed adjacent to each gate electrode 521 of a plurality of transistors, and a film is formed on the floating gate electrode 522. A memory built-in transistor 52 including the tunnel film 524 formed and a control gate electrode 523 stacked on the tunnel film 524 is employed. Based on the transfer of electrons between the control gate electrode 523 and the floating gate electrode 522 through the tunnel film 524 in accordance with the potential applied to the control gate electrode 523, on / off for each bit is performed. It may be set variably. Alternatively, as shown in FIG. 22 corresponding to FIG. 10, the control gate electrode 523a of the transistor 52a with a built-in memory is stacked on the floating gate electrode 522a so as to cover the corner portion of the floating gate electrode 522a. To do. Then, on / off of each bit of the drive information is variably set using the electric field concentration in the corner portion of the floating gate electrode 522a corresponding to the potential applied to the control gate electrode 523a through driving of the voltage control circuit. It is good as well. In short, the present invention can also be applied to a transistor having a VDMOS (Vertical Diffused Metal Oxide Semiconductor) structure.

Furthermore, the scope of application of the present invention is not limited to transistors having an LDMOS structure and a VDMOS structure. In addition, for example, as shown in FIG. 23 as a diagram corresponding to FIGS. 9 and 21, the base region 601 composed of an N-type diffusion layer is compared with the semiconductor substrate 600 that constitutes the most part. A memory built-in transistor 62 having a structure similar to that of the memory built-in transistor 52 may be formed. In such a structure, similarly to the memory built-in transistor 52, the tunnel gate 524 corresponding to the potential applied to the control gate electrode 523 is interposed between the control gate electrode 523 and the floating gate electrode 522. On / off for each bit is variably set based on the exchange of electrons. In the memory built-in transistor 62 that is turned on, the collector contact portion 625 including the diffusion layer (P ⁺ ) having a concentration higher than that of the channel region 102 and the base region 601 is supplied from the circuit power supply Vc. Then, it flows through the emitter region 604 composed of the diffusion layer (N ⁺ ) having a higher concentration than the channel region 102 and the base region 601 and reaches the ground (GND). In addition, as shown in FIG. 24 as a diagram corresponding to FIGS. 10 and 22, the base region 601 composed of an N-type diffusion layer is compared to the semiconductor substrate 600 that constitutes most of the above. A memory built-in transistor 62a having a structure similar to that of the memory built-in transistor 52a may be formed. In this structure, like the memory built-in transistor 52a, the control gate electrode 523a of the memory built-in transistor 62a is laminated on the floating gate electrode 522a so as to cover the corner portion of the floating gate electrode 522a. The Then, on / off for each bit of the drive information is variable by using electric field concentration at the corner of the floating gate electrode 522a according to the potential applied to the control gate electrode 523a through driving of the voltage control circuit. Is set. In the on-memory transistor 62a that is turned on, the current supplied from the circuit power supply Vc is a collector contact portion 625 made of a diffusion layer (P ⁺ ) having a higher concentration than the channel region 102, the base region 601, It flows through the emitter region 604 composed of a diffusion layer (N ⁺ ) having a concentration higher than that of the channel region 102 and the base region 601, and reaches the ground (GND). That is, an IGBT (Insulated Gate Bipolar Transistor) structure in which each collector electrode and emitter electrode are connected so as to be interposed in a current flow path of a drive load as transistors arranged and formed on a semiconductor substrate by being divided into a plurality of transistors. A transistor having the following can also be employed.

The transistor in each of the above embodiments and reference examples is an N-type MOS transistor, but it may be a P-type MOS transistor. A semiconductor device having a so-called CMOS structure in which the conductivity type is appropriately changed, that is, an N-type MOS transistor and a P-type MOS transistor are formed on the same semiconductor substrate may be used.

The transistors in the above fourth to sixth reference examples and modifications are formed on the same semiconductor substrate together with other elements. For example, the transistor 45 in the sixth reference example is the first
When applied to the transistors L21 to L25 (see FIG. 3) in the reference example, together with the transistor 45, the memory cells M21 to M25 constituting the nonvolatile memory region 21 and the MOS transistors N21 to N25 constituting the N channel MOS region 22 are provided. It is formed on one semiconductor substrate.

In the MOS transistor, for example, as shown in FIG. 25A, an N-type source region 702 and a drain region 703 are formed in a P-type well 701, and a well 701 between the source region 702 and the drain region 703 is formed. A gate electrode 704 is formed so as to cover it. The gate electrode 704 is insulated from the well 701 and the like by a gate oxide film 705. This MOS transistor is formed simultaneously with the gate electrode, insulating film, source region, and the like of the transistors of the above embodiments and reference examples .

In the memory cell (nonvolatile memory), for example, as shown in FIG. 25B, an N-type source region 712 and a drain region 713 are formed in a P-type well 711, and the source region 712 and the drain region 713 are formed. A floating gate electrode 714 and a control gate electrode 715 are formed so as to cover the well 711 therebetween. The floating gate electrode 714 is insulated from the well 701 and the like by a tunnel oxide film 716, and a dielectric film 717 is interposed between the floating gate electrode 714 and the control gate electrode 715. The non-volatile memory, said fourth to sixth first gate electrode of the transistor in the reference example, the second gate electrode (sixth reference example the control electrode), the insulating film, a source region, is formed simultaneously with equal .

In addition, a capacitor is formed on the same semiconductor substrate as other elements. The capacitor is included in a voltage control circuit that supplies a predetermined voltage to, for example, the second gate electrode. In this capacitor, as shown in FIG. 25C, a LOCOS oxide film 722 formed on a substrate (or diffusion layer) 721 is formed, and a lower electrode 723 and an upper electrode 724 are formed on the LOCOS oxide film 722. Has been. A dielectric film 725 is interposed between the lower electrode 723 and the upper electrode 724. The capacitor has a first gate electrode of the transistor in the fourth to sixth reference example, the second gate electrode (sixth reference example the control electrode), the insulating film, a source region, is formed simultaneously with equal.

In this manner, other elements formed on the same semiconductor substrate as the transistors in the fourth to sixth reference examples are formed by the same process (for example, the second gate electrode 433 shown in FIG. 11 and FIG. 25 ( With the floating gate electrode 714 shown in b) and the lower electrode 723 shown in FIG. 25C, it is possible to obtain the semiconductor devices of the respective embodiments and reference examples while suppressing an increase in manufacturing steps.

In the above embodiments and reference examples , at least one of the plurality of transistors constituting the LDMOS regions 10 to 40 may be the transistors shown in the fourth to sixth reference examples and the modification examples. With this configuration, by controlling the floating gate, the divided gate electrode, and the control electrode in addition to the control by the memory region and the N-channel MOS region for the plurality of transistors constituting the LDMOS regions 10 to 40, More precise control can be performed.

In the fourth to sixth reference examples and the modification examples, metal wiring may be disposed so as to overlap the gate electrode or the control electrode. Since the gate electrode is made of, for example, polycrystalline silicon, the value of parasitic resistance is larger than that of metal wiring (aluminum, copper, etc.). As in the second and third reference examples , the plurality of transistors L31 to L35 and L41 to L45 constituting the LDMOS regions 30 and 40 are electrically connected in parallel, and the transistors L31 to L35 and L41 to L45 are connected. Are commonly connected to the drive voltage input terminal Vin. Such gate electrodes are formed as one common gate electrode G3, G4 as shown in FIG. 6 and FIG. 8, so that a voltage drop may occur due to parasitic resistance. For this reason, a metal wiring is arranged so as to overlap the gate electrode, and the metal wiring and the gate electrode are connected by contact holes formed at a plurality of locations, thereby reducing the substantial wiring length and reducing the parasitic resistance. As a result, a voltage can be applied to the gate electrode with high accuracy, and more precise control can be performed. Even in the case where the gate electrode of each transistor is formed individually as in the first embodiment and the first reference example , the parasitic resistance of the gate electrode can be reduced by arranging the metal wiring. Will be able to.

  Furthermore, the scope of application of the present invention is not limited to a transistor with a built-in memory, or a transistor having an LDMOS structure, a VDMOS structure, and an IGBT structure. In short, the first and second electrodes connected so as to be interposed in the current flow path, and the gate electrode for controlling the current flowing between the first and second electrodes according to the applied voltage. Any transistor may be used as long as it is arranged on a semiconductor substrate in such a manner that a transistor having a MOS structure is divided into a plurality of transistors electrically connected in parallel to the current flow path. With such a structure, the plurality of divided transistors are regarded as a single transistor according to the number of transistors selectively activated based on driving information of the plurality of transistors variably set in a nonvolatile memory. The effective channel width can be made variable within the semiconductor substrate, and the intended purpose can be achieved.

1 is a circuit diagram showing an example of an entire equivalent circuit including a driving load with a semiconductor substrate as a center, in the first embodiment of a semiconductor device according to the present invention; The top view which showed typically the planar structure about the LDMOS area | region built in the semiconductor substrate of the embodiment. The first reference example of the semi-conductor device, circuit diagram showing an example of an overall equivalent circuit diagram including a drive load at the center of the semiconductor substrate. The top view which showed typically the planar structure about the LDMOS area | region built in the semiconductor substrate of the reference example . A second reference example of the semi-conductor device, circuit diagram showing an example of an overall equivalent circuit, including the driving load around the semiconductor substrate. The top view which showed typically the planar structure about the LDMOS area | region built in the semiconductor substrate of the reference example . A third reference example of a semi-conductor device, circuit diagram showing an example of an overall equivalent circuit, including the driving load around the semiconductor substrate. The top view which showed typically the planar structure about the LDMOS area | region built in the semiconductor substrate of the reference example . A fourth reference example of a semi-conductor device, a side sectional view showing an example of the sectional structure. Side surface sectional drawing which shows an example of the cross-sectional structure about the modification of the semiconductor device of the reference example . Fifth Example of semi-conductor device, a side sectional view showing an example of the sectional structure. Side surface sectional drawing which shows an example of the cross-sectional structure about the modification of the semiconductor device of the reference example . Side surface sectional drawing which shows an example of the cross-sectional structure about the modification of the semiconductor device of the reference example . Side surface sectional drawing which shows an example of the cross-sectional structure about the modification of the semiconductor device of the reference example . (A) for the sixth reference example of the semi-conductor device, a side sectional view showing an example of the sectional structure, (b) is an equivalent circuit diagram. Side surface sectional drawing which shows an example of the cross-sectional structure about the modification of the semiconductor device of the reference example . Side surface sectional drawing which shows an example of the cross-sectional structure about the modification of the semiconductor device of the reference example . Side surface sectional drawing which shows an example of the cross-sectional structure about the modification of the semiconductor device of the reference example . Modification of the second to fifth reference example of the semi-conductor device, plan view schematically showing an example of the planar structure. For another modification of the second to fifth reference example of the semi-conductor device, plan view schematically showing an example of the planar structure. Side surface sectional drawing which shows an example of the cross-sectional structure about the case where 1st Embodiment and 1st - 5th reference example of the conductor apparatus concerning this invention are applied to the transistor which has VDMOS structure. Side surface sectional drawing which shows another example of the cross-sectional structure about the case where 1st Embodiment and 1st - 5th reference example of the semiconductor device concerning this invention are applied to the transistor which has VDMOS structure. Side surface sectional drawing which shows an example of the cross-sectional structure about the case where 1st Embodiment and 1st - 5th reference example of the semiconductor device concerning this invention are applied to the transistor which has IGBT structure. Side surface sectional drawing which shows another example of the cross-section about the case where 1st Embodiment and 1st - 5th reference example of the semiconductor device concerning this invention are applied to the transistor which has IGBT structure. (A)-(c) is side surface sectional drawing which shows an example of the other element formed in the semiconductor device concerning this invention. Side surface sectional drawing which shows the cross-section of the conventional semiconductor device.

Explanation of symbols

10, 20, 30, 40 ... LDMOS region, 11, 21, 31, 41 ... non-volatile memory region, 22, 42 ... N channel MOS region, 32, 32a, 52, 52a, 62, 62a ... transistor with built-in memory, 43, 43a, 43b, 43c ... Transistor, 45, 45a, 45b, 45c ... Transistor, 100, 600, C1 to C6 ... Semiconductor substrate, 101 ... Drain region, 102 ... Channel region, 103 ... Substrate contact portion, 104 ... Source Region 105, drain contact 106, field oxide film (LOCOS oxide film) 107 gate electrode Vc circuit power Vm memory power Vin drive power GND ground power Ld drive load M11 ˜M45... Memory cell, N11 to N45... N channel MOS transistor, L1 L45, Ln1 to Ln5, L1 to L9, transistors, R11 to R15, R211 to R215, R221 to R225, R41 to R45, pull-down resistors, D ... drain electrodes, S ... source electrodes, 321, 431, 431a, 431b, 433, 433a, 433b, 451, 451a, 451b, 521, G, G11 to G15, G21 to G25, G3, G4 ... gate electrodes, 323, 323a, 523, 523a, CG ... control gate electrodes, 322, 322a, 522 522a ... floating gate electrode, 324, 524 ... tunnel film, 434 ... diffusion layer, 452, 452a, 452b ... control electrode, 601 ... base region, 604 ... emitter region, 625 ... collector contact part, ILD ... insulating film, Bc ... Substrate contact part, Dc ... In the contact portion, Is ... the isolation layer.

Claims (7)

MOS structure comprising first and second electrodes connected so as to be interposed in a current flow path, and a gate electrode for controlling a current flowing between the first and second electrodes according to an applied voltage Are arranged on a semiconductor substrate in a manner that is divided into a plurality of transistors that are electrically connected in parallel to the current flow path, and are variably set in a nonvolatile memory. A semiconductor device in which an effective channel width is variable in a semiconductor substrate when the plurality of divided transistors are regarded as a single transistor according to the number of transistors selectively activated based on driving information Because
The drive information variably set in the nonvolatile memory is configured to have the same number of bits as the number of the plurality of transistors as information indicating whether or not the drive voltage can be applied to the gate electrodes of the plurality of transistors. The non-volatile memory in which the drive information is variably set functions as a plurality of switching elements that can be switched on / off according to the logic level of each bit constituting the information, The plurality of switching elements are electrically connected in such a way as to be interposed in the drive voltage application lines for the gate electrodes of the plurality of transistors, and the lines connecting the gate electrodes and the switching elements are respectively pull-down resistors. To the gate electrode corresponding to the switching element in the on state. And the transistor to which a voltage is applied are selectively actively, and characterized in that the effective channel width when the divided plurality of transistors regarded as a single transistor is variable in the semiconductor substrate Semiconductor device. The semiconductor device according to claim 1 , wherein the nonvolatile memory is formed on the same semiconductor substrate as the semiconductor substrate on which the plurality of divided transistors are formed. The plurality of divided transistors are configured such that each first electrode and each second electrode constituting the transistors are electrically connected through diffusion layers formed in the semiconductor substrate, respectively. The semiconductor device according to claim 1 , wherein only each gate electrode is formed so as to be electrically separated. The plurality of divided transistors are separated from each other and arranged in an array or matrix form on a semiconductor substrate, and each first electrode and each second electrode constituting the transistors are respectively connected by wiring. The semiconductor device according to claim 1 , wherein the semiconductor device is electrically connected. In the transistor arrayed on the semiconductor substrate in such a manner that it is divided into a plurality of transistors connected in parallel, each drain electrode and each source electrode, which are the first and second electrodes, are interposed in the current flow path of the driving load. the semiconductor device according to any one of claims 1 to 4 is formed as a transistor having a connection to the LDMOS structure as comprising. In the transistor arrayed on the semiconductor substrate in such a manner that it is divided into a plurality of transistors connected in parallel, each drain electrode and each source electrode, which are the first and second electrodes, are interposed in the current flow path of the driving load. the semiconductor device according to any one of claims 1 to 4 is formed as a transistor having a VDMOS structure connected to composed. The transistors arranged in the semiconductor substrate in the form of being divided into a plurality of transistors connected in parallel have their collector electrodes and emitter electrodes, which are the first and second electrodes, interposed in the current flow path of the driving load. the semiconductor device according to any one of claims 1 to 4 is formed as a transistor having an IGBT structure connected to composed.

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