JPH0779138B2 - Non-volatile semiconductor memory device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device, and more particularly to an improvement for storing at least three or more multi-bits or multi-states in a unit device.

<Prior Art> The non-volatile semiconductor memory device itself is publicly known, and various devices having respective structural and operating mechanism characteristics have been proposed so far.

First, if they are classified with respect to a method of erasing or rewriting the stored contents, an electrically programmable read-only memory, a so-called EPROM, and a read-only memory that can be electrically erased or rewritten as well as programmed (write), That is, it can be divided into EEPROM (EAROM).

As is well known, in the former case, writing can be done electrically, but erasing must be done by another erasing operation such as UV irradiation. It is clear that the latter wins.

On the other hand, if the charge storage members are classified regardless of whether they are EPROM or EEPROM, at least as represented by a polymerized structure of a silicon nitride film and a silicon oxide film in a so-called MNOS structure, at least, for example, One using a charge storage trap of one insulating film, for example
As typified by a FAMOS structure, there is one that uses a conductive floating gate that is embedded in an insulating film and does not form a discharge path anywhere.

Generally, these members and the charge storage traps in them are
It is often referred to generically as "charge storage structure",
In this document, this is regarded as one physical structural member, and hereinafter referred to as "charge storage member", in which it is actually involved in the charge storage, and the channel formation thereunder, or the channel being formed. The part that is involved in changing the state is called the “effective charge storage region”. However, in either case, it means a member capable of accumulating charges and a region capable of effectively accumulating charges, regardless of whether or not the charges are actually accumulated.

However, it is clear that the "effective charge storage region" and the "charge storage member" may not match in terms of the area size or geometrical shape as an object.

For example, in the FAMOS structure and the like described above, the effective charge storage region involved in the memory operation of the element is almost the same as the area occupied by the floating gate in relation to the floating gate as the charge storage member. Since the polymerized film of silicon oxide film and nitride film as the different insulating film polymerized structure is not provided only between the channel formation regions between the source and the drain, it is generally provided on the entire surface of the substrate, and therefore, it is actually nonvolatile. The effective charge storage region involved in the typical memory operation is limited to the area region on a part of the channel formation region therein.

Furthermore, it is also possible to classify the difference in injection mechanism of selected charges (electrons or holes) into the effective charge storage region thus defined, and each principle such as avalanche injection, tunnel injection, channel injection, etc. Used selectively.

In particular, in the case of electrically erasable ones such as EEPROM, for example, the accumulation state of electrons is defined as the accumulation state of holes with respect to logic "1", the neutralization state of accumulated electrons by injection of holes, or the emission of accumulated electrons. When the state is made to correspond to the logic "0", there are some cases where different injection mechanisms are adopted for the injection of electrons and the injection of holes.

In these non-volatile memory devices, generally, effective charge is applied so that a required bias voltage or electric field can be applied to the charge storage member or the charge injection path, and a predetermined gate voltage can be applied at the time of reading. Although a gate electrode is often provided on the storage region, a nonvolatile semiconductor memory device according to any of the above structures or classifications,
The determination of whether or not a predetermined carrier is held in the charge storage member, that is, in which logical place the present device memory content is, is generally, and simply, a certain gate voltage. This can be done depending on whether the channel is "conducting" or "non-conducting".

<Problems to be Solved by the Invention> As described above, a large number of non-volatile semiconductor memory devices have been proposed so far, but all or most of them are not included in one device per unit. I could only remember bits.

Therefore, when many such elements are used in a two-dimensional array, or when the three-dimensional integration which is popular these days, the bit density is naturally limited.

The present invention has been made in view of the above-mentioned point of view by reviewing the existing non-volatile semiconductor memory device to provide a non-volatile semiconductor memory device capable of storing multi-bit or many states even if the same unit device is used. It is a thing.

If that happens, regardless of whether it is an EPROM or an EEPROM as described above, as a problem of another dimension, compared to the conventional,
The bit density within the defined geometrical area (or volume) for memory formation could be greatly improved.

<Means for Solving the Problems> In order to achieve the above-mentioned object, the present invention provides a semiconductor region having a channel forming region between a source and a drain, which are separated from each other, and a channel forming region while maintaining insulating properties. A channel having a shape and size corresponding to the planar shape of the effective charge storage region is provided on the surface of the channel formation region between the source and drain by being provided so as to cover the effective charge storage region. As an improvement in an electrically writable or electrically writable / erasable non-volatile semiconductor memory device having a charge storage member selectively forming or changing a channel state. Three or more storage regions are independent from each other along the channel width direction orthogonal to the channel length direction, which is the direction connecting the source and drain. Configured, and,
We propose a nonvolatile semiconductor memory device in which the widths of the three or more effective charge storage regions are all different from each other.

<Operations and Effects> As is apparent, the present invention is directed to the improvement of the charge storage mechanism portion of the conventional non-volatile semiconductor memory device.

In other words, whether it is configured as an EPROM or an EEPROM, other components required for them are the same as the existing configuration, but as long as they are in accordance with the present invention, at least one source and one drain corresponding to each other are provided. The charge storage member, which has conventionally been capable of forming only a single effective charge storage region facing the channel formation region defined between them, is separated along the channel width direction and is composed of three or more independent ones. is there.

According to the present invention having such a configuration, for a total of three or more effective charge storage regions, how many of them store a predetermined amount of charges, or when an EEPROM structure is adopted, those charges are stored. By selecting how many effective charge storage areas in the stored charge to dissipate, or how many of those effective charge storage areas to neutralize the stored charge by injecting different types of charge. , The number of channels correspondingly formed under each effective charge storage region can be changed, or the state of each channel can be changed. Depending on the state, the number or state of the channels, three or more current output values or voltage output values which are discrete and discriminable from each other can be obtained between the source and the drain. In the semiconductor memory device, one device can store multi-bits of at least 3 bits or more.

As a matter of course, even when viewed as a memory device in which a large number of the elements of the present invention are integrated, it is easy to realize a higher bit density than that in the case of using the conventional elements, and at least 3 bits or more are provided for each element. It also means that a kind of parallel processing that can be handled at one time is possible, which can contribute to speeding up various processing operations related to the memory.

Further, the number of wirings required between the elements or between each element and the input / output, the power supply, and the bias can be greatly reduced as compared with the case where the conventional one-element one-bit type non-volatile semiconductor memory element is used.

<Embodiment> Hereinafter, each embodiment of the nonvolatile semiconductor memory device according to the present invention will be described in detail with reference to the accompanying drawings.

1 and 2 show the first embodiment of the present invention, which adopts the existing MNOS structure or a structure similar thereto.
It is convenient for improving the EEPROM.

In this case, the substrate 1 is a bulk semiconductor substrate 11 of the first conductivity type.
As shown in the plane projection structure of FIG. 1, a source 21 and a drain 22 are formed in the surface region of the semiconductor substrate 11 with a predetermined distance therebetween. .

The source 21 and the drain 22 may be formed in a normal manner with respect to the surface region of the bulk semiconductor substrate 11, and are generally formed as regions of opposite conductivity type to the substrate 11. However, it may be a region of the same conductivity type as the semiconductor substrate 11 as long as it is formed as a region having a lower resistance than other regions.

The semiconductor substrate surface region between the source 21 and the drain 22 can be regarded as a channel forming region 23 in which a channel can be selectively formed under a predetermined gate voltage application condition, as in a normal nonvolatile semiconductor memory device. However, on such a semiconductor substrate surface, as well shown in FIG. 2 which is a sectional view taken along a sectional line II-II in FIG. 1, an insulating film structure usually called a gate insulating film is formed. 8 are provided.

Here, as an example, since the existing MNOS type or a similar non-volatile semiconductor memory device is aimed at improvement, the gate insulating film 8 does not include the charge storage member 6 as recognized in these conventional structures. Combined with at least one insulating film
It has a superposed structure of different kinds of insulating films 61, 62 having a charge storage trap in 62.

As is well known, in the conventional MNOS structure, the first insulating film
Reference numeral 61 denotes a silicon oxide film that is thin enough to allow carriers to be tunneled from the surface of the semiconductor substrate 11, and the second insulating film 62 that overlaps with this is a silicon nitride film including charge accumulation traps. Any combination of heterogeneous dielectric polymer structures that have been previously reported, and may also be reported in the future, can be employed, so long as they can function.

For example, the first insulating film 61 may be a silicon direct nitride film, a silicon oxynitride film, or the like in addition to the above, and the second insulating film 62 may be a tantalum oxide film, an aluminum oxide film, or the like.

It should be noted that a combination polymerization structure of three or more types may also be used, for example, a thin silicon oxide film as the first insulating film, a silicon nitride film as the second insulating film, and a silicon oxide film again as the third insulating film may be used. There is a so-called MONOS structure or the like, which has a characteristic that it can be rewritten at a low voltage, so that it can also be adopted.

Due to such various structures, the charge storage member 6 which also functions as the gate insulating film 8 is originally the source 21 and the drain 22.
It suffices that it is formed only in the interval, but normally it is formed in a series on the entire surface of the substrate for ease of manufacturing.

However, the area of the gate insulating film 8 or the charge storage member 6 corresponding to the area between the source and the drain is
According to the present invention, three or more gate electrodes made of an appropriate conductive material such as polycrystalline silicon, metal, silicide, etc.
1,52,53) are formed.

For each of these gate electrodes 51, 52, 53, the direction connecting the source and drain is defined as the length direction, as clearly shown in FIG. 1 (this is the concept of normal channel length and channel width). It corresponds to the case where it is specified), and is separated from each other along the width direction and exists independently.

Further, the width W ₁ , W ₂ , W ₃ of each of these gate electrodes 51, 52, 53 is
Are all different from each other, and in a sense, as a desirable consideration, the width W ₂ of the second gate electrode 52 is 2 · W ₁ and the width 3 of the widest third is for the first gate electrode 51 having the narrowest width W ₁ . The width W ₃ of the gate electrode 53 is set to 4 · W ₁ .

The reason itself will be described later, but if you put it in advance,
The mutual relationship between the widths of the respective gate electrodes is wide when n is an integer of 3 or more (that is, n ≧ 3) and n gate electrodes are generalized, with the narrowest mutual width relationship as a reference. It means that there is a 2 ^n-1 times series relation (1,2,4,8, ...), which is a so-called multiple relation, because ^{n is} increased by 1.

However, the arrangement order in the width direction does not need to be arranged in order from the first gate electrode 51 having the narrowest width to the third gate electrode 53 having the widest width W ₃ as illustrated, and is arbitrary. is there.

It should be noted here that the fact that the n gate electrodes 51, 52, 53 are provided between the pair of sources and drains in this way means that the members are actually formed as a single or continuous member. In view of its function, the existing charge storage member 6 is divided into n independent effective charge storage regions each having a width corresponding to each of the n gate electrode widths.

In other words, in the case of this embodiment, as defined in the gist of the present invention, means for providing n independent effective charge storage regions along the width direction between the source and drain. As a result, a method of providing n gate electrodes 51, 52, 53 on the charge storage member 6 is adopted.

This will become clearer with reference to the operation description below.

Generally, the operation of the MOS field effect transistor is expressed by the following formula 1) in the region where the drain voltage V _D is small, and is expressed by the following formulas 2) and 3) in the saturation region.

V _Dsat ≈ V _G -V _T ′ ... 3) However, in the above formulas 1) to 3), I _D : drain current, V _G : gate voltage, V _T : threshold voltage, V _T ′: effective threshold voltage, L: channel length, W: channel width, μ: carrier surface mobility, C _i : gate insulating film capacitance.

The above equations 1) and 2) show that for a given drain voltage V _D , gate voltage V _G and threshold voltage V _T (or V _T ′), the drain current I _D is proportional to the channel width W. Shows.

However, in the non-volatile semiconductor memory device of this embodiment of the present invention, in the channel formation region 23 on the surface of the semiconductor substrate below each gate electrode 51, 52, 53, each formed under each gate electrode. The channels C ₁ , C ₂ , and C ₃ can be selectively induced or extinguished under predetermined common gate voltage application conditions depending on whether or not charges are accumulated in the effective charge accumulation region.

Specifically, for example, when a relatively high voltage of a predetermined value or more is applied to the selected gate electrode, electrons are injected from the surface side of the semiconductor substrate only in the portion of the charge storage member 6 corresponding to the area or shape of the gate electrode. Or holes can be injected or expelled from it, and accordingly,
Under the predetermined common gate voltage application condition after removing the high voltage, only the corresponding portion in the channel forming region 23,
The channel is triggered.

In order to schematically show this pattern in FIG. 2, it is induced under each of the gate electrodes and the effective charge storage regions corresponding to the gate electrodes under the predetermined common gate voltage application condition as described above. The respective channels C ₁ , C ₂ , C ₃ are shown in the channel forming region 23 by dotted lines.

For the sake of simplicity, the width of each of the channels C ₁ , C ₂ , and C ₃ is W ₁ , W ₂ , and W ₃ that are the same as the width of the corresponding gate electrode, and of course, their width relation Assuming that the same ratio is 1: 2: 4, in the nonvolatile semiconductor memory device of the present invention in which the source 21 and the drain 22 that are the electrodes at both ends of all the channels are common, the above 1),
The value W in the equation (2) becomes variable depending on the width and number of channels actually induced in the channel formation region 23 under a predetermined common gate voltage application condition and the combination thereof.

For example, when only the narrowest channel C ₁ is induced or “conducted” under a given common gate voltage application condition,
When only the channel C _{3 having the} widest width of 4 times that is conducting, the channel width W naturally becomes 4 · W ₁ , and under the same applied voltage value condition, the obtained drain current I _D also becomes four. Doubled.

Therefore, in the nonvolatile semiconductor memory device having the three individual and independent gate electrodes 51, 52 and 53 as in the first and second illustrated embodiments, under a predetermined common gate voltage application condition. On the contrary, when all channels C ₁ , C ₂ , C ₃ are “non-conducting” and under the same common gate voltage application condition, all channels C ₁ , C ₂ , C ₃ are “conducting” Including time
As shown in the following table, a total of eight channel formation states can be realized.

However, "conduction" is represented by a logical value "1" and "non-conduction" is represented by a logical value "0".

As is apparent, in the nonvolatile semiconductor memory device of this embodiment, eight states can be represented by binary 3 bits, and this binary 3 bit information is also read by the difference of drain current ratio in each case. You know you will get.

That is, as shown in a typical current-voltage characteristic diagram of FIG. 3, in a state where a predetermined common gate voltage V _G is applied to each gate and a predetermined drain voltage V _D is applied, By the previous write operation, since only the channel corresponding to the effective charge storage region accumulating the charge capable of inducing the channel is conducted, a total of eight drain current levels can be discriminated without overlapping, Therefore, if necessary, it is possible to obtain eight kinds of discriminable voltage information by adding a load resistance having an appropriate value.

As can be easily generalized from this embodiment, the number n of effective charge storage regions (or gate electrodes for forming the same) is three or more, and the width of these n effective charge storage regions is set to n. 2 _n-1 : 2 _n-2 ： …… 2: 1, the drain current has an almost constant change width ΔI _D each time the binary number is incremented by 1 or decremented.
It is possible to realize an n-bit nonvolatile memory element in which I _D changes.

Of course, as described above, it is possible that the drain current I _D as the result of reading the stored contents changes with a substantially constant change width ΔI _D each time the stored contents change by a number “1” in binary. For example, after converting this into a voltage value, each storage logic value is discriminated by comparison with (n-1) reference voltage levels which are set to just the middle between adjacent storage logic values. In this case, it is desirable because the maximum discrimination margin allowed for the comparison reference voltage can be taken, but from a theoretical point of view, different values that can be discriminated for each stored logical value and that do not overlap can be used. If the drain current I _{D of} is obtained, the change width ΔI _D does not have to be constant,
Nevertheless, the invention is equally satisfied.

Further, in the above description, it is assumed that the width of each channel selectively formed under a predetermined common gate voltage application condition is equal to the width of each gate electrode or the effective charge storage region for forming it. Although shown by W ₁ , W ₂ , and W ₃ , in an actually manufactured element, all of these relationships may not necessarily match.

In such a case, it is needless to say that the width of the gate electrode and the width of the effective charge storage region associated therewith are designed so that the width of the channel that can be formed under the predetermined common gate voltage application condition has a desired width relationship. become.

As shown in FIG. 1, common source 21
The source electrode 3 and the drain electrode 4 are attached to the common drain 22 and the common drain 22 by a normal technique.

Further, as shown by the phantom line in FIG. 2, the substrate 1 is not the bulk semiconductor substrate 11 as described above,
In the case where a semiconductor layer 13 such as single crystal silicon is heteroepitaxially grown on an insulating substrate 12 such as sapphire or spinel, or a semiconductor layer is generally formed on the insulating substrate. Alternatively, a channel formation region can be provided in the semiconductor layer.

As described above, since it is believed that the basic understanding of the present invention has been obtained through the first embodiment, various cross-sectional structural modifications or examples are given as subordinate conceptual modifications according to the present invention. Go.

However, in any of the following embodiments, the operation principle of the present invention described above can be applied as it is, and also in consideration of modification examples of various members and the like, the same applies unless it is specified that the embodiment is not applicable. Therefore, in order to avoid duplication, in particular, except for individual matters in each embodiment, such operation explanations and modifications are no longer required to be re-posted, and for simplification, three or more number n The effective charge storage region generalized to (3) is also limited to three as in the previous embodiment.

The fourth illustrated embodiment is a case where the present invention is applied to an EEPROM that employs a so-called floating gate structure for a charge storage member. The surface shown is a surface along a section line similar to the surface shown in the second illustration.

When the conductive floating gate 63 is used to form the charge storage member 6, the different insulating film overlapping structures 61 and 62 in the previous embodiment are used.
Unlike the case of adopting, the accumulated charge can move in the floating gate in a plane parallel to the channel formation region, and therefore, in this embodiment, according to the structure of the present invention, it is orthogonal to the direction connecting the source and drain. When forming n effective charge storage regions in the width direction (the same as the channel width direction), the floating gates have predetermined widths W ₁ , W ₂ , W corresponding to the effective charge storage regions substantially one-to-one. ₃ of n 63 _-1, 63 _-2, 63 _-3
I am trying to consist of.

Of course, as in the previous embodiment, if the width of each floating gate 63 _-1 , 63 _-2 , 63 _-3 as the width of each effective charge storage region is defined, the predetermined width is set in the channel formation region 23 accordingly. The width of each corresponding channel C ₁ , C ₂ , C ₃ selectively formed under the condition that the common gate voltage of
63 _-1 , 63 _-2 , 63 _-3 Current drain I _D related to the reading of a total of eight types of memory contents obtained depending on how many charges are stored, including the case where the charges are stored and the case where no charges are stored. The value of is also the corresponding value.

Even in the case of the structure of this embodiment, at least the floating gate and the semiconductor substrate may not be formed of the same insulating film between the semiconductor substrate and the floating gate, and two or more of them may be used. It may have a multi-layer insulation film superposition structure as described above.

The structure shown in FIG. 4 can be expressed in a similar form as shown in FIG. 4 even if it is actually an EPROM instead of an EEPROM, and it depends on the material and thickness of each member, and other parameters. In each floating gate 63 _-i (i = 1,2,3, ... n), only one kind of charge can be electrically stored, or the stored charge can be electrically driven out. Whether or not it is possible to inject charge of opposite polarity also determines whether it is possible to stay in EPROM or EEPROM.

Which method to use may be determined by selecting a method required by a known existing technique, including the avalanche injection in the classic FAMOS and the selection of the injection mechanism, which is directly defined by the present invention. Not a thing.

As in this embodiment, the concept of forming the effective charge storage region in a divided manner as an object can also be applied in principle to the heterogeneous insulating film structure used in the previous embodiment.
The configuration may be as in the illustrated embodiment.

That is, the first insulating film 61 and the second charge storage member 6 made of an insulating film 62, each of the predetermined width W _1, W _2, W each independently portion 64 _{-1 3} 64 _-2, 64 _{- It} consists of _three .

In this embodiment, these n individual heterogeneous insulating film polymerized structures 64 _-1 , 64 _-2 , 64 _-3 are further buried by a suitable protective insulating film 81, and then charge injection is performed thereon. Each gate electrode 51, 52, 53 is provided which contributes only to the charge, or also contributes to the injection of the bipolar charge or the discharge of the accumulated charge.

In this case, each effective charge storage region has a structure in which the different insulating film overlapping structures 64 _-1 , 64 _-2 , 64 formed separately.
_Since the width is defined by the widths W ₁ , W ₂ , and W ₃ set to _-3 , the gate electrodes 51, 52, and 53 formed thereon correspond to themselves unless they overlap each other. The dimensional relationship may be such that it slightly protrudes from the effective charge storage region or the width of the polymerized structure.

Further, in order to obtain the structure of this embodiment, as in the first and second illustrated embodiments, after forming different kinds of insulating film polymerized structures uniformly in parallel to the substrate surface, each individual portion is etched by a technique such as etching.
It can be cut into 64 _-1 , 64 _-2 , 64 _-3 .

However, in the case of using the different insulating film polymerized structure as the charge storage member, it is rather advantageous that it can be uniformly formed on the substrate surface. In other words, in terms of simplifying the manufacturing process, it is advantageous to use the heterogeneous insulating film superposition structure formed over the entire surface as the charge storage member 6 as shown in the first and second illustrations than to use the floating gate 63 _-i. .

In the floating gate 63 _-i , as mentioned above, the injected charges can move in the lateral direction (direction parallel to the substrate surface) within the floating gate. In order to form not only the defined gate electrodes 51, 52 and 53 individually but also the effective charge storage regions of the predetermined widths W ₁ , W ₂ and W ₃ , it is necessary to form them individually as shown in FIG. There is a need to.

Next, an example in which the non-volatile semiconductor memory device according to the present invention can be used as a unit device and the occupied area thereof can be sufficiently reduced will be described.

As shown in FIGS. 6 and 7, the n effective charge storage regions formed by the present invention are all on the main surface of the substrate 1 (in this case, the bulk semiconductor substrate 11) as described above. Rather than being formed only in parallel planes, at least some of them are raised relative to the main surface.
Can be provided on the side surface of.

That is, by etching the surface of the semiconductor substrate 11,
For example, as shown in FIG. 6, the trapezoidal portion 9 having a quadrilateral shape in plan view is left, and as shown in FIG. 7 which is a sectional view taken along a sectional line VII-VII in FIG. After uniformly forming the charge storage member 6 composed of the different insulating film overlapping structures 61 and 62 on the surface of the trapezoidal portion, not only the upper plane of the trapezoidal portion 9 but also the plane of the main surface of the substrate according to the gist of the present invention. For example, if several gate electrodes are formed on the side surface of the trapezoidal part that is in a standing relationship at a certain angle, as in the case of the gate electrodes 51 and 52, a two-dimensional area called an occupied area can be obtained. From such a concept, it is possible to provide a very small one.

In this case, in particular, if the widest gate electrode 53 is attached to the upper surface of the trapezoidal portion 9, the width of the gate electrode 53 is almost the same as that used in the conventional single memory content nonvolatile semiconductor memory device. Since the other gate electrodes 51, 52 may be narrower than this, the thickness of the trapezoidal portion 9 is not required so much, and the size in the height direction is not increased. I'm done.

It should be noted that the source and drain regions and the electrodes 3 and 4 for establishing conduction with them are orthogonal to the side surface of the trapezoidal portion where the gate electrodes 51 and 52 are provided, as clearly shown in FIG. It may be formed on each side surface of the pair of trapezoidal portions.

Of course, in the case of adopting such a configuration, as shown in the eighth drawing, the case where the side surface of the trapezoidal portion 9 rises at a right angle with respect to the main surface of the substrate results in the most saving of the plane dimension. Needless to say.

Also, in the embodiments shown in the sixth, seventh and eighth embodiments, the charge storage member 6 can be changed to the structure of n floating gates as shown in the fourth embodiment.

However, in that case, if the side surfaces of the semiconductor platform 9 to which the respective floating gates are attached rise nearly vertically, they are rather unsuitable for the buried formation of these floating gates. It is easier in manufacturing to have at least some inclination. Nevertheless, compared with the case of arranging n gate electrodes in parallel according to the present invention in a completely flat plane, naturally,
A sufficient effect of reducing the occupied area can be expected.

Further, as shown by the phantom separation line in FIG. 7,
As in the previous embodiment, the active region of this embodiment may be configured with respect to the semiconductor layer 13 formed on the bulk insulator substrate 12, and in this case, only the semiconductor layer is also the trapezoidal portion 9. May be formed so that the insulating substrate 12 thereunder is also processed so that the raised portion of the insulating substrate 12 bites into the inside of the platform 9. It may be. This point is the same in the eighth illustrated embodiment having a steep side surface, although not shown.

By the way, the above-mentioned embodiments have partially shown that the insulating substrate 12 can be used as the lowermost physical support substrate, but rather, the semiconductor platform 9 is provided as described above. In the case of the example, in particular, when a so-called semiconductor island is formed on the insulator substrate 12 and is used as the above-described semiconductor base portion 9, various auxiliary materials are provided as described below at appropriate places. It is more desirable because it can be expected to have an effect.

Figures 9 and 10 show a representative example of such an embodiment. The relationship between both figures is the same as in FIGS. 1, 2 and 6 and 7, and FIG. 10 is taken along the section line XX in FIG.

The substrate 1 is an insulating substrate 12, which may be, for example, sapphire, spinel, or the like. On such an insulator substrate 12, good quality single crystal silicon can be grown by well-known heteroepitaxial growth or the like.

The single crystal silicon film thus grown or formed is subjected to an appropriate dry or wet etching treatment,
Form a “semiconductor island” 9. This semiconductor island 9 corresponds to a semiconductor trapezoidal portion 9 which will be referred to as a series in this document, and as shown in FIG. 9, the planar shape of the semiconductor trapezoidal portion 9 is also a quadrangle in this embodiment. ing.

Among the side surfaces of the semiconductor base portion 9 which are erected at a certain angle with respect to the main surface of the substrate, the side surfaces facing in one direction when viewed in plan have a conductivity opposite to that of the semiconductor base portion 9. Mold,
Alternatively, a source 12 and a drain 22 having lower resistance than the others are formed, and dedicated electrodes 3 and 4 are attached to each of them.

Source 21 and drain 22 and electrodes 3 and 4 that conduct electricity to them
In general, a charge storage member 6 composed of different insulating film superposition structures 61 and 62 is provided on the surface (including the side surface) of the semiconductor base 9 except the connection portion with.

On the other hand, in the direction orthogonal to the direction connecting the source and the drain in plan view, the charge storage member 6 is provided in accordance with the gist of the present invention.
N gate electrodes 51, 52, on the gate insulating film 8 serving also as
53 are provided.

Among them, the gate electrode 53 having the widest width W ₃ is formed in parallel along the flat upper surface of the trapezoidal portion 9 as in the above-described sixth and seventh embodiments, but the narrowest width W ₃ is formed. The gate electrodes 51 and 52 having a width W ₂ intermediate between W ₁ and W ₁ are formed parallel to the side surface of the trapezoidal portion.

This is because the widest width of the gate electrode 53 is formed on the upper surface of the trapezoidal portion 9 so that the thickness of the trapezoidal portion 9 can be minimized, as described in the sixth and seventh embodiments. It also means that, in fact, even a semiconductor layer of a thickness that can be epitaxially grown with good controllability on the insulator substrate 12, can be a sufficient thickness for trapezoidal portion molding, Therefore, it is also possible to prevent the device from becoming larger in the thickness direction.

For easy understanding, the relationship between the widths W ₁ , W ₂ and W ₃ of the n gate electrodes 51, 52 and 53 is shown as 1: 2: 4 also in this embodiment. Therefore, it goes without saying that the operation of the present invention described with reference to the first and second illustrated embodiments, the equations 1) to
The description of 3) and the stored contents and the read relationship thereof can be applied in the same manner in this embodiment.

However, in the case of this embodiment, the gate electrodes 51, 52 formed on the side surface of the trapezoidal portion have the portions 51 ', 52' protruding along the surface of the insulator substrate 12, but these portions 51 ' , 52 ′
Is an ineffective portion for formation of the effective charge storage region or selective channel formation. Therefore, based on the equations described in connection with the equations 1) to 3), the nonvolatile semiconductor memory device of this embodiment is The protruding portions 51 ', 52' need not be taken into account for a similar understanding of the operation.

Rather, as shown in this embodiment, the semiconductor base 9 is formed on the insulator substrate 12 to form the channel forming region 23.
When formed on the side surface of the trapezoidal portion, the gate electrode, the source electrode 3, the drain electrode 4, and the like have protrusions such as the protrusions 51 'and 52'. However, since it is only placed on the insulating substrate, no problems occur, and therefore, the dimensional accuracy of this portion can be relaxed, and there is an advantage that manufacturing is easy.

In the case where the nonvolatile semiconductor memory device of the present invention is formed on the semiconductor base portion on the insulating substrate as described above, in addition to the above, there is an advantage that no special separating means is required between adjacent devices. There is also an advantage that no particular insulation treatment or the like is required on the surface portion of the mutual wiring portion which is in contact with the substrate.

Further, when the nonvolatile semiconductor memory device of the present invention is formed on the insulating substrate, the conductive member 54 covering the lower side of the semiconductor platform 9 is placed in the insulating substrate 12 as in the eleventh embodiment. It can also be formed by embedding in.

And when such a conductive member 54 is provided, it can be used in various ways.

One is sometimes used as an electromagnetic shield. That is, like the usual shield structure, the conductive member 54 forms an electromagnetic barrier against an electromagnetic wave that may wrap around the nonvolatile semiconductor memory device of the present invention from the bottom or the thick side of the substrate. be able to. Of course, although not shown, this conductive member 54 adopts a known existing electrode connection method from an appropriate place and is provided with an electrode or terminal that can be connected to the outside, and this is grounded or dropped to a reference potential. To use.

On the other hand, when the conductive member 54 is used as a kind of auxiliary control gate and a proper bias is applied to it, the nonvolatile semiconductor memory device of the present invention can be controlled in more detail.

For example, by being provided on the side surface of the trapezoidal portion 9, it is possible to finely adjust the channel width of the channels C ₁ and C ₂ corresponding to the gate electrode width near the insulator substrate 12, or each effective channel. Irrespective of the stored contents in the charge storage region, an appropriate bias application to the conductive member 54 can prevent the channel from being induced, or an operation to prevent current from flowing in the channel.

In fact, in the latter case, the conductive member 54 can be used as an electrode for applying a read inhibit command signal when the read inhibit condition is satisfied as a special application.

In other words, in the case where the nonvolatile semiconductor memory element of the present invention is configured to change the state of a channel that has already been formed in accordance with the stored content in each effective charge storage region, It is also possible to follow an instruction to reproduce the conduction state of all channels regardless of the stored contents.

As described above, the conductive member 54 that can be selectively used for various functions can be similarly applied to the embodiment having the insulating substrate or the insulating layer as the lowermost layer in the above-described embodiments. it can.

Of course, in the two embodiments shown in the ninth to eleventh embodiments, the side surface shape of the semiconductor island or the trapezoidal portion 9 is the same as that in the eighth embodiment shown in the above, as shown in the twelfth embodiment. The more vertical it is, the smaller the area occupied by the element can be reduced. Conversely, the multi-bit area of the present invention can be made within the same area as the conventional single-bit non-volatile semiconductor memory element. Or, the multi-state memory function can be realized.

In the same manner, n floating gates 63 _-i can be used as the charge storage member 6 as shown in the thirteenth illustration, and in the twelfth and thirteenth illustrated embodiments, they are also shown by phantom lines. Thus, the auxiliary conductive member 54 shown in FIG. 11 can be similarly incorporated therein.

The operation and various considerations in this case are the same as those already described in connection with the embodiments shown in FIGS. 4 and 11 as a representative, and therefore the repetitive description is omitted here.

As shown by the phantom separation lines in FIG. 10, semiconductors generally referred to as semiconductor islands on the insulating layer in FIGS. 9 to 13 are shown. When forming the trapezoidal portion 9, even if the substrate itself is not the bulk insulator substrate 12, but on the contrary it is a suitable semiconductor substrate 11 or the like, its surface region is oxidized to an appropriate depth, or If the insulating layer 14 is formed by, for example, separately growing separately, by separately forming the semiconductor base portion 9 thereon, those embodiments can function exactly as before. . That is, the surface insulating substrate may be used instead of the bulk insulator substrate.

In particular, for a silicon oxide film, which is an amorphous material, a good quality single crystal silicon film can be formed on it by using an appropriate beam annealing technique.
It may be used as 14, and a processing procedure for forming the trapezoidal portion 9 may be adopted for the single crystal silicon film formed thereon.

Regardless of whether the substrate is a bulk insulator substrate or a surface insulating substrate, at least a semiconductor base portion 9 which is separately formed
When each of the nonvolatile semiconductor memory elements of the present invention is formed for each, in addition to the various incidental effects due to the above-mentioned insulation, it is easy to obtain a three-dimensional laminated structure. That said, it can be expected to have a considerable effect in the future.

The 14th embodiment shows a conceptual configuration in such a case.

That is, as Taki described so far, the non-volatile with n effective charge storage regions according to the present invention on the first substrate _1-1 with bulk insulation or consists of a substrate 12 an insulating layer 14 or on the surface, first one layer of a semiconductor memory device, if the formed, embedding the device by covering the upper surface with a suitable Naru insulator layer 1 _-2 the insulating layer 1 _-2 second substrate to a second surface insulating The process of considering a layer and forming again a nonvolatile semiconductor memory element having the same structure as the embedded nonvolatile semiconductor memory element thereunder is repeated over the required number of stacked layers.

This makes it possible to insulate the upper and lower layers as well as to keep an eye on the separation between the adjacent elements on the surface, and it is possible to repeat the extremely simple process to obtain an extremely high density bit. A non-volatile memory device can be provided.

Of course, in this embodiment also, although not shown in detail in FIG. 14 in order to avoid complication of the drawing,
Accordance with the purpose of the present invention, a pair of the same source, the charge storage member 6 _-1 to form an n number of the effective charge storage regions between the drain 6 _-2, heterologous insulating films 61 and 62, or more It may have a different insulating film superposition structure having a laminated insulating film, or n gate electrodes 51 _-1 , 52 _-1 , 53 _-1 : 51 _-2 that contribute to both writing and / or reading of the memory. , 52
It may be a floating gate structure provided under _-2 , 53 _-2 .

However, so far, it is possible to use the non-volatile semiconductor memory device of the present invention as an EPROM or an EEPROM, but in any case, it is finally limited to the case of handling a digital value, and In the above embodiment, the description has been made that the 3-bit binary value is read.

However, as is apparent, according to the nonvolatile semiconductor memory device of the present invention, not only is it digitally expandable to n bits, but also n charges of the effective charge storage region formed between a pair of source and drain are formed. Since it is possible to obtain the n-stage drain current I _D according to the storage state, the nonvolatile semiconductor memory device of the present invention is essentially a kind of digital-analog converter whose output is obtained. It can be said that it is a multi-bit non-volatile semiconductor memory device with analog conversion output, which is built in the stage, and in that case, the dynamic range of the reproduced analog output is (6n + 1.8) dB at maximum according to the well-known definition formula. Will be done.

Therefore, for example, in the case where the number of effective charge storage regions formed between a pair of sources and drains is 8 and the maximum number of channels is 8 (that is, 8-bit storage element) according to the present invention, the above-described embodiment As can be seen in the inside, even if linear quantization is attempted from the narrowest channel to the maximum width channel in a doubling relationship, the dynamic
A range of about 50 dB can be obtained, the effective charge storage region or channel width is intentionally removed from the doubling relation by an appropriate relation, and along with the known appropriate non-linear quantization, it can be compared with the commercially available PCM digital recording technology. Similarly, a dynamic range of up to 90 dB can be obtained. This is a sufficient value as a matter of course.

In the embodiment using the semiconductor platform 9, the
Although the planar shape of the trapezoidal portion is shown as a quadrangle, the shape is not limited to this. Even if the shape is arbitrary, it is possible to form n effective charge storage regions in the width direction orthogonal to the direction in which the source and the drain are opposed to each other. Further, although related to this, the width direction is not actually defined only within one horizontal plane. As is apparent from the type in which the side surface of the trapezoidal portion is also used, this is a concept that includes the flat surface of each portion where the source and drain are formed, and thus the side surface of the trapezoidal portion in some cases.

[Brief description of drawings]

1 and 2 are schematic configuration diagrams of a basic first embodiment of a multi-bit or multi-state nonvolatile semiconductor memory device according to the present invention,
FIG. 3 is an explanatory diagram of a memory content reading result that can be obtained in the first embodiment or another embodiment, and FIGS. 4 and 5 are schematic configuration diagrams of modified examples of the first embodiment, respectively. FIG. 7 is a schematic configuration diagram of an embodiment in which a nonvolatile semiconductor memory device of the present invention is constructed on a semiconductor base portion formed in a ridge, and FIG. 8 is a schematic configuration diagram of a modified example of the embodiments shown in FIGS. 9 and 10 are schematic configuration diagrams of an example of constructing a nonvolatile semiconductor memory device of the present invention in a semiconductor platform portion formed on an insulating substrate or a surface insulating substrate, FIG. 11, FIG. 12,
Each drawing of FIG. 13 is a schematic configuration diagram of a modified example of the embodiments shown in FIGS. 9 and 10, and FIG. 14 is a concept for developing a nonvolatile semiconductor memory device constructed according to the present invention into a three-dimensional laminated structure. It is explanatory drawing which shows a structure. In the figure, 1 is a substrate, 6 is a charge storage member, 8 is a gate insulating film, 9 is a semiconductor platform, 11 is a bulk semiconductor substrate, 12 is a bulk insulator substrate, 13 is a semiconductor layer, 14 is an insulating layer, 21 source, a drain, 23 denotes a channel forming region 22, 51, 52 gate electrode, 61 and 62 an insulating film, 63 _-1, 63 _-2, 63 _-3 floating gate, 64 _-1, 64 _{- 2} , 64 _-3 are locally formed heterogeneous insulating film polymer structures, C ₁ , C ₂ , C ₃ are channels that can be formed, W ₁ , W ₂ , W ₃
Is the width of the gate electrode or effective charge storage region or channel.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 29/792 (56) References JP 61-50369 (JP, A) JP 62- 94987 (JP, A) JP-A-60-169172 (JP, A)

Claims (3)

[Claims] 1. A semiconductor region having a channel formation region between a source and a drain, which are separated from each other, and a channel formation region, which is provided so as to cover the same while maintaining insulation, and is selected as a predetermined effective charge storage region. By selectively storing electric charge, a channel having a shape and size corresponding to the planar shape of the effective charge storage region is selectively formed on the surface of the channel formation region between the source and the drain, or the channel is formed. An electrically writable or electrically writable and erasable non-volatile semiconductor memory device having a charge storage member that changes the state of the effective charge storage region; and connecting the effective charge storage region between the source and the drain. Along the channel width direction, which is orthogonal to the channel length direction, which is the direction of the channel, is composed of three or more independent ones; and the three or more effective charge storages. The nonvolatile semiconductor memory device according to claim; that the width of each of the regions, all made different from each other. 2. The non-volatile semiconductor memory device according to claim 1, wherein the three or more effective charge storage regions are doubled in width from the narrowest to the widest. A non-volatile semiconductor memory device characterized by: 3. The non-volatile semiconductor memory device according to claim 1, wherein the three or more effective charge storage regions correspond to non-linear quantization for analog conversion and reproduction of stored logical values. , From the narrowest to the widest, the width of which is intentionally removed from the relationship;