JPH06318712A - Nonvolatile semiconductor memory element - Google Patents

Abstract

PURPOSE:To provide a nonvolatile semiconductor memory element which can store a number of bits in one element and, at the same time, has a small occupying area. CONSTITUTION:A trapezoid semiconductor section 9 with a channel forming area 23 on its surface is formed on the main surface of a substrate 1 and a charge storing member 6 is provided on the surface of the section 9. In order to divide the member 6 into effective charge storing areas respectively having prescribed widths of W1, W2, and W3, a first, second, and third gate electrodes 51, 52, and 53 respectively having the corresponding widths W1, W2, and W3 are provided. At least some of the gate electrodes, for example, the first and second gate electrodes 51 and 52 are provided along the side faces of the section 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device, and more particularly, to an improvement for making it possible to store two or more multi-bits or multi-states in a unit device and to reduce the area occupied by the device. .

[0002]

2. Description of the Related Art A non-volatile semiconductor memory device itself is well known, and various devices having respective structural and operating mechanism characteristics have been proposed so far. Electrically programmable read-only memory (EPROM) if they are classified according to the method of erasing or rewriting stored contents.
And a read-only memory (EEPROM or EAROM) that can be electrically erased or rewritten as well as programmed (written). As is well known, the former can only be written electrically, but it must be erased by another erase operation such as UV irradiation. It is clear that the latter is also superior.

On the other hand, if the charge storage members are classified regardless of whether they are EPROMs or EEPROMs, they may be represented by, for example, a polymerized structure of a silicon nitride film and a silicon oxide film in a so-called MNOS structure. And using a charge storage trap of at least one insulating film and a conductive floating gate embedded in the insulating film and not forming a discharge path anywhere, as represented by, for example, a FAMOS structure. There is something. Generally, such members and charge storage traps therein are often collectively referred to as “charge storage structure”, but in this document, they are regarded as one physical structural member, and
In addition to being called the "charge storage member", the portion of the charge storage member that actually participates in charge storage and that is responsible for channel formation and the change of the channel state underneath is called "effective charge storage member". Area ". However, in either case, it means a member capable of accumulating charges and a region capable of effectively accumulating charges, regardless of whether or not the charges are actually accumulated.

However, it is obvious that the "effective charge storage region" and the "charge storage member" may not match in the area size or geometrical shape as an object. For example, in the FAMOS structure or the like described above, the effective charge storage region involved in the memory operation of the element is almost the same as the area occupied by the floating gate with respect to the floating gate as the charge storage member. Since the polymerized film of silicon oxide film and nitride film as the different insulating film polymerized structure is not provided only between the channel formation regions between the source and the drain, it is generally provided on the entire surface of the substrate, and therefore, it is actually nonvolatile. The effective charge storage region involved in the typical memory operation is limited to the area region on a part of the channel formation region therein. Furthermore, it is also possible to classify the difference in injection mechanism of selected charges (electrons or holes) into the effective charge storage region thus defined, and each principle such as avalanche injection, tunnel injection, channel injection, etc. Used selectively.

Particularly, in an electrically erasable one such as an EEPROM, for example, the electron storage state is set to logic "1", whereas the hole storage state or the stored electron neutralization state by injection of holes, or When the emission state of the accumulated electrons is made to correspond to the logic “0”, there are some cases where different injection mechanisms are adopted for the injection of the electrons and the injection of the holes. In these non-volatile memory devices, generally, effective charge is applied so that a required bias voltage or electric field can be applied to the charge storage member or the charge injection path, and a predetermined gate voltage can be applied at the time of reading. Although a gate electrode is often provided on the storage region, in the nonvolatile semiconductor memory device according to any of the above structures or classifications, whether or not a predetermined carrier is held in the charge storage member, that is, the current device is used. Determining which logic value a stored content is, generally and simply, a channel is "conducting" or "non-conducting" at some gate voltage.
It can be done according to

[0006]

As described above, a great number of non-volatile semiconductor memory devices have been proposed so far, but none or most of them have been proposed.
Only one bit could be stored per unit of device. Therefore, when many such elements are used in a two-dimensional array, or when the three-dimensional integration which is popular these days, the bit density is naturally limited.

In view of the above, the present invention reviews the existing non-volatile semiconductor memory device to provide a non-volatile semiconductor memory device capable of storing two or more multi-bits or many states even in the same unit device. It was made according to the sense of purpose of being able to do it. In that case, regardless of whether it is an EPROM or an EEPROM as described above, as a problem of another dimension, compared with the conventional one,
The bit density within the defined geometrical area (or volume) for memory formation could be greatly improved.

Further, the present invention also aims to provide a structure capable of greatly reducing the area occupied by an element even when the number of bits is increased to at least 2 bits as described above.

[0009]

According to the present invention, in order to achieve the above object, (a) an effective charge storage region provided on a channel formation region selectively formed between a source and a drain, which are separated from each other, A plurality of them are provided independently of each other along the channel width direction orthogonal to the channel length direction which is the direction connecting the source and drain, and (b) and
A semiconductor region having a channel formation region is formed on the main surface of the bulk semiconductor substrate or on the main surface of a semiconductor layer formed on the bulk insulator substrate, and the main surface plane of the bulk semiconductor substrate or the semiconductor layer. It is composed of at least a part of the surface region of the semiconductor trapezoidal portion that is formed so as to have a side surface that stands upright, and (c) at least some of the plurality of effective charge storage regions, It is provided along the raised side surface of the semiconductor platform.

[0010]

Embodiments of the nonvolatile semiconductor memory device according to the present invention will be described in detail below with reference to FIGS. 1 to 7.
Before that, a reference element considered by the present inventor in the course of reaching the present invention will be described with reference to FIGS. 8 to 10.

FIGS. 8A and 8B show an example of a reference element as a multi-bit memory type non-volatile memory element proposed and studied in the process of reaching the present invention. This reference element is
Although disclosed in the so-called parent application of the present application,
This is called a first reference element. This first reference device is convenient for improving an existing MNOS structure device which is a single bit memory device or an EEPROM device having a similar structure. Explaining this, the substrate 1 is composed of a bulk semiconductor substrate 11 of the first conductivity type in this case, and as shown in the plane projection structure of FIG. A source 21 and a drain 22 are formed on the substrate 21 with a predetermined distance therebetween.

The source 21 and the drain 22 may be formed in a usual manner with respect to the surface region of the bulk semiconductor substrate 11, and are generally formed as regions of opposite conductivity type to the substrate 11. However, it may be a region having the same conductivity type as the semiconductor substrate 11 as long as it is formed as a region having a lower resistance than the other regions. The surface area of the semiconductor substrate between the source 21 and the drain 22 is the same as a normal nonvolatile semiconductor memory device.
The channel can be considered as a channel forming region 23 in which a channel can be selectively formed under a predetermined gate voltage application condition, but on such a semiconductor substrate surface, cross-section lines 8B-8B in FIG. As best shown in FIG. 8B, which is a cross-sectional view taken along the line, an insulating film structure 8 usually called a gate insulating film 8 is provided. Here, as an example, the existing MN
Since the aim is to improve an OS type or a single bit memory type non-volatile semiconductor memory device similar to the OS type, the gate insulating film 8 also serves as the charge storage member 6, as can be seen from these conventional structures. At least one insulating film 62 has a superposed structure of different kinds of insulating films 61 and 62 having charge storage traps.

As is well known, in the conventional MNOS structure, the first insulating film 61 is a silicon oxide film which is thin enough to allow the tunneling of carriers from the surface of the semiconductor substrate 11, and the second insulating film 61 overlapping the second insulating film 61 overlaps the first insulating film 61. Insulating film 62 is a silicon nitride film containing charge storage traps, but any combination of heterogeneous insulating film polymers that have been previously reported and will also be reported in the future as long as they can perform similar functions. A structure can also be adopted. For example, the first insulating film 61 may be a silicon direct nitride film, a silicon oxynitride film, or the like in addition to the above, and the second insulating film 62 may be a tantalum oxide film, an aluminum oxide film, or the like. Furthermore, a combination polymerization structure of three or more types may be used, for example, a thin silicon oxide film as the first insulating film, a silicon nitride film as the second insulating film, and a silicon oxide film again as the third insulating film may be used. There is a so-called MONOS structure and the like, which has a characteristic that it can be rewritten at a low voltage, and therefore can be adopted. Due to such various structures, the charge storage member 6 which also functions as the gate insulating film 8 is originally the source 21 and the drain.
It suffices if it is formed only in the space between 22. However, it is usually formed in series over the entire surface of the substrate for ease of manufacturing.
The above points can be similarly applied to the embodiments of the present invention described later.

However, in the first reference element shown in FIG. 8, polycrystalline silicon, metal, silicide, etc. are formed in the region corresponding to the source and drain on the gate insulating film 8 or the charge storage member 6. A plurality of gate electrodes made of an appropriate conductive material (three 51, 52, 53 in the case shown) are formed. Each gate electrode 51, 52, 53 defines the direction connecting the source and drain as the length direction, as clearly shown in FIG. 8A (this is the normal channel length,
Corresponding to the case of defining the concept of channel width), they are separated from each other along the width direction and exist independently.

However, in this first reference element, not only are there a plurality of gate electrodes, but also those gate electrodes 51, 5
The widths W ₁ , W ₂ and W ₃ of the respective ₂ and 53 are all different from each other, and as a desirable consideration in a sense, the first gate electrode 51 having the narrowest width W ₁ is different from the second gate electrode 52. Width of
W ₂ is 2W ₁ , the width W ₃ of the widest third gate electrode 53 is 4W ₁ ,
Is set.

Although the reason for this will be described later, if stated in advance, the mutual relationship between the widths of the respective gate electrodes is generalized by using an integer n gate electrodes of 2 or more.
To the wide one based on the narrowest width relationship n
2 ^n-1 times series relation (1,2,4,8, ...)
That is to say, there is a so-called double relationship. However, the arrangement order in the width direction is nothing but the narrowest width.
It is not necessary to arrange the first gate electrode 51 of W ₁ toward the third gate electrode 53 of the widest width W ₃ in order, and it is optional.

However, as described above, the provision of the plurality of gate electrodes 51, 52, 53 between the pair of sources and drains means that the charge storage member is actually a single member or a continuous member. Considering the function of 6,
That is, it is divided into a plurality of independent effective charge storage regions having a width corresponding to the width of each of the plurality of gate electrodes. In other words, in the case of this first reference element, a plurality of gates are formed on the charge storage member 6 as a means for providing a plurality of independent effective charge storage regions along the width direction between the source and the drain. The method of providing the electrodes 51, 52, 53 was adopted.

By the way, generally, the operation of the MOS field effect transistor is as follows 1) in the region where the drain voltage V _D is small.
It is expressed as in the equation below, and in the saturation region as in equations 2) and 3) below. _{I D ≒ (W / L)} · μ · C i · [(V G -V T) V D - (V D 2/2)] ········ 1) I D ≒ (W / 2L ) ・ Μ ・ C _i・ V _Dsat ²・ ・ ・ ・ ・ ・ 2) V _Dsat ≈ V _G −V _T '・ ・ ・ ・ 3) Where, in the above formulas 1) to 3), I _D is drain current, V _G is gate voltage, V _T is threshold voltage, V _T 'is effective threshold voltage, L is channel length, W is channel width, μ is carrier surface mobility, C _i is gate insulating film capacitance ,.

The above equations 1) and 2) are given by the given drain voltage.
It is shown that the drain current I _D is proportional to the channel width W with respect to V _D , the gate voltage V _G, and the threshold voltage V _T or V _T ′. However, in this first reference element, in the channel formation region 23 on the surface of the semiconductor substrate below each gate electrode 51, 52, 53, the charge is stored in each effective charge storage region respectively formed under each gate electrode. It is possible to selectively induce or extinguish the channels C ₁ , C ₂ and C ₃ under a predetermined common gate voltage application condition depending on whether or not is accumulated. Specifically, for example, when a relatively high voltage of a predetermined value or more is applied to the selected gate electrode, the charge storage member 6
In the inside, electrons or holes can be injected from the semiconductor substrate surface side or can be driven out from only the portion corresponding to the area or shape of the gate electrode. Therefore, the high voltage is removed accordingly. A channel is induced only in the corresponding portion in the channel forming region 23 under a predetermined common gate voltage application condition later.

Since this pattern is schematically shown in FIG. 8B, the respective gate electrodes and the effective charge storage regions corresponding to the respective gate electrodes are applied under the predetermined common gate voltage application condition as described above. Below each channel C ₁ , C ₂ ,
C ₃ is in the channel forming region 23 and is shown by a dotted line.

First, for simplicity, each channel C ₁ ,
The widths of C ₂ and C ₃ are W ₁ , W ₂ and W ₃ , respectively, which are the same as the widths of the corresponding gate electrodes 51, 52 and 53, and naturally, the mutual width relationship is 1: 2: If it is 4, the source 21 and the drain, which are the electrodes at both ends of all the channels,
In the first reference element in which 22 is common, the value W in the above formulas 1) and 2) is the width and number of channels actually induced in the channel formation region 23 under a predetermined common gate voltage application condition, It is variable depending on the combination. For example, when only the narrowest channel C ₁ is induced or “conducted” under a predetermined common gate voltage application condition, when only the channel C _{3 having the} widest width of four times is conductive, naturally, The channel width W is also 4W ₁ , and under the same applied voltage value condition, the obtained drain current _ID also becomes four times.

From the above, a nonvolatile semiconductor memory device having three individual and independent gate electrodes 51, 52 and 53, like the first reference device shown in FIGS. 8A and 8B, is provided. In contrast, when all channels C ₁ , C ₂ and C ₃ are "non-conducting" under a given common gate voltage application condition, and under the same common gate voltage application condition, all channels C ₁ , C ₂ , C ₃
9 is a schematic diagram of a typical current-voltage characteristic expected in such an element, including when the element is "conducting", as shown in FIG.
Can be realized. In the figure, "conduction" of the channel is represented by a logical value "1", and "non-conduction" is represented by a logical value "0".

That is, in the state where a certain common gate voltage V _G is applied to each of the gates 51, 52 and 53 and a predetermined drain voltage V _D is applied, by the writing operation before that,
Since only the channel corresponding to the effective charge storage region accumulating the charge capable of inducing the channel is conducted, a total of eight drain current levels can be discriminated without overlapping in the current step ΔI _D , and Further, if necessary, by attaching a load resistance having an appropriate value, it is possible to obtain eight kinds of distinguishable voltage information.

In order to make it easy to generalize further from this, it is assumed that there are n effective charge storage regions (or gate electrodes for forming the same), and the width of these n effective charge storage regions is 2 ^n-1 : 2 ^n-2・ ・ ・ ・ ・ ・ ・ ・ :: 2: 1 In the series relation, the drain current I _D is changed with a substantially constant change width ΔI _D every time the binary number is incremented by “1” or decremented. It is possible to realize an n-bit non-volatile memory element whose value changes.

Of course, as described above, every time the stored content changes in binary by a number "1", the drain current I _D as a result of reading out the stored content changes with a substantially constant change width ΔI _D. For example, after converting this into a voltage value, each memory logic value can be compared with (n-1) reference voltage levels that are set exactly in the middle between adjacent memory logic values. In the case of discrimination, it is desirable because the discrimination margin allowed for the comparison reference voltage can be maximized. However, from a theoretical point of view, it is possible to discriminate each stored logical value and to avoid duplication. If the drain currents I _D having different values are obtained, the change width ΔI _D does not have to be constant.

Further, in the above, each width of the channel selectively formed under a predetermined common gate voltage application condition,
The width of each gate electrode or the width of the effective charge storage region for forming it is assumed to be the same, and the reference numerals W ₁ , W ₂ and W ₃ are shown. However, all may not match. In such a case, of course, it is necessary to design the width of the gate electrode and the width of the effective charge storage region accompanying it so that the width of the channel that can be formed under a predetermined common gate voltage application condition has a desired width relationship. Become. As shown in FIG. 8A, the common source 21 and the common drain 22 are provided with the source electrode 3 and the drain electrode 4, respectively, by a normal technique. In addition, as shown in phantom lines in FIG. 8B, the substrate 1 is not the bulk semiconductor substrate 11 as described above, but single crystal silicon is formed on the insulating substrate 12 such as sapphire or spinel. Etc. semiconductor layer 13
In general, a semiconductor layer 13 may be provided on the insulator substrate 12, such as a heteroepitaxially grown substrate, and in such a case, a channel forming region may be provided in the semiconductor layer 13. .

As described above, FIG. 10A shows an EEPROM type which adopts a so-called floating gate structure as the charge storage member 6 in accordance with the idea that one element can handle multiple bits. The reference example which built the non-volatile memory element is shown. That is, in this reference example (referred to as a second reference element), in order to form a plurality of effective charge storage regions in the channel width direction orthogonal to the direction connecting the source and drain, each floating gate 6 is substantially Each of which has a predetermined width W ₁ ,
It is assumed that it is composed of a plurality of W ₂ , W ₃ 63 _-1 , 63 _-2 , 63 _-3 .

Therefore, if the widths W ₁ , W ₂ and W ₃ of the floating gates 63 _-1 , 63 _-2 and 63 _-3 as the widths of the effective charge storage regions are defined, the predetermined widths can be determined accordingly. The width of each corresponding channel C ₁ , C ₂ , C ₃ selectively formed in the channel formation region 23 under the condition of applying the common gate voltage is also determined, and as a result, the three floating gates 63 _-1 , 63 _-2 , The value of the current drain I _D related to the reading of a total of eight types of stored contents, which is obtained depending on how many charges are stored, including the case where the charges are stored in all 63 _{-3 and} the case where the charges are not stored, is also shown in FIG. Correspondingly, it becomes each value as shown.

Also in the case of this second reference element, at least the floating gate 6 and the semiconductor substrate need not be formed of the same insulating film with respect to the center of the floating gate 6. Alternatively, it may have a multi-layer insulation film superposition structure of more than that. Further, the structure shown in FIG. 10 (A) can be expressed in a similar structure structurally even if the structure is not an EEPROM but an EPROM.
Other parameters allow each floating gate 63 _-i
Whether (i = 1,2,3, ... n) can only electrically store only one kind of charge, or whether the stored charge can be electrically driven out EPROM depending on whether or not it is also possible to inject charges of opposite polarity.
It is decided whether to keep it on or to use EEPROM. Which method should be used may be selected from the methods required by known existing techniques, including the selection of the injection mechanism in addition to the classical avalanche injection.

As can be seen in the division of the floating gate 6,
In principle, the concept of actually forming the effective charge storage region 6 in a divided manner even as an "object" is applicable to the different insulating film structures 61 and 62 used in the first reference element, as shown in FIG.
It can be configured as shown in 0 (B). That is, the charge storage member 6 composed of the first insulating film 61 and the second insulating film 62 is divided into independent portions 64 each having a predetermined width W ₁ , W ₂ , W _3.
It consists of _-1 , _64-2 , and _64-3 . This Figure 10 (B)
In the third reference element of No. 3, the plurality of individual heterogeneous insulating film superposed structures 64 _-1 , 64 _-2 , 64 _-3 are further buried with a suitable protective insulating film 81, and then charges are injected onto the protective insulating film 81. Each of the gate electrodes 51, 52, 53 is provided that contributes only to the charge, or also contributes to the injection of the bipolar charge or the discharge of the accumulated charge. However, in the case of this reference element, as described above,
Each effective charge storage region has a width W ₁ , W ₂ , which is set in each differently formed insulating film overlapping structure 64 _-1 , 64 _-2 , 64 _-3 .
Since the width is defined by W ₃ , each gate electrode 51, 52, 53 formed on it has a width W of the effective charge storage region corresponding to itself or the width W of the superposed structure unless it overlaps with each other. _It may have a dimensional relationship such that it slightly protrudes laterally with respect to ₁ , W ₂ , and W ₃ . In order to obtain the structure of the third reference element, after forming the heterogeneous insulating film superposition structure parallel and uniformly on the substrate surface as in the first reference element shown in FIGS. 8 (A) and 8 (B). The individual parts 64 _-1 , 64 _-2 , 64 _-3 may be cut out by a method such as etching.

However, in the case of using a different type insulating film polymerized structure as the charge storage member 6, one advantage is that it can be uniformly formed on the substrate surface. In other words, in terms of simplifying the manufacturing process, it is better to use the superposed structure of the different types of insulating films 61 and 62 formed over the entire surface as the charge storage member 6 as shown in FIGS. 8 (A) and 8 (B). There are advantages over using a floating gate 63 _-i as in the reference device. In the floating gate 63 _-i , the injected charges may move laterally (parallel to the substrate surface) in the floating gate, so that the gate electrodes 51, 51 of each width defined on one floating gate are formed. It is not enough to provide 52 and 53 individually, and the specified width
In order to form the effective charge storage regions of W ₁ , W ₂ , and W ₃ , it is inevitable that a plurality of floating gates 63 _-i are individually formed as shown in FIG.

The operation of each of the reference elements examined in the course of reaching the present invention was described in detail above, but the following problems still remain. That is, as compared with the conventional single-bit memory type memory element, it is extremely significant to modify it so that one element can store multiple bits or multiple states, as can be seen from the above-described reference elements. However, in view of the reduction of the occupied area as a unit element, it may still not be sufficient to simply arrange all the gates 51, 52, 53 in parallel with the main surface of the substrate as described above.

For example, when it is desired to obtain a large drain current I _{D to} be obtained, or when three or more gates are to be arranged in parallel, the size of each gate is eventually increased, or each gate is individually increased. Is small enough, many gates are arranged side by side in a two-dimensional plane. As a result, the occupied area increases as a whole, and even though it is a single element, it may not be a small element. .

Therefore, the present invention proposes an element as defined in the essential constitution of the present application by further structurally modifying such a reference element. However,
7 to 7, the basic structure and operation principle of the non-volatile memory element in each of the reference elements described above with reference to FIGS. The same can be applied to consideration of modification examples of various members unless otherwise specified. Therefore, in order to avoid duplication, the description of the operation and the description of each member described with respect to each reference element, their modified examples, and the like will be omitted again, except for the individual items of each embodiment of the present invention.

Further, for simplification, the effective charge storage regions of the number generalized to an integer n of 2 or more according to the present invention are not limited to three, as in the above reference device, and each of the following embodiments. Also in the above, the relationship among the widths W ₁ , W ₂ and W ₃ of the first, second and third gate electrodes 51, 52 and 53 is shown as 1: 2: 4. Therefore, of course, the operation as the multi-bit memory type non-volatile memory element explained by using the first reference element shown in FIGS.
The explanations of 1) to 3) and the stored contents and the reading relationship thereof can be applied as they are to the elements of the embodiments of the present invention.

As shown in FIGS. 1A and 1B, the plurality of effective charge storage regions formed according to the present invention are all formed on the substrate 1 (as described above with reference to each reference device). In this case, not only in the plane parallel to the main surface of the bulk semiconductor substrate 11), but at least some of them (at least one or more) are semiconductor trapezoidal shapes that are relatively elevated with respect to the main surface of the substrate. It is provided on the side surface of the portion 9. That is, for example, by etching the surface of the semiconductor substrate 11 as shown in FIG.
As shown in Fig. 1B, the trapezoidal portion 9 having a quadrilateral shape in plan view is left, and as clearly shown in Fig. 1B which is a sectional view taken along a sectional line 1B-1B in Fig. 1A. After uniformly forming the charge storage member 6 including the different insulating film overlapping structures 61 and 62 on the surface of the platform 9, according to the gist of the present invention, not only the upper plane of the platform 9 but also the substrate main Some gate electrodes are also formed on the side surface of the trapezoidal portion which is in a standing relationship at a certain angle relative to the plane surface, as can be seen in, for example, the gate electrodes 51 and 52. As a result, an extremely small element can be provided from the two-dimensional concept of the occupied area as a unit element. That is, the planar occupation area of the first and second gate electrodes 51, 52 formed on the side surface of the trapezoidal portion 9 is smaller than the actual widths W ₁ , W ₂ thereof.

[0037] Specifically, as seen in this embodiment, if face down a third gate electrode 53 of the widest W ₃ on the upper surface of the stand-shaped portion 9, the width W ₃ of the third gate electrode 53 if a conventional Other first gate electrodes and second gate electrodes, when they are kept at about the same level as used in a single-bit memory type nonvolatile semiconductor memory device.
Since the widths W ₁ and W ₂ of 51 and 52 may be narrower than this, the thickness of the trapezoidal portion 9 is not necessary so much, and not only the two-dimensional planar dimension but also the height It is not necessary to increase the size in the direction. The source and drain regions 21,
22 and the electrodes 3 and 4 for conducting them are shown in FIG.
As clearly shown in (A), they may be formed on a pair of side surfaces of the trapezoidal portion orthogonal to the side surface of the trapezoidal portion on which the gate electrodes 51 and 52 are provided.

Further, even if the structure of this first embodiment element is adopted, as in the embodiment element shown in FIG.
If the side surface of the trapezoidal portion 9 is formed so as to stand up at a right angle to the main surface of the substrate, the size of the area occupied by the element can be most saved.

Further, in the device of the embodiment shown in FIGS. 1A, 1B and FIG. 3, the charge storage member 6 is used as shown in FIG.
It is also possible to change to a plurality of floating gate configurations as shown in (A). However, in that case, among the respective floating gates of the semiconductor platform 9, for example, the first and second floating gates 63 _-1 , 63
_{If the} side surface to which _-2 is attached rises almost vertically, it is rather unsuitable for embedding these floating gates 63 _-1 , 63 _-2 in the insulating film 8. It is easier in manufacturing to have at least some inclination. Of course, even if it is provided with an inclination, compared with the reference elements of FIGS. 8 to 10 in which a plurality of gate electrodes are arranged in a completely flat plane, the effect of reducing the occupied area is of course sufficient. Can be expected.

Further, as shown by the phantom separation line in FIG. 1B, the active region of the device of this embodiment is also formed on the bulk insulator substrate 12 as described above with reference to the reference device. It may be configured with respect to the formed semiconductor layer 13, and in this case also, only the semiconductor layer is formed to have the trapezoidal portion 9, as schematically shown by a part of the horizontal imaginary line in the right hand of the drawing. Alternatively, as shown by a continuous imaginary line on the contrary, the insulating substrate 12 underneath is also subjected to trapezoidal processing, and the raised portion of the insulating substrate 12 bites into the inside of the trapezoidal portion 9. You may look like you are out. This point is the same as the embodiment shown in FIG. 3 having a steep side surface, although not shown.

Rather, it is also good to follow the idea that the semiconductor base 9 is provided separately. That is, if a so-called semiconductor island is formed on the insulator substrate 12 and is used as the semiconductor base 9 as described above, various additional effects can be expected, as will be described below at appropriate places. .

FIGS. 2A and 2B show a typical example of such an embodiment. The relationship between the two figures is the same as in Figures 1 (A) and (B).
Fig. 2 (B) is taken along the section line 2B-2B in (A). To explain, the substrate 1 is an insulator substrate 12, which may be, for example, sapphire, spinel, or the like. Good quality single crystal silicon can be grown on the insulator substrate 12 by the well-known heteroepitaxial growth technique or the like. The single crystal silicon film thus grown or formed is subjected to an appropriate dry etching process or wet etching process to form a "semiconductor island" 9.
The semiconductor island 9 thus formed corresponds to the semiconductor base portion 9 which will be referred to as a series in this specification. Regarding the plane shape, as shown in FIG. 2 (A), it is also a quadrilateral in this embodiment.

Among the side surfaces of the semiconductor base portion 9 which are erected at a certain angle relative to the main surface of the substrate, the semiconductor base portion 9 is formed on the side surface facing in one direction in plan view. A source 21 and a drain 22 of opposite conductivity type or lower resistance than the other are formed, and dedicated electrodes 3 and 4 are attached to each. Except for the connection between the source 21 and the drain 22 and the electrodes 3 and 4 that conduct to them, the surface (including the side surface) of the semiconductor base 9 is composed of a superposition structure of different kinds of insulating films 61 and 62. A charge storage member 6 is provided.

On the other hand, in the direction orthogonal to the direction connecting the source and drain in plan view, the first, second and third gate electrodes 51, 51 are formed on the gate insulating film 8 which also serves as the charge storage member 6.
52 and 53 are provided. Of these, similar to the elements of the embodiments shown in FIGS. 1 and ₃ , the third gate electrode 53 having the widest width W ₃ is formed in parallel along the flat upper surface of the trapezoidal portion 9, but First and second gate electrodes with narrow width W ₁ and intermediate width W ₂
51 and 52 are formed parallel to the side surface of the trapezoidal portion. Forming the third gate electrode 53 having the widest width W ₃ on the upper surface of the trapezoidal portion 9 also means that the thickness of the trapezoidal portion 9 can be minimized as described above. In practice, even a semiconductor layer having a thickness that allows epitaxial growth on the insulator substrate 12 with good controllability can be made to have a sufficient thickness for forming the trapezoidal portion 9, and the semiconductor layer in the thickness direction of the element can be formed. It can prevent upsizing.

In the case of this embodiment, the first and second gate electrodes 51, 52 formed on the side surfaces of the trapezoidal portion 9 are the portions 51 ', 52' protruding along the surface of the insulating substrate 12. However, since these protruding portions 51 ′ and 52 ′ are ineffective portions with respect to the formation of the effective charge storage region or the selective formation of the channels C ₁ and C ₂ , 1) to 3). In order to understand the operation of the non-volatile semiconductor memory device of this embodiment based on the equation described in accordance with the equation
51 'and 52' need not be taken into account. Rather, as shown in this embodiment, when the semiconductor platform 9 is formed on the insulator substrate 12 to form the channel forming region 23, the gate electrode formed on the side surface of the platform is formed. 51, 52,
Furthermore, even if the source electrode 3, the drain electrode 4 and the like have protrusions such as the protrusions 51 'and 52' described above, since they are only placed on the insulating substrate, no problem occurs, and therefore this portion Since the dimensional accuracy of is only required, there is an advantage that it is easy to manufacture. In addition to this, it is possible to obtain an advantage that a special separating means is not required between adjacent elements and an advantage that an insulating treatment or the like is not particularly required in a surface portion of the mutual wiring portion which is in contact with the substrate.

Further, when the nonvolatile semiconductor memory element according to the present invention is formed on an insulating substrate, a conductive member 54 covering the lower side of the semiconductor platform 9 is formed as in the embodiment shown in FIG. It can also be embedded in the insulating substrate 12,
If such a conductive member 54 is provided, it can be used in various ways. For one thing, it can be used as an electromagnetic shield. That is, similar to a normal shield structure, the non-volatile semiconductor memory device of the present invention is provided with an electromagnetic barrier against an electromagnetic wave that may wrap around from below or on the thick side of the substrate. 54 can be formed. Of course, although not shown, this conductive member 54 adopts a known existing electrode connection method from an appropriate place and is provided with an electrode or terminal that can be connected to the outside, and this is grounded or dropped to a reference potential. To use.

On the other hand, when the conductive member 54 is used as a kind of auxiliary control gate and an appropriate bias is applied to it, the nonvolatile semiconductor memory device of the present invention can be controlled in more detail. For example, the channels C ₁ and C corresponding to the widths W ₁ and W ₂ of the first and second gate electrodes 51 and 52, respectively, which are provided on the side surface of the platform 9 and are close to the insulator substrate 12, are provided. _The channel is not induced by an appropriate bias application to the conductive member 54 regardless of whether the effective channel width W ₁ or W ₂ of ₂ can be finely adjusted or the stored content in each effective charge storage region. In this way, it is possible to perform an operation such that a current does not flow in the channel. In practice, in the latter case, the conductive member 54
Can be used as a special application as an electrode for applying a read inhibit command signal when the read inhibit condition is satisfied.
In other words, in the case where the nonvolatile semiconductor memory element of the present invention is configured to change the state of a channel that has already been formed in accordance with the stored content in each effective charge storage region, It is also possible to follow an instruction to reproduce the conduction states of all channels regardless of the stored contents.

As described above, the conductive member 54 which can be selectively used for various functions is similarly applied to the embodiment having the insulating substrate or the insulating layer as the lowermost layer in the above-mentioned embodiments. Also, in the embodiment shown in FIGS. 2A, 2B and 4, the side shape of the semiconductor island or the trapezoidal portion 9 is the same as that of the embodiment shown in FIG. Similarly, as shown in FIG. 5, the more vertically the insulating substrate 12 rises vertically to the substrate surface, the smaller the area occupied by the element can be made, and conversely, the conventional single-bit memory type nonvolatile semiconductor. It is possible to realize the multi-bit or multi-state storage function of the present invention within an element formation area similar to that of a memory element.

Further, as described with reference to the reference element described above, as the charge storage member 6, a plurality of floating gates 63 _-i can be used as shown in FIG. 6, and further shown in FIG. 4 and the embodiment shown in FIG. 5 described above, as shown by phantom lines in FIG.
The auxiliary conductive member 54 shown in FIG.

As shown by the phantom separation line in FIG. 2 (B), a semiconductor trapezoidal portion called a semiconductor island in the embodiments shown in FIG. 2 to FIG. 6 is shown. 9 is formed, even if the substrate itself is not the bulk insulator substrate 12 but is a suitable semiconductor substrate 11 or the like, its surface region is oxidized to a proper depth, or intentionally. It suffices that the insulating layer 14 is formed on the surface of the insulating layer 14 by being separately grown. That is, the substrate may be a surface insulating substrate instead of an insulating substrate. In particular, for a silicon oxide film, which is an amorphous material, a high-quality single crystal silicon film can be formed on it by using an appropriate beam annealing technique.
It may be used as 14, and a processing procedure for forming the trapezoidal portion 9 may be adopted for the single crystal silicon film formed thereon.

Further, regardless of whether it is a bulk insulator substrate or a surface insulating substrate, each of the nonvolatile semiconductor memory elements of the present invention is formed on at least one of the semiconductor platform portions 9 which are separately formed. When it is supposed to be done,
In addition to the various incidental effects due to the insulating property described above, it is easy to obtain a three-dimensional laminated structure, and a considerably great effect can be expected in the future.
The embodiment shown in FIG. 7 shows a conceptual configuration in such a case.

That is, as described above, a plurality of effective charge storage regions according to the present invention are provided on the first substrate _{1-1 which} is composed of the bulk insulator substrate 12 or has the insulating layer 14 on the surface thereof. first one layer of non-volatile semiconductor memory device, if the formed, the upper surface Naru suitable insulator layer 1 _-2
In coating to embed the element, the insulating layer 1 _-2 considered second insulator substrate to the second surface insulating layer, in which, similarly to the nonvolatile semiconductor memory device which is buried beneath the The process of re-forming the non-volatile semiconductor memory device having the above structure is repeated over the required number of stacked layers. This makes it possible to insulate the upper and lower layers as well as to keep an eye on the separation between the adjacent elements on the surface, and it is possible to repeat the extremely simple process to obtain an extremely high density bit. A non-volatile memory device can be provided.

Of course, also in this embodiment, FIG.
Although not shown in detail in order to avoid complication of the drawing, a charge storage member 6 _-1 , for forming a plurality of effective charge storage regions between a pair of the same source and drain,
_6-2 may be a heterogeneous insulation film 61, 62 or a heterogeneous insulation film superposition structure having more laminated insulation films, or a plurality of gate electrodes that contribute to both writing and / or reading of the memory. 51 _-1 , 52 _-1 , 53 _-1 : 51 _-2 , 5
It may be a floating gate structure provided under _2-2 and _53-2 .

In the above description, either EPROM or EEPROM can be used, but in any case, the device of the present invention is limited to the case of finally handling a digital value, and specifically, In the above embodiment, the description has been made such that the 3-bit binary value is read. However, as is apparent, according to the nonvolatile semiconductor memory device of the present invention, not only is it digitally expandable to n bits, but also n charges of the effective charge storage region formed between a pair of source and drain are formed. As shown in FIG. 9, an n-stage drain current I _D can be obtained according to the storage state. Therefore, if this is seen as it is, the nonvolatile semiconductor memory device of the present invention is essentially a digital type. -It can be said that a multi-bit non-volatile semiconductor memory device with an analog conversion output, in which an analog converter is built in its output stage,
In that case, the dynamic range of the reproduced analog output can be obtained at a maximum of (6n + 1.8) dB according to a well-known definition formula.

Therefore, for example, according to the present invention, the number of effective charge storage regions formed between a pair of source and drain is eight.
When the maximum number of channels is 8 (that is, when an 8-bit storage element is used), as seen in the above-described embodiment, the channel having the narrowest width reaches the channel having the maximum width in a doubling relationship. Even if linear quantization is attempted, a dynamic range of about 50 dB can be obtained, and the effective charge storage region or channel width is intentionally removed from the double relation by an appropriate relation, and a known appropriate non-linear quantization is performed. According to
As with the PCM digital recording technology already on the market, a dynamic range of up to 90 dB can be obtained. This is, of course, a sufficient value.

In each of the embodiments using the semiconductor trapezoidal part 9, the planar shape of the trapezoidal part 9 is shown as a quadrangle, but the present invention is not limited to this. Even if the shape is arbitrary, a plurality of effective charge storage regions can be formed in the width direction orthogonal to the source and drain facing each other and the direction connecting the source and drain. Further, although related to this, the width direction is not actually defined only within one horizontal plane. As is apparent from the type in which the side surface of the trapezoidal portion is also used, this is a concept that includes the flat surface of each portion where the source and drain are formed, and thus the side surface of the trapezoidal portion in some cases.

[0057]

[Effects of the Invention] The EEPR can be constructed as an EPROM
Although it may be configured as an OM, the other components required for them are the same as in the present invention, even though the other components remain the existing configurations.
A charge storage member facing the channel formation region defined between at least one source and one drain corresponding to each other, which has conventionally been capable of forming only a single effective charge storage region, is separated along the channel width direction. Since it is composed of a plurality of independent channels, it is possible to obtain a plurality of discrete and discriminable current output or voltage output between the source and drain depending on the number or state of the channels. In other words, the nonvolatile semiconductor memory device of the present invention can store many states or multiple bits with one device. Of course, when viewed as a memory device in which the device of the present invention is integrated, compared to the case where a conventional device is used, not only is it easier to realize a higher bit density, but a kind of parallel processing that handles multiple bits at once. It also means that processing is possible, which can contribute to speeding up various processing operations related to the memory. Further, the number of wirings required between the elements or between each element and the input / output, the power supply, and the bias can be greatly reduced as compared with the case where the conventional one-element one-bit type non-volatile semiconductor memory element is used.

According to a further important feature of the present invention, at least some (at least one or more) of the plurality of effective charge storage regions have a side surface erected with respect to the main surface of the substrate. Since it is provided along the side surface of the grooved portion, it is possible to suppress an increase in the area occupied by a single element even though it is a multi-bit memory type, and the conventional single-bit memory type nonvolatile semiconductor memory is supreme. It is also possible to keep the size almost the same as that required for forming one element. In other words, the bit density with respect to the two-dimensional plane is greatly improved by the present invention.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a basic first embodiment of a multi-bit or multi-state memory type non-volatile semiconductor memory device according to the present invention.

FIG. 2 is a schematic configuration diagram of a second embodiment element of the present invention.

FIG. 3 is a schematic configuration diagram showing a modified structure of the device of the first embodiment of the present invention.

FIG. 4 is a schematic configuration diagram showing a modified structure of a second embodiment element of the present invention.

FIG. 5 is a schematic configuration diagram showing another modified structure of the second embodiment element of the present invention.

FIG. 6 is a schematic configuration diagram of an element of still another embodiment of the present invention.

FIG. 7 is an explanatory diagram showing a conceptual configuration when a nonvolatile semiconductor memory device constructed according to the present invention is developed into a three-dimensional laminated structure.

FIG. 8 is a schematic configuration diagram of a multi-bit memory type nonvolatile memory element as a first reference element proposed in the process of reaching the present invention.

FIG. 9 is an explanatory diagram of a memory content read result applicable to the first reference element and each example element of the present invention.

FIG. 10 is a schematic configuration diagram of another reference element proposed in the process of reaching the present invention.

[Explanation of symbols]

1 substrate, 3 source electrode, 4 drain electrode, 6 charge storage member, 8 gate insulating film, 9 base parts, 11 bulk semiconductor substrate, 12 bulk insulating substrate, 13 semiconductor layer, 14 insulating layer, 21 source, 22 drain, 23 channel forming region, 51 the first gate electrode, 52 a second gate electrode, 53 a third gate electrode, 61 the first insulating film, 62 second dielectric film, 63 _-1, 63 _-2, 63 _-3 floating gate, C ₁ , C ₂ , C ₃ channels.

Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 27/115 27/12 Z

Claims (4)

[Claims] 1. A semiconductor region having a channel formation region between a source and a drain, which are separated from each other, and a channel formation region which is provided so as to cover the same while maintaining insulation, and is selected as a predetermined effective charge storage region. By selectively accumulating electric charge, a channel having a shape and size corresponding to the planar shape of the effective charge accumulating region is selectively formed on the surface of the channel forming region between the source and the drain, or the channel is formed. An electrically writable or electrically writable and erasable non-volatile semiconductor memory device having a charge storage member for changing the state of; and connecting the effective charge storage region between the source and the drain. A plurality of them are provided independently of each other along the channel width direction orthogonal to the channel length direction which is the direction; A semiconductor region on a main surface of the bulk semiconductor substrate or on a main surface of a semiconductor layer formed on the bulk insulator substrate and standing upright on the main surface plane of the bulk semiconductor substrate or the semiconductor layer. And at least a part of the surface region of the semiconductor trapezoidal portion that is formed so as to have a side surface; and at least some of the plurality of effective charge storage regions of the semiconductor trapezoidal portion. A non-volatile semiconductor memory device, which is provided along the raised side surface. 2. The non-volatile semiconductor memory device according to claim 1, wherein at least some of the plurality of effective charge storage regions have different widths from each other. . 3. The non-volatile semiconductor memory device according to claim 1, wherein the plurality of effective charge storage regions have different widths, and the widths are doubled from the narrowest one to the widest one. A non-volatile semiconductor memory device characterized by being present. 4. The nonvolatile semiconductor memory device according to claim 1, wherein the plurality of effective charge storage regions are narrowest in order to cope with non-linear quantization for analog conversion and reproduction of stored logical values. A non-volatile semiconductor memory device characterized in that its width is intentionally removed from the relation to a wide one.