JP5087009B2 - Chip-level integrated high-frequency passive device, manufacturing method thereof, and system including the same - Google Patents

Description

  Embodiments generally relate to chip level integration of devices.

  Miniaturized high frequency (RF) devices are attracting attention in situations where a smaller package convenient for the user must be realized. The RF element can use an inductor that requires high inductance (high-Q) associated with power transmission and reception of the RF element during operation.

  Generally, such High-Q elements are placed on a board close to an integrated circuit (IC) die, such as a semiconductor chip on which an active circuit is mounted. The placement of the High-Q element on the board takes into account the cost of the occupied area on the active surface of the semiconductor chip for the active elements integrated in the circuit.

  In the following, a more detailed description of the embodiments briefly described above will be given with reference to the exemplary embodiments shown in the accompanying drawings, in order to show how to obtain the embodiments. These drawings are merely exemplary embodiments and are not drawn to scale. Therefore, it should be understood that the scope of the embodiments is not limited. Embodiments will also be described and explained with additional specificity and detail through the use of the accompanying drawings in which:

FIG. 3 is a cross-sectional elevation view of a wafer being processed in one embodiment.

1B is a transverse elevation view of the wafer shown in FIG. 1A during further processing in one embodiment. FIG.

1B is a cross-sectional elevation view of the wafer shown in FIG. 1B after application of an adhesive tape in one embodiment. FIG.

1D is a cross-sectional elevation view of the wafer shown in FIG. 1C after dielectric layer formation in one embodiment. FIG.

1D is a cross-sectional elevation view of the wafer shown in FIG. 1D after formation of a high frequency passive element layer in one embodiment. FIG.

1E is a cross-sectional elevation view of the wafer shown in FIG. 1E after through-die via formation in one embodiment. FIG.

FIG. 2 is a cross-sectional elevation view of the wafer shown in FIG. 1F after removal of the adhesive tape in one embodiment.

It is an elevation sectional view of a die level high frequency passive element layer in a chip package in one embodiment.

It is an elevational sectional view of a high frequency passive element layer in which a die occupation area in a substrate in a chip package is hidden in an embodiment.

It is an elevational sectional view of the high-frequency passive element layer in which the die occupation area in the substrate in the chip package in one embodiment is partially hidden.

FIG. 6 is an elevational cross-sectional view of an encapsulated high frequency passive device layer with a partially hidden die footprint within a substrate in a chip package in one embodiment.

1 is an elevational cross-sectional view of a flip chip die level high frequency passive device layer in a chip package in one embodiment. FIG.

FIG. 2 is a detail cut away from FIG. 1E in one embodiment.

FIG. 3 is an elevational cross-sectional view of a die level high frequency passive element layer in a chip package that includes a through-die via close to the center in one embodiment.

A die-level high-frequency passive element layer in a chip package that includes a through-die via closer to the center in one embodiment, and also includes a high-frequency passive element layer in which the die occupation area is hidden in the substrate of the chip package in one embodiment FIG.

6 is a flowchart illustrating an embodiment of a method flow.

1 is an elevation view with a portion cut away showing a computer system in one embodiment. FIG.

1 is a schematic diagram of a computer system in one embodiment. FIG.

  Embodiments in this disclosure relate to an apparatus that includes a radio frequency (RF) passive component layer deployed in a chip level size near an IC die. Embodiments relate to placement of RF passive component layers both on-die and in the substrate. Embodiments also relate to a method of assembling an RF passive component layer with an IC die. Embodiments also relate to computer systems that incorporate a die level RF passive component layer. Embodiments further relate to a computer system in which an RF passive component layer is disposed in a substrate.

  The following description includes terms such as up, down, first, second, etc., which are used for illustrative purposes only and are not to be construed as limiting. The devices or articles described herein can be manufactured, used, or shipped in a number of positions or orientations. The terms “die” and “chip” generally refer to an object that is a basic workpiece that is transformed into a desired integrated circuit device by various process operations. The dies are typically isolated from the wafer, which can be formed from a semiconductor material, a non-semiconductor material, or a combination of semiconductor and non-semiconductor materials. The board typically has a resin-impregnated fiberglass structure that functions as a mounting substrate for the die.

Referring to the figure, a similar structure is shown with reference numerals with the same number at the end. In order to best illustrate the structure of the various embodiments, the drawings herein illustrate an integrated circuit structure. Thus, the actual appearance of the manufactured structure may appear different in, for example, micrographs, but includes the essential structure of the illustrated embodiment. Moreover, the drawings show the structures necessary to understand the illustrated embodiment. For the purpose of maintaining the clarity of the drawing, additional structures known in the prior art are not included.

  FIG. 1A is a cross-sectional elevation view of a wafer 100 being processed in one embodiment. Wafer 100 can be any semiconductor-containing material. During processing, the wafer 100 is manipulated to hold active devices.

  FIG. 1B is a cross-sectional elevation view of the wafer 100 shown in FIG. 1A during further processing in one embodiment. The wafer 101 is processed to include an unprocessed semiconductor material 110 (hereinafter referred to as “semiconductor substrate 110”) and an active element circuit 112 that is arbitrarily shown as a structure different from the wafer 101. Connection to the wafer 101 is made by a plurality of die bond pads, one of which is indicated by reference numeral 114. After such processing, the wafer 101 includes an active surface 116 and a backside surface 118.

  In one embodiment, active device circuit 112 includes transistors and other active devices in the semiconductor that form the circuit, such as, for example, static RAM (SRAM), embedded DRAM (eDRAM), and logic circuits.

  FIG. 1C is a cross-sectional elevation view of the wafer 101 shown in FIG. 1B after application of the adhesive tape 120 in one embodiment. Wafer 102 is bonded to adhesive tape 120 to be processed to obtain an RF active device containing layer in one embodiment. In one embodiment, the adhesive tape 120 is a thermal release tape that loses significant tack after heating so that it peels away from the active surface 116 without significantly changing the circuitry and die bond pad 114.

  FIG. 1D is a cross-sectional elevation view of the wafer 102 shown in FIG. 1C after formation of the dielectric layer 122 in one embodiment. The dielectric layer 122 is processed to electrically isolate the active device circuit 112 from the RF active device containing layer to be placed at the chip level.

  In one embodiment, a thermal process is used to grow oxide film 122 as dielectric layer 122. In one embodiment, the wafer 100 (FIG. 1A) is processed to obtain an oxide film 122 under the thermal conditions used prior to operating the wafer 100 to obtain the active device circuit 112. In one embodiment, dielectric layer 122 is an oxide that grows after manipulating wafer 100 (FIG. 1A) to obtain active device circuit 112. In one embodiment, a native oxide is used as the dielectric layer 122.

  In one embodiment, the dielectric layer 122 is a deposited oxide, such as an oxide formed by decomposition of tetraethoxysilane (TEOS). In one embodiment, the dielectric layer 122 is deposited oxynitride. In one embodiment, the dielectric layer 122 is deposited carbide. In one embodiment, the dielectric layer 122 is a deposited sulfide. In one embodiment, the dielectric layer 122 is a deposited oxysulfide. In one embodiment, dielectric layer 122 is a deposited boride. In one embodiment, dielectric layer 122 is a deposited boronitride. In one embodiment, the dielectric layer 122 is an organic layer that is adhered to the backside surface 118 of the die. In one embodiment, dielectric layer 122 is any combination of the above materials. In one embodiment, the dielectric layer 122 is a deposited dielectric material.

  In any case, after the formation of the dielectric layer 122, the die backside surface 119 is formed to cover the original die backside surface 118. Where the dielectric layer 122 has already been formed, “die backside surface” means the surface 119 unless explicitly stated as the original die backside surface 118.

In one embodiment, after processing to obtain the dielectric layer 122, the wafer 103 has an active device circuit 112, a semiconductor substrate 110, and a dielectric layer 122 that has an overall thickness of 124. In one embodiment, die thickness 126 includes the thickness of active device circuit 112 and semiconductor substrate 110, and overall thickness 124 includes die thickness 126 and dielectric layer 122 thickness. In one embodiment, the ratio of the die thickness 126 to the overall thickness 124 is, for example, approximately 1000: 1001, where the dielectric layer 122 is a native oxide on the backside surface 118 of the semiconductor substrate 110. In one embodiment, the ratio of die thickness 126 to total thickness 124 is, for example, approximately 0.5: 1, where the dielectric layer is a pre-fabricated thermal oxidation on wafer 100 (FIG. 1A). It is a material layer. In one embodiment, the ratio of the die thickness 126 to the overall thickness 124 is, for example, approximately 3: 1, where the dielectric layer 122 has a dielectric that is approximately half the thickness of the semiconductor substrate of the SiO ₂ dielectric layer 122. It has the same electrical insulation quality as the layer. In one embodiment, for example, if the dielectric layer 122 is a SiO ₂ dielectric layer 122, the ratio of the die thickness 126 to the total thickness 124 is, for example, approximately 1: 1.

  FIG. 1E is a cross-sectional elevation view of the wafer 103 shown in FIG. 1D after formation of the RF passive device layer 128 in one embodiment. Wafer 104 has been processed by bonding an RF passive element layer 128 to the backside surface 119 of the die.

  FIG. 7 is a detail cut from FIG. 1E in one embodiment. In one embodiment, the RF passive element layer 128 is a laminated material. The inset on the left side of the wafer 104 illustrates one embodiment of a laminate material that forms the RF passive component layer 128. In this embodiment, the RF passive element layer 128 includes a base dielectric 130 disposed in contact with the dielectric layer 122. The RF passive element layer 128 includes a first conductive layer 132, an intermediate dielectric 134, a conductive interconnect 136, a second conductive layer 138, and an outer dielectric 140 disposed in contact with the base dielectric 130. .

  In such a layered structure, the RF passive element layer 128 provides the structure of an element such as an inductor in one embodiment. In one embodiment, the layered tissue 128 shown in FIG. 1E has a spiral inductor according to known techniques. In one embodiment, the lamellar tissue 128 has a helical inductor according to known techniques. In one embodiment, the layered tissue 128 has a two-electrode thin film capacitor (TFC) according to known techniques. In one embodiment, the layered tissue 128 includes conductive layers in addition to the two conductive layers 132 and 138 shown in FIG. 1E to implement an interdigital capacitor (IDC) according to known techniques. In one embodiment, the RF passive element layer 128 includes a single conductive layer that forms a metal resistor in known techniques. In one embodiment, the RF passive component layer 128 includes a diode resistor according to known techniques.

  In one embodiment, conductive layers 132 and 138 are metal, such as copper, that is plated, laminated, or patterned by known techniques, similar to conductive interconnect 136. In one embodiment, base dielectric 130, intermediate dielectric 134, and outer dielectric 140 are high-K dielectric materials that are flexible and patterned using etching or stencil techniques.

  FIG. 1F illustrates a cross-sectional elevation view of the wafer 104 shown in FIG. 1E after formation of the through-die via 142 in one embodiment. The through-die via 142 is formed by a process such as mechanical drilling in one embodiment. The through-die via 142 is formed by a process such as laser drilling in one embodiment. The through-die via 142 is formed by a process such as reactive ion etching (RIE) in one embodiment.

  In one embodiment, the through-die via 142 is formed in the wafer 101 while the process shown in FIG. 1B is performed. In one embodiment, the through-die via 142 is formed in the wafer 102 while the process shown in FIG. 1C is performed. In one embodiment, through-die vias 142 are formed in the wafer 103 while the process illustrated in FIG. 1D is performed. In one embodiment, through-die vias 142 are formed in the wafer 104 while the process illustrated in FIG. 1E is performed.

  FIG. 1G is a cross-sectional elevation view of the wafer 105 shown in FIG. 1F after removal of the adhesive tape in one embodiment. If through-die vias 142 are formed in the wafer 104 during processing, further processing may include techniques such as forming interconnects as also indicated by reference numeral 142 and then using fiducial marks on the backside surface 119 of the wafer. Aligning the RF passive device layer 128 and depositing the RF passive device layer 128 to provide an electrical connection between the RF passive device layer 128 and the interconnect 142.

  If the structure deposited on the die active surface 116 has a stronger adhesion than the adhesive tape 120, the adhesive tape 120 shown in FIG. In one embodiment, the adhesive tape 120 is a heat release material that is first heated and then peeled from the die active surface 116.

  FIG. 2 is a cross-sectional elevation view of die level RF passive component layer 228 in chip package 200 in one embodiment. In one embodiment, a wafer such as wafer 106 is isolated to obtain die 201. The die 201 includes a semiconductor substrate 210, an active device circuit 212 in contact with the active surface 216, a dielectric layer 222, an RF passive device layer 228, and an interconnect 242. In one embodiment, die 201 is bonded to mounting substrate 248. In one embodiment, the die 201 is bonded to the mounting substrate 248 with an adhesive 244 such as a known die adhesive. In one embodiment, the RF passive element layer 228 remains with any known RF passive element.

  A series of bond wires provide electrical signal and power communication between the die 201 and the mounting substrate 248, and one of the bond wires in one embodiment is indicated by reference numeral 250. The bond wire 250 connects the die 201 and the mounting substrate 248 by using the die bond pad 214 and the mounting substrate bond pad. One of the mounting substrate bond pads is indicated by reference numeral 252.

  In one embodiment, at least one RF passive device is included in the RF passive device layer 228, and all electrical communication between the die active surface 216 and the RF passive device layer 228 is interconnect 242 in one embodiment. Made through. Thus, any inductive loop effect can be minimized because electrical communication between the die active surface 216 and the RF passive element is contained within the die footprint on the mounting substrate 248. Incidentally, inductive loop effects are significant when RF passive elements must be attached to the die sideways by old technology compared to some embodiments described in this disclosure.

  FIG. 3 is a cross-sectional elevation view of the RF passive element layer 328 with hidden die footprint within the mounting substrate 348 of the chip package 300 in one embodiment. In one embodiment, a wafer, such as wafer 106, is isolated to obtain die 301. The die 301 includes a semiconductor substrate 310, an active device circuit 312 in contact with the active surface 316, a dielectric layer 322 in contact with the backside surface 318, and an interconnect 342.

  The die 301 is bonded to the mounting substrate 348 in one embodiment. In one embodiment, the RF passive element layer 328 is disposed within the mounting substrate 348. Thus, during fabrication of the mounting substrate 348, the RF passive component layer 328 is fabricated in situ along with traces, bond fingers, interconnects, and other structures that may generally be required within the wire bond mounting substrate 348. Is done. In one embodiment, any known RF passive device may remain in the RF passive device layer 328.

  A series of bond wires provides electrical signal and power communication between the die 301 and the mounting substrate 348. In one embodiment, one of the bond wires is indicated by reference numeral 350. The bond wire 350 connects between the die 301 and the mounting substrate 348 using the die bond pad 314 and the mounting substrate bond pad. One of the die bond pads is indicated by reference numeral 352. In one embodiment, the RF passive device layer 328 includes at least one RF passive device, and all electrical communication between the die active surface 316 and the RF passive device layer 328 is an interconnect bond pad in one embodiment. By using 354, it is made via interconnect 342. Thus, any inductive loop effect can be minimized because the electrical communication between the die active surface 316 and the RF passive element is contained within the die footprint on the mounting substrate 348. In one embodiment, the dielectric layer 322 may be removed if the electrical insulation caused by the presence of the dielectric coating 347 or 349 on the mounting substrate is sufficient.

  FIG. 4 is a cross-sectional elevation view of the RF passive component layer 428 with the die occupying area partially hidden within the mounting substrate 448 of the chip package 400 in one embodiment. In one embodiment, a wafer, such as wafer 106, is isolated to obtain die 401. Die 401 includes semiconductor substrate 410, active device circuitry 412 on active surface 416, dielectric layer 422 in contact with backside surface 418, and interconnect 442.

  The die 401 is bonded to the mounting substrate 448 in one embodiment at the backside surface 419 of the dielectric layer. In one embodiment, the RF passive element layer 428 is disposed in the mounting substrate 448. Thus, during fabrication of the mounting substrate 448, the RF passive component layer 428 is fabricated in situ along with traces, bond fingers, interconnects, and other structures that may be typically required for the wire bond mounting substrate 448. The In one embodiment, any known RF passive element may remain in the RF passive element layer 428.

  A series of bond wires provides electrical signal and power communication between the die 401 and the mounting substrate 448. In one embodiment, one of the bond wires is indicated by reference numeral 450 and the other is indicated by reference numeral 456. The first bond wire 450 connects the die 401 and the mounting substrate 448 by using the die bond pad 414 and the first bond pad of the mounting substrate. One of the first bond pads is indicated by reference numeral 452. The second bond wire 456 connects the die 401 and the mounting substrate 448 using the die bond pad 414 that may be outside the plane shown in the cross-sectional view of FIG. 4 and the second bond pad of the mounting substrate. To do. One of the second bond pads is indicated by reference numeral 460.

  In one embodiment, the RF passive element layer 428 includes at least one RF passive element, with a slight amount between the die active surface 416 and the RF passive element layer 428 via the interconnect 442 and the interconnect bond pad 454. Telecommunications are made. Some electrical communication occurs between the die active surface 416 and the RF passive device layer 428 via the second bond wire 456 and the second attachment substrate bond pad 460. Thus, inductive loop effects are almost minimized because electrical communication between the die active surface 416 and the RF passive element is contained within the area occupied by the die 401 on the mounting substrate 448. The loop passes from the die active surface 416 just prior to the area occupied by the die 401 in the second mounting substrate bond pad 460 on the mounting substrate 448, so there is some induction between the die active surface 416 and the RF passive element. A loop effect is felt. Such an embodiment occurs when access to the RF passive device in the RF passive device layer 428 is selected to be outside the die footprint. In one embodiment, the location of the first bond pad 452 and the second bond pad 460 on the substrate is a cross-section taken from FIG. 4, so that one of them is aligned so that it is hidden in FIG.

  FIG. 5 is a cross-sectional elevation view of an RF passive device layer 528 with a hidden encapsulated die footprint within a substrate 548 of a chip package 500 in one embodiment. In one embodiment, a wafer, such as wafer 106, is isolated to obtain die 501. The die 501 includes a semiconductor substrate 510, an active device circuit 512 on the active surface 516, a dielectric layer 522 on the backside surface 518, and an interconnect 542.

  The die 501 is bonded to the mounting substrate 548 and is protected by the capsule function 562 in one embodiment. In one embodiment, the capsule function can be applied to any of the structures shown in FIGS.

  Between the die 501 and the mounting substrate 548, electrical signals and power communication are performed by a series of bond wires. In one embodiment, one of the bond wires is indicated by reference numeral 550. Bond wire 550 connects between die 501 and mounting substrate 548 using die bond pad 514 and mounting substrate bond pad. One of the bond pads is indicated by reference numeral 552.

  FIG. 6 is a cross-sectional elevation view of a flip chip die level RF passive component layer 628 in a chip package 600 in one embodiment. In one embodiment, a wafer, such as wafer 106, is isolated to obtain die 601. The die 601 includes a semiconductor substrate 610, an active device circuit 612 on the active surface 616, and a dielectric layer 622 disposed on the backside surface 618 of the semiconductor substrate 610. The die 601 also includes an RF passive element layer 628 and an interconnect 642. The RF passive element layer 628 is adhered to the backside surface 619 of the die in one embodiment. In one embodiment, any known RF passive device may remain in the RF passive device layer 628.

  Between the die 601 and the mounting substrate 648, electrical signals and power communication are performed by a series of solder bumps. In one embodiment, one of the solder bumps is indicated by reference numeral 664. The solder bump 664 connects the die 601 and the mounting substrate 648 by using the die bond pad 614 and the mounting substrate bond pad. One of the mounting substrate bond pads is indicated by reference numeral 652. The die 601 is further bonded to the mounting substrate 648 by using an underfill material 666 that protects the circuitry of the die active surface 616 in one embodiment.

  FIG. 8 is a cross-sectional elevation view of a die level RF passive component layer 828 in a chip package 800 that includes a through-die via 842 centered in one embodiment. In one embodiment, the die 801 is obtained by isolating the wafer. The die 801 includes a semiconductor substrate 810, an active device circuit 812 on the active surface 816, a dielectric layer 822, an RF passive device layer 828, and an interconnect 842. In one embodiment, the die 801 is spatially defined by a symmetry line 870 that bisects the die 801 laterally. The symmetry line 870 defines a first distance 872 to the die end 874 and a distance 876 to the interconnect 842. In one embodiment, the first distance 872 divided by the second distance 876 is approximately the same as the spatial depiction distance in FIGS. 1G and 2-7. In one embodiment, the first distance 872 divided by the second distance 876 is greater than the spatial depiction distance in FIGS. In each given arrangement of interconnects 842 to obtain a predetermined ratio of first distance 872 divided by second distance 876, for example, active surface 816 and RF passive elements in RF passive element layer 828 A given ratio may be selected to achieve a loop inductance that is useful for a given layout of the locations.

  The die 801 is bonded to the mounting substrate 848 in one embodiment. In one embodiment, the die 801 is bonded to the mounting substrate 848 with an adhesive such as the known die adhesive 844. In one embodiment, any known RF passive device may remain in the RF passive device layer 828.

  Electrical signals and power are communicated between the die 801 and the mounting substrate 848 by a series of bond wires. In one embodiment, one of the bond wires is indicated by reference numeral 850. The bond wire 850 connects the die 801 and the mounting substrate 848 using the die bond pad 814 and the mounting substrate bond pad. One of the mounting substrate bond pads is indicated by reference numeral 852.

  In one embodiment, RF passive element layer 828 includes at least one RF passive element, and all electrical communication between die active surface 816 and RF passive element layer 828 is interconnected in one embodiment. Via 842. Thus, electrical communication between the die active surface 816 and the RF passive element is contained within the area occupied by the die 801 on the mounting substrate 848 so that any inductive loop effects can be minimized. If the RF passive element must be mounted next to the die, the inductive loop effect is significant compared to some embodiments described in this disclosure.

  FIG. 9 is a cross-sectional elevation view of a die level high frequency passive component layer 928 in a chip package 900 that includes a through-die via 942 centered in one embodiment. In one embodiment, the die 901 is spatially defined by a symmetry line 970 that bisects the die 901 laterally. The symmetry line 970 defines a first distance 972 to the die end 974 and a second distance 976 to the interconnect 942. In one embodiment, the first distance 972 divided by the second distance 976 is approximately equal to the spatial depiction distance in FIGS. 1G and 2-7. In one embodiment, the first distance 972 divided by the second distance 976 is greater than the spatial depiction in FIGS. In each given arrangement of interconnects 942 to achieve a predetermined ratio of the first distance 972 divided by the second distance 976, for example, the active surface 916 and the RF passive element of the RF passive element layer 928 A given ratio can be chosen to achieve a loop inductance useful for a given layout of positions.

  The die 901 is bonded to the mounting substrate 948 in one embodiment. In one embodiment, the RF passive element layer 928 is disposed within the mounting substrate 948. Thus, during fabrication of the mounting substrate 948, the RF passive component layer 928 is fabricated in-situ along with traces, bond fingers, interconnects, and other structures that may generally be required with a wire bond mounting substrate 948. The In one embodiment, any known RF passive device may remain in the RF passive device layer 928.

  By using a series of bond wires, electrical signals and power communication is made between the die 901 and the mounting substrate 948. In one embodiment, one of the bond wires is indicated by reference numeral 950. Bond wire 950 connects between die 901 and mounting substrate 948 using die bond pad 914 and mounting substrate bond pad. One of the mounting substrate bond pads is indicated by reference numeral 952.

  In one embodiment, the RF passive element layer 928 includes at least one RF passive element, and in one embodiment, all electrical communication between the die active surface 916 and the RF passive element layer 928 is performed with an interconnect bond. This is done via the interconnect 942 using the pad 954. Thus, inductive loop effects are minimized because electrical communication between the die active surface 916 and the RF passive element is contained within the die footprint on the mounting substrate 948. In one embodiment, dielectric layer 922 may be removed if the electrical insulation caused by the presence of mounting substrate dielectric 947 or 949 is sufficient.

FIG. 10 is a flowchart 1000 illustrating a method flow embodiment. At 1010, the method includes forming a dielectric layer on the backside surface of the wafer. In one exemplary embodiment, the dielectric layer 122 is a SiO ₂ layer formed by thermally processing the wafer 100 shown in FIG. 1A.

  At 1020, the method includes forming a stack of RF passive elements on a dielectric layer. In one exemplary embodiment, the RF passive device stack 128 is aligned with the dielectric layer 122 and bonded by thermal processing (FIG. 1E). In one exemplary embodiment, dielectric layer 322 is mounted on RF passive device stack 328 that is integrated with mounting substrate 348. In one embodiment, the method ends at 1020.

  At 1030, the method includes electrically connecting a wafer or a die taken from the wafer to an RF passive device stack. In one exemplary embodiment, the RF passive element stack 128 electrically connects to the die 201 as soon as it is attached to the back surface 219 of the die (FIG. 2). In one exemplary embodiment, the RF passive element stack 328 is electrically connected to the die 301 as soon as the die 301 is mounted on the mounting substrate 348 integrally including the RF passive element stack 328 (FIG. 3). In one exemplary embodiment, the RF passive device stack 428 is electrically connected to the die 401 upon wire bonding to the mounting substrate second bond pad 460 that couples the die 401 to the RF passive device stack 428 (see FIG. FIG. 4).

  At 1040, the method includes forming a through-wafer via through the wafer. In one exemplary embodiment, the through-wafer via 142 is formed with the structure shown in FIG. 1D prior to further processing subsequent to 1020.

  At 1050, the method includes dicing the wafer. In one exemplary embodiment, the through-wafer via 142 is formed at 1040 and then the wafer is diced at 1050. In one embodiment, the method ends at 1050.

  At 1060, the method includes disposing a mounting substrate. In one exemplary embodiment, the method includes fitting the chip 201 to the mounting substrate 248. In one exemplary embodiment, the method includes fitting the chip 201 to the mounting substrate 248. In an exemplary embodiment, the method includes a method 1062 in which an RF passive element layer is included in the mounting substrate. Thus, the method flows from 1010 to 1060 and then 1062. In one embodiment, the method ends at 1062.

  FIG. 11 is an elevational view with a portion cut away showing the computer system 1100. One or more of the aforementioned RF passive device layer embodiments may be utilized in a computer system, such as the computer system 1100 of FIG. Hereinafter, embodiments of the RF passive element layer will be described alone or in combination with other embodiments, but will be referred to as one embodiment or multiple embodiments.

  The computer system 1100 includes, for example, at least one processor (not shown) enclosed in an IC chip package 1110, a data storage system 1112, at least one input device such as a keyboard 1114, and at least one output device such as a monitor 1116. Including. Computer system 1100 includes a processor that processes data signals, and may include, for example, a microprocessor available from Intel. In addition to the keyboard 1114, the computer system 1100 may include other user input devices such as a mouse 1118, for example. Computer system 1100 may include a given RF passive device layer embodiment after processing as shown in FIGS. 1G and 2-9.

  For purposes of this disclosure, a computer system 1100 incorporating components in accordance with the claimed subject matter is coupled to data storage such as, for example, dynamic RAM (DRAM), polymer memory, flash memory, and phase change memory. Any system utilizing a microelectronic device system that may include at least one of the RF passive component layer embodiments may be included. In this embodiment, the embodiment is coupled to any combination of these functions by being coupled to the processor. However, in one embodiment, the configuration of the embodiment / embodiments described in this disclosure is coupled to any of those functions. For example, in one embodiment, the data store includes embedded DRAM on the die. Also, in one embodiment, the configuration of the embodiment coupled to a processor (not shown) is part of a system having the configuration of the embodiment coupled to data storage in a DRAM cache. Further, in one embodiment, the configuration of the embodiment is coupled to data store 1112.

  In one embodiment, the computer system 1100 may also have a digital signal processor (DSP), microcontroller, application specific integrated circuit (ASIC), or die that includes a microprocessor. In this embodiment, the configuration of the embodiment is coupled to any combination of these functions by being coupled to the processor. For example, in one embodiment, the DSP is part of a chipset that may include a stand-alone processor as a separate part of the chipset on the board 1120 and the DSP. In this embodiment, the configuration of the embodiment is coupled to the DSP, and there is a configuration of another embodiment that is coupled to the processor in the IC chip package 1110. In one embodiment, the configuration of the embodiment is coupled to a DSP that is mounted on the same board 1120 as the IC chip package 1110. The configurations of the embodiments can be combined as described with respect to the computer system 1100 with the configurations of the embodiments described by the various embodiments of the RF passive device layer within the scope of this disclosure and their equivalents. I want you to understand.

  It should be understood that the embodiments described within this disclosure are applicable to devices and apparatuses other than conventional computers. For example, the die can be implemented with the configuration of the embodiment, and can be installed in a portable terminal such as a wireless communication device or a handheld device such as a PDA. Another example is a die that can be implemented with the configuration of the embodiment and placed in a vehicle such as, for example, an automobile, a locomotive, a ship, or a spacecraft.

FIG. 12 is a schematic diagram of an electronic system 1200 in one embodiment. The electronic system 1200 shown may represent the computer system 1100 shown in FIG. 11, but is more generally represented. The electronic system 1200 incorporates at least one electronic assembly 1210, such as the IC die shown in FIGS. In one embodiment, electronic system 1200 includes a system bus 1220 that electrically couples various components of electronic system 1200. The system bus 1220 is a single bus or any combination of buses in various embodiments. The electronic system 1200 includes a voltage source 1230 that provides power to the integrated circuit 1210. In some embodiments, voltage source 1230 provides current to integrated circuit 1210 via system bus 1220.

  In one embodiment, integrated circuit 1210 is electrically coupled to system bus 1220 and includes any circuit or combination of circuits. In one embodiment, integrated circuit 1210 includes any type of processor 1212. As used herein, processor 1212 means any type of circuit, such as, but not limited to, a microprocessor, microcontroller, graphics processor, digital signal processor, or other processor. . Another type of circuit that may be included in the integrated circuit 1210 is a custom circuit or ASIC such as a communication circuit 1214 used in wireless devices such as mobile phones, pagers, portable computers, two-way radios, and similar electronic systems. . In one embodiment, processor 1210 includes on-die memory 1216, such as SRAM. In one embodiment, processor 1210 includes on-die memory 1216, such as DRAM.

  In one embodiment, the electronic system 1200 also includes an external memory 1240 that includes a main memory 1242 in RAM format, one or more hard drives 1244, and / or a diskette, compact disc (CD), digital video. It may include one or more memory elements suitable for a particular application, such as a disk (DVD), removable media 1246 such as a flash memory key, and one or more drives that handle other known removable media.

In one embodiment, the electronic system 1200 also includes a display 1250 and an audio output 1260. In one embodiment, electronic system 1200 includes a controller 1270 such as a keyboard, mouse, trackball, game controller, microphone, voice recognition device, or any other device that inputs information to electronic system 1200.

  As shown herein, integrated circuit 1210 may be an electronic package, an electronic system, a computer system, one or more methods of manufacturing an integrated circuit, as well as an integrated circuit and the various described herein. Can be implemented in a number of different embodiments, including one or more methods of manufacturing electronic assemblies including RF passive component containing layers in these embodiments, and their technically recognized equivalents. The elements, materials, geometry, dimensions, and order of operations can all be changed to suit specific implementation requirements.

  The abstract follows U.S. 37 CFR 1.72 (b) so that the reader can quickly ascertain the nature and spirit of the technical disclosure. It should be understood that the summary is not intended to be used to interpret or limit the spirit or meaning of the claims. In the foregoing detailed description, various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, the appended claims reflect less subject matter than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, each of which constitutes a separate preferred embodiment.

  Those skilled in the art will recognize the details, materials, arrangement of parts, and method steps that have been described and illustrated to explain the nature of the invention from the principles and scope of the invention as expressed in the appended claims. It will be readily understood that various changes can be made without departing.

Claims (18)

A die including an active surface and a backside surface;
A dielectric layer disposed on the backside surface;
A mounting substrate disposed adjacent to the dielectric layer;
At least one high-frequency passive element (RF passive element) disposed in the mounting substrate;
An electrical connection between the active surface and the at least one RF passive element;
A device comprising:   The apparatus of claim 1, wherein the electrical connection comprises a die-through interconnect through the die.   3. The device of claim 1 or claim 2, wherein the dielectric layer is selected from oxides, oxynitrides, carbides, sulfides, oxysulfides, borides, boronitrides, organics, and combinations thereof. .   The apparatus according to any one of claims 1 to 3, wherein the RF passive element comprises an inductor selected from a spiral inductor, a helical inductor, and combinations thereof.   The apparatus according to any one of claims 1 to 3, wherein the RF passive element includes a capacitor selected from a two-electrode thin film capacitor, an interdigital capacitor, and combinations thereof.   4. The apparatus of any one of claims 1 to 3, wherein the RF passive element comprises a resistor selected from a metal resistor, a diode, and combinations thereof.   The apparatus according to any one of claims 1 to 3, wherein the RF passive element includes at least two of an inductor, a capacitor, and a resistor.   The electrical connection is a die-through interconnect, the die having a die end and a die center, and the die-through interconnect is disposed closer to the die end than the die center. A device according to any one of claims 1 to 7.   The electrical connection is a die-through interconnect, the die having a die end and a die center, and the die-through interconnect is disposed closer to the die center than the die end. A device according to any one of claims 1 to 7.   The apparatus according to any one of claims 1 to 9, wherein the die is disposed on the mounting substrate in a configuration selected from wire bond and flip chip. Forming a dielectric layer on the backside surface of the wafer including an active surface and a backside surface;
Dicing the wafer to obtain at least one die;
Bonding the die to a mounting substrate,
The mounting substrate includes a high-frequency passive element-containing layer (RF passive element-containing layer) electrically connected to the active surface, and the dielectric layer includes the active surface of the die and the RF passive element-containing layer. Placed between,
Method. Forming a dielectric layer on the backside surface of the wafer including an active surface and a backside surface;
Forming a through-die via in the wafer;
Dicing the wafer to obtain at least one die;
Bonding the die to a mounting substrate including a high frequency passive element containing layer (RF passive element containing layer);
And said through-die through-via will be connected to the active surface of the wafer and the RF passive-device-containing layer,
And the dielectric layer is disposed between the active surface of the die and the RF passive element containing layer .   13. The method of claim 11 or claim 12, wherein the mounting substrate receives the die with the RF passive element containing layer. Bonding the die to the RF passive element containing layer by a method selected from bonding through a die-through via using an interconnect, bonding by wire bonding, and a combination thereof To do
14. The method according to any one of claims 11 to 13, further comprising: Obtaining at least one die by dicing the wafer results in the at least one die including a die end and a die center;
The method further includes coupling the die to the RF passive component containing layer by using interconnects and through-die vias;
The through-die via is disposed closer to the center of the die than the end of the die.
14. A method according to any one of claims 11 to 13. A die including an active surface and a backside surface;
A dielectric layer disposed on the backside surface;
A mounting substrate disposed adjacent to the dielectric layer;
At least one high-frequency passive element (RF passive element) disposed in the mounting substrate;
An electrical connection between the active surface and the at least one RF passive element;
Dynamic RAM coupled to the die;
A system comprising:   The system of claim 16, wherein the system is located in one of a computer, a wireless communicator, a handheld device, an automobile, a locomotive, an aircraft, a ship, and a spacecraft.   18. The system of claim 16 or claim 17, wherein the die is selected from a data storage device, a digital signal processor, a microcontroller, an application specific IC, and a microprocessor.

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