FR2832855A1 - Integrated circuit with inductance comprises spiral channel in which metal deposit forms inductance winding - Google Patents

Abstract

The monolithic circuit includes a substrate (11) on which an inductance is formed. This is achieved by depositing a conducting material on one wall of a spiral channel. The channel may be filled with insulating material. The monolithic circuit includes a substrate (11) on which an inductance is formed. On one surface of the substrate a channel (21) is formed, and this may be in the form of a spiral, extending between a central hole and an outer hole defining the outer end of the spiral. This channel may be formed by laser action. The surface of the channel and that of the end hole is then insulated. Insulation may be achieved in the process by thermal oxidation, whilst the channel itself may alternatively be cut by plasma etching. A conducting material is deposited on at least one wall of the channel, defining a conductive path between the two extreme holes. This conductive spiral forms the inductance. The channel may finally be filled with a further quantity of insulating material.

Description

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La présente invention concerne un circuit monolithique intégrant des éléments passifs, de type inductance, résistance, condensateur, et un nombre limité d'éléments actifs, tels qu'une diode de protection. DOUBLE SIDED MONOLITHIC CIRCUIT

The present invention relates to a monolithic circuit integrating passive elements, of the inductance, resistance, capacitor type, and a limited number of active elements, such as a protection diode.

More particularly, the present invention relates to a monolithic circuit comprising connection pads intended to receive, for example, solder balls for directly connecting one of the faces of the monolithic circuit to an external element, for example a printed circuit, according to a so-called "flip-chip" mounting.

FIG. 1 represents a section of a conventional monolithic circuit 10 comprising, by way of example, an inductor 11, a resistor 12, a capacitor 13, and a protection diode 14, connected in series. Only three metallization levels are shown in Figure 1. The monolithic circuit could possibly include one or more additional metallization levels not playing a role in the present invention.

A semiconductor substrate 15, for example silicon, contains semiconductor components, for example a lightly doped N-type well 16 in which a P-type anode region 17 of the diode 14 and a

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 N-type cathode region 18 more heavily doped than well 16.

 The substrate 15 is covered with a stack of first 20, second 21 and third 22 insulating layers. The first insulating layer 20 can be made of silicon oxide, and the second and third insulating layers 21, 22 of a material with a low dielectric coefficient, for example benzo-cyclo-butene (BCB).

 The inductor 11 comprises a conductive spiral 23, for example made of copper, belonging to the second metallization level and which rests on the upper surface of the second insulating layer 21. The inductor 11 has a first end 24 at the edge of the spiral and a second end 25, located substantially in the center of the spiral 23.

 The resistor 12 is produced on the first insulating layer 20. It comprises a first terminal 26, covering a metal portion 27, for example made of aluminum, of the first level of metallization. The first terminal 26 is connected to a second terminal 28 by a resistive strip 29, for example, of tantalum nitride (TaN), deposited on the first insulating layer 20. The second terminal 28 of the resistor 12 covers a metal portion 30, for example aluminum, of the first level of metallization.

 The capacitor 13 is produced on the first insulating layer 20. It comprises a first plate 31 which is composed for example of a metal strip, for example of aluminum, of the first level of metallization. A second plate 32 extends over the first plate 31 and is separated from the latter by a dielectric layer, for example made of silicon nitride 33. The second plate 32 is made of a metal, for example copper, of the second level of metallization, deposited on the layer of silicon nitride 33 at an opening made in the second insulating layer 21.

 The first end 24 of the inductor 11 is extended by a first connection track 34 connected to a

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 first connection pad 35 of the third metallization level. The first connection pad 35 is intended to receive a solder ball 36 for fixing the monolithic circuit 10 to an external element.

 The second end of the inductor 25 is connected, via a via 37 passing through the second insulating layer 21, to one end of a connection track 38, made of a metal, for example aluminum , of the first metallization level deposited on the first insulating layer 20. The opposite end of the connection track 38 is connected, via a via 39 passing through the second insulating layer 21, to a second connection track 40 consisting of a metal strip, for example copper, of the second metallization level, deposited on the second insulating layer 21.

 The second connection track 40 makes the connection between the inductor 11 and the resistor 12. The second connection track 40 is connected, via a via 41 passing through the second insulating layer 21, to the first terminal 26 of the resistor 12.

 The second terminal 28 of the resistor 12 is connected, via a via 42 passing through the second insulating layer 21, to a third connection track 43, consisting of a metal strip, for example copper, of the second metallization level, deposited on the second insulating layer 21. The third connection track 43 connects the resistor 12 to the capacitor 13, and is connected to the first plate 31 of the capacitor 13 by a via 44 passing through the second insulating layer 21. It is also connected to a second pad of connection 45, of the third metallization level, receiving a solder ball 46.

 The second plate 32 of the capacitor 13 is extended by a fourth connection track 47, connected at one end to the anode region 17 of the diode 14 by a via 48 passing through the second insulating layer 21.

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 The cathode region 18 of the diode 14 is connected, via a via 49 passing through the second insulating layer 21, to a fifth connection track 50, consisting of a metal strip, for example copper, of the second metallization level, deposited on the second insulating layer 21. The fifth connection track 50 is connected to a third connection pad 51 receiving a solder ball 52.

 The three connection pads 35, 45, 51 belong to a set of pads, formed in the third metallization level, intended, for example, for direct mounting of the upper face of the monolithic circuit on a printed circuit, according to the so-called "assembly". flip-chip ".

 One drawback of such a structure is that the possibilities of arrangement of the connection pads 35, 45, 51 are limited. In fact, during direct mounting of the monolithic circuit 10 on a printed circuit, pressure is exerted at the level of the connection pads 35, 45, 51. When a connection pad 35, 45, 51 is close to a passive component, the stresses exerted on the connection pad can damage the component. For example, in the case of the capacitor 13, the dielectric layer 33 can be damaged. We therefore seek to move the connection pads as far as possible from the passive components. However, it is often difficult to separate the connection pads sufficiently, so that the risk of degrading the reliability of the passive components cannot be completely avoided.

 In addition, as it is often desired to integrate a diode 14 in the monolithic circuit, the substrate 15 is chosen from a semiconductor material, for example silicon. The first insulating layer 20 must be thin for compatibility with the fabrication of the diode, parasitic capacitive and resistive couplings occur between the passive components 11, 12, 13 and the substrate 15, and more particularly between the inductance 11 and the substrate 15. In addition, the first insulating layer can, when strong voltage peaks are

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 applied to the monolithic circuit 10, snap and cause the shortening of the metal strips, deposited on the first insulating layer 20, and of the substrate 15.

 The present invention aims to propose a monolithic circuit comprising passive components and connection pads for directly connecting a face of the monolithic circuit to an external element in which the arrangement of the connection pads is not limited by the presence of the passive components.

 It also aims to obtain a monolithic circuit comprising a semiconductor substrate and having reduced capacitive and resistive couplings between the semiconductor substrate and the passive components.

 To achieve these objects, the present invention provides a monolithic circuit comprising passive components and at least one active component, a semiconductor substrate having a first face and a second face opposite the first, and connection pads intended to receive means for connection to fix the monolithic circuit on an external element, in which the passive components are produced on the side of the first face of the substrate; the active component is produced in the substrate on the side of the second face; and the connection pads are made on the side of the second face of the substrate.

 According to another characteristic of the invention, terminals of the passive components are connected to connection pads and / or to terminals of the active component via vias passing through the semiconductor substrate from the first face to the second face .

 According to another characteristic of the invention, the semiconductor substrate comprises an insulating box of porous silicon oxidized on the side of the first face.

 According to another characteristic of the invention, the circuit comprises an inductor disposed directly on the first face of the substrate at the level of the insulating box.

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 According to another characteristic of the invention, the circuit comprises an insulating substrate disposed between the passive components and the semiconductor substrate, the insulating substrate being fixed on the first face of the semiconductor substrate.

 According to another characteristic of the invention, the insulating substrate is made of glass.

 According to another characteristic of the invention, the passive components and the active components are interconnected by vias passing through the semiconductor substrate and the insulating substrate.

According to another characteristic of the invention, the circuit comprises an inductor produced directly on the insulating substrate
These objects, characteristics and advantages, as well as others of the present invention will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures, among which: FIG. 1, previously described , shows a section of a conventional monolithic circuit comprising an inductance, a resistor, a capacitor and a diode; FIG. 2 represents a section of a first embodiment of a monolithic circuit according to the invention; and FIG. 3 represents a section of a second embodiment of a monolithic circuit according to the invention.

 Three embodiments of the present invention will be described in detail. It will be noted that in the various figures, as is usual in the field of the representation of a monolithic circuit, the thicknesses and lateral dimensions of the various layers are not drawn to scale neither within the same figure, nor from one figure to another to improve the visibility of this figure. Furthermore, the same references will denote, in the different figures, the same elements.

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 As shown in FIG. 2, the monolithic circuit comprises a substrate 15 covered with a stack of first, second and third insulating layers 20, 21, 22.

The monolithic circuit comprises an inductor 11, a resistor 12 and a capacitor 13 connected in series, with structures identical to those of FIG. 1. The first insulating layer 20 may be thick.

 The three passive components are produced on the side of a first face 60 of the substrate 15. An active component such as a protective diode 65 is produced in the substrate 15 on the side of a second face 61 opposite the first face 60. The diode 65 is composed of a lightly doped N-type well 66, which comprises a P-type anode region 67 and a N-type cathode region 68 more heavily doped than the well 66.

 On the side of the second face 61, the substrate 15 is covered with fourth and fifth insulating layers 68,69. The fourth insulating layer 68 can be made of silicon oxide, and the fifth insulating layer 69 of a material with a low dielectric coefficient.

 On the side of the second face 61, a first connection track 34, connected to one end 24 of the inductor 11, is connected, via a via 70 passing through the second insulating layer 21, to a metal strip 75 of the first metallization level deposited on the first insulating layer 20. The metal strip 75 is connected by a via 76 traversing the entire thickness of the substrate 15 from the first face 60 to the second face 61, to a fifth connection track 77, of the first level of metallization deposited on the fourth insulating layer 68.

 A fourth connection track 47 extending the second plate 32 of the capacitor 13 is connected, via a via 79 passing through the second insulating layer 18, to a metal strip 80, of the first metallization level, deposited on the first insulating layer 20. The strip metallic 80 is connected, via a via 81 passing through the thickness of the substrate 15, to

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 a sixth connection track 82, of the first metallization level, deposited on the fourth insulating layer 68.

 The vias 76, 81 passing through the semiconductor substrate 15 can be manufactured by any known means, for example from perforations, by electrolysis, by temperature gradient methods, etc. The walls of the vias can be isolated if necessary. The conductor of the vias may be a metallic material or a strongly doped semiconductor with a conductivity type opposite to that of the substrate.

 The sixth connection track 82 connects the anode region 67 of the diode 65. The cathode region 68 of the diode is connected to a seventh connection track 83, of the first metallization level, deposited on the fourth insulating layer 68. The fifth and seventh connection tracks 77, 82 are respectively connected to connection pads 85, 86, produced in a second metallization level, each receiving a solder ball 87, 88.

 The connection pads 85.86 belong to a set of connection pads formed on the side of the second face 61 of the substrate 15, in the second metallization level, intended, for example, for direct mounting of the underside of the monolithic circuit on a printed circuit, according to a so-called "flip-chip" circuit.

 Figure 3 shows a sectional view of a second embodiment of a monolithic circuit according to the invention.

 The substrate 15 comprises an insulating box 89, made of porous oxidized silicon, produced on the side of the first face 60, and which extends over the entire first face 60. The insulating box 89 can be obtained by localized electrolysis of the substrate 15 followed oxidation. The first insulating layer present in the first embodiment is then no longer necessary in the second embodiment.

 The inductor 11 is made directly on the oxidized porous silicon box 89. It comprises a metal spiral 90, for example aluminum, of the first level

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 metallization, a first central end 91 of which is connected, via a via 92 passing through the insulating layer 21, to a connection track 93 of the second metallization level. The connection track 93 is connected, via a via 94 passing through the insulating layer 21, to a terminal 26 of the resistor 12.

The outer end 95 of the inductor 11 is connected to via 76 passing through the substrate 15.

 During the production of the oxidized porous silicon box 89, portions of monocrystalline silicon may be left in place at the vias 76, 81 passing through the entire thickness of the substrate 15 if the embodiment of the vias requires it.

 According to a variant of the second embodiment, the insulating box 89 is produced only at the level of the inductor 11, an insulating layer similar to the first insulating layer of the first embodiment being provided everywhere else.

 According to a third embodiment, the semiconductor substrate is bonded on the side of its first face on an insulating substrate, for example glass, on which the various passive components are made. The substrates can be glued with a conventional glue or by a technique called "wafer bonding". The structure obtained has a representation similar to that of FIG. 3, the box 89 being in fact replaced by the glass substrate. In particular, the inductor 11 is produced directly on the insulating substrate. In the third embodiment, the vias 70.80 can be produced in common with the silicon and glass substrate once the two substrates are bonded to each other or produced separately on the silicon substrate and the substrate. glass.

 The present invention has many advantages.

 For the three embodiments of the invention, the connection pads, making it possible to connect one face of the monolithic circuit directly to a printed circuit, are

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 arranged on the side of the second face of the substrate opposite the face where the various passive components are made.

 Consequently, during the mounting of the monolithic circuit on a printed circuit, the stresses which appear at the level of the connection pads are not transmitted to the various passive components.

 In addition, the realization of a monolithic circuit whose connection pads are located on the side opposite the side where the passive components are made improves by about 40% the integration of this sector.

 In addition, on the side of the second face of the substrate, the absence of passive components gives more freedom during the arrangement of the connection pads which can be chosen to obtain optimal fixing.

 For the three embodiments of the invention, the thickness of insulation present between the passive components and the substrate can be increased, which makes it possible to reduce the resistive and capacitive couplings between the passive components and the semiconductor substrate and Avoid any short circuit between the metal strips of the first metallization level and the substrate when applying voltage spikes.

 This is obtained, in the first embodiment by the first thick insulating layer, in the second embodiment, by the thick insulating box, and in the third embodiment, by the insulating substrate.

 In addition, in the second and third embodiments, the inductance can be performed directly on the first face of the substrate with an improved quality factor.

 Of course, the present invention is susceptible to various variants and modifications which will appear to those skilled in the art. In particular, only two connection pads have been shown in FIGS. 2 and 3. Those skilled in the art will be able to choose the number and arrangement of the different connection pads as a function of the fixing characteristics that they wish to obtain. In addition, one can choose, depending on the

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 envisaged manufacturing technologies, insulating and conductive materials other than those specifically described. Finally, to ensure the connection between a metal strip of a higher metallization level with a metal strip of a lower metallization level, it is possible, instead of a via passing through the insulating layer separating the two metal strips, opening in the insulating layer in which extends one end of the metal strip of the upper metallization level to connect to the metal strip of the lower level.

Claims (8)

1. Monolithic circuit (10) comprising passive components (11,12, 13) and at least one active component (65), a semiconductor substrate (15) having a first face (60) and a second face (61) opposite to the first, and connection pads (85.86) intended to receive connection means (87.88) for fixing the monolithic circuit to an external element, characterized in that: - the passive components are produced on the side of the first face of the substrate; the active component is produced in the substrate on the side of the second face; and - the connection pads are produced on the side of the second face of the substrate.  2. Monolithic circuit according to claim 1, characterized in that terminals of the passive components (11,12, 13) are connected to connection pads (85,86) and / or to terminals of the active component (65) by via vias (76, 81) passing through the semiconductor substrate (15) from the first face (60) to the second face (61).  3. Monolithic circuit according to claim 1, characterized in that the semiconductor substrate (15) comprises an insulating box (89) of porous silicon oxidized on the side of the first face (60).  4. Monolithic circuit according to claim 3, characterized in that it comprises an inductor (11) disposed directly on the first face (60) of the substrate (15) at the level of the insulating box (89).  5. Monolithic circuit according to claim 1, characterized in that it comprises an insulating substrate disposed between the passive components and the semiconductor substrate, the insulating substrate being fixed on the first face (60) of the semiconductor substrate (15).  6. Monolithic circuit according to claim 5, characterized in that the insulating substrate is made of glass. <Desc / Clms Page number 13>  7. Monolithic circuit according to claim 5, characterized in that the passive components and the active components are interconnected by vias passing through the semiconductor substrate and the insulating substrate.  8. Monolithic circuit according to claim 5, characterized in that it comprises an inductor produced directly on the insulating substrate.