JP5080894B2 - Display device - Google Patents

Description

  The present invention relates to a display device, and more particularly to a display device capable of improving the luminance of the display device and further reducing power consumption.

  A general liquid crystal display device includes two display panels each having a pixel electrode and a common electrode, and a liquid crystal layer having dielectric anisotropy sandwiched therebetween. The pixel electrodes are arranged in a matrix, are connected to switching elements such as thin film transistors (TFTs), and receive data signals sequentially row by row. The common electrode is formed over the entire surface of the display panel and receives a common voltage. The pixel electrode, the common electrode, and the liquid crystal layer between them constitute a liquid crystal capacitor in terms of circuit, and the liquid crystal capacitor is a basic unit constituting a pixel together with a switching element connected thereto.

  In such a liquid crystal display device, a voltage is applied to two electrodes to generate an electric field in the liquid crystal layer, and the intensity of this electric field is adjusted to adjust the transmittance of light passing through the liquid crystal layer. Get an image. At this time, the voltage polarity of the data signal with respect to the common voltage is inverted for each frame, for each row, or for each pixel in order to prevent a deterioration phenomenon caused by a long application of an electric field in one direction to the liquid crystal layer.

  However, in the case of row inversion, the range of the data voltage for image display is smaller than in the case of dot inversion in which the polarity of the data voltage with respect to the common voltage is inverted for each pixel. Therefore, when the threshold voltage for driving the liquid crystal is high as in a VA (vertical alignment) mode liquid crystal display device, the range of the data voltage used to represent the gradation for actual image display is only the threshold voltage. As a result, there is a problem that a desired luminance cannot be obtained.

  In addition, in the case of a small and medium-sized display device used for a mobile phone or the like among liquid crystal display devices, row inversion that reverses the polarity of a data voltage with respect to a common voltage for each row is performed in order to save power consumption. However, even small and medium-sized display devices have a problem that the resolution is gradually increased and the power consumption is gradually increasing.

Accordingly, the present invention has been made in view of the above-described problems in the conventional display device, and an object of the present invention is to provide a display device capable of improving the luminance of the display device.
Another object of the present invention is to provide a display device capable of reducing the power consumption of the display device.

In order to achieve the above object, a display device according to the present invention includes a plurality of gate lines that transmit a general gate signal including a gate-on voltage and a gate-off voltage, and a plurality of data lines that cross the gate line and transmit a data voltage. A plurality of storage electrode lines that extend in parallel with the gate line and transmit a sustain signal; a switching element connected to the gate line and the data line; and a common voltage having a certain value with the switching element. A plurality of pixels each having a liquid crystal capacitor connected to the storage element, a storage capacitor connected between the switching element and the storage electrode line, and a similar gate based on the general gate signal A plurality of similar gate driving circuits for generating a signal, and a plurality of sustain signal generating circuits for generating the sustain signal based on the similar gate signal When have, when the data voltage charged is positive, the sustain signal changes from a low level to a high level, when the data voltage to be the charge is negative, the sustain signal is high The similar gate driving circuit generates the similar gate signal by delaying the general gate signal by a time of 2 horizontal periods [2H], and the sustain signal generation circuit applies to each pixel. Immediately after the charging of the data voltage to the liquid crystal capacitor and the storage capacitor is completed, the applied sustain signal is applied to the sustain electrode line, and each of the similar gate driving circuits corresponds to the general gate line. An input unit that applies an output voltage in response to a gate signal, an output unit that applies a similar gate signal in response to a first clock signal based on the output voltage, and a connection to the output unit A stabilization unit that applies the gate-off voltage, the second clock signal, and the output voltage, and stabilizes the state of the similar gate signal according to a state change of the first clock signal; and the stabilization unit The gate-off voltage, the next-stage similar gate signal and the previous-stage similar gate signal, and the output voltage are applied, and the state of the output voltage is stabilized according to the state change of the first clock signal. And a reset unit for resetting the operation of the similar gate driving circuit .

At this time, the predetermined time is preferably 2 horizontal periods [2H].
Before Symbol further includes a gate driver for generating gate signals, the gate driver is preferably a bi-directional gate driver.

Before Stories second clock signal has the gate-on voltage same pulse width and preferably has the first clock signal and the 180 ° phase difference.
Preferably, the high level voltage of the first and second clock signals is the same as the gate-on voltage, and the low level voltage of the first and second clock signals is the same as the gate-off voltage.
The difference in application timing between the gate-on voltage of the similar gate signal of the next stage and the previous stage and the gate-on voltage of the input general gate signal is preferably 2 horizontal periods [2H].

The display device according to claim 7, wherein the input unit includes a first switching element in which the general gate signal is input to an input terminal and a control terminal, and the output voltage is output from an output terminal.
The output unit includes a second switching element that inputs the first clock signal to an input terminal, inputs the output voltage to a control terminal, and outputs the similar gate signal from the output terminal; and controls the second switching element It is preferable that the 1st capacitor connected between a terminal and an output terminal is included.
The stabilizing unit, said input terminal coupled to the output terminal of the second switching element, wherein a control terminal coupled to the second clock signal, the third switching element comprising an output terminal connected to the gate-off voltage When an input terminal connected to said output terminal of said second switching element, wherein an output terminal connected to the gate-off voltage, a second capacitor connected to the first clock signal, a fourth comprising a control terminal include a switching element, the input terminal connected to the control terminal of the fourth switching element, a control terminal connected to said output voltage, a fifth switching element including an output terminal connected to the gate-off voltage, the Is preferred.

The reset section, an input terminal connected to said output voltage, and a control terminal connected to said control terminal of said fourth switching element, and a sixth switching element comprising an output terminal connected to the gate-off voltage, an input terminal connected to said output voltage, a control terminal coupled to said next similar gate signal, and a seventh switching element comprising an output terminal connected to the gate-off voltage, which is connected to the output voltage It is preferable to include an input terminal, a control terminal connected to the previous similar gate signal, and an eighth switching element including an output terminal connected to the gate-off voltage.
The sustain signal generation circuit preferably displays an image composed of a plurality of frames by inverting the voltage level of the sustain signal generated corresponding to each frame .

  According to the display device of the present invention, after the common voltage is fixed to a predetermined voltage, a sustain signal whose voltage level changes at a predetermined cycle is applied to the sustain electrode line, so that the range of the pixel electrode voltage is increased. However, the pixel voltage range is also widened, and the voltage range for expressing the gradation is widened, so that the image quality is improved.

In addition, when a data voltage of the same magnitude is applied, a wider range of pixel voltages is generated than when a constant voltage sustain voltage is applied. The voltage is fixed to a constant value, and the power consumption is further reduced.
Further, there is an effect that it is possible to realize a liquid crystal display device that employs a bidirectional gate driver and a sustain signal generator without adding a separate selection circuit.

Next, a specific example of the best mode for carrying out the display device according to the present invention will be described with reference to the drawings.
In the drawings, the thickness is enlarged to clearly show various layers and regions. Similar parts are denoted by the same reference numerals throughout the specification. When a part such as a layer, a film, a region, or a plate is “on top” of another part, this is not limited to the case of “on top” of the other part. Including some cases. Conversely, when a part is “just above” another part, this means that there is no other part in the middle.

A liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.
FIG. 1 is a block diagram of a liquid crystal display device according to an embodiment of the present invention. FIG. 2 is an equivalent circuit diagram of one pixel in the liquid crystal display device according to the embodiment of the present invention.

Referring to FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400, a data driver 500, a gray voltage generator 800 connected to the data driver 500, A maintenance signal generation unit 700 and a signal control unit 600 are included.
According to an equivalent circuit, the liquid crystal panel assembly 300 includes a plurality of signal lines (G _{1 to} G _2n , G _d , D _{1 to} D _m , S _{1 to} S _2n ) and a plurality of pixels (PX). On the other hand, according to the structure shown in FIG. 2, the liquid crystal panel assembly 300 includes lower and upper display panels 100 and 200 facing each other and the liquid crystal layer 3 interposed therebetween.

The signal lines (G _{1 to} G _2n , G _d , D _{1 to} D _m , S _{1 to} S _2n ) are a plurality of gate lines (G _{1 to} G _2n , G _d ) and a plurality of data lines (D _{1 to} D _m) and a plurality of storage electrode lines containing _(S 1 _{~S 2n).}
The gate lines (G _{1 to} G _2n , G _d ) transmit gate signals (also referred to as scanning signals) and include general gate lines (G _{1 to} G _2n ) and additional gate lines (G _d ). The storage electrode lines (S _{1 to} S _2n ) are alternately arranged with the general gate lines (G _{1 to} G _2n ), and transmit the maintenance signal. The data lines (D _{1 to} D _m ) transmit a data voltage.
The gate lines (G _{1 to} G _2n , G _d ) and the storage electrode lines (S _{1 to} S _2n ) extend substantially in the row direction and are substantially parallel to each other, and the data lines (D _{1 to} D _m ) are substantially column-shaped. Extending in the direction and substantially parallel to each other.

As shown in FIG. 1, the pixels PX are connected to general gate lines (G _{1 to} G _2n ), data lines (D _{1 to} D _m ), and storage electrode lines (S _{1 to} S _2n ). Is arranged. Each pixel (PX), for example, the pixel (PX) in the i-th (i = 1, 2,..., 2n) row and j-th (j = 1, 2,..., M) column, as shown in FIG. , A switching element (Q) connected to the i-th general gate line (G _i ) and the j-th data line (D _j ), a liquid crystal capacitor (Clc) connected to the switching element (Q), and a switching element (Q) and a storage capacitor (Cst) connected to the i-th storage electrode line (S _i ).

The switching element (Q) is a three-terminal element such as a thin film transistor provided in the lower display panel 100, and its control terminal is connected to a general gate line (G _i ), and its input terminal is a data line (D _j ). The output terminal is connected to the pixel electrode 191 and, in turn, to the liquid crystal capacitor (Clc) and the storage capacitor (Cst).
In the liquid crystal capacitor (Clc), the pixel electrode 191 of the lower display panel 100 and the common electrode 270 of the upper display panel 200 serve as two terminals, and the liquid crystal layer 3 between the two electrodes (191, 270) functions as a dielectric. . The pixel electrode 191 is connected to the switching element (Q), and the common electrode 270 is formed on the entire surface of the upper display panel 200 and receives a common voltage (Vcom).

The common voltage (Vcom) is a direct current (DC) voltage having a certain magnitude. Unlike FIG. 2, the common electrode 270 may be installed on the lower display panel 100. In this case, at least one of the two electrodes 191 and 270 may be formed in a linear or rod shape. Good.
The storage capacitor (Cst), which plays an auxiliary role for the liquid crystal capacitor (Clc), is formed by overlapping the pixel electrode 191 and the storage electrode line (S _i ) with an insulator interposed therebetween.

On the other hand, in order to realize color display, each pixel (PX) uniquely displays one of the basic colors (space division), or each pixel (PX) alternately displays the basic color according to time. (Time division), the desired color is recognized by the spatial and temporal effects of these basic colors. Examples of basic colors include three primary colors such as red, green, and blue. FIG. 2 is an example of space division, and each pixel (PX) includes a color filter 230 indicating one of the basic colors in the region of the upper display panel 200 corresponding to the pixel electrode 191. Unlike FIG. 2, the color filter 230 may be provided above or below the pixel electrode 191 of the lower display panel 100.
The liquid crystal panel assembly 300 includes at least one polarizer (not shown).

  Referring to FIG. 1 again, the gray voltage generator 800 generates a whole gray voltage or a limited number of gray voltages (hereinafter referred to as reference gray voltages) related to the transmittance of the pixel (PX). To do. The (reference) gradation voltage may include a positive voltage with respect to the common voltage (Vcom) and a negative voltage.

The gate driving unit 400 includes first and second gate driving circuits 400 a and 400 b disposed on both sides of the liquid crystal panel assembly 300, for example, left and right ends.
The first gate driving circuit 400a is connected to the odd-numbered general gate lines (G ₁ , G ₃ , G _2n-1 ) and the additional gate line (G _d ) at one end, and the second gate driving circuit 400b General gate lines (G ₂ , G ₄ ,..., G _2n ) at one end. However, the present invention is not limited to this, and conversely, odd-numbered general gate lines (G ₁ , G ₃ ,..., G _2n−1 ) and additional gate lines (G _d ) are added to the second gate driving circuit 400b. Even-numbered general gate lines (G ₂ , G ₄ ,..., G _2n ) may be connected to the first gate driving circuit 400a.

The first and second gate driving circuits 400a and 400b apply a gate signal composed of a combination of a gate-on voltage (Von) and a gate-off voltage (Voff) to the connected gate lines (G _{1 to} G _2n , G _d ).
The gate driver 400 is integrated in the liquid crystal panel assembly 300 together with signal lines (G _{1 to} G _2n , G _d , D _{1 to} D _m , S _{1 to} S _2n ), a thin film transistor switching element (Q), and the like. However, the gate driver 400 is mounted directly on the liquid crystal panel assembly 300 in the form of at least one integrated circuit chip, or mounted on a flexible printed circuit film (not shown) and is a TCP (tape carrier package). The liquid crystal panel assembly 300 may be attached to the LCD panel 300 or mounted on a separate printed circuit board (not shown).

The sustain signal generator 700 includes first and second sustain signal generators 700a disposed on both sides of the liquid crystal panel assembly 300, for example, adjacent to the first and second gate driving circuits 400a and 400b. 700b.
The first sustain signal generation circuit 700a is connected to odd-numbered sustain electrode lines (S ₁ , S ₃ ,..., S _2n-1 ) and even-numbered general gate lines (G ₂ , G ₄ ,..., G _2n ). Then, a sustain signal composed of a high level voltage and a low level voltage is applied to the odd-numbered sustain electrode lines (S ₁ , S ₃ ,..., S _2n−1 ).
The second sustain signal generating circuit 700b includes an odd-numbered general gate line (G ₃ ) excluding the even-numbered sustain electrode lines (S ₂ , S ₄ ,..., S _2n ) and the first general gate line (G ₁ ). , G ₅ ,..., G _2n−1 ) and the additional gate line (G _d ), and a sustain signal is applied to the even-numbered sustain electrode lines (S ₂ , S ₄ ,..., S _2n ).

In contrast, the sustain signal generator 700 is not supplied with a necessary signal through a separate additional gate line (G _d ) connected to the gate driver 400, but a separate signal generator or signal controller. Necessary signals may be supplied from a separate device such as 600. In this case, the additional gate line (G _d ) connected to the gate driver 400 does not need to be formed in the liquid crystal panel assembly 300.

The sustain signal generator 700 is integrated in the liquid crystal panel assembly 300 together with signal lines (G _{1 to} G _2n , G _d , D _{1 to} D _m , S _{1 to} S _2n ), a thin film transistor switching element (Q), and the like. .
However, the sustain signal generator 700 may be mounted directly on the liquid crystal panel assembly 300 in the form of at least one integrated circuit chip, or mounted on a flexible printed circuit film (not shown) and TCP (tape carrier package). ) May be attached to the liquid crystal panel assembly 300 or mounted on a separate printed circuit board (not shown).

The data driver 500 is connected to the data lines (D _{1 to} D _m ) of the liquid crystal panel assembly 300, selects a gray voltage from the gray voltage generator 800, and uses the gray voltage as a data voltage to select the data line (D _{1 to} D _m ). However, when the gray voltage generator 800 does not provide all the gray voltages, but only provides a limited number of reference gray voltages, the data driver 500 divides the reference gray voltages. To generate a desired data voltage.
The data driver 500 is mounted directly on the liquid crystal display panel assembly 300 in the form of at least one integrated circuit chip, or mounted on a flexible printed circuit film (not shown) to form a liquid crystal display panel assembly in the form of TCP. It may be attached to the solid 300 or mounted on a separate printed circuit board (not shown).

  The signal controller 600 controls the gate driver 400, the data driver 500, the sustain signal generator 700, and the like.

  Each of the data driver 500, the signal controller 600, and the gray voltage generator 800 is directly mounted on the liquid crystal panel assembly 300 in the form of at least one integrated circuit chip, or a flexible printed circuit film (not shown). Or attached to the liquid crystal panel assembly 300 in the form of TCP, or mounted on a separate printed circuit board (not shown).

Alternatively, these drives (500,600,800) the signal line _{(G 1 ~G 2n, G d} , D 1 ~D m, S 1 ~S 2n) and thin film transistor switching element (Q) LCD with such The display panel assembly 300 may be integrated. In addition, the driving device (500, 600, 800) may be integrated on a single chip, and in this case, at least one of them or at least one circuit element forming them is located outside the single chip. May be.

Next, the operation of such a liquid crystal display device will be described in detail.
The signal controller 600 receives an input image signal (R, G, B) and an input control signal for controlling display thereof from an external graphic controller (not shown). The input image signal (R, G, B) includes luminance information of each pixel (PX), and the luminance is a predetermined number, for example, 1024 (= 2 ¹⁰ ), 256 (= 2 ⁸ ) or 64 ( = 2 ⁶ ) gray levels. Examples of the input control signal include a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a main clock signal (MCLK), and a data enable signal (DE).

  The signal control unit 600 appropriately processes the input image signals (R, G, B) so as to meet the operating conditions of the liquid crystal panel assembly 300 based on the input image signals (R, G, B) and the input control signals. After generating the gate control signal (CONT1), the data control signal (CONT2), the maintenance control signal (CONT3), etc., the gate control signal (CONT1) is sent to the gate driver 400, and the data control signal (CONT2) The processed digital image signal (DAT) is sent to the data driver 500, and the maintenance control signal (CONT3) is sent to the maintenance signal generator 700.

  The gate control signal (CONT1) includes at least one clock signal for controlling a scanning start signal (STV1, STV2) for instructing scanning start and an output period of the gate-on voltage (Von). The gate control signal (CONT1) may further include an output enable signal (OE) that limits a duration of the gate-on voltage (Von).

The data control signal (CONT2) is the application of analog data voltages to the horizontal synchronization start signal for informing the start of transmission of digital image signals (DAT) for a row of pixels (PX) (STH) and data lines _(D 1 ~D _m) A load signal (LOAD) to instruct and a data clock signal (HCLK) are included. The data control signal CONT2 further includes an inversion signal (RVS) for inverting the polarity of the data voltage with respect to the common voltage (Vcom) (hereinafter, the polarity of the data voltage with respect to the common voltage is abbreviated as the polarity of the data voltage). Can do.

In response to the data control signal (CONT2) from the signal controller 600, the data driver 500 receives a digital image signal (DAT) for a pixel (PX) in one row, for example, the i-th row, and receives each digital image signal ( The digital image signal (DAT) is converted into an analog data voltage by selecting a gradation voltage corresponding to DAT), and then applied to the data lines (D _{1 to} D _m ).

The gate driver 400 receives a gate signal applied to one of the gate lines (G _{1 to} G _2n ), for example, the i-th gate line (G _i ) according to a gate control signal (CONT 1) from the signal controller 600. Is switched to the gate-on voltage (Von) to turn on the switching element (Q) connected to the gate line (G _i ) (however, the switching element (Q) is connected to the additional gate line (G _d )). Except because there is no). As a result, the data voltage applied to the data lines (D _{1 to} D _m ) is applied to the pixel (PX) in the i-th row through the turned on switching element (Q), and as a result, the liquid crystal capacitor in the pixel (PX) (Clc) and the storage capacitor (Cst) are charged.

  The charging voltage of the liquid crystal capacitor (Clc), that is, the pixel voltage is almost the same as the difference between the data voltage applied to the pixel (PX) and the common voltage (Vcom). The arrangement of the liquid crystal molecules differs depending on the magnitude of the pixel voltage, and therefore the polarization of light passing through the liquid crystal layer 3 changes. Such a change in polarization is indicated as a change in light transmittance by the polarizer, whereby the pixel (PX) displays the luminance indicated by the gradation of the digital image signal (DAT).

One horizontal cycle (also referred to as “1H”, which is the same as one cycle of the horizontal synchronization signal Hsync and the data enable signal DE) elapses, and the data driver 500 applies the data voltage to the pixel (PX) in the (i + 1) th row. Is applied to the data lines (D _{1 to} D _m ), the gate driver 400 changes the gate signal applied to the i-th gate line (G _i ) to the gate-off voltage (Voff), and then the gate line (G _{i + 1).} ) Is changed to a gate-on voltage (Von). As a result, the switching element (Q) of the i-th pixel row is turned off, and the pixel electrode 191 is in a floating state.

The sustain signal generator 700 applies the sustain control signal (CONT3) from the signal controller 600 to the i-th sustain electrode line (S _i ) by increasing the voltage of the gate signal applied to the (i + 1) th gate line (G _{i + 1} ). Change the voltage level of the sustain signal applied. As a result, the voltage of the pixel electrode 191 that is one terminal of the storage capacitor (Cst) in the i-th pixel row changes according to the voltage change of the storage electrode line (S _i ) that is the other terminal.
By repeating such a process for all the pixel rows, the liquid crystal display device displays an image of one frame.

  When one frame is finished, the next frame is started, and the inverted signal (RVS) applied to the data driver 500 is set so that the polarity of the data voltage applied to each pixel (PX) is opposite to that of the previous frame. ) Is controlled (frame inversion). The polarities of the data voltages applied to the pixels (PX) in one row are all the same, and the polarities of the data voltages applied to the pixels (PX) in two adjacent rows are opposite (row inversion).

As described above, since the liquid crystal display device according to the present embodiment performs frame inversion and row inversion, the data voltages applied to a pixel (PX) in a certain row are all positive or negative and have polarities in units of frames. change.
At this time, the sustain signal applied to the sustain electrode lines (S _{1 to} S _2n ) changes from the low level voltage to the high level voltage when the pixel electrode 191 is charged with the positive data voltage. When the electrode 191 is charged with a negative data voltage, the voltage changes from a high level voltage to a low level voltage.

  Accordingly, the voltage of the pixel electrode 191 further increases when charged with a positive data voltage, and further decreases when charged with a negative data voltage. As a result, the voltage range of the pixel electrode 191 is wider than the range of the gradation voltage that is the basis of the data voltage, so that a wide range of luminance can be realized even with a low basic voltage.

On the other hand, the first and second storage signal generating circuits 700a, 700b may include a plurality of signal generating circuit 710 are respectively connected to each sustain electrode lines _(S 1 _{to S 2n),} such signal generation circuit An example of 710 will be described in detail with reference to FIGS.

FIG. 3 is a circuit diagram of a signal generation circuit according to an embodiment of the present invention. FIG. 4 is a timing diagram of signals used in the liquid crystal display device including the signal generation circuit shown in FIG.
As shown in FIG. 3, the signal generation circuit 710 has an input terminal (IP) and an output terminal (OP). In the case of the i-th signal generation circuit, the input terminal (IP) is connected to the (i + 1) -th gate line (G _{i + 1} ), receives the (i + 1) -th gate signal (g _{i + 1} ) (hereinafter referred to as an input signal), and outputs it. The end (OP) is connected to the i-th sustain electrode line (S _i ) and outputs the i-th sustain signal (V _si ).

Similarly, in the case of the (i + 1) th signal generation circuit, the input terminal (IP) is connected to the (i + 2) th gate line (G _{i + 2} ) and receives the (i + 2) th gate signal (g _{i + 2} ) as an input signal. The output terminal (OP) is connected to the (i + 1) th sustain electrode line (S _{i + 1} ) and outputs the (i + 1) th sustain signal (V _{si + 1} ).
The signal generation circuit 710 receives first, second, and third clock signals (CK1, CK1B, CK2), which are a kind of maintenance control signal (CONT3), from the signal control unit 600, and receives a high signal from the signal control unit 600 or the outside. A voltage (AVDD) and a low voltage (AVSS) are received.

  As shown in FIG. 4, the first to third clock signals (CK1, CK1B, CK2) may have a period of 2H and a duty ratio may be about 50%. The first clock signal (CK1) and the second clock signal (CK1B) are inverted signals having a phase difference of about 180 °, and the phases of the second clock signal (CK1B) and the third clock signal (CK2) are Are identical to each other. The waveforms of the first to third clock signals (CK1, CK1B, CK2) are inverted in units of frames.

  The high level voltage (Vh1) of the first and second clock signals (CK1, CK1B) may be about 15V, the low level voltage (Vl1) may be about 0V, and the high level of the third clock signal (CK2). The voltage (Vh2) can be about 5V and the low level voltage (Vl2) can be about 0V. The high voltage (AVDD) is about 5 V, similarly to the high level voltage (Vh2) of the third clock signal (CK2), and the low voltage (AVSS) is the low level voltage (Vl2) of the third clock signal (CK2). Similarly, it can be about 0V.

The signal generation circuit 710 includes five transistors (Tr1, Tr2, Tr3, Tr4, Tr5) each having a control terminal, an input terminal, and an output terminal, and two capacitors (C1, C2).
The control terminal of the transistor (Tr1) is connected to the input terminal (IP), the input terminal is connected to the third clock signal (CK2), and the output terminal is connected to the output terminal (OP).
The control terminals of the transistors (Tr2) and (Tr3) are connected to the input terminal (IP), and the input terminals are connected to the first and second clock signals (CK1, CK1B), respectively.

The control terminals of the transistor (Tr4) and the transistor (Tr5) are connected to the output terminals of the transistor (Tr2) and the transistor (Tr3), respectively, and the input terminals are connected to the low voltage (AVSS) and the high voltage (AVDD), respectively. The terminal is connected to the output terminal (OP).
The capacitors (C1, C2) are connected between the control terminal of the transistor (Tr4) and the low voltage (AVSS), and between the control terminal of the transistor (Tr5) and the high voltage (AVDD).
The transistors (Tr1 to Tr5) can be made of amorphous silicon or polycrystalline silicon thin film transistors.

Hereinafter, the operation of such a signal generation circuit will be described in detail.
According to this embodiment, as shown in FIG. 4, the application time of the gate-on voltage (Von) applied to two adjacent gate lines is partially overlapped, and at this time, the gate-on voltage (Von) is superimposed. The time can be about 1H. As a result, the pixels in all the rows are charged for about 1H with the data voltage applied to the pixels in the immediately preceding row, but the remaining about 1H is charged with its own data voltage for normal image display. Operation is performed.

First, the i-th signal generation circuit will be described.
When the input signal, that is, the gate signal (g _{i + 1} ) applied to the (i + 1) th gate line (G _{i + 1} ) becomes the gate-on voltage (Von), the first to third transistors (Tr1 to Tr3) are turned on. The turned-on transistor (Tr1) transmits the third clock signal (CK2) to the output terminal (OP), and the voltage level of the sustain signal (V _si ) is reduced by the low level voltage (Vl2) of the third clock signal (CK2). It becomes a low level voltage (V-). On the other hand, the turned-on transistor (Tr2) transmits the first clock signal (CK1) to the control terminal of the transistor (Tr4), and the turned-on transistor (Tr3) sends the second clock signal (CK1B) to the transistor (Tr5). Transmit to control terminal.

  Since the first clock signal (CK1) and the second clock signal (CK1B) are inverted signals, the transistor (Tr4) and the transistor (Tr5) operate in opposite directions. That is, when the transistor (Tr4) is turned on, the transistor (Tr5) is turned off. Conversely, when the transistor (Tr4) is turned off, the transistor (Tr5) is turned on. When the transistor (Tr4) is turned on and the transistor (Tr5) is turned off, the low voltage (AVSS) is transmitted to the output terminal (OP), the transistor (Tr4) is turned off, and the transistor (Tr5) is turned on, the high voltage (AVDD) Is transmitted to the output terminal (OP).

The state of the gate-on voltage (Von) of the gate signal (g _{i + 1} ) is maintained for 2H, for example, and the first half 1H is the first half section (T1) and the second half 1H is the second half section (T2).
In the first half section (T1), the first clock signal (CK1) is a high level voltage (Vh1), and the second and third clock signals (CK1B, CK2) are low level voltages (Vl1, Vl2). The low voltage (AVSS) transmitted by the transistor (Tr4) is applied to the output terminal (OP) to which the low level voltage (Vl2) of the third clock signal (CK2) transmitted by (Tr1) is applied.

Therefore, the sustain signal (V _si ) is a low level voltage (V−) having the same magnitude as the low level voltage (Vl2) and the low voltage (AVSS).
On the other hand, in the first half section (T1), the capacitor (C1) is charged with a voltage corresponding to the difference between the high level voltage (Vh1) and the low voltage (AVSS) of the first clock signal (CK1), and the capacitor (C2) is charged. The voltage corresponding to the difference between the low level voltage (Vl1) and the high voltage (AVDD) of the second clock signal (CK1B) is charged.

  In the second half section (T2), the first clock signal (CK1) is a low level voltage (Vl1), and the second and third clock signals (CK1B, CK2) are high level voltages (Vh1, Vh2). Contrary to the section (T1), the transistor (Tr5) is turned on and the transistor (Tr4) is turned off.

Accordingly, the high level voltage (Vh2) of the third clock signal (CK2) transmitted through the turned-on transistor (Tr1) is applied to the output terminal (OP), and the sustain signal (V _si ) is set to the low level voltage ( _Vsi ). V−) changes to a high level voltage (V +) at the same level as the high level voltage (Vh2).
Further, a high voltage (AVDD) having the same level as the high level voltage (V +) is applied to the output terminal (OP) through the turned on transistor (Tr5).

  On the other hand, the charging voltage of the capacitor (C1) is equal to the difference between the low level voltage (Vl1) and the low voltage (AVSS) of the first clock signal (CK1). Therefore, if these two voltages are the same, the capacitor (C1) Is discharged. Since the charging voltage of the capacitor (C2) is equal to the difference between the high level voltage (Vl1) and the high voltage (AVDD) of the second clock signal (CK1B), if these two voltages are different from each other, the charging voltage of the capacitor (C2) Is not zero. As described above, when the high level voltage (Vh1) of the second clock signal (CK1B) is about 15V and the high voltage (AVDD) is about 5V, a voltage of about 10V is charged in the capacitor (C2). .

When the second half period (T2) ends and the gate signal (g _{i + 1} ) changes from the gate-on voltage (Von) to the gate-off voltage (Voff), the transistors (Tr1 to Tr3) change to the turn-off state. Therefore, the output terminal of the transistor (Tr1) becomes isolated, the electrical connection between the transistor (Tr1) and the output terminal (OP) becomes isolated, and the output terminals of the transistors (Tr2, Tr3) become isolated. As a result, the control terminals of the transistors (Tr4, Tr5) are also in an isolated state.

Since the capacitor (C1) is not charged with voltage, the transistor (Tr4) maintains the turn-off state. However, since the capacitor (C2) is charged with a voltage due to the difference between the high level voltage (Vh1) and the high voltage (AVDD) of the second clock signal (CK1B), the voltage is the threshold voltage of the transistor (Tr5). If it is above, transistor (Tr5) maintains a turn-on state. Therefore, the high voltage (AVDD) is transmitted to the output terminal (OP) and is output as the sustain signal (V _si ). As a result, the sustain signal (V _si ) maintains a high level voltage (V +).

Next, the operation of the (i + 1) th signal generation circuit will be described.
When the gate-on voltage (Von) of the (i + 2) th gate signal (g _{i + 1} ) is applied to the (i + 1) th signal generation circuit (not shown), the (i + 1) th signal generation circuit operates.

As shown in FIG. 4, when the (i + 2) th gate signal (g _{i + 2} ) becomes a gate-on voltage (Von), the states of the first to third clock signals (CK1, CK1B, CK2) at this time are (i + 1). This is the reverse of the state when the _ith gate signal (g _{i + 1} ) becomes the gate-on voltage (Von).

Accordingly, the operation in the first half gate on voltage (Von) section (T1) of the (i + 2) th gate signal (g _{i + 2} ) is performed in the _second half gate on voltage (Von) section (T2) of the (i + 1) th gate signal (g _{i + 1} ). The high level voltage (Vh2) and the high voltage (AVDD) of the third clock signal (CK2) are applied to the output terminal (OP) by the turn-on operation of the transistors (Tr1, Tr3, Tr5). Thus, the sustain signal (V _{si + 1} ) becomes a high level voltage (V +).

However, the operation of the (i + 2) th gate signal (g _{i + 2} ) in the second half gate on voltage (Von) section (T2) is performed in the first half gate on voltage (Von) section (T1) of the (i + 1) th gate signal (g _{i + 1} ). The operation is the same, and the low level voltage (Vl2) and the low voltage (AVSS) of the third clock signal (CK2) are applied to the output terminal (OP) by the turn-on operation of the transistors (Tr1, Tr2, Tr4). The sustain signal (V _{si + 1} ) changes from the high level voltage (V +) to the low level voltage (V−).

As described above, the transistor (Tr1) is a transistor for applying the third clock signal (CK2) as the sustain signal while the voltage state of the input signal maintains the gate-on voltage (Von), and the remaining transistors ( Tr2-Tr5) are applied to the storage electrode line using the capacitors (C1, C2) when the input signal is a gate-off voltage (Voff) and the output terminal (OP) is isolated from the transistor (Tr1). This is a transistor for maintaining the voltage state of the sustain signal until the next frame.
That is, the transistor (Tr1) is for initially applying a sustain signal to the sustain electrode line, and the remaining transistors (Tr2-Tr5) are for maintaining the output sustain signal constant. The size of the transistors (Tr2 to Tr5) may be much smaller than the size of the first transistor (Tr1).

The pixel electrode voltage (Vp) increases or decreases due to the voltage change of the sustain signal (Vs). Hereinafter, the capacitors and the capacitances of these capacitors are denoted by the same reference numerals.
That is, the pixel electrode voltage (Vp) is obtained from the following formula 1. In Equation 1, V _D is a data voltage, Clc and Cst are capacitances of a liquid crystal capacitor and a storage capacitor, V _H is a high level voltage (V +) of the sustain signal (Vs), and V _L is This is the low level voltage (V−) of the sustain signal (Vs).

As can be seen from Equation 1, the pixel electrode voltage (Vp) is obtained by changing the amount of change (Δ) determined by the voltage change of the capacitance (Clc, Cst) and the sustain signal (Vs) of the capacitor to the data voltage (V _D ). It is an adjusted value.
Accordingly, when the pixel electrode voltage (Vp) is charged with the positive data voltage by adding or subtracting the change amount (Δ) of the sustain signal (Vs) to the charged data voltage (V _D ), the pixel electrode voltage (Vp) The voltage (Vp) increases by the amount of change (Δ). Conversely, when charged with the negative data voltage, the pixel electrode voltage (Vp) decreases by the amount of change (Δ). As a result, the change in the pixel voltage becomes wider than the range of the gradation voltage due to the increased or decreased pixel electrode voltage (Vp), and the expressed luminance range is also widened.

Further, as already described, since the common voltage (Vcom) is fixed to a constant voltage, power consumption is reduced as compared to applying a low voltage and a high voltage alternately.
According to the present embodiment, after the common voltage (Vcom) is fixed to a predetermined voltage, the sustain signal whose level is changed at a predetermined cycle is applied to the sustain electrode line to thereby set the range of the pixel electrode voltage. increase. As a result, the range of the pixel voltage is widened, and the voltage range for expressing the gradation is widened, so that the image quality is improved.

  In addition, when data voltages of the same magnitude are applied, a wider range of pixel voltages is generated than when a constant voltage sustain voltage is applied. Since the range of the data voltage can be reduced, the power consumption is reduced. Further, the common voltage is fixed at a constant value, and the power consumption is further reduced.

Next, a liquid crystal display device according to another embodiment of the present invention will be described with reference to FIGS.
FIG. 5 is a block diagram of a liquid crystal display device according to another embodiment of the present invention. FIG. 6 is a block diagram of a similar gate signal generation circuit according to another embodiment of the present invention. FIG. 7 is a circuit diagram of a similar gate driving circuit according to another embodiment of the present invention. FIG. 8 is a timing diagram of signals used in the liquid crystal display device including the similar gate driving circuit shown in FIG.

The liquid crystal display device shown in FIG. 5 is substantially the same as the liquid crystal display device shown in FIG. 1, and therefore, parts having the same functions are denoted by the same reference numerals and detailed description thereof is omitted.
As shown in FIG. 5, the liquid crystal display according to another embodiment of the present invention is connected to the gate driver 401 connected to the gate lines (G _{1 to} G _2n ) and the data lines (D _{1 to} D _m ). data driver 500, sustain electrode lines _(S 1 _{to S 2n)} connected to have been storage signal generator 701, connected gray voltage generator 800 to the data driver 500, gate driver 401 (the first and second 2 gate driving circuits 401 a and 401 b) and a signal control unit 601 connected to the data driving unit 500.

However, the gate driver 401 according to the present embodiment is a bidirectional gate driver that changes the scanning direction of the general gate lines (G _{1 to} G _2n ) according to an external selection signal.
That is, according to the state of the selection signal, the gate driver 401 sequentially transmits the gate-on voltage (Von) from the first general gate line (G1) to the last general gate line (G _2n ). Alternatively, the gate-on voltage (Von) is sequentially transmitted in the opposite direction, that is, from the last general gate line (G _2n ) to the first general gate line (G ₁ ).

  For this purpose, the liquid crystal display device may further include a selection switch (not shown) that outputs a selection signal of the state from the signal control unit 601 or the like according to a user's selection. The signal control unit 601 includes a gate control signal ( It is possible to transmit the operation state of the selection switch through CONT1) and control the gate driving unit 401 to operate in the selected state.

As shown in FIG. 5, the sustain signal generation unit 701 includes first and second sustain signal generation circuits 701a and 701b. However, unlike FIG. 1, the first sustain signal generation circuit 701a according to the present embodiment is connected to even-numbered sustain electrode lines (S ₂ , S ₄ ,..., S _2n ), and the second sustain signal generation circuit 701b is It is connected to odd-numbered sustain electrode lines (S ₁ , S ₃ ,..., S _2n−1 ).

However, when compared with the first and second sustain signal generating circuits 700a and 700b shown in FIG. 1, the first and second sustain signal generating circuits 701a and 701b are connected to the sustain electrode lines (S _{1 to} S _2n ). Only the connection relationship is different, and the internal structure is the same. The connection relationship between the first and second sustain signal generation circuits 701a and 702b is not limited to this and can be changed as necessary.
Further, unlike FIG. 1, the liquid crystal display device according to the present embodiment further includes a similar gate signal generation unit 720 connected to the general gate lines (G _{1 to} G _2n ) and the sustain signal generation unit 701.

The similar gate signal generation unit 720 includes first and second similar gate signal generation circuits 720a and 720b connected to the first and second sustain signal generation circuits 701a and 701b, respectively.
The first similar gate signal generation circuit 720a is connected to the odd-numbered general gate lines (G ₁ , G ₃ ,..., G _2n−1 ) and the first sustain signal generation circuit 701a, and is input to the first sustain signal generation circuit 701a. A similar gate signal composed of a gate-on voltage (Von) and a gate-off voltage (Voff) is applied to the end (IP), and the second similar gate signal generation circuit 720b receives the even-numbered general gate lines (G ₂ , G ₄ ,..., G _2n ) and the second sustain signal generating circuit 701b, and a similar gate signal is applied to the input terminal (IP) of the second sustain signal generating circuit 700b.

For this purpose, the signal controller 601 further generates similar gate control signals (CONT4a, CONT4b) and applies them to the first and second similar gate signal generation circuits 720a, 720b.
The similar gate signal generator 720 can be directly integrated in the liquid crystal panel assembly 301. However, the similar gate signal generator 720 is mounted directly on the liquid crystal panel assembly 300 in the form of at least one integrated circuit chip, or mounted on a flexible printed circuit film (not shown) and in the form of TCP. It may be attached to the liquid crystal panel assembly 301 or mounted on a separate printed circuit board (not shown).

  As shown in FIG. 6, the first and second similar gate signal generation circuits 720a and 720b receive a fourth clock signal (CK3) and a fifth clock signal CK3, which are a kind of similar gate control signals (CONT4a and CONT4b) from the signal controller 601. The clock signal (CK3B), the sixth clock signal (CK4), the seventh clock signal (CK4B), and the gate-off voltage (Voff) are applied.

That is, the first similar gate signal generation circuit 720a receives inputs of the fourth and fifth clock signals (CK3, CK3B), which are a kind of similar gate control signal (CONT4a), and the second similar gate signal generation circuit 720b The sixth and seventh clock signals (CK4, CK4B), which are a kind of similar gate control signal (CONT4b), are input.
The first and second similar gate signal generation circuits 720a and 720b include a plurality of similar gate driving circuits 730 connected to the signal generation circuits 710 of the first and second sustain signal generation circuits 701a and 701b, respectively.

As shown in FIG. 6, each similar gate driving circuit 730 includes an input terminal (IN), a clock terminal (CK, CKB), a reset terminal (R1, R2), a gate voltage terminal (GV), and an output terminal (OUT). Have
As already described, each similar gate drive circuit 730 of the first similar gate signal generation circuit 720a receives an odd-numbered gate signal (g ₁ , g ₃ ,..., G _2n−1 ) and receives the second similar gate. Each similar gate driving circuit 730 of the signal generation circuit 720b receives an even-numbered gate signal (g ₂ , g ₄ ,..., G _2n ).

For example, in the case of the i (i is an odd number) -th similar gate driving circuit 730 included in the first similar gate signal generation circuit 720a, the input terminal (IN) is connected to the i-th gate line (G _i ) and the i-th gate. The reset terminal (R1) receives the signal (g _i ) and is connected to the (i + 2) th similar gate signal generation circuit 720a to receive the (i + 2) th similar gate signal (Pg _{i + 2} ), and the reset terminal (R2). Is connected to the (i-2) th similar gate signal generation circuit 720a to receive the (i-2) th similar gate signal (Pg _i-2 ), and the clock ends (CK, CKB) are respectively the fourth and the fourth. The 5-clock signal (CK3, CK3B) is received, and the gate voltage terminal (GV) receives the gate-off voltage (Voff). The output terminal (OUT) is connected to the input terminal (IP) of the (i) th signal generation circuit 710 of the sustain signal generation unit 701 connected to the (i) th sustain electrode line (S _i ).

Similarly, in the case of the (i + 1) th similar gate drive circuit 730 included in the second similar gate signal generation circuit 720b, the input terminal (IN) is connected to the (i + 1) th gate line (G _{i + 1} ). The (i + 1) th gate signal (g _{i + 1} ) is received, and the reset terminal (R1) is connected to the (i + 3) th similar gate signal generation circuit 720b to receive the (i + 3) th similar gate signal (Pg _{i + 3} ), The reset terminal (R2) is connected to the (i-3) th similar gate signal generation circuit 720b to receive the (i-3) th similar gate signal (Pg _i-3 ), and the clock terminals (CK, CKB) are The sixth and seventh clock signals (CK4, CK4B) are received, and the gate voltage terminal (GV) receives the gate-off voltage (Voff). The output terminal (OUT) is connected to the input terminal (IP) of the (i + 1) th signal generation circuit 710 of the sustain signal generation unit 701 connected to the (i + 1) th storage electrode line (S _{i + 1} ).

  However, another dummy signal (DS11, DS12) is used instead of the similar gate signal at the reset terminal (R2) of the first similar gate drive circuit 730 of the first similar gate signal generation circuit 720a and the second similar gate signal generation circuit 720b. ) And another dummy signal (DS21, DS22) is input to the reset terminal (R1) of the last similar gate drive circuit 730 of the first similar gate signal generation circuit 720a and the second similar gate signal generation circuit 720b. Is done.

These dummy signals (DS11, DS12, DS21, DS22) can be generated by the signal control unit 601 based on the scanning start signal.
In contrast, the dummy signals (DS11, DS12, DS21, DS22) can be transmitted from the gate driver 401 through another additional gate line connected to the gate driver 401.

  As shown in FIG. 8, the fourth and fifth clock signals (CK3, CK3B) and the sixth and seventh clock signals (CK4, CK4B) have a high level voltage (Vh3) and a low level voltage (Vl3). The high level voltage (Vh3) may be the same as the gate on voltage (Von), and the low level voltage (Vl3) may be the same as the gate off voltage (Voff).

The pulse widths of the fourth and fifth clock signals (CK3, CK3B) and the sixth and seventh clock signals (CK4, CK4B) are the same as the pulse width of the gate-on voltage (Von). The period of CK3B, CK4, CK4B) may be about 4H, and the duty ratio may be about 50%.
The fourth clock signal (CK3) and the fifth clock signal (CK3B), and the sixth clock signal (CK4) and the seventh clock signal (CK4B) are inverted signals having a phase difference of about 180 °. The fourth clock signal (CK3) and the sixth clock signal (CK4) have a phase difference of about 90 °.

  Referring to FIG. 7, each similar gate driving circuit 730 includes eight transistors (Q1 to Q8) each having a control terminal, an input terminal, and an output terminal, and two capacitors (Cc, Cb). The transistors (Q1 to Q8) are NMOS transistors, but PMOS transistors can also be used. The capacitors (Cc, Cb) may be a parasitic capacitance between the gate and the drain / source that is actually formed during the process.

The input terminal of the transistor (Q1) is connected to the clock terminal (CK), and the output terminal is connected to the output terminal (OUT).
The input terminal and the control terminal of the transistor (Q2) are connected to the input terminal (IN), and the output terminal is connected to the control terminal of the transistor (Q1) through the contact (n1).
The input terminal of the transistor (Q3) is connected to the output terminal of the transistor (Q2) through the contact (n1), the control terminal is connected to the reset terminal (R1), and the gate terminal voltage (Voff) is input to the output terminal. Connected to the gate voltage terminal (GV).

The input terminal of the transistor (Q4) is connected to the output terminal of the transistor (Q2) through the contact (n1), and the output terminal is connected to the gate voltage terminal (GV) to which the gate-off voltage (Voff) is input.
The input terminal of the transistor (Q5) is connected to the output terminal of the transistor (Q1), the control terminal is connected to the control terminal of the transistor (Q4), and the output terminal is a gate voltage to which a gate-off voltage (Voff) is input. It is connected to the end (GV).
The input terminal of the transistor (Q6) is connected to the output terminal of the transistor (Q1), the control terminal is connected to the clock terminal (CKB), and the output terminal is connected to the gate voltage terminal (GV).

The input terminal of the transistor (Q7) is connected to the control terminal of the transistor (Q4, Q5) through the contact (n2), the control terminal is connected to the output terminal of the transistor (Q1) through the contact (n1), and the output terminal is Are connected to the gate voltage terminal (GV).
The input terminal of the transistor (Q8) is connected to the output terminal of the transistor (Q2) through the contact (n1), the control terminal is connected to the reset terminal (R2), and the output terminal is connected to the gate voltage terminal (GV). Has been.
The capacitor (Cc) is connected between the clock end (CK) to which the third clock signal (CK3) is input and the contact (n2), and the capacitor (Cb) is connected between the contact (n1) and the output end (OUT). Connected between.

The operation of the similar gate driving circuit 730 is as follows.
The operation of the similar gate driving circuit 730 when the scanning direction of the gate driving unit 401 is the forward direction according to the state of the selection signal will be described.
First, it is assumed that the transistors (Q1 to Q8) are turned on by a gate-on voltage (Von) and turned off by a gate-off voltage (Voff).

For example, the operation of the i-th similar gate driving circuit 730 will be described with reference to FIGS.
The fourth clock signal (CK3) is shifted from the high level voltage (Vh3) at a low level voltage (Vl3), the voltage of the fifth clock signal (CK3B) and a gate signal applied to the input terminal (IN) _{(g i)} When the level changes from the gate-off voltage (Voff) to the gate-on voltage (Von), the transistor (Q2) and the transistor (Q6) are turned on. As a result, the gate-on voltage (Von) is transmitted to the contact (n1) through the transistor (Q2), thereby turning on the transistors (Q1, Q7).

A gate-off voltage (Voff) is transmitted to the contact (n2) through the transistor (Q7), thereby turning off the transistors (Q4, Q5). At this time, since the voltage level of the (i + 2) -th similar gate signal (Pg _{i + 2} ) at the next stage is the gate-off voltage (Voff), the transistor (Q3) maintains the turn-off state. Meanwhile, the output terminal (OUT) applies the gate-off voltage (Voff) to the input terminal (IP) of the i-th signal generation circuit 710 through the two turned-on transistors (Q1, Q6) as the i-th similar gate signal (Pg _i ). To do.

  At this time, the capacitor (Cb) is charged with a voltage corresponding to the difference between the gate-on voltage (Von) and the gate-off voltage (Voff), and the state of the contact (n2) is the low level voltage (CK3) of the fourth clock signal (CK3). The low level voltage is maintained by Vl3), and the state of the transistor (Q5) maintains the turn-off state.

Next, the voltage levels of the i-th gate signal (g _i ) and the fifth clock signal (CK3B) transition to a gate-off voltage (Voff) and a low-level voltage (Vl3), and the fourth clock signal (CK3) is a high-level voltage. When the transition is made to (Vh3), the transistors (Q2, Q6) are turned off. At this time, the similar gate signal (Pg _{i + 2} ) of the next stage is maintained at the low level, so that the transistor (Q3) is also maintained in the turn-off state. Contacts (n1) by the transistor (Q2) is turned off is connected to the i-th gate signal (g _i) is isolated is blocked.

Accordingly, the transistors (Q1, Q7) are kept turned on, and a gate-off voltage is applied to the contact (n2), and thus the transistors (Q4, Q5) are kept turned off. Since all the transistors (Q5, Q6) are turned off, the gate-off voltage (Voff) transmitted to the output terminal (OUT) is cut off, and the transistor (Q1) maintains the turn-on state, so that the clock signal (CK3) is high. Only the gate-on voltage (Von) which is the level voltage (Vh3) is transmitted to the output terminal (OUT) and output.
At this time, since the capacitor (Cb) maintains a constant voltage, the voltage of the contact (n1), which is in an isolated state as the voltage of the output terminal (OUT) rises to the gate-on voltage (Von), is increased. Only rise.

  At this time, the capacitor (Cc) is a voltage corresponding to the difference between the gate-on voltage (Von) which is the high level voltage (Vh3) of the fourth clock signal (CK3) and the gate-off voltage (Voff) which is the voltage of the contact (n2). Therefore, the state of the contact (n2) is maintained at a low voltage, and the state of the transistor (Q5) is maintained in the turn-off state. As a result, the gate-on voltage (Von) is stably output through the output terminal (OUT).

The fourth clock signal (CK3) transitions to the low level voltage (Vl3), and the voltage levels of the fifth clock signal (CKB3) and the next stage similar gate signal (Pg _{i + 2} ) are the high level voltage (Vh3) and the gate on voltage (Von). if transition to), it turns on the transistor (Q3, Q6) is, at this time, the gate signal _{(g i)} so to maintain the gate-off voltage (Voff), the transistor (Q2) is in an oFF state. When the transistor (Q3) is turned on, a gate-off voltage (Voff) is transmitted to the contact (n1), and the transistors (Q1, Q7) are turned off.

When the transistor (Q7) is turned off, the contact (n2) is in an isolated state. At this time, the capacitor (Cc) maintains a constant voltage, so that the fourth clock signal (CK3) transitions to the low level voltage (Vl3). Along with this, the voltage at the contact (n2) further decreases below the gate-off voltage (Voff).
However, when the voltage at the contact (n2) drops below the gate-off voltage (Voff), the transistor (Q7) is turned on again to transmit the gate-off voltage (Voff) to the contact (n2). The voltage (n2) is substantially equal to the gate-off voltage (Voff). As a result, the transistors (Q4, Q5) continue to be turned off.

  On the other hand, since the transistor (Q1) is turned off and the transistor (Q6) is turned on, the gate-off voltage (Voff) is transmitted to and output from the output terminal (OUT), and the capacitor (Cb) is discharged.

  Thereafter, only the fourth and fifth clock signals (CK3, CK3B) repeat the high level voltage (Vh3) and the low level voltage (Vl3). However, a level change of the fourth clock signal (CK3) periodically turns on and off the transistor (Q5), and a level change of the fifth clock signal (CK3B) periodically turns on and off the transistor (Q6). As a result, the gate-off voltage (Voff) is continuously applied to the output terminal (OUT), so that the voltage level of the output terminal (OUT) is stable regardless of the change of the fourth clock signal (CK3). Voff) is maintained.

In addition, when the fourth clock signal (CK3) is the high level voltage (Vh3), the transistor (Q4) is also turned on, and the contact (n1) is connected to the gate-off voltage (Voff) so that the state of the contact (n1) is The gate-off voltage (Voff) is stably maintained.
In this case, the previous stage gate signal (gi _-2 ) which is the gate-off voltage (Voff) state is applied to the reset terminal (R2) connected to the control terminal of the transistor (Q8), and the turn-off state is always maintained.

Thus, as shown in FIG. 8, the i-th similarity gate driving circuit 730, a gate-on voltage (Von) applied timing of the normal gate signal applied to the input terminal (IN) _{(g i),} the output terminal (OUT ) From the gate-on voltage (Von) application time of the similar gate signal (P _gi ) output from the same gate signal (P _gi ), the similar gate signal (P _gi ) is different from the (i + 2) th gate signal (g _{i + 2} ). The similar gate signal (Pg _{i + 1} ) output from the (i + 1) th similar gate driving circuit 730 is substantially the same as the (i + 3) th gate signal (g _{i + 3} ).

In contrast, when the scanning direction is reverse depending on the state of the selection signal, the i-th similar gate driving circuit 730, as described above, includes the transistors (Q1, Q2, Q4 to Q7) and the capacitors (Cc, Cb). ) _Operates to generate a similar gate signal (P _gi ) applied to the i-th signal generation circuit 710 through the output terminal (OUT). However, unlike the forward case, the transistor (Q3) to which the next-stage similar gate signal (Pg _{i + 2} ) is applied functions as the transistor (Q8) to which the previous-stage similar gate signal (Pg _i−2 ) is applied. Do it instead.

Thus, as shown in FIG. 1, instead of directly connecting the sustain signal generator 700 and the gate lines (G _{2 to} G _2n , G _d ), in this embodiment, the sustain signal generator 700 is applied to the sustain signal generator 700. By adding a similar gate signal generation unit that generates a similar gate signal that is substantially the same as the gate signal, an additional selection circuit such as a multiplexer as well as the effect of the embodiment with reference to FIGS. A similar signal generator can be used together with the bidirectional gate driver without adding.

That is, when the gate driver operates in both directions, it is necessary to add a separate selection signal such as a multiplexer that selects one of the previous stage and next stage gate signals. This is difficult to manufacture. However, a similar gate signal generator mounted directly on the liquid crystal display panel assembly 301 together with the signal lines (G _{1 to} G _n , D _{1 to} D _m , S _{1 to} S _n ) is added, and the sustain signal generator A similar gate signal applied as an input signal is directly generated. Accordingly, the sustain signal generator can be used in the liquid crystal display device using the bidirectional gate driver.
At this time, the similar gate signal generation unit can be designed with a transistor having a size smaller than that of the gate driving unit, and does not significantly affect the design margin of the liquid crystal display device.

  In the embodiment of the present invention, the gate driving units 400 and 401 and the sustain signal generating units 700 and 701 are disposed on both sides of the liquid crystal panel assembly 300 and 301, respectively. One gate driver and one sustain signal generator disposed on either side of the plate assemblies 300 and 301 may be used. In this case, the number of similar gate signal generation units connected to the sustain signal generation unit may also be one.

  Further, in the present embodiment, two adjacent gate-on voltages are superimposed for a predetermined time, but the sustain signal generation unit according to the present invention can be used even in a case where this is not the case, and in this case, a similar gate signal generation circuit is also used. , Controlling the pulse widths of the applied fourth and fifth pulse signals (clock signals) and sixth and seventh pulse signals (clock signals) to generate a similar gate signal applied to the sustain signal generator. it can.

  The present invention is not limited to the embodiment described above. Various modifications can be made without departing from the technical scope of the present invention.

1 is a block diagram of a liquid crystal display device according to an embodiment of the present invention. FIG. 3 is an equivalent circuit diagram of one pixel in the liquid crystal display device according to the embodiment of the present invention. 1 is a circuit diagram of a signal generation circuit according to an embodiment of the present invention. FIG. 4 is a timing diagram of signals used in a liquid crystal display device having the signal generation circuit of FIG. 3. It is a block diagram of the liquid crystal display device by other embodiment of this invention. FIG. 6 is a block diagram of a similar gate signal generation circuit according to another embodiment of the present invention. FIG. 6 is a circuit diagram of a similar gate driving circuit according to another embodiment of the present invention. FIG. 8 is a timing diagram of signals used in the liquid crystal display device having the similar gate driving circuit shown in FIG. 7.

Explanation of symbols

3 Liquid crystal layer 100, 200 (lower and upper) display panel 191 pixel electrode 230 color filter 270 common electrode 300, 301 liquid crystal display panel assembly 400, 401 gate driver 400a, 401a, 400b, 401b (first and second) Gate drive circuit 500 Data drive unit 600, 601 Signal control unit 700, 701 Maintenance signal generation unit 700a, 701a, 700b, 701b (first and second) maintenance signal generation circuit 720 Similar gate signal generation unit 720a, 720b (first And 2) a similar gate signal generation circuit 730, a similar gate drive circuit 800, a gradation voltage generation unit

Claims (10)

A plurality of gate lines for transmitting a plurality of general gate signals composed of a gate-on voltage and a gate-off voltage;
A plurality of data lines that cross the gate line and transmit a plurality of data voltages;
A plurality of sustain electrode lines extending in parallel with the gate lines and transmitting a plurality of sustain signals;
A switching element connected to the gate line and the data line, a liquid crystal capacitor connected between the switching element and a common voltage having a certain value, and connected between the switching element and the storage electrode line A plurality of pixels each having a storage capacitor and arranged in a matrix;
A plurality of similar gate driving circuits connected to the gate line and generating a similar gate signal based on the general gate signal;
Connected to said storage electrode line, anda plurality of storage signal generator circuit for generating the storage signals based on the similarity gate signal,
When the charged data voltage is positive, the sustain signal changes from a low level to a high level, and when the charged data voltage is negative, the sustain signal changes from a high level to a low level. And
The similar gate driving circuit generates the similar gate signal by delaying the general gate signal by a time of 2 horizontal periods [2H],
The sustain signal generation circuit applies a sustain signal applied to each pixel to the sustain electrode line immediately after the liquid crystal capacitor and the storage capacitor are completely charged with the data voltage ,
Each of the similar gate driving circuits includes an input unit that applies an output voltage in response to the general gate signal corresponding to the gate line;
An output unit for applying a similar gate signal in response to a first clock signal based on the output voltage;
A stabilization unit connected to the output unit, to which the gate-off voltage, the second clock signal, and the output voltage are applied, and the state of the similar gate signal is stabilized according to a state change of the first clock signal; ,
Connected to the stabilization unit, the gate-off voltage, the next-stage similar gate signal and the previous-stage similar gate signal, and the output voltage are applied, and the state of the output voltage according to the state change of the first clock signal And a reset unit that resets the operation of the similar gate driving circuit . A gate driver connected to the gate line and generating the general gate signal;
The display device according to claim 1 , wherein the gate driver is a bidirectional gate driver. The display device according to claim 1 , wherein the second clock signal has the same pulse width as the gate-on voltage and has a phase difference of 180 ° with respect to the first clock signal. The high level voltages of the first and second clock signals are the same as the gate-on voltage, and the first
The display device of claim 1 , wherein the low level voltage of the second clock signal is the same as the gate-off voltage. The difference in applied time of the gate-on voltage of the common gate signal input gate-on voltage of the next stage and the previous stage of the similar gate signal, according to claim 1, characterized in that the two horizontal period [2H] Display device. The display device according to claim 1 , wherein the input unit includes a first switching element in which the general gate signal is input to an input terminal and a control terminal, and the output voltage is output from an output terminal. The output unit includes: a second switching element configured to input the first clock signal to an input terminal, input the output voltage to a control terminal, and output the similar gate signal from the output terminal;
The display device according to claim 6 , further comprising a first capacitor connected between a control terminal and an output terminal of the second switching element. The stabilizing unit includes a third switching element including an input terminal connected to the output terminal of the second switching element, a control terminal connected to the second clock signal, and an output terminal connected to the gate-off voltage. When,
A fourth switching element including an input terminal connected to the output terminal of the second switching element, an output terminal connected to the gate-off voltage, a second capacitor connected to the first clock signal, and a control terminal; When,
And a fifth switching element including an input terminal connected to the control terminal of the fourth switching element, a control terminal connected to the output voltage, and an output terminal connected to the gate-off voltage. The display device according to claim 7 . The reset unit includes: an input terminal connected to the output voltage; a control terminal connected to the control terminal of the fourth switching element; a sixth switching element including an output terminal connected to the gate-off voltage;
A seventh switching element including an input terminal connected to the output voltage, a control terminal connected to the similar gate signal of the next stage, and an output terminal connected to the gate-off voltage;
An input terminal connected to the output voltage, a control terminal connected to the similar gate signal in the previous stage, and an eighth switching element including an output terminal connected to the gate-off voltage. Item 9. The display device according to Item 8 . The display device according to claim 1, wherein the sustain signal generation circuit displays an image composed of a plurality of frames by inverting the voltage level of the sustain signal generated corresponding to each frame. .

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