JP5781299B2 - Display device - Google Patents

Description

  The present invention relates to a display device and a driving method.

  In recent years, for example, a liquid crystal display is used as a display device of various apparatuses such as a mobile phone, a PC (Personal Computer), and a television receiver. In the display device having the display function as described above, for example, power saving is demanded in order to extend the driving time or increase in social needs.

  Under such circumstances, techniques for reducing power consumption in liquid crystal display devices have been developed. Examples of techniques for reducing power consumption by performing charge sharing include Patent Document 1 and Patent Document 2.

JP 2002-244661 A JP 2007-058177 A

  In a liquid crystal display device (hereinafter, simply referred to as “display device”), polarity inversion driving is performed at a constant period in order to reduce deterioration of a liquid crystal element. In addition, charge sharing refers to, for example, polarity reversal driving by selectively causing a short circuit with a counter electrode (hereinafter sometimes referred to as a “VCOM electrode”) to recycle charges. This means reducing the power consumed. Therefore, by using a conventional technique for performing charge sharing (hereinafter, sometimes collectively referred to as “conventional technique”) as shown in Patent Document 1 and Patent Document 2, the display device can be saved. There is a possibility that power can be achieved to some extent.

  However, for example, the technology for performing charge sharing disclosed in Patent Document 1 (hereinafter sometimes referred to as “conventional technology 1”) is a driver outside the active area of the display panel during charge sharing (at the time of short circuit). The source drive line (data line) and the VCOM electrode are short-circuited at a portion close to. Here, in the conventional technique 1, the inside of the display panel is not driven at the time of a short circuit, and the source drive line and the VCOM electrode are changed to the same potential by using the charge charged in the display panel. However, how close it can be to the same potential at this time depends on the size of the load and the length of the short-circuiting time. In Conventional Technology 1, the short-circuit point (switch transistor) is outside the active area of the display panel (around the panel) or inside the driver IC (Integrated Circuit). It takes time to reach a certain potential.

  Therefore, even if the conventional technique 1 is used, there may be a portion where the effect of charge sharing cannot be obtained in the display panel, and thus it is not always possible to sufficiently reduce power consumption in the display device. .

  Further, in the technology for performing charge sharing shown in Patent Document 2 (hereinafter, sometimes referred to as “conventional technology 2”), the arrangement positions of the short-circuit points are arranged at both ends of the source drive line. Therefore, when the conventional technique 2 is used, there is a possibility that the time required for charge sharing can be reduced as compared with the case where the conventional technique 1 is used. However, even if the conventional technique 2 is used, as in the case of using the conventional technique 1, the load is large at a portion far from the short-circuit point, and it takes time to reach a sufficient potential. It is not always possible to sufficiently reduce power consumption.

  Therefore, even if the conventional technique is used, there is a possibility that power consumption in the display device cannot be sufficiently reduced.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a new and improved display device and driving method capable of reducing power consumption in a liquid crystal display device. Is to provide.

  In order to achieve the above object, according to the first aspect of the present invention, signal lines and scanning lines arranged in a matrix are arranged in correspondence with intersections of the signal lines and the scanning lines. A display unit having a pixel circuit, a scanning line driving unit that applies a scanning signal to the scanning line, a signal line driving unit that applies a data signal to the signal line, a counter electrode driving unit that drives a counter electrode, The pixel circuit includes a first switching element having a first terminal connected to the signal line and selectively conducting in accordance with a logic level of the scanning signal applied to the scanning line connected to the gate terminal. A liquid crystal capacitor formed between the pixel electrode connected to the second terminal of the first switching element, the counter electrode, and a storage capacitor formed between the pixel electrode and the counter electrode To the gate terminal A second switching element that conducts according to a logic level of a first charge sharing drive signal applied to a subsequent charge sharing drive line and selectively short-circuits both ends of the storage capacitor to the counter electrode; A display device is provided.

  With this configuration, charge sharing between the counter electrode and the pixel capacitance (liquid crystal capacitance and storage capacitance) can be performed in each pixel, so that power consumption in the liquid crystal display device can be reduced.

  The charge sharing drive line may be wired in parallel with the scan line.

  The scanning line driving unit generates the first charge sharing driving signal using shift data used for generating the scanning signal, and the generated charge sharing driving signal is used as the charge sharing driving. It may be applied to the line.

  In addition, the scanning line driving unit, the signal line driving unit, the timing control unit for controlling the driving timing of each of the counter electrode driving units, the counter electrode driving unit, and the counter electrode are configured to perform second charge sharing driving. The first switching unit that is selectively turned on in accordance with the logic level of the signal, the connection between the signal line and the signal line driving unit constituting the display unit, or the signal line and the signal line constituting the display unit A second switching unit that switches the connection with the counter electrode according to the logic level of the second charge sharing drive signal, and selectively short-circuits the signal line constituting the display unit to the counter electrode; The second charge sharing drive signal may be generated by the timing control unit.

  The scanning line driving unit generates the first charge sharing driving signal using the shift data used for generating the scanning signal and the second charge sharing driving signal, and generates the generated first charge. A sharing drive signal may be applied to the charge sharing drive line.

  In addition, the first charge sharing that short-circuits both ends of the storage capacitor to the counter electrode and the second charge sharing that short-circuits the signal line constituting the display unit to the counter electrode are performed simultaneously. May be.

  In addition, the scanning line driving unit conducts the first switching element constituting the pixel circuit after the first charge sharing and the second charge sharing are started, and the signal line is opposed to the signal line. You may short-circuit to an electrode.

  Further, the first charge sharing for short-circuiting both ends of the storage capacitor to the counter electrode and the second charge sharing for short-circuiting the signal line constituting the display unit to the counter electrode are performed separately. It may be broken.

  In addition, the second charge sharing may be performed after the first charge sharing is started.

  The first charge sharing may be performed in a horizontal period immediately before a horizontal period in which the second charge sharing is performed.

  A first charge sharing circuit that short-circuits both ends of the storage capacitor to the counter electrode; a second charge sharing circuit that short-circuits the signal line constituting the display portion to the counter electrode; and the pixel circuit. The third charge sharing, in which the signal line is short-circuited to the counter electrode by conducting the first switching element and the second switching element, is the scanning signal generated by the scanning line driving unit. The second charge sharing drive signal generated by the timing control unit may be controlled.

  Further, in one horizontal period, pixel writing in which the data signal is applied to the pixel circuit, first charge sharing in which both ends of the storage capacitor are short-circuited to the counter electrode, and the signal constituting the display unit The second charge sharing in which the line is short-circuited to the counter electrode may be performed in an arbitrary order.

  Further, the first charge sharing and the second charge sharing are started simultaneously, the conduction of the first switching element constituting the pixel circuit is cut off, and the signal line constituting the display unit After the connection with the signal line driver, the first switching element may be turned on and the pixel writing may be performed.

  In addition, after the first charge sharing is started or at the same time, a third charge share that short-circuits the signal line to the counter electrode when the first switching element constituting the pixel circuit is turned on. The pixel writing may be performed by applying the data signal to the pixel circuit after ringing is performed and the second switching element constituting the pixel circuit is turned off.

  In addition, after the first charge sharing for short-circuiting both ends of the storage capacitor to the counter electrode is started, the first switching element constituting the pixel circuit is turned on, whereby the signal line is opposed to the counter electrode. Third charge sharing is performed to short-circuit the electrode, and after the first switching element and the second switching element constituting the pixel circuit are cut off, the first switching element is turned on and the pixel is turned on. Pixel writing in which the data signal is applied to the circuit may be performed.

  In order to achieve the above object, according to the second aspect of the present invention, the signal lines and the scanning lines arranged in a matrix are arranged in correspondence with the intersections of the signal lines and the scanning lines, respectively. A display unit having a pixel circuit, a scanning line driving unit that applies a scanning signal to the scanning line, a signal line driving unit that applies a data signal to the signal line, and a counter electrode driving unit that drives a counter electrode A timing control unit that controls drive timings of the scanning line driving unit, the signal line driving unit, and the counter electrode driving unit, and the counter electrode driving unit and the counter electrode generated by the timing control unit. A first switching unit that is selectively turned on according to a logic level of the second charge sharing driving signal, and a connection between the signal line that constitutes the display unit and the signal line driving unit Alternatively, the connection between the signal line constituting the display unit and the counter electrode is switched according to the logic level of the second charge sharing drive signal, and the signal line constituting the display unit is selectively switched A second switching unit that short-circuits the counter electrode, and the pixel circuit has a first terminal connected to the signal line and a logic level of the scanning signal applied to the scanning line connected to the gate terminal. A first switching element selectively turned on, a pixel electrode connected to the second terminal of the first switching element, a liquid crystal capacitor formed between the counter electrode, the pixel electrode, and the counter electrode Is selectively guided according to the logic level of the first charge sharing drive signal applied to the storage capacitor formed between and the charge sharing drive line connected to the gate terminal. A driving method for pixel writing that applies the data signal to the pixel circuit, applicable to a display device including a second switching element that short-circuits both ends of the storage capacitor to the counter electrode, A first step of simultaneously starting a first charge sharing for short-circuiting both ends of the storage capacitor to the counter electrode and a second charge sharing for short-circuiting the signal line constituting the display unit to the counter electrode; After the first step, the second step of cutting off the conduction of the first switching element constituting the pixel circuit and connecting the signal line constituting the display unit and the signal line driving unit; After the second step, there is provided a driving method including a third step of applying the data signal to the signal line.

  By using this method, power consumption in the liquid crystal display device can be reduced.

  According to the present invention, it is possible to reduce power consumption in a liquid crystal display device.

It is explanatory drawing for demonstrating the technique used as the premise of the structure which concerns on the display apparatus which concerns on embodiment of this invention. It is explanatory drawing for demonstrating the technique used as the premise of the structure which concerns on the display apparatus which concerns on embodiment of this invention. It is explanatory drawing for demonstrating the technique used as the premise of the structure which concerns on the display apparatus which concerns on embodiment of this invention. It is explanatory drawing for demonstrating the technique used as the premise of the structure which concerns on the display apparatus which concerns on embodiment of this invention. It is explanatory drawing for demonstrating the technique used as the premise of the structure which concerns on the display apparatus which concerns on embodiment of this invention. It is explanatory drawing for demonstrating the technique used as the premise of the structure which concerns on the display apparatus which concerns on embodiment of this invention. It is explanatory drawing for demonstrating the technique used as the premise of the structure which concerns on the display apparatus which concerns on embodiment of this invention. It is explanatory drawing which shows the pixel circuit (equivalent circuit of a pixel) of the pixel with which the display apparatus which concerns on embodiment of this invention is provided. It is explanatory drawing which shows an example of a structure of the display apparatus which concerns on embodiment of this invention. It is explanatory drawing which shows an example of a structure of the gate driver (scanning drive part) which concerns on embodiment of this invention. It is explanatory drawing which shows the other example of a structure of the gate driver (scanning drive part) which concerns on embodiment of this invention. It is explanatory drawing which shows the other example of a structure of the display apparatus which concerns on embodiment of this invention. It is explanatory drawing which shows the waveform which concerns on the operation | movement regarding the charge sharing in the display apparatus which concerns on embodiment of this invention. It is explanatory drawing which shows the waveform which concerns on the operation | movement regarding the charge sharing in the display apparatus which concerns on embodiment of this invention. It is explanatory drawing which shows the waveform which concerns on the operation | movement regarding the charge sharing in the display apparatus which concerns on embodiment of this invention. It is explanatory drawing which shows the waveform which concerns on the operation | movement regarding the charge sharing in the display apparatus which concerns on embodiment of this invention. It is explanatory drawing which shows the waveform which concerns on the operation | movement regarding the charge sharing in the display apparatus which concerns on embodiment of this invention.

  Exemplary embodiments of the present invention will be described below in detail with reference to the accompanying drawings. In the present specification and drawings, components having substantially the same functional configuration are denoted by the same reference numerals, and redundant description is omitted.

(Assumption)
Prior to the description of the configuration of a display device according to an embodiment of the present invention (hereinafter sometimes referred to as “display device 100”), a technology that is a premise of the configuration of the display device 100 will be described.

  FIGS. 1-7 is explanatory drawing for demonstrating the technique used as the premise of the structure which concerns on the display apparatus 100 which concerns on embodiment of this invention.

FIG. 1 shows a pixel circuit (pixel equivalent circuit) of a pixel included in a general liquid crystal display device. Here, the general pixel includes, for example, a transistor TR1, a liquid crystal capacitor _CLC formed between a pixel electrode (not shown) and a VCOM electrode (counter electrode), and between the pixel electrode and the VCOM electrode. And a storage capacitor _CST . The transistor TR1 is selectively turned on according to the logic level of the gate drive line signal G _PX (scanning signal) applied to the gate terminal. When the transistor TR1 is selectively turned on, a source drive line signal (data signal) applied to the source drive line (signal line) connected to the first terminal is written.

  FIG. 2 shows an example of the configuration (configuration related to charge sharing) of a conventional display device (hereinafter sometimes referred to as “display device 10”). The display device 10 includes a display panel 12 (display unit), a gate driver 14 (scanning line driving unit), a source driver 16 (signal line driving unit), a VCOM driver 18 (counter electrode driving unit), and a timing control unit. 20, a first switching unit SW <b> 1, and a second switching unit 22.

  The display panel 12 includes source drive lines (signal lines) and gate drive lines (scanning lines) arranged in a matrix, and the pixel circuit shown in FIG. 1 is provided at each intersection of the source drive lines and the gate drive lines. Is provided. Hereinafter, the drive lines included in the display panel 12 may be referred to as “internal drive lines”.

  The gate driver 14 applies a gate drive line signal (scanning signal) to the gate drive line. The source driver 16 applies a source drive line signal (data signal) to the source drive line (signal line). The VCOM driver 18 drives the VCOM electrode. The timing control unit 20 controls the drive timing of each of the gate driver 14, the source driver 16, and the VCOM driver 18.

  The first switching unit SW1 selectively makes the VCOM driver 18 and the VCOM electrode conductive in accordance with the logic level of the applied charge sharing drive signal CSE (hereinafter sometimes referred to as “CSE signal”). . Here, the charge sharing drive signal CSE is applied by the timing control unit 20. The second switching unit 22 includes a switch SW2 for each source drive line that constitutes the display panel 12, and connects the source drive line and the source driver 16 or connects the source drive line and the VCOM electrode with a charge share. The source drive line is selectively short-circuited to the VCOM electrode by switching according to the logic level of the ring drive signal CSE. That is, the display device 10 includes the first switching unit SW1 and the second switching unit 22 to perform charge sharing.

  FIG. 3 shows a circuit configuration of the gate driver 14 included in the display device 10. The gate driver 14 includes a plurality of shift registers and an OR circuit, and includes a circuit 30 that generates a signal based on the shift data STV, and a driver circuit 32 corresponding to each gate drive line. Here, “STV” shown in FIG. 3 indicates gate driver shift data, and “CKV” indicates gate driver shift clock (hereinafter the same). In addition, “GE” shown in FIG. 3 is a gate driver output enable (hereinafter sometimes referred to as “GE signal”), “CSE” is charge sharing enable, and “XSR [n]” is shift data ( n is a natural number, “HE” is a horizontal effective period (horizontal period), and “GL [n]” is a gate drive line (n is a natural number) (hereinafter the same).

  FIG. 4 shows a drive waveform for one screen scan, and FIG. 5 shows a shaping waveform of the gate drive line signal. Here, “VS” shown in FIGS. 4 and 5 indicates a vertical synchronization signal, and “HS” indicates a horizontal synchronization signal. 4 and 5, “CSE” indicates charge sharing enable, “S [m]” indicates a source driver output (m is a natural number), and “VCOMP” indicates a VCOM driver output (hereinafter referred to as “COMP”). The same shall apply). Further, “Timing-A” shown in FIG. 5 shows an example in which the overlap period of the GE signal and the CSE signal is not provided, and “Timing-B” provides the overlap period of the GE signal and the CSE signal. An example of the case is shown. “Timing-C” indicates an example in which an overlap period of the GE signal and the CSE signal is provided, and then the GE signal is once turned off.

  FIG. 6 shows waveforms related to the operation related to conventional charge sharing in the display device 10. Here, FIG. 6 shows drive waveforms for two rows. FIG. 6 shows the row n and row n + 1 driving units of each driver locally. The waveforms of the drivers are the driver end (driver output), the VCOM electrode and the source drive line, and the pixel (n, m). , The potential state of the pixel (n + 1, m). FIG. 6 mainly illustrates polarity line inversion driving and VCOM pulse driving as an example, but the principle is the same for, for example, polarity column inversion driving (column inversion) and polarity dot inversion driving. In the polarity column inversion driving and polarity dot inversion driving, for example, VCOM constant voltage driving is often used, but the same technique can be used here. Here, the case where the VCOM potential in FIG. 6 is taken as a reference corresponds to the VCOM constant voltage drive. Further, the gradation writing condition in FIG. 6 is that the same gradation is written in the same pixel in both the previous frame and the current frame with polarity reversed, and in FIG. 6, the gradation (210) is applied to the pixel (n, m). In this example, 84 levels of gradation are written to the pixel (n + 1, m). Further, FIG. 6 shows an example in which the gradation 170 level is written in the pixel (n−1, m) which is the preceding and following pixels, and the gradation 255 level is written in the pixel (n + 2, m). Note that n and m are natural numbers.

Referring to FIG. 6, the display device 10 enables the CSE signal when the polarity of the driver output is reversed in one horizontal period, and connects the output terminals of the source driver 16 and the VCOM driver 18 and the internal drive lines of the display panel 12. The first switching unit SW1 and the switch SW2 constituting the second switching unit 22 are used for separation. At this time, the VCOM electrode and the source drive line are separated from each driver that activates them and are in a floating state. Further, the VCOM electrode and the source drive line are short-circuited by the switch SW2. Immediately before the short circuit, the source drive line and the VCOM electrode are charged to a voltage value necessary for writing the pixel in the row n-1. Further, the writing of the pixels has already been completed, and the role of the charges charged in the wiring capacity of the source drive line and the VCOM electrode, the interlayer parasitic capacity, and the like is finished. At this time, each pixel holds a potential difference (gradation) written in a state where the liquid crystal capacitor (C _LC ) and the storage capacitor (C _ST ) and the VCOM electrode are capacitively coupled.

  Here, when the display unit 10 does not include a charge sharing mechanism, the source driver 16 collects the charge that has become unnecessary in the source drive line and is charged (written) to a desired potential. Driven by. In the case of polarity line inversion driving (row inversion) and VCOM pulse driving, the VCOM electrode always changes its potential from a high potential to a low potential or from a low potential to a high potential in order to perform polarity inversion. This charging is also performed by the VCOM driver 18. For this reason, if the charge sharing mechanism is not provided, a large potential transition occurs during polarity inversion of the VCOM electrode and the source drive line, which are preparations before pixel writing, and power consumption increases due to large charge movement. .

  In the conventional technology, by performing charge sharing at the timing of the above polarity inversion, unnecessary charges accumulated in the VCOM electrode and the source drive line are short-circuited and neutralized, and the VCOM electrode and the source drive line are changed to the same potential. I am letting. Since the above operation shifts in the potential direction of pixel writing in row n, it also plays a role of supporting driver driving, and brings about an effect similar to the precharge operation. At this time, power is not consumed.

The charge sharing period is not a period in which each driver is actively charging, but neutralizes the charges accumulated in the VCOM electrode and the source drive line and determines the potential according to the respective capacitance division ratio ( The purpose of charge sharing is to make transition without supplying external charge to the middle point). Charge sharing is intended to reduce power consumption by reusing charges. . Therefore, in order to maximize the charge sharing effect, for example, it is necessary to reduce the capacitance and impedance of the VCOM electrode, the source drive line, and the short-circuit point, or to maintain a long charge sharing period. In the configuration shown in FIGS. 1 and 2, since charge sharing and pixel writing must be performed in a time division within one horizontal period, for example, as shown in FIGS. Within the period, the order is as follows (i) to (iii).
(I) Charge sharing ON
(Ii) Polarity inversion drive (iii) Charge sharing OFF

  When one horizontal period is constant, the pixel writing period is compressed when the charge sharing period is long. On the other hand, in order to perform pixel writing in a short time, it is necessary to increase the driving capability of the source driver, and in order to increase the driving capability, it is necessary to increase the constant current of the buffer and the amplifier constituting the source driver. Here, increasing the constant currents of the buffer and the amplifier as described above is contrary to the purpose of the charge sharing and leads to an increase in power.

  In general, scanning for one screen in the display device does not depend on the resolution and is always constant (for example, about 60 “Hz”). For this reason, an increase in horizontal resolution is directly linked to a decrease in one horizontal period. At present, when the resolution is increasing, one horizontal period is decreasing. Further, as the resolution increases, the number of pixel write control switching elements (corresponding to the transistor TR1 shown in FIG. 1) connected to the source drive line also increases, so the load also increases. Therefore, the charge sharing period cannot be kept longer as the display device has higher resolution and higher frame rate. When the charge sharing period cannot be secured for a long time, the display device 10 does not perform complete charge sharing as shown in FIG. 6A, leaving an unnecessary charge. Further, in the display device 10, since the potential transition is insufficient, an effective driving power reduction effect cannot be expected.

  Therefore, the conventional display device 10 having the configuration shown in FIG. 2 according to the prior art cannot reduce power consumption in the liquid crystal display device. Here, the problem in the configuration shown in FIG. 2 is that the impedance of the short circuit point is high. Since the short circuit is caused only at the driver end, the current density at the time of charge transfer between the VCOM electrode and the source drive line is increased at the short circuit point. In other words, in the configuration shown in FIG. 2, the effect of charge sharing decreases as the distance from the short-circuit point increases.

  FIG. 7 shows another configuration of the conventional display device 10 for solving the problem related to the configuration shown in FIG. In the configuration shown in FIG. 7, the switching unit 24 is provided at the other end of the source drive line (the end opposite to the end of the source drive line to which the switching unit 22 is connected). That is, the display device 10 having the configuration shown in FIG. 7 reduces the impedance by providing short-circuit points at both ends of the source drive line. Therefore, the display device 10 having the configuration shown in FIG. 3 can improve the charge sharing effect more than the display device 10 having the configuration shown in FIG. However, in the display device 10 having the configuration shown in FIG. 3, the load becomes higher toward the middle point of the source drive line, so that the effect of charge sharing becomes weaker toward the middle point. Therefore, even if the configuration shown in FIG. 3 according to the prior art is taken, it is not always possible to reduce power consumption in the liquid crystal display device.

(Display device 100 according to an embodiment of the present invention)
[Outline of Display Device 100 according to Embodiment of Present Invention]
As described above, even if the conventional technique is used, it is not always possible to reduce power consumption in the liquid crystal display device. In view of this, the display device 100 according to the embodiment of the present invention employs a circuit configuration that further reduces the impedance of the short-circuit point, and uses a driving method that shortens the time required for charge sharing while increasing the reuse rate of unnecessary charges. By improving the charge sharing effect.

  Hereinafter, a configuration of a circuit configuration according to the embodiment of the present invention and a driving method according to the embodiment of the present invention will be described. In the following, a waveform corresponding to the waveform shown in FIG. 6 is used in the description in order to make it easier to compare the difference between the conventional technique and the technique related to the display device 100 according to the embodiment of the present invention.

[Circuit Configuration According to the Embodiment of the Present Invention]
FIG. 8 is an explanatory diagram illustrating a pixel circuit (equivalent circuit of a pixel) of a pixel included in the display device 100 according to the embodiment of the present invention. The pixel according to the embodiment of the present invention includes, for example, a first switching element TR1, a liquid crystal capacitor _CLC formed between a pixel electrode (not shown) and a VCOM electrode (counter electrode), a pixel electrode, and a VCOM. having a storage capacitor C _ST is formed between the electrodes, so as to bypass the ends of the storage capacitor C _ST an electrically controllable second switching element TR2.

The first switching element TR1 is selectively turned on according to the logic level of the gate drive line signal _GPX (scanning signal) applied to the gate terminal. When the first switching element TR1 is selectively turned on, the source drive line signal (data signal) applied to the source drive line (signal line) connected to the first terminal is written. The second switching element TR2 is rendered conductive in response to the logic level of the first charge sharing driving signals GS _PX applied to the charge sharing driving line connected to the gate terminal. By the second switching element TR2 is conductive, both ends of the storage capacitor _{C ST} is shorted to the VCOM electrode.

  Therefore, the display device 100 can perform charge sharing in the pixel by providing the pixel circuit with the second switching element TR2. Hereinafter, the charge sharing in the pixel according to the embodiment of the present invention may be referred to as “first charge sharing”.

  Here, FIG. 8 shows an example in which the first switching element TR1 and the second switching element TR2 are N-channel FETs (Field Effect Transistors), but the first switching element TR1 and the second switching element. TR2 is not limited to an N-channel FET. For example, the first switching element TR1 and the second switching element TR2 may be P-channel FETs. Even with the configuration described above, the first switching element TR1 and the second switching element TR2 can be selectively conducted according to the logic level of the signal applied to the gate terminal. Further, the first switching element TR1 and the second switching element TR2 can be composed of arbitrary switching elements having the same characteristics.

  Further, as shown in FIG. 8, the pixel is manufactured as a switching element (N-channel FET in FIG. 8) in which the first switching element TR1 and the second switching element TR2 have the same characteristics. Compared with the case where the pixel shown in 1 is manufactured, the manufacturing cost does not change.

  FIG. 9 is an explanatory diagram showing an example of the configuration of the display device 100 according to the embodiment of the present invention. The display device 100 includes a display panel 102 (display unit), a gate driver 104 (scanning line driving unit), a source driver 106 (signal line driving unit), a VCOM driver 108 (counter electrode driving unit), and a timing control unit. 110, a first switching unit SW1, and a second switching unit 112.

  The display panel 102 includes source drive lines (signal lines, S [m]) and gate drive lines (scanning lines, GL [n]) arranged in a matrix, and intersections between the source drive lines and the gate drive lines. Each is provided with a pixel circuit shown in FIG. Hereinafter, the drive lines included in the display panel 102 may be referred to as “internal drive lines”. In addition, the display panel 102 has a charge sharing drive line (CS [n]) wired in parallel with the gate drive line as an internal drive line.

The gate driver 104 applies a gate drive line signal _GPX (scanning signal) to the gate drive line (GL [n]). Further, the gate driver 104 applies the first charge sharing drive signal GS _PX to the charge sharing drive line (CS [n]).

[Configuration Example of Gate Driver 104]
FIG. 10 is an explanatory diagram showing an example of the configuration of the gate driver 104 (scan driving unit) according to the embodiment of the present invention. The gate driver 104 has a configuration similar to that of the circuit 30 shown in FIG. 3, and generates a signal 150 based on the shift data STV, and a driver circuit 152 corresponding to each gate drive line and each charge sharing drive line. Is provided. Here, the gate driver 104 adds an input of a charge sharing control signal (CSE, hereinafter referred to as “second charge sharing control signal”) to the conventional gate driver 14 shown in FIG. This is connected to the output of the second charge sharing control signal CSE of the timing control unit 110. Further, the gate driver 104 generates the first charge sharing drive signal _GSPX in the n-row horizontal period in the gate driver 1-bit cell. More specifically, the gate driver 104 logically gates the node (HE [n]) that is valid in one horizontal period in the gate driver 1-bit cell and the second charge sharing control signal CSE. to generate a first charge sharing driving signals GS _PX corresponding to the charge sharing driving line (CS [n]).

  As shown in FIG. 10, the gate driver 104 logically gates the shift data of the shift register and the second charge sharing drive signal CSE in each cell of the gate driver 104 in the same manner as the gate drive line. Drive the ring drive line. When the gate driver 104 has the above-described configuration, the display device 100 controls the timing of the GE signal and the CSE signal within one horizontal period, so that the gate driving line and the charge sharing driving line can be set to arbitrary timings. Can be controlled.

With the configuration shown in FIG. 10, the gate driver 104 generates the first charge sharing drive signal GS _PX using the shift data STV used for generating the gate drive line signal G _PX (scanning signal), The generated first charge sharing drive signal _GSPX is applied to the charge sharing drive line (CS [n]). Further, the gate driver 104 uses the shift data STV used for generating the gate drive line signal G _PX (scanning signal) and the second charge sharing drive signal CSE (by logic gate) to perform the first charge share. The ring drive signal GS _PX is generated, and the generated first charge sharing drive signal GS _PX is applied to the charge sharing drive line (CS [n]).

  Note that the configuration of the gate driver 104 according to the embodiment of the present invention is not limited to the configuration shown in FIG. FIG. 11 is an explanatory diagram showing another example of the configuration of the gate driver 104 (scan driving unit) according to the embodiment of the present invention.

The gate driver 104 shown in FIG. 11 includes a circuit 154 that generates a signal based on the shift data STV, and a driver circuit 156 corresponding to each gate drive line and each charge sharing drive line. Here, similarly to FIG. 10, the gate driver 104 adds the input of the second charge sharing control signal (CSE) to the conventional gate driver 14 shown in FIG. 3, and the second charge sharing of the timing controller 110. This is connected to the output of the control signal CSE. Further, the gate driver 104 generates the first charge sharing drive signal GS _PX in the n−1 row and n row horizontal periods in the gate driver 1-bit cell. More specifically, the gate driver 104 logically gates the shift data node (SR [n]) shifted by the half latch in the gate driver 1-bit cell and the second charge sharing control signal CSE. Thus, the first charge sharing drive signal GS _PX corresponding to the charge sharing drive line (CS [n]) is generated.

The gate driver 104 according to the embodiment of the present invention generates, for example, the gate drive line signal G _PX and the first charge sharing drive signal GS _PX by taking the configuration shown in FIGS. GL [n]) and the charge sharing driving line (CS [n]) to apply a gate drive line signal _{G PX} in the first charge sharing driving signals _{GS PX.} Needless to say, the configuration of the gate driver 104 according to the embodiment of the present invention is not limited to the configurations shown in FIGS. 10 and 11.

  With reference to FIG. 9 again, an example of the configuration of the display device 100 according to the embodiment of the present invention will be described. The source driver 106 applies a source drive line signal (data signal) to the source drive line (signal line). The VCOM driver 108 drives the VCOM electrode. The timing control unit 110 controls the drive timing of each of the gate driver 104, the source driver 106, and the VCOM driver 108.

  The first switching unit SW1 selectively conducts the VCOM driver 108 and the VCOM electrode according to the logic level of the applied second charge sharing drive signal CSE. Here, the timing controller 110 applies the second charge sharing drive signal CSE. The second switching unit 122 includes a switch SW2 (for example, a three-pole switch) for each source drive line (S [m]) constituting the display panel 102, and each source drive line (S [m]), the source driver 106, and the like. Or the connection between the source drive line (S [m]) and the VCOM electrode is switched according to the logic level of the second charge sharing drive signal CSE, and the source drive line (S [m]) is selectively selected. Is shorted to the VCOM electrode.

  More specifically, the display device 100 controls the ethical level of the second charge sharing drive signal CSE so that the first switching unit SW1 is connected to the VCOM driver output when charge sharing is disabled, When the ring is active, make it float. Further, the display device 100 controls the ethical level of the second charge sharing drive signal CSE, so that each switch SW2 [m] constituting the second switching unit 112 has a source driver output when charge sharing is disabled. When the charge sharing is valid, the display device 100 is connected to the VCOM electrode. That is, the display device 100 can select either the VCOM driver output or the floating connection destination to the VCOM electrode. SW1 and a second switching unit 122 are provided.

  Therefore, the display device 100 can perform charge sharing similar to that of the display device 10 illustrated in FIG. 2 by including the first switching unit SW1 and the second switching unit 122. Hereinafter, the charge sharing by short-circuiting the source drive line (signal line, S [m]) constituting the display panel 102 (display unit) to the VCOM electrode may be referred to as “second charge sharing”. is there.

  The display device 100 can perform, for example, the first charge sharing in the pixel in addition to the second charge sharing similar to the configuration illustrated in FIG. 2 by adopting the configuration illustrated in FIG. 9. The effect of the display device 100 according to the embodiment of the present invention further performing the first charge sharing will be described in the driving method according to the embodiment of the present invention described later.

  In addition, the structure of the display apparatus 100 which concerns on embodiment of this invention is not restricted to the structure shown in FIG. For example, the display device 100 according to the embodiment of the present invention may further include a switching unit (third switching unit) having the same configuration as the switching unit 24 included in the display device 10 illustrated in FIG. In the above configuration, one of the switch poles of each switch SW3 [m] constituting the third switching unit is connected to the source drive line, and the other switch pole is connected to the VCOM electrode. With the above configuration, the display device 100 changes the ethical level of the second charge sharing drive signal CSE that controls each switch SW3 [m], thereby floating the connection destination of the source drive line when charge sharing is disabled. When the charge sharing is effective, the VCOM electrode can be used.

  FIG. 12 is an explanatory diagram illustrating another example of the configuration of the display device 100 according to the embodiment of the present invention. As shown in FIG. 12, the display device 100 according to the embodiment of the present invention can be configured not to perform charge sharing (second charge sharing) according to the conventional technique. Even in the configuration illustrated in FIG. 12, the display device 100 can perform the first charge sharing, and thus is driven with lower power consumption than a display device having a configuration without a charge sharing mechanism. can do.

[Driving Method According to Embodiment of the Present Invention]
Next, a driving method of the display device 100 according to the embodiment of the present invention shown in FIG. 9 will be described, for example.

(0) Basic Drive First, the basic drive in the display device 100 according to the embodiment of the present invention will be described.

  The gate driver 104 performs row scanning driving by using the vertical direction start data STV as shift data and shifting the shift register in the gate driver 104 with the gate driver / shift clock CKV. The gate driver 104 forms one horizontal period by shaping the shift data (HE [n]).

  In a row in which HE [n] is valid, all pixels in the row are in a pixel writing state during a period in which the gate control signal GE controlled by the timing control unit 110 is valid.

In the pixel writing state, the switching element TR1 of the pixel is turned on, and the potential difference from the source drive line is charged to the pixel capacitor with the VCOM potential as a base point. Here, the pixel capacitor according to the embodiment of the present invention refers to a volume including a liquid crystal capacitor C _LC and _the storage capacitor C _ST.

  After the pixel writing charge is completed, the gate control signal GE is invalidated and the switching element TR1 is opened, so that the pixel capacitor holds the pixel potential in a state of being capacitively coupled to the VCOM electrode.

  Since the pixel potential is held as a capacitive component, the pixel potential is discharged over time. Therefore, the display device 100 performs rewriting at a cycle that does not fall below a desired gradation potential.

  In the active matrix display device as shown in FIG. 9, pixels in the row direction are written simultaneously, and the column direction is written by sequential scanning. That is, the display device 100 displays one image on the display screen by performing scanning for one screen.

  Since the pixels need to be rewritten, scanning of one screen is repeated according to the refresh rate (period) while the display device 100 displays an image.

  In addition, in a liquid crystal display device such as the display device 100, it is necessary to switch between writing a positive potential and a negative potential at the VCOM potential base point in order to reduce deterioration in the characteristics of the liquid crystal element (VCOM potential reference point) Polarity reversal).

  Here, examples of the polarity inversion method include polarity line inversion, polarity column inversion, and polarity dot inversion. Further, there are mainly two operations of the source driver 106 and the VCOM driver 208 for driving the polarity inversion, one is the VCOM constant voltage driving and the other is the VCOM pulse driving. In the VCOM constant voltage drive, the polarity inversion drive is performed when the output of the VCOM driver 108 is a constant voltage and the source driver 106 outputs a positive potential (positive polarity) or a negative potential (negative polarity) based on the VCOM potential. In the VCOM pulse drive, the VCOM driver 108 outputs a binary sine wave. If the high potential of the sine wave is VCOMH and the low potential is VCOML, VCOML is output in the positive polarity and VCOMH is output in the negative polarity. The source driver 106 outputs a positive potential for the positive polarity and a negative potential for the negative polarity based on the VCOM potential. Since the VCOM potential, which is the base potential, changes, the absolute amplitude of the source driver 106 becomes smaller than that in the VCOM constant voltage drive. Therefore, low voltage driving is possible.

  Further, as shown in FIG. 5, for example, in polarity line inversion and polarity dot inversion, polarity inversion driving is performed every time a row scan changes.

  Here, a large amount of power is consumed when driving the VCOM electrode, the charge / discharge of the source drive line, and the charge / discharge of the pixel capacitance at the time of pixel writing, which are preparations before the pixel writing. Therefore, driving the VCOM electrode and the source drive line with low power consumption and performing pixel writing with low power consumption lead to reduction of power consumption in the liquid crystal display device.

  The display device 100 performs the basic drive as described above. Next, a driving method in the display device 100 according to the embodiment of the present invention will be described. Hereinafter, an example of a driving method (first driving method) when the display device 100 includes the gate driver 104 illustrated in FIG. 10 and a driving method (first driving method) when the display device 100 includes the gate driver 104 illustrated in FIG. An example of the second driving method) will be described.

(1) First Driving Method FIG. 13 is an explanatory diagram showing waveforms related to operations related to charge sharing in the display device 100 according to the embodiment of the present invention. Here, “CS [n]” shown in FIG. 13 indicates a charge sharing drive line (n is a natural number) (hereinafter the same). Further, “Timing-A” shown in FIG. 13 shows an example in which the overlap period of the GE signal and the CSE signal is not provided, and “Timing-B” provides the overlap period of the GE signal and the CSE signal. An example of the case is shown. “Timing-C” indicates an example in which an overlap period of the GE signal and the CSE signal is provided, and then the GE signal is once turned off.

  First, an outline of operations related to charge sharing in the display device 100 will be described with reference to FIG.

(1-0) Initial State Immediately before the transition to the horizontal period of row n by scanning of the gate driver 104, the gate drive control signal GE is invalid and the first charge sharing control signal GS _PX is invalid. The drive line (GL [n]) and the charge sharing drive line (CS [n]) are invalid. That is, the initial state is a state where both the first switching element TR1 and the second switching element TR2 in the pixel (n, m) are in an open state.

(1-1) Timing-A
FIG. 14 is an explanatory diagram showing a waveform related to an operation related to charge sharing in the display device 100 according to the embodiment of the present invention, and shows an operation waveform related to Timing-A. A driving method in Timing-A will be described with reference to FIGS. 13 and 14.

  After the horizontal period transitions to the current row n, first, the CSE signal is enabled, the second charge sharing (VCOM electrode-source drive line charge sharing), and the first charge sharing (VCOM electrode- Implement charge sharing between pixel capacitors. Since the CSE signal is effective, the VCOM electrode and the VCOM driver 108 are disconnected by the first switching unit SW1, and the source drive line is short-circuited with the VCOM electrode by the switch SW2 [m] configuring the second switching unit 112. In addition, the second switching element TR2 of each pixel in the current row is turned on, and both ends of the pixel capacitor are short-circuited to the VCOM electrode. At this time, since the first switching element TR1 is open, each charge sharing is performed independently. Here, power is not consumed during charge sharing (first state).

  The CSE signal is invalidated and charge sharing ends. At this time, the source drive line is electrically connected to the VCOM driver output by the switch SW2 [m] constituting the second switching unit 112, and the VCOM electrode is electrically connected to the VCOM driver by the first switching unit SW1, and is driven by the VCOM driver. (Second state).

  The GE signal is enabled and pixel writing is performed. At this time, the first switching element TR1 of each pixel in the current row is electrically connected to each source drive line, and the potential difference from the VCOM electrode potential is charged to the pixel capacitance. Further, since the second switching element TR2 is in the open state, it does not affect the charging operation (third state).

  After the charging of a desired potential (gradation) is completed by the pixel writing operation, the GE signal is invalidated and the pixel writing state is ended. At this time, the first switching element TR1 is opened, and the pixel capacitance holds the pixel potential in a state of being capacitively coupled to the VCOM electrode (fourth state).

  In Timing-A illustrated in FIG. 14, the display device 100 operates as described above, for example.

(1-2) Timing-B
FIG. 15 is an explanatory diagram illustrating a waveform related to an operation related to charge sharing in the display device 100 according to the embodiment of the present invention, and illustrates an operation waveform related to Timing-B. A driving method in Timing-B will be described with reference to FIGS. 13 and 15.

  After the horizontal period transitions to the current row n, first, the CSE signal is enabled, the second charge sharing (VCOM electrode-source drive line charge sharing), and the first charge sharing (VCOM electrode- Implement charge sharing between pixel capacitors. Since the CSE signal is effective, the VCOM electrode and the VCOM driver 108 are disconnected by the first switching unit SW1, and the source drive line is short-circuited with the VCOM electrode by the switch SW2 [m] configuring the second switching unit 112. In addition, the second switching element TR2 of each pixel in the current row is turned on, and both ends of the pixel capacitor are short-circuited to the VCOM electrode. At this time, since the first switching element TR1 is open, each charge sharing is performed independently. Here, power is not consumed during charge sharing (first state).

  By making the GE signal valid, an overlap period with the CSE signal is generated. At this time, since the second switching element TR2 of each pixel in the current row is in a conductive state and the first switching element TR1 is in a conductive state, a path for short-circuiting the VCOM electrode-source drive line is formed in each pixel. In the second charge sharing (VCOM electrode-source drive line charge sharing), the impedance at the short-circuit point decreases, and the time constant decreases, so the charge neutralization rate increases (second State). Here, as described above, the charge sharing that short-circuits the source drive line (signal line) to the VCOM electrode (counter electrode) by conducting the first switching element TR1 and the second switching element TR2 is a low impedance, This can be regarded as charge sharing (third charge sharing).

  The CSE signal is invalidated and charge sharing ends. At this time, the source drive line is electrically connected to the VCOM driver output by the switch SW2 [m] constituting the second switching unit 112, and the VCOM electrode is electrically connected to the VCOM driver by the first switching unit SW1, and is driven by the VCOM driver. Is done. Further, since the GE signal is valid, pixel writing is performed. At this time, the first switching element TR1 of each pixel in the current row is electrically connected to each source drive line, and the potential difference from the VCOM electrode potential is charged in the pixel capacitance. Further, since the second switching element TR2 is in the open state, it does not affect the charging operation (third state).

  After the charging of a desired potential (gradation) is completed by the pixel writing operation, the GE signal is invalidated and the pixel writing state is ended. At this time, the first switching element TR1 is opened, and the pixel capacitance holds the pixel potential while being capacitively coupled to the VCOM electrode (fourth state).

  In Timing-B shown in FIG. 15, the display device 100 operates as described above, for example.

(1-3) Timing-C
The display device 100 generates a GE signal and CSE signal invalid state between the second state and the third state of Timing-B, and generates a second state of Timing-A.

  Thereafter, the display device 100 shifts to the third state and the fourth state of Timing-A.

  In Timing-C, the display device 100 operates as described above, for example.

The display device 100 using the first driving method operates as described above, for example. Here, in the operation of the display device 100, the following driving (I) to (III) is performed in a time-sharing manner in the horizontal period, as in the prior art.
(I) Charge sharing ON
(II) Polarity reversal drive (III) Charge sharing OFF

At this time, a portion that is greatly different from the conventional technique is that the VCOM electrode and the source drive line are short-circuited during the charge sharing period, and at the same time, all the pixels in the current row to be written are stored in the respective storage capacitors (C _ST ) Is short-circuited to the VCOM electrode.

  The superiority of the driving method according to the embodiment of the present invention will be described with reference to FIG. By using the driving method according to the embodiment of the present invention, the second charge sharing (VCOM electrode-source drive line charge sharing) and the first charge sharing (VCOM electrode-pixel capacitance charge sharing) are performed. ) Are performed independently. Charge sharing is performed between the VCOM electrode and the source drive line as in the prior art, and charge sharing is performed for all the pixels in the row direction between the VCOM electrode and the pixel capacitor.

  As shown in FIG. 14B and FIG. 14C, the capacitance and impedance between the VCOM electrode capacitance and the pixel capacitance are smaller than the capacitance and impedance between the VCOM electrode and the source drive line. Therefore, when compared with the time required for the second charge sharing (VCOM electrode-source drive line charge sharing), the charge sharing within the pixel is completed in a short time.

  Further, since the pixel capacitance has a negligible capacitance difference with the VCOM electrode capacitance, the pixel potential is almost the same potential as the VCOM electrode (potential offset by the threshold voltage Vth of the second switching element TR2). Transition to. Here, in the conventional technique, the charge in the pixel is held until it is driven by each driver. In the pixel, the potential changes greatly because the height relationship between the VCOM potential and the pixel potential is always reversed due to the polarity inversion. Then, a large amount of power is consumed when the above drive is performed.

  On the other hand, in the display device 100 according to the embodiment of the present invention, since the potential is always changed to the VCOM potential before being driven by each driver, the potential inversion occurs when writing to a desired gradation. The potential transition amount is also reduced. Accordingly, the display device 100 can reduce power consumption, and thus can reduce power consumption.

  Further, in the conventional technique, as shown in Timing-B and Timing-C in FIG. 5 in the conventional technique, it is possible to provide an overlap period between the CSE signal and the GE signal. As shown in FIG. 1, by enabling the GE signal, the transistor TR1 is short-circuited and connected to the source drive line. In this case, the display device 100 according to the embodiment of the present invention is similar to the display device 100 in terms of potential drive, but is greatly different in actual operation.

  More specifically, in the conventional technique, a method of short-circuiting the transistor TR1 is employed. However, since the pixel capacitance in this case is capacitively coupled to the VCOM electrode, the charge supply (movement) is performed by the transistor TR1. Done through. That is, when viewed from the charge sharing short-circuit point, the load corresponding to the pixel capacitance is increased. Therefore, when the charge sharing according to the conventional technology and the charge sharing according to the embodiment of the present invention are performed in the same charge sharing period, the effect of the charge sharing according to the conventional technology is: This is less than the effect of charge sharing according to the embodiment of the present invention.

  Further, as shown in Timing-B and Timing-C in FIG. 13, the display device 100 according to the embodiment of the present invention can provide an overlap period between the CSE signal and the GE signal as in the conventional technique. is there. Further, in the display device 100, the effect of further improving the charge sharing effect is exerted compared to the case where the conventional technique is used. With reference to FIG. 15, the effect according to the embodiment of the present invention will be described.

  First, the CSE signal is validated in the GE signal invalid state. This state is the same as described above, and the second charge sharing (VCOM electrode-source drive line charge sharing) and the first charge sharing (VCOM electrode-pixel capacitor charge sharing) are respectively performed. It is done independently. At this time, the charge accumulated in the VCOM electrode and the source drive line is charge-shared by the short-circuit point, and the pixel capacitance is very small compared to the load between the VCOM electrode and the source drive line. Transition to the potential of the VCOM electrode by the first charge sharing (charge sharing between the VCOM electrode and the pixel capacitor) in a time earlier than the time required for charge sharing (charge sharing between the VCOM electrode and the source drive line) ( First state).

  Thereafter, by enabling the GE signal, the display device 100 generates an overlap period with the CSE signal. At this time, the first switching element TR1 of the pixel is short-circuited in a state where the charge sharing function is effective (second state). Further, by subsequently disabling the CSE signal, the VCOM electrode is driven by the VCOM driver, and the source driver 106 and the current pixel are driven to a desired potential by the source driver 106 (third state). After the writing to the desired potential is completed, the GE signal is invalidated, the pixel capacitance and the source drive line are disconnected, and the pixel potential is held by capacitive coupling with the VCOM electrode (fourth state).

  The superiority of the display device 100 according to the embodiment of the present invention over the conventional display device 10 is in the second state. The second state in the prior art increases the driving load and reduces the charge sharing effect. However, in the display device 100 according to the embodiment of the present invention, the pixel capacitance and the VCOM electrode are short-circuited in the pixel by the second switching element TR2 and have already transitioned to the VCOM potential in the first state. The second switching elements TR2 of all the current row pixels act as short-circuit points. That is, in the display device 100, the impedance between the VCOM electrode and the source drive line is lowered.

  Therefore, in the display device 100, the second charge sharing (VCOM electrode-source drive line charge sharing) is effectively performed, and the time required for charge sharing is shortened.

  Here, by shortening the charge sharing period, the display device 100 can take a longer driving time (fourth state) for each driver. Further, if the fourth state can be made long, the constant currents of the buffers and amplifiers of the source driver 106 and the VCOM driver 108 can be lowered to suppress the driving capability. Therefore, the display device 100 can realize further low power consumption driving.

  Note that Timing-C in FIG. 13 is configured so that both the CSE signal and the GE signal are once invalidated before the transition to the fourth state, so that the source is driven by the driver before the pixel writing period after the charge sharing period. It is the drive which performs drive line charge ahead. Therefore, even when driving with Timing-C in FIG. 13, the display device 100 can reduce power consumption.

(2) Second Driving Method Next, a driving method when the display device 100 includes the gate driver 104 illustrated in FIG. 11 will be described.

  FIG. 16 is an explanatory diagram showing waveforms relating to operations related to charge sharing in the display device 100 according to the embodiment of the present invention. Here, “Timing-A” shown in FIG. 16 performs charge sharing (first charge sharing) in the pixel in advance in the scanning row n−1 immediately before the current row n, An example in which low impedance charge sharing (third charge sharing) is performed in row n of FIG. Similarly to Timing-A, “Timing-B” performs charge sharing in the pixel in advance in scanning row n−1, and after performing low impedance charge sharing in current row n, An example in which pixel writing is performed and completed is shown.

  First, an outline of operations related to charge sharing in the display device 100 will be described with reference to FIG.

(2-0) Initial State Immediately before the scanning of the gate driver 104 makes a transition to the horizontal period of the scanning row n-1 immediately before the current row and the current row n, the gate drive control signal GE is invalid and the charge share The ring control signal GS _PX is invalid, and the gate drive line (GL [n]) and the charge sharing drive line (CS [n]) are invalid. That is, the initial state is a state where both the first switching element TR1 and the second switching element TR2 in the pixel (n, m) are in an open state.

(2-1) Timing-A
FIG. 17 is an explanatory diagram showing a waveform related to an operation related to charge sharing in the display device 100 according to the embodiment of the present invention, and shows an operation waveform related to Timing-A. A driving method in Timing-A will be described with reference to FIGS.

  After the horizontal period transitions to the scanning row n−1 immediately before the current row, the CSE signal is first validated. At this time, the charge sharing drive line (CS [n]) of the current row n becomes effective. Since the gate drive line (GL [n]) in the current row n is in an invalid state, the switching element TR2 of each pixel in the current row is turned on, and both ends of the pixel capacitance are short-circuited to the VCOM electrode. At this time, since the switching element TR1 is open, the source drive line and the pixel capacitor are separated. (First state).

  The CSE signal is invalidated, the first charge sharing (VCOM electrode-pixel capacitance charge sharing) is terminated, and the state is maintained until the current row is scanned (second state).

  After the horizontal period transitions to the current row n, the CSE signal is made valid again, the second charge sharing (VCOM electrode-source drive line charge sharing), and the first charge sharing (VCOM electrode-pixel capacitance). Inter-charge sharing). Since the CSE signal is effective, the VCOM electrode and the VCOM driver 108 are disconnected by the first switching unit SW1, and the source drive line is short-circuited with the VCOM electrode by the switch SW2 [m] configuring the second switching unit 112. In addition, the switching element TR2 of each pixel in the current row is turned on, and both ends of the pixel capacitor are short-circuited to the VCOM electrode (third state).

  The overlap period with the CSE signal is generated by enabling the GE signal simultaneously with the third state or after the third state. At this time, since the switching element TR2 of each pixel in the current row is in a conductive state and the switching element TR1 is in a conductive state, a path for short-circuiting the VCOM electrode-source drive line is formed in each pixel. The above means that the impedance of the short-circuit point decreases in the second charge sharing (VCOM electrode-source drive line charge sharing), and since the time constant decreases, the charge neutralization rate increases (fourth). State).

  The CSE signal is invalidated and charge sharing ends. At this time, the source drive line is electrically connected to the VCOM driver output by the switch SW2 [m] constituting the second switching unit 112, and the VCOM electrode is electrically connected to the VCOM driver 108 by the first switching unit SW1. Driven by. Further, since the GE signal is valid, pixel writing is performed. At this time, the switching element TR1 of each pixel in the current row is electrically connected to each source drive line, and the potential difference from the VCOM electrode potential is charged in the pixel capacitance. Further, since the switching element TR2 is in the open state, it does not affect the charging operation (fifth state).

  After the charging of a desired potential (gradation) is completed by the pixel writing operation, the display device 100 invalidates the GE signal and ends the pixel writing state. At this time, the switching element TR1 of each pixel in the current row is opened, and the pixel capacitance holds the pixel potential in a state of capacitive coupling with the VCOM electrode (sixth state).

  In Timing-A shown in FIG. 16, the display device 100 operates as described above, for example.

(2-2) Timing-B
The display device 100 performs the operations from the first state to the fourth state as in Timing-A.

  Thereafter, the display device 100 shifts to the third state and the fourth state of Timing-A according to the first driving method.

  In Timing-C, the display device 100 operates as described above, for example.

  The display device 100 using the second driving method operates as described above, for example. When the display device 100 includes the gate driver 104 having the circuit configuration illustrated in FIG. 11, the drive timing is as illustrated in FIG. 16, and the pixel capacitance can be charge shared in advance. Here, the purpose of charge sharing of the pixels in advance is to shorten the charge sharing period.

  When writing the current row, the charge sharing drive line of the current row pixel is driven in the previous horizontal period, and charge sharing of the current row is performed. At this time, although the CSE signal and the GE signal overlap, only the first charge sharing (charge sharing between the VCOM electrode and the pixel capacitor) is performed because the gate drive line in the current row is not driven. As described above, at the timing of transition to the horizontal period of the current row, the pixels of the current row have already transitioned to the VCOM electrode potential. Then, after the transition to the horizontal period of the current row, the charge sharing drive line of the current row is driven again. In the current row, an overlap period of the CSE signal and the GE signal is generated, so that the gate drive line is also driven at the same time. Since the above state corresponds to the second state described above, the impedance at the short-circuit point during charge sharing is low.

  Therefore, since the time required for charge sharing is shortened in the display device 100, the constant current of the buffers and amplifiers of the source driver 106 and the VCOM driver 108 is lowered as in the case of using the first driving method. Since the capability can be suppressed, further low power consumption driving can be realized.

  As described above, the display device 100 according to the embodiment of the present invention has a circuit configuration that further reduces the impedance of the short-circuit point, and drives to shorten the time required for charge sharing while increasing the reuse rate of unnecessary charges. Use the method.

  Here, the display device 100 can charge share the pixel capacitance potential on a pixel basis (first charge sharing). Therefore, for example, when only the first charge sharing is performed, the display device 100 can be driven with lower power consumption than the configuration without the charge sharing mechanism.

  Further, the display device 100 performs the first charge sharing (VCOM electrode-pixel capacitor charge sharing) and the second charge sharing (VCOM electrode-source drive line charge sharing) independently or simultaneously. By doing so, the charge sharing effect can be improved as compared with the case of using the conventional technique for performing charge sharing between the VCOM electrode and the source drive line.

  Further, the display device 100 reduces the impedance of the short circuit point by overlapping the CSE signal and the GE signal. As described above, the display device 100 can shorten the time required for charge sharing while increasing the reuse rate of unnecessary charges. Further, it is possible to secure a long pixel writing period by the driver by shortening the charge sharing period. That is, by making the pixel writing period longer, the source driver 106 can be driven with a lower driving capability of the source driver than when the conventional technique is used. The constant current of the amplifier can be kept low. Therefore, the display device 100 can be driven with lower power consumption than in the case of using the conventional technique.

  In addition, when the display device 100 includes the gate driver 104 having the circuit configuration illustrated in FIG. 11, the charge sharing is performed in advance within the horizontal period immediately before the pixel capacitor, and thus the time required for charge sharing. Is subdivided, and when considered in one horizontal period, the time required for charge sharing can be further shortened while increasing the reuse rate of unnecessary charges. Therefore, even when the display device 100 includes the gate driver 104 having the circuit configuration illustrated in FIG. 11, the display device 100 can be driven with lower power consumption than in the case of using the conventional technique.

  Therefore, the display device 100 can reduce power consumption in the liquid crystal display device.

  Furthermore, since the display device 100 is driven using the same drive control lines as in the prior art, it is not necessary to provide a new control line in the timing control unit 110 (driver IC). Therefore, when an external mechanism such as a driver IC driving the CSE signal is driven, it is possible to suppress an increase in cost due to an increase in terminals. Further, it is possible to use a driver IC that has been used in the past as it is, which can greatly reduce the development cost and is excellent in terms of component management.

  As mentioned above, although the display apparatus 100 was mentioned and demonstrated as embodiment of this invention, embodiment of this invention is not restricted to this form. Embodiments of the present invention include, for example, portable communication devices such as mobile phones, computers such as notebook PCs and PCs, imaging devices such as digital cameras (digital still cameras / digital video cameras), game machines, and television receivers. The present invention can be applied to various devices such as a display device in which an active matrix liquid crystal display is used as a display device.

(Program according to an embodiment of the present invention)
Reduction of power consumption in the liquid crystal display device by a program for causing the computer to function as the display device according to the embodiment of the present invention (for example, a program for realizing processing related to the driving method according to the embodiment of the present invention) Can be achieved.

(Recording medium recording a program according to an embodiment of the present invention)
In the above description, it has been shown that a program (computer program) for causing a computer to function as the display device according to the embodiment of the present invention is provided. However, the embodiment of the present invention further stores the program. The recorded recording medium can also be provided.

  As mentioned above, although preferred embodiment of this invention was described referring an accompanying drawing, it cannot be overemphasized that this invention is not limited to the example which concerns. It will be apparent to those skilled in the art that various changes and modifications can be made within the scope of the claims, and these are naturally within the technical scope of the present invention. Understood.

10, 100 Display device 12, 102 Display panel 14, 104 Gate driver 14
16, 106 Source driver 16
18, 108 VCOM driver 20, 110 Timing control unit 22, 112 Second switching unit SW1 First switching unit

Claims (10)

A display unit having signal lines and scanning lines arranged in a matrix, and pixel circuits arranged in correspondence with intersections of the signal lines and the scanning lines,
A scanning line driver for applying a scanning signal to the scanning line;
A signal line driver for applying a data signal to the signal line;
A counter electrode driving unit for driving the counter electrode;
With
The pixel circuit includes:
A first switching element having a first terminal connected to the signal line and selectively conducting according to a logic level of the scanning signal applied to the scanning line connected to a gate terminal;
A liquid crystal capacitor formed between a pixel electrode connected to the second terminal of the first switching element and the counter electrode;
A storage capacitor formed between the pixel electrode and the counter electrode;
A second switching element that conducts in accordance with a logic level of a first charge sharing drive signal applied to a charge sharing drive line connected to a gate terminal and selectively short-circuits both ends of the storage capacitor to the counter electrode; When,
A timing control unit for controlling the driving timing of each of the scanning line driving unit, the signal line driving unit, and the counter electrode driving unit;
A first switching unit for selectively conducting the counter electrode driving unit and the counter electrode according to a logic level of a second charge sharing driving signal;
The connection between the signal line that constitutes the display unit and the signal line driving unit, or the connection between the signal line that constitutes the display unit and the counter electrode, is a logical level of the second charge sharing drive signal. And a second switching unit that selectively short-circuits the signal line constituting the display unit to the counter electrode,
With
The scanning line driving unit starts first charge sharing in which both ends of the storage capacitor are short-circuited to the counter electrode and second charge sharing in which the signal line constituting the display unit is short-circuited to the counter electrode. After that, the display device is characterized in that the first switching element constituting the pixel circuit is made conductive and the signal line is short-circuited to the counter electrode.   The display device according to claim 1, wherein the charge sharing drive line is wired in parallel with the scan line.   The scanning line driving unit generates the first charge sharing driving signal using shift data used for generating the scanning signal, and uses the generated first charge sharing driving signal to the charge sharing driving line. The display device according to claim 2, which is applied.   The display device according to claim 1, wherein the second charge sharing drive signal is generated by the timing control unit.   The scanning line driving unit generates the first charge sharing driving signal using shift data used for generating the scanning signal and the second charge sharing driving signal, and generates the generated first charge sharing. The display device according to claim 4, wherein a drive signal is applied to the charge sharing drive line.   The display device according to claim 4, wherein the first charge sharing and the second charge sharing are performed simultaneously.   6. The display device according to claim 4, wherein the first charge sharing and the second charge sharing are performed separately. 6.   The display device according to claim 7, wherein the second charge sharing is performed after the first charge sharing is started.   A first charge sharing circuit that short-circuits both ends of the storage capacitor to the counter electrode, a second charge sharing circuit that short-circuits the signal line forming the display unit to the counter electrode, and the pixel circuit. The third charge sharing that short-circuits the signal line to the counter electrode by conducting the first switching element and the second switching element is the scanning signal generated by the scanning line driving unit, The display device according to claim 4, wherein the display device is controlled by the second charge sharing drive signal generated by the timing control unit. After the first charge sharing for short-circuiting both ends of the storage capacitor to the counter electrode is started, the first switching element constituting the pixel circuit is turned on, whereby the signal line is connected to the counter electrode. A third charge sharing is done to short circuit,
After the conduction of the first switching element and the second switching element constituting the pixel circuit is cut off, pixel writing is performed in which the first switching element is turned on and the data signal is applied to the pixel circuit. The display device according to claim 1, wherein the display device is a display device.

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