JP2004118183A - Liquid crystal display device and method for driving liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display device capable of obtaining a picture with small luminance unevenness as a liquid crystal display device having an analog buffer circuit. <P>SOLUTION: A source signal line driving circuit has a plurality of analog buffer circuits. The connection of the analog buffer circuits and source signal lines are changed for each period, and output variance among the analog buffer circuits is leveled to obtain a uniform picture. <P>COPYRIGHT: (C)2004,JPO

Description

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device using a thin film transistor (TFT) formed on a transparent substrate such as glass or plastic and a driving method thereof. Further, the present invention relates to an electronic device using the liquid crystal display device.

携 帯 In recent years, mobile phones have become widespread with the progress of communication technology. In the future, transmission of moving images and more information transmission are expected. On the other hand, as for personal computers, mobile-friendly products have been produced due to their light weight. A large number of information terminals called PDAs, which began with electronic organizers, have been produced and are becoming popular. Also, due to the development of display devices, most of these portable information devices are equipped with flat panel displays.

Recent technologies are moving toward using active matrix display devices as the display devices to be used. In the active matrix type display device, a TFT is arranged for each pixel, and a screen is controlled by the TFT. Such an active matrix display device has advantages such as higher performance, higher image quality, and compatibility with moving images as compared with a passive matrix display device. Therefore, it is considered that the mainstream of the liquid crystal display device shifts from passive to active.

In addition, among active matrix display devices, in recent years, a display device using low-temperature polysilicon has been commercialized. In low-temperature polysilicon, not only pixels but also a driving circuit can be integrally formed around a pixel portion, so that a display device can be downsized and a high definition can be achieved. .

The operation of the pixel portion of the active matrix type liquid crystal display device will be described below. FIG. 3 shows an example of the configuration of an active matrix liquid crystal display device. One pixel 302 includes a source signal line S1, a gate signal line G1, a capacitor line C1, a pixel TFT 303, and a storage capacitor 304. However, the capacitance line is not necessarily required as long as it can be used as another wiring. The gate electrode of the pixel TFT 303 is connected to the gate signal line G1, one of the drain region or the source region of the pixel TFT 303 is connected to the source signal line S1, and the other is connected to the storage capacitor 304 and the pixel electrode 305. ing.

The gate signal lines are sequentially selected in the line cycle. When the pixel TFT is Nch, it is active when the gate signal line is Hi, and the pixel TFT is turned on. When the pixel TFT is turned on, the potential of the source signal line is written to the storage capacitor and the liquid crystal. In the next line period, the adjacent gate signal line becomes active, and the potential of the source signal line is written to the storage capacitor and the liquid crystal in the same manner.

Next, the operation of the source line driving circuit will be described. FIG. 2 shows an example of a conventional source signal line driving circuit. FIG. 2 is an example of a source signal line drive circuit of an analog dot sequential drive. In this example, the circuit includes a shift register 201, a NAND circuit 207, a buffer circuit 208, and an analog switch 209. First, a source start pulse SSP is input to the first stage of the shift register via the switch 206. The switch 206 determines the scanning direction of the shift register. When SL / R is Lo, scanning is performed from left to right in FIG. 2, and when SL / R is Hi, scanning is performed from right to left. Each stage of the shift register is constituted by a DFF 202. The DFF 202 is constituted by clocked inverters 203, 204 and an inverter 205, and shifts a pulse each time the clock pulses CL and CLb are input.

The output of the shift register is input to the buffer circuit 208 via the NAND circuit 207. The analog switches 209 to 212 are turned on by the output of the buffer circuit, and the video signals are sampled on the source signal lines S1 to S4.

When the size of the liquid crystal panel is medium or small, the panel can be operated by the dot-sequential driving as described above. However, in a large panel, the wiring capacitance of the source signal line is about 100 pF, , The writing time of the source signal line is short in the dot sequential driving, and writing cannot be performed. Therefore, in a large-sized panel, line-sequential driving is necessary in which data is once stored in a memory inside the source signal line driving circuit, and writing is performed on the source signal line using the next one line period.

(4) When such line-sequential driving is performed, an analog buffer circuit is required after the memory. FIG. 4 shows an example of a source signal line driving circuit corresponding to line sequential. The operations of the analog switches 401 to 404 are the same as those of the source signal line driving circuit corresponding to the dot sequence shown in FIG. Compared to FIG. 2, the analog switches 401 to 404 are driven not by the source signal lines but by the capacitors 405 to 408 as analog memories. When data for one line is sequentially stored in the analog memory, the signals of TRN and TRNb become active during the next retrace period, and the analog switches 409 to 412 are turned on. As a result, the data in the analog memories 405 to 408 is transferred to the analog memory capacities 413 to 416.

{Before the next sampling, the analog switches 409 to 412 are turned off before the analog switches 401 to 404 are turned on. The data in the analog memories 413 to 416 are output to the source signal lines S1 to S4 via the analog buffer circuits 417 to 420. Since the data in the analog memories 413 to 416 is held for one line period, the analog buffer circuits 417 to 420 can charge the source line over one line period. In this manner, the large-sized panel has an analog memory and an analog buffer circuit, so that line-sequential driving is possible.

However, when an analog buffer circuit is used using TFTs, the variation of the analog buffer circuit poses a problem. Even if the analog buffer circuit has a variation, even if a video signal of the same gradation is input, the variation occurs in the output. As a result, the vertical stripes are generated on the screen, and the image quality is extremely deteriorated. appear.

When a liquid crystal display device is manufactured using low-temperature polysilicon, a driver circuit is integrally formed. However, compared to a case where a driver circuit is manufactured using single crystal silicon, variation in transistors is large. There are drawbacks. It is said that this is due to variations in crystallization and damage due to static electricity during the process. In the case where a driver circuit is formed using such a transistor, a portion that performs an analog operation from a logic portion, particularly an analog buffer circuit, has a significant variation.

4 Consider a difference voltage between the output voltage of each analog buffer circuit and the average value of the outputs of a plurality of analog buffer circuits in the conventional source signal line driving circuit shown in FIG. The difference voltage between the average output value and the analog buffer circuit output A is ΔVA, and similarly, the difference voltages between the average output value and the analog buffer circuit outputs B, C, and D are ΔVB, ΔVC, and ΔVD. Further, assuming that ΔVA is +100 mV, ΔVB is -100 mV, ΔVC is −50 mV, and ΔVD is +30 mV, the difference between the source signal lines S2 and S3 is 50 mV, but the difference between the source signal lines S1 and S2 is 50 mV. Is 200 mV, and the gray level difference is recognized by human eyes.

In order to solve the above-mentioned problem, in the present invention, the switch is switched between the analog buffer circuit and the source signal line, and the output is switched. By performing such processing, variations in the output of the analog buffer circuit are averaged over time, and display unevenness can be reduced.

Hereinafter, the configuration of the present invention will be described.

The present invention relates to a liquid crystal display device having a plurality of source signal lines, a plurality of gate signal lines, a plurality of pixels, and a source signal line driving circuit for driving the signal lines on an insulating substrate, wherein the source signal line driving circuit Has a plurality of analog buffer circuits, and the source signal lines are periodically connected to different analog buffer circuits.

The present invention relates to a liquid crystal display device having a plurality of source signal lines, a plurality of gate signal lines, a plurality of pixels, and a source signal line driving circuit for driving the signal lines on an insulating substrate, wherein the source signal line driving circuit Has a plurality of analog buffer circuits, and the source signal lines are connected to different analog buffer circuits at random in time.

According to the present invention, a plurality of pixels, a plurality of source signal lines, a plurality of gate signal lines, and a source signal line driving circuit are arranged on an insulating substrate, and the source signal line driving circuit drives the source signal lines. (N is a natural number that satisfies 2 ≦ n) number of periods are periodically repeated in a liquid crystal display device having an analog buffer circuit for , M-th (m is a natural number satisfying 1 ≦ m) source signal lines are connected to the (m + r−1) -th analog buffer.

According to the present invention, a plurality of pixels, a plurality of source signal lines, a plurality of gate signal lines, and a source signal line driving circuit are arranged on an insulating substrate, and the source signal line driving circuit drives the source signal lines. (N is a natural number that satisfies 2 ≦ n) periods are randomly repeated in time, and the r-th (r is a natural number that satisfies 1 ≦ r ≦ n) In the period, the m-th (m is a natural number satisfying 1 ≦ m) signal line is connected to the (m + r−1) -th analog buffer.

(5) In the configuration of the present invention, the analog buffer circuit is a source follower or a voltage follower.

A method for driving a liquid crystal display device according to the present invention is directed to a liquid crystal display device including a plurality of source signal lines, a plurality of gate signal lines, a plurality of pixels, and a source signal line driving circuit for driving the signal lines on an insulating substrate. In the driving method, the source signal line driving circuit includes a plurality of analog buffer circuits, and the source signal lines are periodically driven by different analog buffer circuits.

A method for driving a liquid crystal display device according to the present invention is directed to a liquid crystal display device including a plurality of source signal lines, a plurality of gate signal lines, a plurality of pixels, and a source signal line driving circuit for driving the signal lines on an insulating substrate. In the driving method, the source signal line driving circuit has a plurality of analog buffer circuits, and the source signal lines are driven by different analog buffer circuits at random in time.

A method for driving a liquid crystal display device according to the present invention includes disposing a plurality of pixels, a plurality of source signal lines, a plurality of gate signal lines, and a source signal line driving circuit on an insulating substrate, wherein the source signal line driving circuit is In the method for driving a liquid crystal display device having an analog buffer circuit for driving the source signal line, n (n is a natural number satisfying 2 ≦ n) periods are periodically repeated, and an r-th period (r is 1 ≦ In the period of r ≦ n, a m-th (m is a natural number satisfying 1 ≦ m) signal line is driven by an m + r−1 analog buffer.

A method for driving a liquid crystal display device according to the present invention includes disposing a plurality of pixels, a plurality of source signal lines, a plurality of gate signal lines, and a source signal line driving circuit on an insulating substrate, wherein the source signal line driving circuit is In the method for driving a liquid crystal display device having an analog buffer circuit for driving the source signal line, n (n is a natural number satisfying 2 ≦ n) periods are randomly repeated in time, and an r (r is In a period of 1 ≦ r ≦ n, a m-th (m is a natural number that satisfies 1 ≦ m) signal line is driven by an (m + r−1) -th analog buffer.

In the above-described method for driving a liquid crystal display device according to the present invention, the analog buffer circuit is a source follower or a voltage follower.

According to the above, it is possible to prevent the occurrence of vertical stripes on the screen during display even if the analog buffer circuit formed on the insulating substrate has output variations.

(4) In the conventional liquid crystal display device, when an analog buffer circuit is used for an output, there is a problem that vertical stripes are generated due to the variation and the image quality is deteriorated.

According to the present invention, the output variation can be reduced by temporally switching the output of the analog buffer circuit and averaging the output voltage variation.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a liquid crystal display device of the present invention. The shift register and the like are the same as those described in the conventional example. The difference from the related art is that switches 138 to 144 are provided between the analog buffer circuits 131 to 137 and the source signal lines S1 to S7. The operation of the present embodiment will be described below. Although the switches 138 to 144 are described taking a four-contact switch as an example, the present invention is not limited to four contacts, and the present invention can be realized even if the number of contacts is different.

で は In the present invention, the connection contents of the switches 138 to 144 are switched. Here, the cycle is described as one frame, but the present invention is not limited to this. The following is a description. First, in the first frame, the switches 138 to 144 are in the connection state of “1”, and in this case, the output A of the analog buffer circuit 131 is connected to the source signal line S1. Similarly, outputs B, C, D, E, F, and G of the analog buffer circuits 132 to 137 are connected to source signal lines S2, S3, S4, S5, S6, and S7.

Next, in the second frame, the switches 138 to 144 are in the connection state of “2”, and the output B of the analog buffer circuit 132 is connected to the source signal line S1. Similarly, outputs C, D, E, F, and G of the analog buffer circuits 133 to 137 are connected to source signal lines S2, S3, S4, S5, and S6, respectively. Next, in the third frame, the switches 138 to 144 are in the connection state of “3”, and the output C of the analog buffer circuit 133 is connected to the source signal line S1. Similarly, outputs D, E, F, and G of the analog buffer circuits 134 to 137 are connected to source signal lines S2, S3, S4, and S5, respectively.

Next, in the fourth frame, the switches 138 to 144 are in the connection state of “4”, and the output D of the analog buffer circuit 134 is connected to the source signal line S1. Similarly, outputs E, F, and G of the analog buffer circuits 135 to 137 are connected to source signal lines S2, S3, and S4, respectively.

Next, in the fifth frame, the switches 138 to 144 are again in the connection state of “1”, and the output A of the analog buffer circuit 131 is connected to the source signal line S1. Similarly, the outputs B, C, D, E, F, and G of the analog buffer circuits 132 to 137 are connected to source signal lines S2, S3, S4, S5, S6, and S7, respectively. As described above, the switches 138 to 144 repeat the connection change at a cycle of four frames.

(4) Since the switch has four contacts, it changes in a four-frame cycle. However, as described above, the cycle can be changed by changing the number of contacts. Also, there is no need to stick to each frame. What is necessary is just a period which can be averaged visually. FIG. 10 shows the output of the analog buffer circuit corresponding to each source signal line.

を Consider a difference voltage between the output voltage of each analog buffer circuit and the average value of the outputs of a plurality of analog buffer circuits as in the conventional example. Assuming that the difference voltage between the output average value and the analog buffer circuit output A is ΔVA, and similarly the difference voltage between the output average value and the analog buffer circuit outputs B, C, and D is ΔVB, ΔVC, ΔVD, these are noticed to human eyes. Are averaged, the output potential difference between the source signal lines S1, S2, S3, and S4 is (ΔVA + ΔVB + ΔVC + ΔVD) / 4.

Assuming that ΔVA is +100 mV, ΔVB is −100 mV, ΔVC is −50 mV, and ΔVD is +30 mV, the voltages of the source signal lines S1 to S4 are −5 mV, which is a problem in the conventional example. Such a problem that a potential difference of 200 mV is generated between adjacent portions and vertical stripes are conspicuous can be prevented.

In the above, the switch has four contacts and the repetition period is four periods. However, the period is not limited to four, and n (n is a natural number satisfying 2 ≦ n) periods are set, and the r-th period (r is 1 ≦ In the period of r ≦ n, which is a natural number, the m-th (m is a natural number that satisfies 1 ≦ m) source signal line is connected to the (m + r−1) -th analog buffer. Obtainable. Further, by driving the m-th source signal line with the (m + r-1) -th analog buffer, a desired effect can be obtained.

FIG. 7 shows a first embodiment. FIG. 7 is a specific circuit example of the switch 123 shown in FIG. The switches are composed of TFTs 701 to 708, and are controlled by control lines 1 to 4b connected to the gate terminals of the respective TFTs. FIG. 8 shows a timing chart of the control lines 1 to 4b. By the control signals as shown in FIG. 8, D in FIG. 1 is a source signal line S4 in the first frame, a source signal line S3 in the second frame, a source signal line S2 in the third frame, and a source signal line S1 in the fourth frame. Connected to. Although the circuit diagram shown in FIG. 7 has a CMOS configuration, it may have an NMOS or PMOS configuration. In that case, the number of control lines can be halved.

FIG. 5 shows an operational amplifier circuit as an example of the analog buffer circuit. In this type of analog buffer circuit, the variation in output voltage is determined by the variation in characteristics of the TFTs 503 and 504 constituting the differential circuit and the variation in the TFTs 501 and 502 constituting the current mirror circuit. However, if the adjacent variation of the TFTs in the set is suppressed, there is no problem even if the variation of the entire panel is large, so this is a circuit often used in an integrated circuit.

で は In this example, the differential circuit is created by Nch and the current mirror circuit is created by Pch, but the present invention is not limited to this. The reverse is also acceptable. Also, the circuit type is not limited to such a circuit connection, and any circuit that satisfies the function as an operational amplifier can be used.

FIG. 6 shows an example of a source follower circuit as an example of the analog buffer circuit. The source follower circuit includes a buffer TFT 601 and a constant current source 602. In this example, the buffer TFT is constituted by Nch, but may be constituted by Pch. In the source follower circuit, when Nch is used, the output potential is reduced by Vgs of the TFT with respect to the input potential, or when Pch is used, the output potential is increased by Vgs of the TFT with respect to the input potential. On the other hand, however, there is an advantage that the configuration is simple and realization is possible without using CMOS. When a unipolar process is employed to reduce the number of TFT steps, it is difficult to configure an operational amplifier type analog buffer circuit, and thus a source follower is used.

FIG. 11 shows an example in which a circuit for switching a video signal input to a source signal line driving circuit is disposed outside the source signal line driving circuit in order to use the circuit of the present invention. If the switching of the source signal line of the present invention is performed only between the analog switch and the source signal line, the output variation is reduced, but the output of the analog buffer is output to the four source signal lines. No image is obtained. Therefore, a normal image can be created by exchanging the signals in advance before being input to the analog buffer circuit and exchanging the signals again with the switches after the analog buffer.

考 え る Consider a case where switching is performed for each frame as in the embodiment of the present invention. First, in the first frame, the output of the video circuit 1150 is connected to the video signal line 1145 with the switch 1154 connected to “1”. The signal of the video signal line 1145 is input to the analog buffer circuit 1131 through the switch 1103 and the switch 1117. In the first frame, the switch 1138 is connected to “1”, so that the output of the analog buffer circuit 1131 is connected to the source signal line S1. Similarly, the outputs of the video circuits 1151, 1152, 1153 are connected to source signal lines S2, S3, S4, respectively.

Next, in the second frame, the output of the video circuit 1150 is connected to the video signal line 1146 with the switch 1154 connected to “2”. The signal of the video signal line 1146 is input to the analog buffer circuit 1132 through the switch 1104 and the switch 1118. In the second frame, the switch 1138 is connected to “2”, so that the output of the analog buffer circuit 1132 is connected to the source signal line S1. Similarly, the outputs of the video circuits 1151, 1152, 1153 are connected to source signal lines S2, S3, S4, respectively.

Next, in the third frame, the output of the video circuit 1150 is connected to the video signal line 1147 with the switch 1154 connected to “3”. The signal of the video signal line 1147 is input to the analog buffer circuit 1133 via the switch 1105 and the switch 1119. In the third frame, the switch 1138 is connected to “3”, so that the output of the analog buffer circuit 1133 is connected to the source signal line S1. Similarly, the outputs of the video circuits 1151, 1152, 1153 are connected to source signal lines S2, S3, S4, respectively.

Next, in the fourth frame, the output of the video circuit 1150 is connected to the video signal line 1148 with the switch 1154 connected to “4”. The signal of the video signal line 1148 is input to the analog buffer circuit 1134 through the switch 1106 and the switch 1120. In the fourth frame, the switch 1138 is connected to “4”, so that the output of the analog buffer circuit 1134 is connected to the source signal line S1. Similarly, the outputs of the video circuits 1151, 1152, 1153 are connected to source signal lines S2, S3, S4, respectively.

Thus, in any frame, the output of the video circuit 1150 is connected to the source signal line S1. This makes it possible to replace the analog buffer circuit to be used in the normal state of the image and for each frame. Similarly, the outputs of the video circuits 1151, 1152, and 1153 are connected to the source signal lines S2, S3, and S4, respectively, in any frame.

Such a circuit may be formed by providing another substrate (printed substrate, flexible substrate) outside the TFT substrate, by attaching an LSI chip on the TFT substrate, or by using a TFT to form the same circuit. It may be formed on a substrate.

In this embodiment, the switching circuit is built in the source signal line driving circuit. In this embodiment, an example in which a switching circuit before an analog buffer circuit is provided between the switching circuit and a video signal line will be described with reference to FIGS.

考 え る Consider a case where switching is performed for each frame as in the embodiment of the present invention. First, in the first frame, the output of the video signal line 1252 passes through the switch 1203, the switch 1210 is connected to “1”, and the output is connected to the analog memory 1217 and the switch 1224. The signal is input to the analog memory 1231 and the analog buffer circuit 1238 via the switch 1224. In the first frame, the switch 1245 is connected to “1”, so that the output of the analog buffer circuit 1238 is connected to the source signal line S1. Similarly, the outputs of the video signal lines 1253, 1254, 1255 are connected to the source signal lines S2, S3, S4, respectively.

Next, in the second frame, after the output of the video signal line 1252 passes through the switch 1203, the switch 1210 is connected to “2”, and is connected to the analog memory 1218 and the switch 1225. The signal is input to the analog memory 1232 and the analog buffer circuit 1239 via the switch 1225. In the second frame, the switch 1245 is connected to “2”, so that the output of the analog buffer circuit 1239 is connected to the source signal line S1. Similarly, the outputs of the video signal lines 1253, 1254, 1255 are connected to the source signal lines S2, S3, S4, respectively.

Next, in the third frame, after the output of the video signal line 1252 passes through the switch 1203, the switch 1210 is connected to “3”, and is connected to the analog memory 1219 and the switch 1226. The signal is input to the analog memory 1233 and the analog buffer circuit 1240 via the switch 1226. In the third frame, the switch 1245 is connected to “3”, so that the output of the analog buffer circuit 1240 is connected to the source signal line S1. Similarly, the outputs of the video signal lines 1253, 1254, 1255 are connected to the source signal lines S2, S3, S4, respectively.

Next, in the fourth frame, after the output of the video signal line 1252 passes through the switch 1203, the switch 1210 is connected to “4”, and is connected to the analog memory 1220 and the switch 1227. The signal is input to the analog memory 1234 and the analog buffer circuit 1241 via the switch 1227. In the fourth frame, the switch 1245 is connected to “4”, so that the output of the analog buffer circuit 1241 is connected to the source signal line S1. Similarly, the outputs of the video signal lines 1253, 1254, 1255 are connected to the source signal lines S2, S3, S4, respectively.

In this manner, in any frame, the output of the video signal line 1252 is connected to the source signal line S1. This makes it possible to replace the analog buffer circuit to be used in the normal state of the image and for each frame. Similarly, the outputs of the video signal lines 1253, 1254, and 1255 are connected to the source signal lines S2, S3, and S4, respectively, in any frame.

In the embodiment of the present invention, and in the first, fourth, and fifth embodiments, the switching of the switches is periodically performed in a predetermined order, but the switching may not be fixed. That is, in the embodiment, the source signal line S1 is connected to the analog buffer outputs A, B, C, and D in the first four frames, and is connected to A, B, C, and D in the next four frames. Was repeatedly repeated. However, the order of appearance may be random instead of fixed, such as A, B, C, D in the first four frames, but C, B, D, A in the next four frames. . In this case, the circuits shown in Embodiments 1 to 5 can be freely combined.

Note that the display device of the present invention is not limited to the configuration of the source signal line driving circuit of the present embodiment, and a known source signal line driving circuit can be used freely.

In this embodiment, a configuration example of a gate signal line driver circuit of a display device of the present invention will be described.

The gate signal line driving circuit includes a shift register, a scanning direction switching circuit, and the like. Although not shown here, a level shifter, a buffer, and the like may be appropriately provided.

(4) A start pulse GSP, a clock pulse GCL, and the like are input to the shift register, and a gate signal line selection signal is output. The structure of the gate signal line driver circuit is described with reference to FIG.

The shift register 901 includes clocked inverters 902 and 903, an inverter 904, and a NAND 907. A start pulse GSP is input to the shift register 901, and the clocked inverters 902 and 903 are turned on and off by a clock pulse GCL and an inverted clock pulse GCLb which is a signal whose polarity is inverted, The sampling pulses are output in order from the NAND 907.

The scanning direction switching circuit includes a switch 905 and a switch 906, and functions to switch the operation direction of the shift register to the left or right in the drawing. In FIG. 9, when the scanning direction switching signal U / D corresponds to the Lo signal, the shift register outputs sampling pulses in order from left to right in the drawing. On the other hand, when the scanning direction switching signal U / D corresponds to the Hi signal, the sampling pulse is output sequentially from right to left in the drawing.

(4) The sampling pulse output from the shift register is input to the NOR 908, and is calculated with the enable signal ENB. This calculation is performed to prevent a situation in which adjacent gate signal lines are simultaneously selected due to the rounding of the sampling pulse. The signal output from the NOR 908 is output to the gate signal lines G1 to Gy via the buffers 909 and 910.

(4) The start pulse GSP, the clock pulse GCL, and the like input to the shifter register are input from an external timing controller.

Note that the display device of the present invention is not limited to the configuration of the gate signal line driving circuit of the present embodiment, and a gate signal line driving circuit having a known configuration can be used freely. This embodiment can be used in combination with another embodiment of the present invention.

FIG. 15 shows an embodiment of a digital input source signal line drive circuit. The output of the shift register 1501 is input to the latch circuit 1503 via the buffer circuit 1502. The latch circuit has a function of taking in and storing a digital video signal when the output of the buffer circuit becomes active. The shift register fetches a digital video signal as needed during one line period, and digital data for one line is stored. After storage of one line is completed, a latch pulse is input during a flyback period, and data of the latch circuit 1503 is taken into the latch circuit 1504.

Since the data of the latch circuit 1504 is held until the next retrace period, the data of the latch circuit 1504 is converted into an analog signal by the D / A converter 1505 during that time. An output of the D / A converter 1505 drives a source signal line via an analog buffer circuit 1506 and a switch 1513.

Here, the operation of the switch circuit 1513 is the same as that described in the embodiment, and the source signal line S1 is connected to the analog buffer circuit 1506 in the first frame, and the analog buffer circuit 1507 in the second frame. Are connected to the analog buffer circuit 1508 in the third frame, and are connected to the analog buffer circuit 1509 in the fourth frame. In this manner, as in the embodiment, the output variations of the analog buffer circuits of each source signal line are averaged, so that display unevenness can be reduced and image quality can be improved. This embodiment can be used in combination with another embodiment.

FIG. 16 shows a specific example of the latch circuit shown in the eighth embodiment. FIG. 16A shows a latch circuit using a clocked inverter, which is also used for a shift register of the above-described signal line driver circuit. FIG. 16B illustrates a combination of an inverter and an analog switch. FIG. 16C is a diagram in which one analog switch is deleted from FIG. 16B. Of the two inverter circuits, the drive capability of the inverter whose output is connected to the analog switch is smaller than the drive capability of the analog switch. It is designed so that the storage state can be changed by the operation of the analog switch. Any of the latch circuits may be used. Further, circuits other than those shown here may be used. This embodiment can be used in combination with another embodiment of the present invention.

FIG. 13 shows an example in which a shift register is formed using unipolar TFTs. FIG. 13 shows an example of Nch, but the unipolarity may be either Nch only or Pch only. By using a unipolar process, the number of masks can be reduced.

In FIG. 13, the start pulse is input to the scanning direction changeover switch 1302, and is input to the shift register 1301 via the switching TFT 1311. The shift register is a set-reset type shift register using a bootstrap. Hereinafter, the operation of the shift register 1301 will be described.

The start pulse is input to the gate of the TFT 1303 and the gate of the TFT 1306. When the TFT 1306 is turned on, the gate of the TFT 1304 becomes low and the TFT 1304 is turned off. Further, since the gate of the TFT 1310 is also low, the TFT 1310 is also turned off. Since the gate of the TFT 1303 rises to the power supply potential, the gate of the TFT 1309 first rises to the power supply -Vgs. Since the output 1 has an initial low potential, the TFT 1309 raises the source potential while charging the output 1 and the capacitor 1308. When the gate of the TFT 1309 rises to the power supply -Vgs, the TFT 1309 is still on. , Output 1 continues to rise. Since the gate of the TFT 1309 has no discharge path, it rises in accordance with the source, and keeps rising even if the power is exceeded.

(4) When the drain and the source of the TFT 1309 have the same potential, the current stops flowing to the output, and the potential of the TFT 1309 stops rising. Thus, the output 1 can output a high potential equal to the power supply potential. At this time, the potential of CLb is set to high. When CLb falls to low, the charge of the capacitor 1308 passes through the TFT 1309 to CLb, and the output 1 falls to low. The output 1 pulse is transmitted to the next stage shift register. The above is the operation of the circuit in FIG. This embodiment can be used in combination with another embodiment of the present invention.

FIG. 14 is a top view of the liquid crystal display device of the present invention. A pixel portion 1403, a source signal line driver circuit 1401, a gate signal line driver circuit 1402, an external input terminal 1404 to which an FPC terminal 1408 is attached, wirings 1407a and 1407b connecting the external input terminal to an input portion of each circuit are formed. The active matrix substrate and a counter substrate 1411 provided with a color filter and the like are attached to each other with a sealant 1410 interposed therebetween.

(4) A light-blocking layer 1405 is provided on the counter substrate side so as to overlap with the source signal line driver circuit 1401, and a light-blocking layer 1406 is formed on the counter substrate side so as to overlap with the gate signal line driver circuit 1402. In the color filter 1409 provided on the counter substrate side over the pixel portion 1403, a light-shielding layer and colored layers of red (R), green (G), and blue (B) are provided for each pixel. Have been. In actual display, a color display is formed by three colors of a red (R) coloring layer, a green (G) coloring layer, and a blue (B) coloring layer. It is optional.

Here, the color filter 1409 is provided on the opposite substrate in order to achieve colorization; however, there is no particular limitation. When an active matrix substrate is manufactured, a color filter may be formed on the active matrix substrate.

遮光 Further, a light-shielding layer is provided between adjacent pixels in the color filter, and blocks portions other than the display area from light. Further, here, the light-blocking layers 1405 and 1406 are provided also in a region covering the driving circuit; however, the region covering the driving circuit is covered with a cover when the liquid crystal display device is later incorporated as a display portion of an electronic device. A structure without a light-blocking layer may be employed. When manufacturing an active matrix substrate, a light-blocking layer may be formed over the active matrix substrate.

In addition, without providing the light-shielding layer, a colored layer constituting a color filter is appropriately arranged between the opposing substrate and the opposing electrode so as to shield light by a stacked layer of a plurality of layers, and a portion other than the display area (each pixel electrode And the drive circuit may be shielded from light.

液晶 Thus, a liquid crystal display device is completed. In this embodiment, a method for manufacturing a transmission type active matrix type liquid crystal display device is described. However, a reflection type active matrix type liquid crystal display device can be manufactured by a similar method. This embodiment can be used in combination with another embodiment of the present invention.

液晶 The liquid crystal display device manufactured as described above can constitute a liquid crystal module, and the liquid crystal display device can be used as a display portion of various electronic devices. Hereinafter, electronic devices in which a liquid crystal display device formed by using the present invention is incorporated as a display medium will be described.

Such electronic devices include a video camera, a digital camera, a goggle-type display (head-mounted display), a navigation system, a sound reproducing device (car audio, audio component, etc.), a notebook personal computer, a game device, a portable information terminal ( An image reproducing apparatus provided with a recording medium (specifically, a mobile computer, a mobile phone, a portable game machine or an electronic book, etc.) (specifically, a display capable of reproducing a recording medium such as a digital video disk (DVD) and displaying the image) Device equipped with a device). One example of them is shown in FIG.

FIG. 17A illustrates a display device, which includes a housing 2001, a support 2002, a display portion 2003, a speaker portion 2004, a video input terminal 2005, and the like. The display device is manufactured by using the light-emitting device manufactured according to the present invention for the display portion 2003. Since a light-emitting device having a light-emitting element is a self-luminous type, it does not require a backlight and can have a thinner display portion than a liquid crystal display device. The display devices include all information display devices for personal computers, TV broadcast reception, advertisement display, and the like.

FIG. 17B illustrates a digital still camera, which includes a main body 2101, a display portion 2102, an image receiving portion 2103, operation keys 2104, an external connection port 2105, a shutter 2106, and the like. The display device is manufactured by using the light-emitting device manufactured according to the present invention for the display portion 2102.

FIG. 17C illustrates a laptop personal computer, which includes a main body 2201, a housing 2202, a display portion 2203, a keyboard 2204, an external connection port 2205, a pointing mouse 2206, and the like. The display device is manufactured by using the light-emitting device manufactured according to the present invention for the display portion 2203.

FIG. 17D illustrates a mobile computer, which includes a main body 2301, a display portion 2302, a switch 2303, operation keys 2304, an infrared port 2305, and the like. The display device is manufactured by using the light emitting device manufactured according to the present invention for the display portion 2302.

FIG. 17E illustrates a portable image reproducing device (specifically, a DVD reproducing device) including a recording medium, which includes a main body 2401, a housing 2402, a display portion A 2403, a display portion B 2404, and a recording medium (DVD or the like). A reading unit 2405, operation keys 2406, a speaker unit 2407, and the like are included. The display portion A 2403 mainly displays image information and the display portion B 2404 mainly displays character information. The display portion A 2403 is manufactured by using the light emitting device manufactured according to the present invention for the display portions A, B 2403, and 2404. Note that the image reproducing device provided with the recording medium includes a home game machine and the like.

FIG. 17F shows a goggle-type display (head-mounted display), which includes a main body 2501, a display portion 2502, and an arm portion 2503. The display device 2502 is manufactured using the light-emitting device manufactured according to the present invention for the display portion 2502.

FIG. 17G illustrates a video camera, which includes a main body 2601, a display portion 2602, a housing 2603, an external connection port 2604, a remote control receiving portion 2605, an image receiving portion 2606, a battery 2607, a voice input portion 2608, operation keys 2609, and an eyepiece. Unit 2610 and the like. The display device is manufactured by using the light emitting device manufactured according to the present invention for the display portion 2602.

Here, FIG. 17H illustrates a mobile phone, which includes a main body 2701, a housing 2702, a display portion 2703, a sound input portion 2704, a sound output portion 2705, operation keys 2706, an external connection port 2707, an antenna 2708, and the like. The display device is manufactured by using the light-emitting device manufactured according to the present invention for the display portion 2703. Note that the display portion 2703 can display power of the mobile phone by displaying white characters on a black background.

As described above, the applicable range of the present invention is extremely wide, and can be applied to electronic devices in all fields. Further, the electronic apparatus of the present embodiment can be realized by using a configuration composed of any combination of the first to fourth embodiments.

FIG. 2 is a block diagram of a source signal line driving circuit of the liquid crystal display device of the present invention. FIG. 9 is a block diagram of a source signal line driving circuit of a conventional liquid crystal display device. FIG. 4 illustrates a structure of a pixel portion of a liquid crystal display device. FIG. 11 is a block diagram of a source signal line driving circuit of a conventional liquid crystal display device. FIG. 3 is a circuit diagram of an operational amplifier type analog buffer. FIG. 3 is a circuit diagram of a source follower type analog buffer. FIG. 3 is a circuit diagram of a switch according to the present invention. FIG. 3 is a diagram showing a timing chart of the switch of the present invention. FIG. 2 is a circuit diagram of a gate signal line driving circuit of the present invention. FIG. 4 is a diagram illustrating an output of an analog buffer circuit corresponding to each source signal line. FIG. 4 is a diagram showing video signal switching of the liquid crystal display device of the present invention. FIG. 4 is a diagram showing video signal switching of the liquid crystal display device of the present invention. FIG. 13 is a circuit diagram of a shift register using a unipolar transistor. 1 is an external view of a liquid crystal display device of the present invention. FIG. 2 is a block diagram of a digital source signal line driver circuit using the present invention. FIG. 3 is a circuit diagram of a latch circuit of the digital source signal line driver circuit. FIG. 13 is a diagram of an electronic device using the liquid crystal display device of the present invention.

Claims (13)

A plurality of source signal lines, a plurality of gate signal lines, a plurality of pixels,
In a liquid crystal display device having a source signal line driving circuit for driving the signal line,
The source signal line driving circuit has a plurality of analog buffer circuits,
The liquid crystal display device has a switching circuit between the analog buffer circuit and the source signal line,
The liquid crystal display device, wherein the source signal line is periodically connected to different analog buffer circuits by the switching circuit. A plurality of source signal lines, a plurality of gate signal lines, a plurality of pixels,
In a liquid crystal display device having a source signal line driving circuit for driving the signal line,
The source signal line driving circuit has a plurality of analog buffer circuits,
The liquid crystal display device has a switching circuit between the analog buffer circuit and the source signal line,
2. The liquid crystal display device according to claim 1, wherein the source signal lines are connected to different analog buffer circuits by the switching circuit at random in time. A plurality of pixels, a plurality of source signal lines, a plurality of gate signal lines, and a source signal line driving circuit are arranged on an insulating substrate, and the source signal line driving circuit is an analog buffer for driving the source signal lines. In a liquid crystal display device having a circuit,
The liquid crystal display device has a switching circuit between the analog buffer circuit and the source signal line,
n (n is a natural number satisfying 2 ≦ n) periods are periodically repeated,
In the r-th (r is a natural number satisfying 1 ≦ r ≦ n) period, the m-th (m is a natural number satisfying 1 ≦ m) source signal line is connected to the (m + r−1) -th analog buffer by the switching circuit. A liquid crystal display device characterized by the following. A plurality of pixels, a plurality of source signal lines, a plurality of gate signal lines, and a source signal line driving circuit are arranged on an insulating substrate, and the source signal line driving circuit is an analog buffer for driving the source signal lines. In a liquid crystal display device having a circuit,
The liquid crystal display device has a switching circuit between the analog buffer circuit and the source signal line,
n (n is a natural number satisfying 2 ≦ n) time periods are randomly repeated in time,
In the r-th (r is a natural number satisfying 1 ≦ r ≦ n) period, the m-th (m is a natural number satisfying 1 ≦ m) source signal line is connected to the (m + r−1) -th analog buffer by the switching circuit. A liquid crystal display device characterized in that: 5. The liquid crystal display device according to claim 1, wherein the analog buffer circuit is a source follower. 5. The liquid crystal display device according to claim 1, wherein the analog buffer circuit is a voltage follower. A plurality of source signal lines, a plurality of gate signal lines, a plurality of pixels,
In a method for driving a liquid crystal display device having a source signal line driving circuit for driving the signal line,
The method of driving a liquid crystal display device, wherein the source signal line driving circuit has a plurality of analog buffer circuits, and the source signal lines are periodically driven by different analog buffer circuits. A plurality of source signal lines, a plurality of gate signal lines, a plurality of pixels,
In a method for driving a liquid crystal display device having a source signal line driving circuit for driving the signal line,
The method of driving a liquid crystal display device, wherein the source signal line driving circuit has a plurality of analog buffer circuits, and the source signal lines are driven by different analog buffer circuits at random in time. A plurality of pixels, a plurality of source signal lines, a plurality of gate signal lines, and a source signal line driving circuit are arranged on an insulating substrate, and the source signal line driving circuit is an analog buffer for driving the source signal lines. In a method for driving a liquid crystal display device having a circuit,
n (n is a natural number satisfying 2 ≦ n) periods are periodically repeated,
In an r-th (r is a natural number satisfying 1 ≦ r ≦ n) period, an m-th (m is a natural number satisfying 1 ≦ m) source signal line is driven by an (m + r−1) -th analog buffer. For driving a liquid crystal display device. A plurality of pixels, a plurality of source signal lines, a plurality of gate signal lines, and a source signal line driving circuit are arranged on an insulating substrate, and the source signal line driving circuit is an analog buffer for driving the source signal lines. In a method for driving a liquid crystal display device having a circuit,
n (n is a natural number satisfying 2 ≦ n) time periods are randomly repeated in time,
In an r-th (r is a natural number satisfying 1 ≦ r ≦ n) period, an m-th (m is a natural number satisfying 1 ≦ m) source signal line is driven by an (m + r−1) -th analog buffer. For driving a liquid crystal display device. 11. The driving method of a liquid crystal display device according to claim 7, wherein the analog buffer circuit is a source follower. 11. The driving method of a liquid crystal display device according to claim 7, wherein the analog buffer circuit is a voltage follower. An electronic apparatus using the liquid crystal display device according to any one of claims 1 to 6.

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