JP2001242839A - Semiconductor display device and electronics - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device permitting to display a picture of high definition, high resolution, and multi-gradations. SOLUTION: A semiconductor device is characterized by that the sequence of m-pieces of split video signals is changed before they are imputed to a buffer circuit, and is changed back into the original sequence after they are outputted from the buffer circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a driving circuit for a semiconductor display device. In particular, the present invention relates to a circuit for generating an analog or digital signal input to a source signal line driver circuit of a semiconductor display device. In particular, a serial-to-parallel conversion circuit (Serial-to-Parallel)
l Conversion Circuit: SPC)
The present invention relates to a circuit for processing a parallel analog or digital divided signal output from a source signal line driving circuit before inputting it to a source signal line driving circuit. Further, the present invention relates to a semiconductor display device having a circuit for generating an analog or digital signal input to a source signal line driver circuit.

[0002]

2. Description of the Related Art In recent years, a semiconductor element formed by using a semiconductor thin film on an insulating substrate, for example, a thin film transistor (T
The technology for making FT) is developing rapidly. The reason is that a semiconductor display device using a semiconductor element (typically,
(Active matrix type semiconductor display devices). Note that in this specification, an insulating substrate having a semiconductor element formed on a surface is referred to as an active matrix substrate.

An active matrix type semiconductor display device displays an image by controlling tens to millions of pixel electrode charges arranged in a matrix by using TFTs of the pixels.

[0004] A drive circuit of an active matrix type semiconductor display device is required to operate at high speed. In particular, among the driver circuits, the source signal line driver circuit needs to sequentially input signals to all the pixel TFTs connected to the gate signal line during a period in which the signal is input to the gate signal line. Therefore, the source signal line driver circuit needs to operate at higher speed than the gate signal line driver circuit. For example, VGA
In the case of the active matrix type semiconductor display device, the driving frequency of the source signal line driving circuit is generally about 20 MHz.
It is.

It is desired that an active matrix type semiconductor display device displays a high-definition, high-resolution, multi-gradation image. Therefore, the number of horizontal pixels (the number of horizontal pixels: Hn) of the active matrix semiconductor display device tends to increase.

As the number of horizontal pixels Hn increases, it is required to operate the source signal line driving circuit at higher speed.
When the operation speed of the source signal line drive circuit is reduced, the image display speed is reduced, and various problems such as flickering and flicker of a displayed image occur.

In order to increase the number of pixels in the active matrix semiconductor display device in the horizontal direction while avoiding the above problems, the drive frequency of the source signal line drive circuit must be increased. However, as the driving frequency of the source signal line driver circuit is increased, the response speed of the TFT included in the source signal line driver circuit cannot correspond to the driving frequency of the source signal line driver circuit, and the operation becomes impossible or the operation becomes impossible There could be difficulties in terms of gender.

Therefore, in order to suppress the driving frequency of the source signal line driving circuit without lowering the image display speed, a split driving method has been conventionally used. The division driving is a driving method in which pixels arranged in the horizontal direction are divided into m groups, and a signal having image information is simultaneously input to the pixels in each group during one line period.

In this specification, one line period is defined as
A period from when a signal having image information is input to the first pixel among pixels of one line arranged in the horizontal direction to immediately before a signal having image information is input to the first pixel of the next one line. Means

In the case of division driving in m divisions (m is a positive number larger than 1 and generally a natural number), if the length of one line period is the same as that in the case of no division, it is one more than in the case of no division. The period during which a signal (image signal) having image information per pixel is input becomes m times. Therefore, the driving frequency of the source signal line driving circuit is 1 / m, and the driving frequency of the source signal line driving circuit can be reduced until the source signal line driving circuit can operate completely.

In the case of m-divided driving, a video signal (divided video signal) having image information corresponding to m pixels
Are sampled in the source signal line driving circuit, and m
The image signals are simultaneously input to each of the m pixels.

The divided video signal input to the source signal line driving circuit is generally formed on an IC chip (single-crystal silicon) connected to an active matrix substrate via a flexible printed circuit (FPC). Is generated in a circuit group provided on a semiconductor circuit configured by the MOSFETs. FIG. 17 shows a circuit group for generating a divided video signal input to a source signal line driver circuit in an analog drive active matrix semiconductor display device.

Reference numeral 901 denotes a control circuit; 902, an A / D conversion circuit; 903, a gamma correction circuit; 904, a D / A conversion circuit;
05 denotes a dividing circuit, and 906 denotes a buffer circuit group.

The Hsync signal and the Vsync signal are input to the control circuit 901. Then, a clock signal (CK) for driving the source signal line driving circuit from the control circuit 901;
A start pulse signal (SP) or the like is input to the source signal line driving circuit. Further, from the control circuit 901, the A / D
Conversion circuit 902, γ correction circuit 903, D / A conversion circuit 9
Signals for driving the respective circuits are input to the circuit 04 and the division circuit 905.

An analog video signal having image information is input to the A / D conversion circuit 902. The analog video signal input to the A / D conversion circuit 902 is converted to a digital video signal and input to the γ correction circuit 903. The digital video signal input to the γ correction circuit 903 is γ corrected and input to the D / A conversion circuit 904. The digital video signal input to the D / A conversion circuit 904 is converted into an analog video signal again and input to the division circuit 905.

The analog video signal input to the division circuit 905 is subjected to serial-parallel conversion, and is converted into the same number of divided video signals as the number of divisions for the division driving. In the case of m-divided driving, an analog video signal is converted into m divided video signals.

The m divided video signals are input to a buffer circuit group 906. The buffer circuit group 906 includes buffer circuits 906_1 to 906_m, and the m divided video signals respectively correspond to the corresponding buffer circuits 906_1.
To 906 — m.

When a signal output from one circuit is input to another circuit, the rise or fall of the signal becomes dull and the signal waveform does not become rectangular, or the potential and amplitude of the signal change. Or you may.
This is because load capacitance (parasitic capacitance) exists in a circuit to which a signal is input. This is a phenomenon that appears more conspicuously as the number of circuit elements included in the circuit to which a signal is input increases and the circuit configuration becomes more complicated. A buffer circuit is a circuit that buffers and amplifies a signal output from a certain circuit so that the waveform, potential and amplitude of the signal do not change when the signal is input to another circuit.

The m divided video signals are supplied to a buffer circuit 9
The signals are buffer-amplified at 06_1 to 906_m and input to the source signal line driver circuit. In the case of an active matrix type semiconductor display device driven by analog driving, m divided video signals are sampled in a source signal line driving circuit and input to corresponding pixels as m image signals via a source signal line.

[0020]

SUMMARY OF THE INVENTION Buffer circuit group 906
Have the same configuration in theory. However, actually, the characteristics of the individual buffer circuits are not exactly the same. Depending on the buffer circuit, the degree of amplitude amplification (amplification degree) between the input signal and the output signal is different, or the output signal has an offset potential. The characteristics of the buffer circuit depend on manufacturing errors of circuit elements included in the buffer circuit and the ambient temperature of the buffer circuit.

Therefore, the potential and amplitude of the divided video signal output from the buffer circuit are always affected by the characteristics of the buffer circuit. Therefore, the divided video signals output from the buffer circuits having different characteristics have different amplitudes from other divided video signals, have an offset potential, and have a potential difference from other divided video signals. I will.

When the divided video signal having the potential difference is sampled in the source signal line driving circuit,
An image signal input to a pixel by sampling also has a potential difference. Then, the potential difference of the image signal is displayed as bright and dark on the screen, and the observer visually recognizes the bright and dark fringes (divided fringes).

In view of the above, according to the present invention, when performing the division driving, the division stripes are hard to be visually recognized by an observer,
It is an object to provide an active matrix semiconductor display device capable of displaying a high-resolution and multi-gradation image.

[0024]

The inventor of the present invention believes that the divisional fringes are visually recognized by an observer when a bright portion or a dark portion displayed on a screen by a potential difference of an image signal is connected to a specific source signal line. We thought that this was because it always appeared in the connected pixels. This is because the plurality of divided video signals output from the divided circuits are always input to the specific buffer circuits corresponding to the respective divided video signals.

Therefore, in the present invention, a plurality of divided video signals output from the dividing circuit are not always inputted to a specific buffer circuit, but are inputted to different buffer circuits every certain period. That is, a plurality of input divided video signals and a plurality of input buffer circuits correspond one-to-one, and a plurality of buffer circuits for each of the plurality of divided video signals are replaced with each other every certain period of time, in other words, The combination of the divided video signal and the buffer circuit is changed every certain period.

According to the above configuration, even if a divided video signal output from a buffer circuit having different characteristics has a potential difference between the divided video signal and another divided video signal, a divided stripe may be displayed on a screen. Since the position at which the divisional stripe is displayed moves every period, the divisional stripes are difficult to be visually recognized by an observer.

In the present invention, it is important to set the number of patterns of the combination of the divided video signal and the buffer circuit, and the period until the combination is changed, to such an extent that the divided stripes are hardly recognized by the observer. . It is preferable that the number of types of combinations of the divided video signal and the buffer circuit is as large as possible, and the divided stripes are more difficult to be visually recognized by an observer. It is preferable that the period until the combination is changed be shorter, and it is desirable that the period be 1/20 sec or less.

Therefore, according to the present invention, when performing the division driving, the division stripes are hardly visually recognized by an observer. Further, by performing the division driving, it is possible to display a high-definition, high-resolution, multi-tone image.

The configuration of the present invention will be described below.

According to the present invention, there is provided a semiconductor display device having m buffer circuits and a source signal line driving circuit, wherein each of the m buffer circuits is provided for each of m divided video signals as parallel data. The m buffer circuits corresponding to each of the m divided video signals are replaced with each other at certain intervals, and the m buffer circuits inputted to the m buffer circuits are replaced with each other.
The divided video signals are output from the m buffer circuits and input to the source signal line driving circuit, and the m divided video signals input to the source signal line driving circuit are sampled, A semiconductor display device is provided which is input to predetermined m source signal lines corresponding to each of m divided video signals.

According to the present invention, there is provided a semiconductor display device including a division circuit, a first replacement circuit, a second replacement circuit, m buffer circuits, and a source signal line driving circuit, wherein a video signal is serially transmitted. The m divided video signals formed by the parallel conversion are output from the dividing circuit, and the m divided video signals output from the dividing circuit are input to the first switching circuit, and the first switching circuit Are input to the corresponding m buffer circuits, respectively, and the m divided video signals are input to the corresponding m buffer circuits.
The m divided video signals input to the buffer circuits are output from the m buffer circuits, input to the second switching circuit, and the m divided video signals input to the second switching circuit. Are respectively input to predetermined m divided video signal lines corresponding to the m divided video signals, and the m divided video signals input to the m divided video signal lines are the source signals. M buffer signals corresponding to each of the m divided video signals which are input to and sampled by the line driving circuit, respectively input to predetermined m source signal lines corresponding to the m divided video signals, and A semiconductor display device is provided in which the circuits are replaced with each other every certain period.

According to the present invention, there is provided a semiconductor display device including a division circuit, a first switching circuit, m buffer circuits, and a source signal line driving circuit, wherein the source signal line driving circuit is a second switching circuit. M divided video signals formed by serial-parallel conversion of a video signal are output from the division circuit, and the m divided video signals output from the division circuit are the first divided video signals. The m divided video signals input to the replacement circuit and input to the first replacement circuit are respectively associated with the corresponding m
M divided video signals input to the m buffer circuits and input to the m buffer circuits are output from the m buffer circuits and input to the second switching circuit, and the second switching circuit The m divided video signals input to are input to predetermined m source signal lines corresponding to the m divided video signals, respectively, and correspond to each of the m divided video signals. The semiconductor display device is characterized in that the m buffer circuits are replaced with each other every certain period.

The replacement of the m buffer circuits corresponding to each of the m divided video signals may be controlled by a replacement data circuit.

The replacement data circuit may determine how the m buffer circuits corresponding to the m divided video signals are replaced with each other.

The replacement data circuit has a memory circuit and a counter circuit, and the memory circuit has information on a combination of m buffer circuits corresponding to each of the m divided video signals. A plurality of replacement data may be stored, and one of the replacement data may be selected by the counter circuit.

According to the present invention, a multiplexer circuit and l
1. A semiconductor display device having D / A conversion circuits and l division circuits, wherein each of the l D / A conversion circuits includes l digital distribution signals output from the multiplexer circuit. And one of the D / D signals corresponding to each of the l digital distribution signals.
The A conversion circuits are switched with each other every certain period, and the l digital distribution signals input to the l D / A conversion circuits are converted into l analog distribution signals, and A semiconductor display device is provided, which is input to the corresponding predetermined l divided circuits.

[0037] The semiconductor display device may use liquid crystal.

The semiconductor display device may use a light emitting element.

The present invention may be a computer using the semiconductor display device.

The present invention may be a video camera using the semiconductor display device.

According to the present invention, the D
It may be a VD player.

[0042]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A circuit group for generating a divided video signal according to the present invention will be described with reference to FIG. Note that here, a case will be described in which an active matrix type semiconductor display device driven by analog driving is divided into m units.

Reference numeral 101 denotes a control circuit, 102 denotes an A / D conversion circuit, 103 denotes a gamma correction circuit, 104 denotes a D / A conversion circuit,
05 denotes a dividing circuit, and 106 denotes a replacement data circuit.

The Hsync signal and the Vsync signal are input to the control circuit 101. Then, a clock signal (CK) for driving the source signal line driving circuit from the control circuit 101,
A start pulse signal (SP) or the like is input to the source signal line driving circuit. Further, from the control circuit 101, the A / D
Conversion circuit 102, gamma correction circuit 103, D / A conversion circuit 1
04, the dividing circuit 105, the replacement data circuit 106,
Signals for driving the respective circuits are input.

An analog video signal having image information is input to the A / D conversion circuit 102. The analog video signal input to the A / D conversion circuit 102 is
The converted video signal is converted into a digital video signal by the conversion circuit 102 and input to the gamma correction circuit 103. γ correction circuit 103
Γ-corrected digital video signal input to
/ A conversion circuit 104. D / A conversion circuit 10
The digital video signal after the γ correction input to 4 is converted into an analog video signal again and input to the dividing circuit 105.

The analog video signal input to the division circuit 105 is subjected to serial-parallel conversion, and becomes a divided video signal divided by the number of divisions for division driving. In the case of m-divided driving, an analog video signal is converted into m divided video signals.

The m divided video signals are simultaneously input to the first switching circuit 108. FIG. 2 is a detailed block diagram of a portion 107 surrounded by a dotted line. 108 is a first replacement circuit, 109 is a buffer circuit group, 110 is a second replacement circuit, and 111 is a replacement data processing circuit. The buffer circuit group 109 includes at least m buffer circuits (1
09_1 to 109_m).

The first replacement circuit 108 inputs the input divided video signals (Vs1 to Vsm) to the buffer circuits (109_1 to 109_m) according to the first replacement signal input from the replacement data processing circuit 111. At this time, the input m divided video signals (Vs1 to Vsm) and the m buffer circuits (109_109) are input.
1 to 109 — m) correspond one-to-one. And m
Which of the divided video signals is m
Which of the buffer circuits is to be input is determined by the first exchange signal input from the exchange data processing circuit 111.

Buffer circuit (109_1 to 109_m)
M divided video signals (Vs1 to Vsm) input to
Are buffer-amplified in each buffer circuit and input to the second replacement circuit 110.

The second replacement circuit 110 specifies m divided video signals (Vs1 to Vsm) output from the buffer circuits (109_1 to 109_m) by the second replacement signal input from the replacement data processing circuit 111, respectively. To the divided video signal lines (V11 to Vlm). That is, regardless of which buffer circuit (109_1 to 109_m) each of the m divided video signals (Vs1 to Vsm) is input by the first replacement signal, the m buffer circuits (109_1 to 109_m) are input.
m) output from m divided video signals (Vs1 to Vs
sm) is connected to a predetermined divided video signal line (Vl
1 to Vlm).

The m divided video signals (Vs1 to Vsm) input to the divided video signal lines (V11 to Vlm) are input to a source signal line driving circuit. In the case of an active matrix type semiconductor display device driven by analog driving, m divided video signals are sampled in a source signal line driving circuit, and the signals (image signals) having m pieces of image information respectively corresponding to m pixels are obtained. , And m source signal lines connected to the corresponding pixel.

Next, the replacement data circuit 106 will be described. The replacement data signal generated in the replacement data circuit 106 is replaced with a replacement data processing circuit 111.
, A first replacement signal and a second replacement signal are generated.

FIG. 3 shows a block diagram of the replacement data circuit 106. 112 is a counter circuit, and 113 is a memory circuit. The memory circuit 113 stores data on which divided video signal is input to which buffer circuit, in other words, data (replacement data) of a combination of the divided video signals (Vs1 to Vsm) and the buffer circuits (109_1 to 109_m). (Q is a natural number of 2 or more) are stored.

The q between the divided video signal and the buffer circuit
The different combinations are stored as replacement data from address 0 to address (q-1) of the memory address of the memory circuit 113, respectively.

The counter circuit 112 is driven by a signal input from the control circuit 101 and determines a counter value for specifying a memory address of the memory circuit 113.
For example, if the counter value is 0, the memory address of the memory circuit 113 is specified as address 0, if the counter value is 1, the address is 1, if the counter value is 2, the address is 2, and the counter value is q-1.
Then, the address (q-1) is specified. Information on the counter value is input from the counter circuit 112 to the memory circuit 113 as a counter signal.

The address of the memory address is specified by the counter signal input to the memory circuit 113. Then, replacement data, which is information on the combination of the divided video signal and the buffer circuit stored at the designated address, is input to the replacement data processing circuit 106 as a replacement data signal.

Note that the counter value changes every certain period. Each time the value of the counter value changes, information on the counter value is transmitted to the memory circuit 113 as a counter signal. The period until the counter value changes corresponds to the period until the combination of the divided video signal and the buffer circuit changes.

After the counter value takes one value from 0 to q-1, the value from 0 to q-1 is taken again.
In other words, if the address of the memory address of the memory circuit 113 is designated from address 0 to address (q-1) once, 0
The designation from the address to the address (q-1) is started. There is no particular order in the values taken by the counter values, and values from 0 to q-1 may be taken in order, or may be random.

The larger the number q of replacement data, which is data of a combination of the divided video signals (Vs1 to Vsm) and the buffer circuits (109_1 to 109_m), the better.
However, compared to the conventional example shown in FIG. 17 in which the combination of the divided video signal and the buffer circuit is not rearranged, it is sufficient that the number of the divided stripes is small enough to make it difficult for the observer to visually recognize the divided stripes.

In the combination of the divided video signal and the buffer circuit stored in the memory circuit 113, the divided stripes are visually recognized by the observer as compared with the conventional example shown in FIG. 17 in which the combination of the divided video signal and the buffer circuit is not rearranged. Any combination can be used as long as the combination can be made difficult. A combination of the divided video signal and the buffer circuit may be set using a random number or another function.

The combination of the divided video signal and the buffer circuit may be random, but need not be so, and may have a certain regularity.
For example, assume that a divided video signal Vsp (p is an arbitrary number from 1 to m) is input to the buffer circuit 109_p in a certain period. Then, in the next period, the divided video signal Vsp is input to the buffer circuit 109_ (p + 1) (if p = m, the buffer circuit 109_1). In the next period, the divided video signal Vsp is supplied to the buffer circuit 109_ (p + 2) (when p = m, the buffer circuit 1
09_2, p = m + 1, the buffer circuit 109_
Input to 1). As described above, a buffer circuit corresponding to a certain divided video signal may be replaced with a certain regularity.

In the present invention, it is important to set the period from the time when the combination of the divided video signal and the buffer circuit is changed to the time when the combination is changed again to such a length that the divided stripes are hardly recognized by the observer. It is. The period from the change of the combination of the buffer circuits to the next change of the combination is, in other words, the period from the change of the counter value to the change of the counter value again. During that period, the first replacement signal and the second
This corresponds to a period from when the information of the switching signal changes to when the information of the first switching signal and the information of the second switching signal change next.

It is preferable that the period until the combination of the divided video signal and the buffer circuit is changed is shorter. If the period is shorter, the divided stripes are more difficult to be visually recognized by an observer. The period until the combination of the divided video signal and the buffer circuit changes is 1
/ 20 sec or less is desirable. In this embodiment, the setting is made so that the combination of the divided video signal and the buffer circuit changes every frame period.

In this embodiment, a circuit group shown in FIG. 1 for forming a divided video signal is used as an external circuit as an IC chip (a MOSF formed on single crystal silicon).
(A semiconductor circuit composed of ET). The circuit group is connected to a source signal line drive circuit provided on an active matrix substrate via an FPC (Flexible Print Circuit). Note that the present invention is not limited to the above structure, and a structure in which a source signal line driver circuit is provided on an IC chip together with the circuit group may be employed. Alternatively, part or all of the circuit group 107 may be provided over an active matrix substrate.

According to the present invention, the divided video signal output from the buffer circuit having the different characteristic has a potential difference between the divided video signal and the other divided video signals. ) Is displayed, the position at which the divisional stripe is displayed moves every certain period. Therefore, even if the divisional stripes are displayed on the screen, it is difficult for the observer to visually recognize the divisional stripes.

Therefore, according to the present invention, when performing the division driving, the division stripes are hardly visually recognized by an observer. Even by increasing the number of pixels in the horizontal direction of the active matrix type semiconductor display device, it is possible to suppress flickering and flickering of the displayed image while suppressing the driving frequency of the source signal line driving circuit, by performing the division driving. It is possible to display a high-resolution, multi-tone image.

The present invention is not limited to the configuration shown in FIG. For each certain period, the combination of the plurality of divided video signals and the plurality of buffer circuits for inputting the plurality of divided video signals is changed, and the plurality of divided video signals output from the plurality of buffer circuits are sampled. ,
What is necessary is just to have a configuration in which each is input to a predetermined specific source signal line.

[0068]

Examples of the present invention will be described below.

(Embodiment 1) The structure of an active matrix type semiconductor display device using liquid crystal (active matrix type liquid crystal display device) having a circuit group for generating a divided video signal of the present invention will be described. FIG. 4 is a block diagram showing an example of an active matrix liquid crystal display device having a circuit group for generating a divided video signal according to the present invention.
The present invention is not limited to this configuration.

In this embodiment, a circuit group for generating a divided video signal having the configuration shown in FIG. 1 is used.
The circuit group for generating the divided video signal used in the present embodiment is not limited to the configuration shown in FIG. For each certain period, the combination of the plurality of buffer circuits and the plurality of divided video signals input to the plurality of buffer circuits is changed, and the plurality of divided video signals output from the plurality of buffer circuits are changed. , Respectively, as long as they are configured to be input to predetermined specific divided video signal lines.

Reference numeral 115 denotes a source signal line driving circuit, 116 denotes a gate signal line driving circuit, 120 denotes a pixel portion, and 110 denotes a second replacement circuit in a circuit group for generating a divided video signal. In this embodiment, one source signal line driving circuit and one gate signal line driving circuit are provided, but the present invention is not limited to this configuration. Two source signal line driver circuits may be provided, or two gate signal line driver circuits may be provided.

The source signal line driving circuit 115 includes a shift register circuit 115_1, a level shift circuit 115_2,
It has a sampling circuit 115_3. Note that the level shift circuit may be used as needed, and may not necessarily be used. Although the level shift circuit 115_2 is provided between the shift register circuit 115_1 and the sampling circuit 115_3 in this embodiment, the present invention is not limited to this structure. Shift register circuit 11
5_1 may have a structure in which the level shift circuit 115_2 is incorporated.

The clock signal (CLK) and the start pulse signal (SP) are input from the control circuit 101 shown in FIG. 1 to the shift register circuit 115_1. In this embodiment, a circuit group for generating a divided video signal is provided on an IC chip, and is connected to a source signal line driving circuit 115 on an active matrix substrate via an FPC.

A sampling signal for sampling the divided video signal is output from shift register circuit 115_1. The output sampling signal is input to the level shift circuit 115_2, where the amplitude of the potential is increased and output.

The sampling signal output from the level shift circuit 115_2 is input to the sampling circuit 115_3. At the same time, the divided video signals (Vs1 to Vs1) are output from the second replacement circuit 110 via the divided video signal lines.
Vsm) is input to the sampling circuit 115_3. The second replacement circuit 110 is included in the circuit group for generating the divided video signal shown in FIG.

In the sampling circuit 115_3, the input divided video signals (Vs1 to Vsm) are respectively sampled by the sampling signals, and input to predetermined pixels as m image signals via the source signal line 117.

In the pixel portion 120, a source signal line 117 connected to the source signal line driving circuit 115 and a gate signal line 118 connected to the gate signal line driving circuit 116 intersect. In a region surrounded by the source signal line 117 and the gate signal line 118, a thin film transistor (pixel TFT) 121 of a pixel 119, a liquid crystal cell 122 having liquid crystal interposed between a counter electrode and a pixel electrode, a storage capacitor 123, Is provided.

The pixel TFT 121 operates according to a selection signal input from the gate signal line driving circuit 116 via the gate signal line 118. The m image signals input to the corresponding m source signal lines out of the source signal lines 117 are selected by the pixel TFT 121 and simultaneously written to a predetermined pixel electrode.

An example of the operation of the active matrix type liquid crystal display device in which the source signal lines are divided and driven in m divisions will be described below with reference to FIG.

As shown in FIG. 5, one frame period is composed of a plurality of line periods. Note that in this specification, one frame period (F) refers to a period after data for displaying one screen (frame) in a pixel portion starts to be input.
This means a period until data for displaying the next screen starts to be input. And one line period (L) is
After the selection signal starts to be input to a certain gate signal line,
This means a period until a selection signal is input to the next gate signal line.

In this embodiment, the source signal lines exist from the first to the n-th, and the gate signal lines exist from the first to the r-th. Therefore, during one frame period, L
There will be 1 to Lr line periods. Note that n,
r is any positive integer.

In the line period L1, a selection signal is input from the gate signal line drive circuit 116 to the first gate signal line. As a result, the pixel TFTs of the pixels connected to the first gate signal line are all turned on. That is, all the pixels (1, 1), (1, 2),..., (1, m),.
The pixel TFT included in n) is turned on.

Then, from the source signal line driving circuit 115,
M image signals are simultaneously input to each of the first to m-th source signal lines. That is, the pixels (1, 1), (1, 2),..., (1) connected to the first gate signal line and connected to any of the first to m-th m source signal lines. 1, m), m image signals are simultaneously input. As a result, the liquid crystal is driven by the potential of the inputted m image signals, the transmitted light amount is controlled, and the pixels (1, 1),
(1, m), a part of an image (screen) is displayed (image corresponding to pixels (1, 1), (1, 2), ..., (1, m)). You.

Next, the pixels (1, 1), (1, 2),.
While holding the state in which the image is displayed at (1, m) by a storage capacitor or the like, the source signal line driving circuit 115 sends m images to each of the (m + 1) th to 2mth m source signal lines. Signals are input simultaneously. That is, pixels (1, m + 1), (1, m + 2),... Connected to the first gate signal line and connected to any of the m source signal lines from the (m + 1) th to the 2mth source signal lines.
M image signals are simultaneously input to each of (1, 2m). As a result, the liquid crystal is driven by the input potentials of the m image signals, and the amount of transmitted light is controlled, and the pixels (1, m + 1), (1, m + 2),.
Part of the image (pixels (1, m + 1), (1, m + 2),
, (An image corresponding to (1, 2m)) is displayed.

By performing such display operations sequentially, the pixels (1, 1), (1, 1) connected to the first gate signal line are displayed.
2) A part of the image is sequentially displayed on all of (1, m),..., (1, n). During the first line period L1, the selection signal is continuously input to the first gate signal line. Then, the pixel in which a part of the image has been displayed once keeps the displayed state by a storage capacitor or the like until the image signal is input to the pixel again.

When a signal having image information is input to all the pixels connected to the first gate signal line, the first line period L1 ends, and the selection signal is applied to the first gate signal line. No more input. Subsequently, the second line period L2 starts, and the selection signal is input only to the second gate signal line. Then, as in the case of the line period L1, the image signal is input to all the pixels connected to the second gate signal line. As a result, a part of the image is successively displayed on all the pixels connected to the second gate signal line. During this time, the selection signal continues to be input to the second gate signal line.

When the second line period L2 is completed, a third line period L3 is formed, and the r-th line period L
The same operation is repeated until r. When the r-th line period Lr ends, one image (frame) is displayed on the pixel unit 120. Although not shown in FIG. 5, a retrace period may be provided between the r-th line period Lr and the first line period L1 of the next frame period. When the retrace period is provided, one frame period includes the line periods L1 to Lr and the retrace period.

An image is displayed on the pixel section 120 by sequentially repeating these display operations.

In this embodiment, L1 is the first to m-th source signal line, L2 is the (m + 1) th to 2m-th source signal line, and L3 is 2m.
Image signals were sequentially input to the + 1st to 3mth source signal lines and m source signal lines. However, the present invention is not limited to this configuration. In each line period, the m source signal lines for inputting image signals may be selected in any order.

In the present invention, the division driving is performed as described above.
FIG. 1 is a block diagram of the present invention for forming a divided video signal.
The divided video signals output from the buffer circuits having different characteristics have potential differences between the divided video signals and the other divided video signals, so that bright and dark stripes (divided stripes) are displayed on the screen. Even so, the position where the divided stripe is displayed moves every certain period. Therefore, even if the divisional stripes are displayed on the screen, it is difficult for the observer to visually recognize the divisional stripes.

Therefore, in the present invention, when performing the above-described division driving, the division stripes are not easily recognized by the observer. Further, by performing the division driving, it is possible to display a high-definition, high-resolution, multi-tone image.

(Embodiment 2) In this embodiment, a detailed circuit configuration of the source signal line driving circuit shown in Embodiment 1 will be described. Note that the source signal line driver circuit described in Embodiment 1 is not limited to the configuration described in Embodiment 3. In this embodiment, division driving in the case of four divisions will be described.

FIG. 6 is a circuit diagram of the source signal line driving circuit of this embodiment. 115_1 is a shift register circuit, 11
5_2 indicates a level shift circuit, and 115_3 indicates a sampling circuit.

The clock signal CLK, the start pulse signal SP, and the driving direction switching signal SL / R are input to the shift register circuit 115_1 from the wirings shown in FIG. The divided video signal is input to the sampling circuit 115_3 through the divided video signal line 124. Since the driving is divided into four parts, there are four divided video signal lines 124.

The divided video signal input to each divided video signal line 124 is sampled in the sampling circuit 115_3 by the sampling signal input from the level shift circuit 115_2. In particular,
The divided video signal is sampled by the analog switch 125 of the sampling circuit 115_3,
Source signal lines 1 corresponding to the respective image signals
17_1 to 117_4.

By repeating the above operation, image signals are input to all the source signal lines.

FIG. 7A is an equivalent circuit diagram of the analog switch 125. The analog switch 125 has an n-channel TFT and a p-channel TFT. The divided video signal is input as Vin from the wiring shown in the figure.
Then, a sampling signal output from the level shift circuit 115_2 and a signal having a polarity opposite to that of the sampling signal are input from IN or INb, respectively.
The divided video signal is sampled by the sampling signal, and the image signal is transmitted from the analog switch to Vout.
Is output as

FIG. 7B shows a level shift circuit 115_2.
The equivalent circuit diagram of FIG. The sampling signal output from the shift register circuit 115_1 and a signal having a polarity opposite to the sampling signal are Vin and Vi, respectively.
nb. Vddh is a plus voltage,
Vss indicates the application of a negative voltage. The level shift circuit 115_2 is designed such that a signal obtained by increasing the voltage of a signal input to Vin and inverting the signal is output from Voutb. That is, when Hi is input to Vin, a signal corresponding to Vss is output from Voutb, and when Lo is input, a signal corresponding to Vddh is output from Vout.

The structure of the present embodiment can be implemented by freely combining with Embodiment 1.

(Embodiment 3) In this embodiment, the embodiment,
An analog-driven active matrix semiconductor display device according to the present invention, which has a different form from those shown in the first and second embodiments, will be described.

A circuit group for generating a divided video signal according to the present embodiment will be described with reference to FIG. Here, a case will be described in which an active matrix type semiconductor display device driven by analog driving is divided into m units.

601 is a control circuit, 602 is an A / D conversion circuit, 603 is a gamma correction circuit, 604 is a D / A conversion circuit,
05 denotes a division circuit, and 606 denotes a replacement data circuit.

The Hsync signal and the Vsync signal are input to the control circuit 601. A clock signal (CK) for driving the source signal line driving circuit from the control circuit 601;
A start pulse signal (SP) and the like are input to the source signal line driving circuit. Further, from the control circuit 601, A
/ D conversion circuit 602, γ correction circuit 603, D / A conversion circuit 604, division circuit 605, exchange data circuit 606
, Signals for driving the respective circuits are input.

An analog video signal having image information is input to the A / D conversion circuit 602. The analog video signal input to the A / D conversion circuit 602 is converted to a digital video signal and input to the γ correction circuit 603. The digital video signal input to the γ correction circuit 603 is γ corrected and input to the D / A conversion circuit 604. The digital video signal after the γ correction input to the D / A conversion circuit 604 is converted into an analog video signal again and input to the division circuit 605.

The analog video signal input to the division circuit 605 is subjected to serial-parallel conversion, and becomes a divided video signal divided by the number of divisions for division driving. In the case of m-divided driving, an analog video signal is converted into m divided video signals.

The m divided video signals are simultaneously input to the first replacement circuit 608. FIG. 9 shows a detailed block diagram of a portion 607 surrounded by a dotted line. 608 is a first replacement circuit, 609 is a buffer circuit group, and 611a is a first replacement data processing circuit. The buffer circuit group 609 includes at least m buffer circuits (609_1 to 609_
m).

The first replacement circuit 608 inputs the input divided video signals (Vs1 to Vsm) to the buffer circuits (609_1 to 609_m) according to the first replacement signal input from the first replacement data processing circuit 611a. I do. At this time, the m divided video signals (Vs1 to Vsm) to be input and the m buffer circuits (609) are input.
— 1 to 609 — m) in one-to-one correspondence. And which of the m divided video signals is
Which buffer circuit of the m buffer circuits is input is determined by the first replacement signal input from the first replacement data processing circuit 611a.

Buffer circuits (609_1 to 609_m)
M divided video signals (Vs1 to Vsm) input to
Is buffer-amplified in each buffer circuit and input to the second replacement circuit 615_3. At the same time, the first replacement data processing circuit 611a to the second replacement circuit 615
_3 receives the first replacement information signal. The first replacement information signal is obtained by dividing the divided video signals (Vs1 to Vsm) and the buffer circuit (609) in the first replacement circuit 608.
— 1 — 609 — m) is a signal containing information on how the combination was changed by the first replacement signal. In this embodiment, the second replacement circuit 615_3 is incorporated in the source signal line driving circuit.

Next, referring to FIG. 11, the second replacement circuit 6 will be described.
The operation of 15_3 and the second replacement data processing circuit 611b will be described. Note that the configuration shown in FIG. 11 is an example of an active matrix liquid crystal display device having a circuit group for generating a divided video signal of the present invention, and the present invention is not limited to this configuration.

In the active matrix type liquid crystal display device shown in FIG. 11, the second signal exchange circuit 615_3 and the second exchange data processing circuit 611b, which are part of a circuit group for generating a divided video signal, are connected to the source on the active matrix substrate. It is provided in the signal line driver circuit 615.
Note that the second replacement data processing circuit 611b may not be provided in the source signal line driving circuit 615.

[0111] A clock signal (CLK), a start pulse signal (SP), and the like are input from the control circuit 601 to the shift register circuit 615_1 in the source signal line driving circuit 615.

A sampling signal for sampling the divided video signal is output from the shift register circuit 615_1. The output sampling signal is also supplied to the level shift circuit 615_ in the source signal line drive circuit 615.
2 and output with its amplitude increased.

Note that the level shift circuit may be used as needed, and may not necessarily be used. In this embodiment, the level shift circuit 615_2 is provided between the shift register circuit 615_1 and the second replacement circuit 615_3; however, the present invention is not limited to this structure.
A structure in which the level shift circuit 615_2 is incorporated in the shift register circuit 615_1 may be employed.

The sampling signal output from the level shift circuit 615_2 is input to a second replacement circuit 615_3 in the source signal line driving circuit 615.

On the other hand, the first replacement data processing circuit 611
The first exchange information signal output from a is input to the second exchange data processing circuit 611b. Then, according to the first exchange information signal, the second exchange signal output from the second exchange data processing circuit 611b is input to the second exchange circuit 615_3.

At the same time, the divided video signals (Vs1 to Vsm) output from the buffer circuit group 609 are input to the second replacement circuit 615_3 via the divided video signal lines.

In response to the second replacement signal, the second replacement circuit 615_3 causes the divided video signal lines (V11 to Vlm) to which the divided video signals (Vs1 to Vsm) to be input to the m source signal lines are input. Select one by one. Then, m divided video signals (Vs1 to Vsm) are sampled by the sampling signal, and m
The image signals are input to predetermined m source signal lines, respectively. That is, regardless of which buffer circuit (609_1 to 609_m) each of the m divided video signals (Vs1 to Vsm) is input by the first replacement signal, the m buffer circuits (609_609_m) are input.
M-divided video signals (Vs1 to Vsm) output from m.1 to 609_m) are input to m predetermined source signal lines, respectively.

The m image signals input to the source signal line are input to predetermined pixels.

In the pixel section 617, the second replacement circuit 61
The source signal line connected to the gate signal line 1b and the gate signal line connected to the gate signal line driving circuit 616 cross each other.
In the area surrounded by the source signal line and the gate signal line,
A thin film transistor (pixel TFT) of a pixel, a liquid crystal cell in which liquid crystal is interposed between a counter electrode and a pixel electrode, and a storage capacitor are provided.

The pixel TFT operates according to a selection signal input from a gate signal line driving circuit via a gate signal line. The m image signals respectively input to the corresponding m source signal lines among the source signal lines are selected by the pixel TFT, and are simultaneously written to a predetermined pixel electrode.

Next, the replacement data circuit 606 will be described. The first exchange data signal generated by the exchange data circuit 606 is input to the first exchange data processing circuit 611a, so that the first exchange signal and the first exchange information signal are generated.

FIG. 10 is a block diagram of the replacement data circuit 606. 612 is a counter circuit, and 613 is a memory circuit. The memory circuit 613 stores data indicating which divided video signal is input to which buffer circuit, in other words, data (replacement data) of a combination of the divided video signals (Vs1 to Vsm) and the buffer circuits (609_1 to 609_m). Are stored q times.

The q between the divided video signal and the buffer circuit
Each combination is stored as replacement data from address 0 to address (q-1) of the memory address of the memory circuit.

The counter circuit 612 is driven by a signal input from the control circuit 601 to determine a counter value for specifying a memory address of the memory circuit 613.
For example, if the counter value is 0, the memory address of the memory circuit 113 is designated as address 0, if the counter value is 1, the address is 1, if the counter value is 2, the address is 2, and the counter value is (q-
In the case of 1), the address (q-1) is specified. Information on the counter value is input from the counter circuit 612 to the memory circuit 613 as a counter signal.

The address of the memory address is designated by the counter signal input to the memory circuit 613. Then, replacement data, which is information on the combination of the divided video signal and the buffer circuit stored at the designated address, is input to the first replacement data processing circuit 611a as a replacement data signal.

The counter value changes every certain period. Each time the value of the counter value changes, information on the counter value is transmitted to the memory circuit 613 as a counter signal. The period until the counter value changes corresponds to the period until the combination of the divided video signal and the buffer circuit changes.

When the counter value takes one value from 0 to (q-1), the value from 0 to (q-1) is taken again. In other words, when the address of the memory address of the memory circuit 613 is completely specified from address 0 to address (q-1), the specification from address 0 to address (q-1) is started again. There is no particular order in the values taken by the counter values, and values from 0 to (q-1) may be taken in order, or may be random.

The larger the number q of replacement data, which is data of a combination of the divided video signals (Vs1 to Vsm) and the buffer circuits (609_1 to 609_m), the better. However, compared to the conventional example shown in FIG. 17 in which the combination of the divided video signal and the buffer circuit is not rearranged, it is sufficient that the number of the divided stripes is small enough to make it difficult for the observer to visually recognize the divided stripes.

In the combination of the divided video signal and the buffer circuit stored in the memory circuit 613, the divided stripes are visually recognized by the observer as compared with the conventional example shown in FIG. Any combination can be used as long as the combination can be made difficult. A combination of the divided video signal and the buffer circuit may be set using a random number or another function.

The combination of the divided video signal and the buffer circuit may be random, but need not be so. As described in the embodiment, the combination of the divided video signal and the buffer circuit may have a certain regularity. What is important in the present invention is that the combination of the divided video signal and the buffer circuit is changed every certain period so that the divided stripes are hardly seen by an observer.

In this embodiment, one source signal line driving circuit and one gate signal line driving circuit are provided, but the present invention is not limited to this configuration. Two source signal line driver circuits may be provided, or two gate signal line driver circuits may be provided.

In the present invention, it is important to set the period from the time when the combination of the divided video signal and the buffer circuit is changed to the time when the combination is changed again to such a length that the divided stripes are hardly recognized by the observer. It is. The period from the change of the combination of the buffer circuits to the next change of the combination is, in other words, the period from the change of the counter value to the change of the counter value again. During that period, the first replacement signal and the second
This corresponds to a period from when the information of the switching signal changes to when the information of the first switching signal and the information of the second switching signal change next.

It is preferable that the period until the combination of the divided video signal and the buffer circuit changes is shorter, and the divided stripes are more difficult to be visually recognized by the observer. The period until the combination of the divided video signal and the buffer circuit changes is 1 / 20s
ec or less. In this embodiment, the setting is made so that the combination of the divided video signal and the buffer circuit changes every frame period.

In this embodiment, the second replacement circuit, which is a part of the circuit group for forming the divided video signal in the first embodiment, is formed in the source signal line driving circuit, and at the same time, has a function as a sampling circuit. I let you. However, the present invention is not limited to this configuration. The second replacement circuit may not have a function as a sampling circuit, and a sampling circuit may be separately provided in the source signal line driving circuit. Further, the second replacement circuit may be formed on the active matrix substrate separately from the source signal line driving circuit. In this case, the second
The replacement circuit is provided between the circuit group for forming a divided video signal provided on the IC chip as an external circuit and the source signal line drive circuit provided on the active matrix substrate, and is provided on the IC chip. A circuit group for forming the divided video signal thus divided and the second replacement circuit
You may have the structure connected via PC.

Although the second replacement data processing circuit is provided in the source signal line driving circuit in this embodiment, it is needless to say that the second replacement data processing circuit is formed on the active matrix substrate separately from the source signal line driving circuit. You may. In addition, the first replacement data processing circuit and the second replacement data processing circuit are integrally provided on an IC chip, and the second replacement signal is input to the second replacement circuit on the active matrix substrate via the FPC. May be.

In this embodiment, the exchange data signal is input only to the first exchange data processing circuit, and the first exchange information signal is input from the first exchange data processing circuit to the second exchange data processing circuit. ing. However, the present invention is not limited to this configuration, and inputs the replacement data signal to both the first replacement data processing circuit and the second replacement data processing circuit, and in the second replacement data processing circuit, not from the first replacement information signal. ,
The configuration may be such that the second exchange signal is generated from the exchange data signal.

According to the present invention, the divided video signal output from the buffer circuit having different characteristics has a potential difference between the divided video signal and the other divided video signals. ) Is displayed, the position at which the divisional stripe is displayed moves every certain period. Therefore, even if the divisional stripes are displayed on the screen, it is difficult for the observer to visually recognize the divisional stripes.

Therefore, according to the present invention, when performing the division driving, the division stripes are hard to be visually recognized by the observer. Even by increasing the number of pixels in the horizontal direction of the active matrix type semiconductor display device, it is possible to suppress flickering and flickering of the displayed image while suppressing the driving frequency of the source signal line driving circuit, by performing the division driving. It is possible to display a high-resolution, multi-tone image.

This embodiment is not limited to the configuration shown in FIGS. For each certain period, a plurality of buffer circuits, a combination of a plurality of divided video signals respectively input to the plurality of buffer circuits is changed, and a plurality of divided video signals are sampled, and each of the plurality of divided video signals is sampled in a predetermined specific manner. What is necessary is just to have a configuration to be input to the source signal line.

(Example 4)

In this embodiment, a detailed circuit configuration of the source signal line driving circuit shown in Embodiment 3 will be described. Note that the source signal line driver circuit described in Embodiment 3 is not limited to the configuration described in Embodiment 3. In this embodiment, for ease of explanation, a division drive in the case of four divisions will be described as an example.

FIG. 12 is a circuit diagram of the source signal line driving circuit of this embodiment. 615_1 is a shift register circuit;
Reference numeral 15_2 denotes a level shift circuit, 615_3 denotes a second replacement circuit, and 611b denotes a second replacement data processing circuit.

A clock signal CLK, a start pulse signal SP, and a driving direction switching signal SL / R are input to the shift register circuit 615_1 from the wirings shown in the figure.

The divided video signal is supplied to the divided video signal line 616.
Is input to the second replacement circuit 615_3 via the. 4
Because of the divisional drive, there are four divided video signal lines 616.

The first exchange information signal is input to the second exchange data processing circuit 611b, and the second exchange signal is output. The output second replacement signal is input to the NAND circuit 619 included in the second replacement circuit 615_3. At the same time, the sampling signal output from the level shift circuit 615_2 is input to the NAND circuit 619.

One of the divided video signal lines is selected by the second replacement signal and the sampling signal input to the NAND circuit 619, and the divided video signal input to the divided video signal line is sampled. Then, the sampled divided video signal is input to the source signal line as an image signal. Specifically, the divided video signal is sampled by the analog switch 617 included in the second switching circuit 615_3, and is simultaneously input as image signals to the corresponding source signal lines 618_1 to 618_4.

By repeating the above operation, image signals are input to all the source signal lines.

Note that the analog switch 617 and the level shift circuit 615_2 used in this embodiment are
It has the configuration shown in FIG. However, it goes without saying that the present embodiment is not limited to this configuration.

Embodiment 5 In this embodiment, an example in which the structure of the present invention is applied to a digitally driven active matrix liquid crystal display device will be described. Note that, here, a case where division driving is performed by m divisions will be described.

FIG. 13 is a block diagram of a circuit group for generating a divided video signal according to the present embodiment. 701 is a control circuit, 7
02 denotes an A / D conversion circuit, 703 denotes a gamma correction circuit, 705 denotes a division circuit, and 706 denotes a replacement data circuit.

The Hsync signal and the Vsync signal are input to the control circuit 701. Then, a clock signal (CK) for driving the source signal line driving circuit from the control circuit 701,
A start pulse signal (SP) or the like is input to the source signal line driving circuit. Further, from the control circuit 701, the A / D
A conversion circuit 702, a gamma correction circuit 703, a division circuit 705,
A signal for driving each circuit is input to the replacement data circuit 706.

An analog video signal having image information is input to the A / D conversion circuit 702. The input analog video signal is converted into a digital video signal and input to the gamma correction circuit 703. γ correction circuit 703
Are input to the division circuit 705 after γ correction.

The input digital video signal is subjected to serial-parallel conversion in a division circuit 705, and is converted into a divided video signal divided by the number of divisions of division driving. In the case of m-divided driving, a digital video signal is converted into m divided video signals. In the case of s-bit (s is a positive integer) digital drive, each of the m divided video signals is composed of s digital divided video signals D ₀ to D _S.

The m divided video signals are input to the first replacement circuit 708. The part 70 surrounded by the dotted line in FIG.
7 shows a detailed block diagram. 708 is a first replacement circuit, 709 is a buffer circuit group, and 711 is a replacement data processing circuit. The buffer circuit group 709 has at least m
Buffer circuits (709_1 to 709_m).

The first replacement circuit 708 inputs the input divided video signals (Vs1 to Vsm) to the buffer circuits (709_1 to 709_m) according to the first replacement signal input from the replacement data processing circuit 711. At this time, the input m divided video signals (Vs1 to Vsm) and the m buffer circuits (709_
1 to 709 — m) in one-to-one correspondence. And m
Which of the divided video signals is m
Which of the buffer circuits is input is determined by the first exchange signal input from the exchange data processing circuit 711.

Buffer circuits (709_1 to 709_m)
M divided video signals (Vs1 to Vsm) input to
Is buffer-amplified in each buffer circuit and input to the latch circuit 1801-2 included in the source signal line driving circuit.

FIG. 15 is a schematic block diagram of the active matrix type liquid crystal display device of this embodiment. Reference numeral 801 denotes a source signal line driving circuit, and 802 denotes a gate signal line driving circuit. 803 is a pixel portion.

The source signal line driving circuit 801 includes a shift register circuit 801-1, a latch circuit 1 (801-2),
Latch circuit 2 (801-3), selector circuit 1 (801
-4), D / A conversion circuit 801-5, selector circuit 2
(801-6). In addition, a buffer circuit and a level shift circuit (both not shown) may be provided. Further, the DAC 801-5 may include a level shift circuit.

In this embodiment, one source signal line driving circuit and one gate signal line driving circuit are provided, but the present invention is not limited to this configuration. Two source signal line driver circuits may be provided, or two gate signal line driver circuits may be provided.

The gate signal line driving circuit 802 has a shift register circuit and a buffer circuit (both not shown). Further, a level shift circuit may be provided.

The pixel section 803 has a plurality of pixels. Each pixel is provided with a pixel TFT, and each pixel T
A source signal line is electrically connected to the source region of the FT, and a gate signal line is electrically connected to the gate electrode. A pixel electrode is electrically connected to a drain region of each pixel TFT. Each pixel TFT controls supply of a video signal (analog signal) to a pixel electrode electrically connected to each pixel TFT. Video signal (analog signal) for each pixel electrode
Is supplied, and a voltage is applied to the liquid crystal sandwiched between each pixel electrode and the counter electrode to drive the liquid crystal.

The operation of the source signal line side driving circuit 801 will be described. A clock signal (CK) and a start pulse (SP) are input to the shift register circuit 801-1. The shift register circuit 801-1 sequentially generates a timing signal based on these clock signal (CK) and start pulse (SP), and latch circuit 1 (801)
-2) to sequentially supply timing signals.

The latch circuit 1 (801-2) has a latch circuit for processing m divided video signals each consisting of an s-bit digital divided video signal. When the timing signal is input, the latch circuit 1 (801-2) sequentially captures and holds m divided video signals supplied from the buffer circuit 709 shown in FIG.

The time until the writing of the divided video signal to the latch circuits of all the stages of the latch circuit 1 (801-2) is completed is called a line period. That is, from the time when the writing of the divided video signal to the latch circuit of the leftmost stage in the latch circuit 1 (801-2) starts, the writing of the divided video signal to the latch circuit of the rightmost stage ends. The time interval up to the point in time is the line period. Actually, a period in which the horizontal retrace period is added to the line period may be referred to as a line period.

After the end of one line period, the latch circuit 2 (8
01-3), a latch signal is supplied. At this moment, the divided video signal written and held in the latch circuit 1 (801-2) is
(801-3) and sent to the latch circuit 2 (80
The data is written and held in the latch circuits of all the stages in 1-3).

The divided video signal is supplied to the latch circuit 2 (801-
The latch circuit 1 (801-2) that has finished sending to 3) has:
Based on the timing signal from the shift register circuit 801-1, writing of divided video signals supplied again from the buffer circuit 709 via the divided video signal lines is performed sequentially m by m.

During the second one line period, the divided video signals written and held in the latch circuit 2 (801-3) are sequentially selected by the selector circuit 1 (801-4). / A conversion circuit (DAC) 801-5
Supplied to

The divided video signal selected by the selector circuit 801-4 is supplied to the DAC 801-5.

The DAC 801-5 converts the digital divided video signal into m analog divided video signals, and sequentially supplies the m divided video signals to the source signal lines selected by the selector circuit 2 (801-6).

In this embodiment, the selector circuit 2 (801-801)
6), the second exchange signal is input from the exchange data processing circuit 711. Selector circuit 1 (801-
4), according to the second replacement signal input from the replacement data processing circuit 711, m analog divided video signals output from the DAC 801-5 are respectively input to specific source signal lines. That is, each of the m divided video signals (Vs1 to Vsm) is converted into one of the buffer circuits (709_1 to 709_m) by the first replacement signal.
, The m analog divided video signals (Vs1-Vs) output from the DAC 801-5.
m) is input to each of m predetermined source signal lines.

The first replacement signal and the second replacement signal are:
It is generated by inputting a replacement data signal to the replacement data processing circuit 711. The exchange data signal is generated in an exchange data circuit 706. Note that the operation of the replacement data circuit 706 in this embodiment is the same as the operation of the replacement data circuit in the case of analog driving described in the embodiment.

The analog divided video signal supplied to the source signal line is supplied to the source region of the pixel TFT of the pixel connected to the source signal line.

In the gate signal line driving circuit 802,
A timing signal from a shift register (not shown) is supplied to a buffer circuit (not shown) and supplied to a corresponding gate signal line (scanning line). The gate signal line is connected to the gate electrode of the pixel TFT for one line.
Since all pixel TFTs for a line must be turned on at the same time, a buffer circuit having a large current capacity is used.

As described above, the gate signal line driving circuit 802
The switching of the corresponding pixel TFT is performed by the selection signal from, the analog divided video signal from the source signal line driving circuit is supplied to the pixel TFT, and the liquid crystal molecules are driven.

According to the present invention, a buffer circuit having different characteristics due to the above-described configuration and a D / D circuit included in a source signal line driving circuit are provided.
Even if a divided video signal output from the A-conversion circuit has a potential difference between the divided video signal and another divided video signal, a bright and dark fringe (divided fringe) is displayed on the screen, and the divided fringe is displayed every certain period. The position where the divisional stripe is displayed moves. Therefore, even if the divisional stripes are displayed on the screen, it is difficult for the observer to visually recognize the divisional stripes.

In the present invention, it is important to set the period from the time when the combination of the divided video signal and the buffer circuit is changed to the time when the combination is changed again to such a length that the divided stripes are difficult to be visually recognized by an observer. It is. The period from the change of the combination of the buffer circuits to the next change of the combination is, in other words, the period from the change of the counter value to the change of the counter value again. During that period, the first replacement signal and the second
This corresponds to a period from when the information of the switching signal changes to when the information of the first switching signal and the information of the second switching signal change next.

[0177] It is preferable that the period until the combination of the divided video signal and the buffer circuit is changed is shorter, and the divided stripes are more difficult to be visually recognized by the observer. The period until the combination of the divided video signal and the buffer circuit changes is 1 / 20s
ec or less. In this embodiment, the setting is made so that the combination of the divided video signal and the buffer circuit changes every frame period.

Therefore, according to the present invention, when performing the division driving, it is difficult for the observer to visually recognize the divisional stripes. Even by increasing the number of pixels in the horizontal direction of the active matrix type semiconductor display device, it is possible to suppress flickering and flickering of the displayed image while suppressing the driving frequency of the source signal line driving circuit, by performing the division driving. It is possible to display a high-resolution, multi-tone image.

The present invention is not limited to the configurations shown in FIGS. For each predetermined period, a plurality of buffer circuits and a combination of a plurality of divided video signals input to the plurality of buffer circuits are arbitrarily rearranged, and the plurality of divided video signals are sampled and the corresponding source signals are respectively obtained. What is necessary is just to have the structure input to a line.

Embodiment 6 FIG. 16 shows an example in which an active matrix type liquid crystal display device is formed using the active matrix substrates having the structures shown in Embodiments 1 to 5.
FIG. 16 shows a portion corresponding to a display of an active matrix liquid crystal display device, which is also called a liquid crystal panel. In this embodiment, since a portion of the liquid crystal panel to be bonded to the FPC is described, a sealing material and a cell component are not shown for convenience.

In FIG. 16, reference numeral 8001 denotes an active matrix substrate;
A plurality of TFTs are formed on one. These TFTs
Denotes a pixel portion 8002 and a gate signal line driving circuit 80 on a substrate.
03, constituting the source signal line driving circuit 8004. A counter substrate 800 for such an active matrix substrate
6 are pasted together. Liquid crystal (not shown) is interposed between the active matrix substrate and the counter substrate 8006.

In the structure shown in FIG. 16, it is desirable that the side surface of active matrix substrate 8001 and the side surface of counter substrate 8006 are all aligned except for one side.
This makes it possible to efficiently increase the number of multi-face removal from the large-size substrate. Further, in the above-mentioned one side, the opposite substrate 8
006 to remove the active matrix substrate 80
01 and expose FPC (flexible
(Print Circuit) 8007 is attached. FPC
A circuit group for generating a divided video signal of the present invention, which is provided on an IC chip, is connected to a gate signal line driving circuit 8003 and a source signal line driving circuit 8004 of the active matrix substrate 8001 provided on an IC chip via 8007.

(Embodiment 7) In this embodiment, an example of a method for manufacturing an active matrix liquid crystal display device which is one of the semiconductor display devices of the present invention will be described with reference to FIGS. Here, a method is described in which a pixel TFT in a pixel portion and a TFT of a driver circuit (a source signal line driver circuit, a gate signal line driver circuit, a D / A conversion circuit, and the like) provided around the pixel portion are formed over the same substrate. Will be described in detail. However, for the sake of simplicity, a CMOS circuit, which is a basic circuit such as a shift register circuit, a buffer circuit, and a D / A conversion circuit, and an n-channel TFT are illustrated in the driving circuit.

In FIG. 18A, a low alkali glass substrate or a quartz substrate can be used as a substrate (active matrix substrate) 6001. In this embodiment, a low alkali glass substrate was used. In this case, heat treatment may be performed in advance at a temperature lower by about 10 to 20 ° C. than the glass strain point. A base film 6002 such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed on a surface of the substrate 6001 where a TFT is to be formed, in order to prevent impurity diffusion from the substrate 6001. For example, plasma C
A silicon oxynitride film formed from SiH ₄ , NH ₃ , and N ₂ O is formed to a thickness of 100 nm by the VD method, and a silicon oxynitride film formed from SiH ₄ and N ₂ O is similarly formed to a thickness of 200 nm.

Next, 20 to 150 nm (preferably 30 to 150 nm)
Semiconductor film 60 having an amorphous structure with a thickness of
03a is formed by a known method such as a plasma CVD method or a sputtering method. In this embodiment, an amorphous silicon film is formed to a thickness of 55 nm by a plasma CVD method. As the semiconductor film having an amorphous structure, there are an amorphous semiconductor film and a microcrystalline semiconductor film, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be used.
In addition, since the base film 6002 and the amorphous silicon film 6003a can be formed by the same film formation method, both may be formed continuously. After the formation of the base film, it is possible to prevent the surface from being contaminated by not once exposing it to the atmosphere, thereby reducing the variation in the characteristics of the TFT to be manufactured and the fluctuation of the threshold voltage. (FIG. 18A)

Then, the amorphous silicon film 6003a is removed from the crystalline silicon film 6003a using a known crystallization technique.
b is formed. For example, a laser crystallization method or a thermal crystallization method (solid phase growth method) may be applied. At the time of laser crystallization, a continuous emission excimer laser may be used. Here, a crystalline silicon film 6003b was formed by a crystallization method using a catalytic element according to the technique disclosed in Japanese Patent Application Laid-Open No. Hei 7-130652. Prior to the crystallization step, depending on the hydrogen content of the amorphous silicon film, 400 to 500
Heat treatment at ℃ for about 1 hour, hydrogen content is 5 atomic
% Or less. When the amorphous silicon film is crystallized, the rearrangement of atoms occurs and the density of the amorphous silicon film is increased. Also decreased by about 1 to 15%. (FIG. 18 (B))

Then, the crystalline silicon film 6003b is divided into islands to form island-like semiconductor layers 6004 to 6007. After that, a mask layer 6008 made of a silicon oxide film having a thickness of 50 to 100 nm is formed by a plasma CVD method or a sputtering method. (FIG. 18 (C))

Then, a resist mask 6009 is provided, and n
Island-shaped semiconductor layers 6005 to 6 forming a channel type TFT
1 × 10 for the purpose of controlling the threshold voltage over the entire surface of 007
Boron (B) was added as an impurity element imparting p-type at a concentration of about ^{16 to} 5 × 10 ¹⁷ atoms / cm ³ . Boron (B) may be added by an ion doping method, or may be added simultaneously with the formation of the amorphous silicon film. Although addition of boron (B) is not always necessary here, the semiconductor layer 6010 to which boron (B) is added is added.
6012 was preferably formed to keep the threshold voltage of the n-channel TFT within a predetermined range.
(FIG. 18D)

LDD region of n-channel type TFT of drive circuit
In order to form the region, the impurity element imparting n-type
It is selectively added to the semiconductor layers 6010 and 6011. That
Therefore, the resist masks 6013 to 6016 are
Formed. As an impurity element imparting n-type, phosphorus
(P) or arsenic (As) may be used.
Phosphine (PH) to add (P)_Three)
An ion doping method was applied. Impurity region 60 formed
The phosphorus (P) concentration of 17, 6018 is 2 × 10¹⁶~ 5 × 1
0¹⁹atoms / cm^ThreeShould be within the range. In this specification,
Included in impurity regions 6017 to 6019 formed here
(N) ^-) And table
You. Further, the impurity region 6019 serves as a storage capacitor of the pixel portion.
This is the semiconductor layer to be formed.
Added phosphorus (P). (FIG. 19A)

Next, a step of removing the mask layer 6008 with hydrofluoric acid or the like to activate the impurity element added in FIGS. 18D and 19A is performed. The activation can be performed by a heat treatment at 500 to 600 ° C. for 1 to 4 hours in a nitrogen atmosphere or a laser activation method. Further, both may be performed in combination. In the present embodiment, a KrF excimer laser beam (wavelength 2
48 nm) to form a linear beam, an oscillation frequency of 5 to 300 Hz, and an energy density of 100 to 500 mJ /
cm ^{2 and the} overlap ratio of the linear beam is 50 to
By scanning at 90%, the entire surface of the substrate on which the island-shaped semiconductor layer was formed was processed. There are no particular restrictions on the laser light irradiation conditions, and the conditions may be determined appropriately by the practitioner. Activation may be performed using a continuous light excimer laser.

Then, the gate insulating film 6020 is formed of an insulating film containing silicon with a thickness of 10 to 150 nm by a plasma CVD method or a sputtering method. For example, 12
A silicon oxynitride film is formed with a thickness of 0 nm. As the gate insulating film, another insulating film containing silicon may be used as a single layer or a stacked structure. (FIG. 19B)

Next, a first conductive layer is formed to form a gate electrode. The first conductive layer may be formed as a single layer, or may be formed as a two-layer or three-layer structure as necessary. In this embodiment, a conductive layer (A) 6021 made of a conductive nitride metal film and a conductive layer (B) 6022 made of a metal film are stacked. Conductive layer (B) 602
2 is an element selected from tantalum (Ta), titanium (Ti), molybdenum (Mo), and tungsten (W), an alloy containing the above elements as a main component, or an alloy film combining the above elements (typically, The conductive layer (A) 6021 may be formed of tantalum nitride (TaN), tungsten nitride (WN), titanium nitride (TiN), or molybdenum nitride (MoN). Form. The conductive layer (A) 6021 is used as an alternative material.
Tungsten silicide, titanium silicide, or molybdenum silicide may be used. The conductive layer (B) may have a low impurity concentration in order to reduce the resistance, and it is particularly preferable that the oxygen concentration be 30 ppm or less. For example, tungsten (W) has an oxygen concentration of 30.
A specific resistance of 20 μΩcm or less could be realized by setting the content to ppm or less.

The conductive layer (A) 6021 has a thickness of 10 to 50 nm.
(Preferably 20 to 30 nm), and the conductive layer (B) 60
22 is 200 to 400 nm (preferably 250 to 350 nm)
nm). In this embodiment, the conductive layer (A) 60
A 21 nm-thick tantalum nitride film was used for 21, and a 350 nm-thick Ta film was used for the conductive layer (B) 6022, both of which were formed by sputtering. In the film formation by the sputtering method, if an appropriate amount of Xe or Kr is added to Ar of the gas for sputtering, the internal stress of the film to be formed can be relaxed and the film can be prevented from peeling. Although not shown, it is effective to form a silicon film doped with phosphorus (P) with a thickness of about 2 to 20 nm under the conductive layer (A) 6021. Thereby, the adhesion of the conductive film formed thereon is improved and oxidation is prevented, and at the same time, a small amount of the alkali metal element contained in the conductive layer (A) or the conductive layer (B) diffuses into the gate insulating film 6020. Can be prevented.
(FIG. 19C)

Next, resist masks 6023 to 6027
Are formed, and a conductive layer (A) 6021 and a conductive layer (B) 602 are formed.
2 and the gate electrodes 6028-60
31 and a capacitor wiring 6032 are formed. Gate electrode 602
8 to 6031 and the capacitor wiring 6032 are formed integrally with 6028a to 6032a made of a conductive layer (A) and 6028b to 6032b made of a conductive layer (B). At this time, a gate electrode 6029 formed in the driver circuit,
6030 is formed so as to overlap with part of the impurity regions 6017 and 6018 with the gate insulating film 6020 interposed therebetween.
(FIG. 19D)

Next, in order to form a source region and a drain region of the p-channel TFT of the driver circuit, a step of adding an impurity element imparting p-type is performed. Here, the impurity region is formed in a self-aligned manner using the gate electrode 6028 as a mask. At this time, the n-channel TFT
Are formed with a resist mask 6033. Then, an impurity region 6034 was formed by an ion doping method using diborane (B ₂ H ₆ ). The boron (B) concentration in this region is set to 3 × 10 ^{20 to} 3 × 10 ²¹ atoms / cm ³ . In this specification, the concentration of the impurity element imparting p-type contained in the impurity region 6034 formed here is expressed as (p ⁺ ). (FIG. 20A)

Next, in the n-channel TFT, an impurity region functioning as a source region or a drain region was formed. Resist masks 6035 to 6037 were formed, and an impurity element imparting n-type was added to form impurity regions 6038 to 6042. This is performed by an ion doping method using phosphine (PH ₃ ), and the concentration of phosphorus (P) in this region is set to 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ^3.
And In this specification, the concentration of the impurity element imparting n-type contained in the impurity regions 6038 to 6042 formed here is expressed as (n ⁺ ). (FIG. 20 (B))

The impurity regions 6038 to 6042 contain phosphorus (P) or boron (B) already added in the previous step, but phosphorus (P) is added at a sufficiently high concentration. Therefore, it is not necessary to consider the influence of phosphorus (P) or boron (B) added in the previous step.
The concentration of phosphorus (P) added to impurity region 6038 is １ ／ of the concentration of boron (B) added in FIG.
Since it was １ ／, p-type conductivity was ensured, and there was no effect on the characteristics of the TFT.

The L of the n-channel TFT in the pixel portion is
An n-type impurity-imparting process for forming a DD region was performed. Here, an impurity element imparting n-type in a self-aligned manner is added by an ion doping method using the gate electrode 6031 as a mask. The concentration of phosphorus (P) to be added is 1 × 1
0 ^{16 to} 5 × 10 ¹⁸ atoms / cm ^3, which is substantially lower than that of the impurity element added in FIGS. 19A, 20A, and 20B. Only impurity regions 6043 and 6044 are formed. In this specification, n included in impurity regions 6043 and 6044
The concentration of the impurity element imparting the mold is represented by (n ⁻ ). (FIG. 20 (C))

Thereafter, a heat treatment step is performed to activate the impurity elements imparting n-type or p-type added at the respective concentrations. This step can be performed by a furnace annealing method, a laser annealing method, or a rapid thermal annealing method (RTA method). Here, the activation step was performed by the furnace annealing method. The heat treatment is performed in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less, at 400 to 800 ° C, typically 500 to 600 ° C.
In this embodiment, the heat treatment was performed at 550 ° C. for 4 hours. When a substrate having heat resistance such as a quartz substrate is used as the substrate 6001,
The heat treatment may be performed for a long time, and the activation of the impurity element and the junction between the impurity region to which the impurity element is added and the channel formation region can be favorably formed.

In this heat treatment, the gate electrode 6028
Film 6028 for forming the capacitor wiring 6032 with the capacitor wiring 6032
In b to 6032b, conductive layers (C) 6028c to 6032c are formed with a thickness of 5 to 80 nm from the surface.
For example, when the conductive layers (B) 6028b to 6032b are tungsten (W), tungsten nitride (WN) is formed, and when tantalum (Ta) is used, tantalum nitride (TN) is formed.
aN). In the present invention, a laminate of a silicon (Si) film, a WN film and a W film,
The gate electrode may be formed using a stacked film of a W film having i, a stacked film of a W film and a W film having Si, and Si, a W film having Mo, or a Ta film having Mo. The conductive layers (C) 6028c to 6032c are
The gate electrodes 6028 to 6031 can be similarly formed by exposing the gate electrodes 6028 to 6031 to a plasma atmosphere containing nitrogen using nitrogen or ammonia. Further, heat treatment was performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% of hydrogen to hydrogenate the island-shaped semiconductor layer. In this step, dangling bonds in the semiconductor layer are terminated by thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma or hydrogen converted into plasma) may be performed.

The island-like semiconductor layer is formed from an amorphous silicon film.
When produced by the crystallization method using a medium element,
A trace amount of catalytic element remained in the conductor layer. Of course
It is possible to complete the TFT in such a state,
Remove the remaining catalyst element from at least the channel formation region.
I preferred to leave. Remove this catalytic element
Utilizing the gettering action of phosphorus (P) as one of the means
There was a way to do that. Phosphorus (P) required for gettering
The concentration is the impurity region (n ⁺Same as)
Of the activation process performed here.
And n-channel TFT and p-channel TFT.
Gettering the catalytic element from the channel formation region
Was completed. (FIG. 20 (D))

When the activation and hydrogenation steps are completed,
A second conductive film serving as a gate wiring is formed. This second conductive film is formed by adding a conductive layer (D) mainly composed of aluminum (Al) or copper (Cu), which is a low-resistance material, to titanium (T
i) or a conductive layer (E) made of tantalum (Ta), tungsten (W), or molybdenum (Mo). In this embodiment, titanium (Ti) is contained in an amount of 0.1 to 2% by weight.
The aluminum (Al) film containing the conductive film was formed as a conductive layer (D) 6045, and the titanium (Ti) film was formed as a conductive layer (E) 6046. The conductive layer (D) 6045 has a thickness of 200 to 400 nm.
(Preferably 250 to 350 nm), and the conductive layer (E) 6046 has a thickness of 50 to 200 nm (preferably 10 to 200 nm).
(0-150 nm). (FIG. 21A)

Then, a conductive layer (E) 6046 and a conductive layer (D) are formed to form a gate wiring connected to the gate electrode.
6045 and the gate wiring 604
7, 6048 and a capacitor wiring 6049 were formed. In the etching treatment, first, a part of the conductive layer (D) is removed from the surface of the conductive layer (E) by a dry etching method using a mixed gas of SiCl ₄ , Cl ₂ and BCl _3, and then a phosphoric acid-based etching solution is used. Conductive layer (D) by wet etching
As a result, the gate wiring could be formed while maintaining the selectivity with the base. (FIG. 21 (B))

The first interlayer insulating film 6050 is 500 to 15
A contact hole which is formed of a silicon oxide film or a silicon oxynitride film with a thickness of 00 nm and reaches a source region or a drain region formed in each of the island-shaped semiconductor layers is formed.
Then, drain wirings 6055 to 6058 are formed. Although not shown, in this embodiment, this electrode is
A three-layer laminated film in which 0 nm, an aluminum film containing Ti, 300 nm, and a Ti film, 150 nm, were continuously formed by a sputtering method.

Next, as the passivation film 6059, a silicon nitride film, a silicon oxide film, or a silicon nitride oxide film is formed to a thickness of 50 to 500 nm (typically, 100 to 3 nm).
(00 nm). When hydrogenation was performed in this state, favorable results were obtained with respect to the improvement of TFT characteristics. For example, in an atmosphere containing 3 to 100% hydrogen, 3
It is good to perform heat treatment at 00 to 450 ° C. for 1 to 12 hours,
Alternatively, the same effect was obtained by using the plasma hydrogenation method. Here, at a position where a contact hole for connecting the pixel electrode and the drain wiring is formed later,
An opening may be formed in the passivation film 6059. (FIG. 21 (C))

Thereafter, a second interlayer insulating film 6060 made of an organic resin is formed to a thickness of 1.0 to 1.5 μm. As the organic resin, polyimide, acrylic, polyamide,
Polyimide amide, BCB (benzocyclobutene) and the like can be used. Here, a polyimide of a type that is thermally polymerized after being applied to the substrate and baked at 300 ° C. is used. Then, a contact hole reaching the drain wiring 6058 is formed in the second interlayer insulating film 6060 and the passivation film 6059, and the pixel electrodes 6061 and 6061 are formed.
62 is formed. As the pixel electrode, a transparent conductive film may be used for a transmission type liquid crystal display device, and a metal film may be used for a reflection type liquid crystal display device. In this embodiment, an indium tin oxide (ITO) film is formed to a thickness of 100 nm by a sputtering method in order to obtain a transmission type liquid crystal display device. (FIG. 22)

Thus, the TFT of the driving circuit is formed on the same substrate.
And a substrate having pixel TFTs in the pixel portion. The driving circuit includes a p-channel TFT 6101,
A first n-channel TFT 6102, a second n-channel TFT 6103, a pixel TFT 6104 in the pixel portion, and a storage capacitor 6105 were formed. In this specification, such a substrate is referred to as an active matrix substrate for convenience.

In the p-channel TFT 6101 of the driver circuit, the channel formation region 610 is formed in the island-shaped semiconductor layer 6004.
6, source regions 6107a and 6107b, and drain regions 6108a and 6108b. In the first n-channel TFT 6102, an L overlapping the channel formation region 6109 and the gate electrode 6029 in the island-shaped semiconductor layer 6005.
DD region 6110 (hereinafter, such an LDD region is referred to as Lov
, Source region 6111 and drain region 6112
have. The length of the Lov region in the channel length direction is 0.5 to 3.0 μm, preferably 1.0 to 1.5 μm. The second n-channel TFT 6103 includes a channel formation region 6113, LDD regions 6114 and 6115, a source region 6116, and a drain region 6117 in the island-shaped semiconductor layer 6006. This LDD region is an LDD region that does not overlap with the Lov region and the gate electrode 6030 (hereinafter referred to as an LDD region).
Such an LDD region is referred to as Loff).
The length of the Loff region in the channel length direction is 0.3 to 2.
0 μm, preferably 0.5 to 1.5 μm. Pixel T
In the FT 6104, channel formation regions 6118 and 6119 and Loff regions 6120 to 61 are formed in the island-shaped semiconductor layer 6007.
23, a source or drain region 6124-6126. The length of the Loff region in the channel length direction is 0.
It is 5-3.0 μm, preferably 1.5-2.5 μm. Further, the capacitor wirings 6032 and 6049, an insulating film made of the same material as the gate insulating film, and a pixel TFT 6104
From the semiconductor layer 6127 to which the impurity element imparting n-type is added.
105 is formed. In FIG. 22, the pixel TFT 610
4 has a double gate structure, but may have a single gate structure or a multi-gate structure provided with a plurality of gate electrodes.

As described above, in the present embodiment, the TFTs constituting each circuit according to the specifications required by the pixel TFT and the driving circuit.
By optimizing the structure of the FT, it is possible to improve the operation performance and reliability of the semiconductor display device. Further, the gate electrode is formed of a conductive material having heat resistance, thereby facilitating activation of the LDD region, the source region, and the drain region, and the wiring resistance can be sufficiently reduced by forming the gate wiring with a low-resistance material. Therefore, the present invention can be applied to a display device having a pixel portion (screen size) of 4 inch class or more.

[0210] In this embodiment, the transmission type liquid crystal panel has been described. However, the present invention is not limited to this, and can be used for a reflective liquid crystal panel.

Embodiment 8 In this embodiment, an example in which a light emitting device is manufactured by using the present invention will be described.

The light emitting device is a self light emitting type, unlike the liquid crystal display device. A light-emitting element has a structure in which a layer containing an organic compound (hereinafter, referred to as an organic compound layer) is sandwiched between a pair of electrodes (anode and cathode), and the organic compound layer usually has a laminated structure. I have. A typical example is a laminated structure of “hole transport layer / light emitting layer / electron transport layer” proposed by Tang et al. Of Kodak Eastman Company. This structure has a very high luminous efficiency, and most light emitting devices currently under research and development are adopting this structure.

[0213] The light emitting element has an anode layer, an organic compound layer, and a cathode layer when luminescence (Electro Luminescence) generated by applying an electric field is obtained. Luminescence of an organic compound includes light emission (fluorescence) when returning from a singlet excited state to a ground state and light emission (phosphorescence) when returning to a ground state from a triplet excited state. Either light emission may be used.

FIG. 23A is a top view of a light emitting device using the present invention. In FIG. 23A, reference numeral 4010 denotes a substrate, 4011 denotes a pixel portion, 4012 denotes a source signal line driver circuit, 4013 denotes a gate signal line driver circuit, and each driver circuit is connected to the FPC 40 via wirings 4014 to 4016.
17 and is connected to a circuit group for generating a divided video signal of the present invention.

At this time, the cover material 600 is formed so as to surround at least the pixel portion, preferably the driving circuit and the pixel portion.
0, sealing material (also referred to as housing material) 7000,
A sealing material (a second sealing material) 7001 is provided.

FIG. 23B shows a cross-sectional structure of the light emitting device of this embodiment, in which a TFT for a driving circuit (here, n-channel type TF) is provided on a substrate 4010 and a base film 4021.
A CMOS circuit combining a T and a p-channel TFT is illustrated) 4022 and a TFT 4023 for a pixel portion.
(However, here, only the TFT for controlling the current to the light emitting element is shown). These TFTs
A known structure (a top gate structure or a bottom gate structure) may be used.

TFT 4022 for drive circuit, TF for pixel portion
When T4023 is completed, a pixel electrode 4027 made of a transparent conductive film electrically connected to the drain of the pixel portion TFT 4023 is formed on an interlayer insulating film (flattening film) 4026 made of a resin material. As the transparent conductive film, a compound of indium oxide and tin oxide (called ITO) or a compound of indium oxide and zinc oxide can be used. After the pixel electrode 4027 is formed, an insulating film 4028 is formed, and an opening is formed over the pixel electrode 4027.

Next, an organic compound layer 4029 is formed.
The organic compound layer 4029 has a stacked structure formed by freely combining known organic compound materials (a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, or an electron injection layer) capable of obtaining luminescence generated by applying an electric field. Alternatively, a single-layer structure may be used. A known technique may be used to determine the structure. Organic compound materials include low molecular weight materials and high molecular weight (polymer) materials. When a low molecular material is used, an evaporation method is used. When a high molecular material is used, a simple method such as a spin coating method, a printing method, or an ink jet method can be used.

In this embodiment, an organic compound layer is formed by an evaporation method using a shadow mask. By forming a light-emitting layer (a red light-emitting layer, a green light-emitting layer, and a blue light-emitting layer) capable of emitting light having different wavelengths for each pixel using a shadow mask, color display becomes possible. In addition, there are a method in which a color conversion layer (CCM) and a color filter are combined, and a method in which a white light emitting layer and a color filter are combined, and any method may be used. Needless to say, a light emitting device that emits monochromatic light can also be used.

After forming the organic compound layer 4029, the cathode 4030 is formed thereon. It is desirable to remove moisture and oxygen existing at the interface between the cathode 4030 and the organic compound layer 4029 as much as possible. Therefore, it is necessary to devise a method of continuously forming the organic compound layer 4029 and the cathode 4030 in a vacuum, or forming the organic compound layer 4029 in an inert atmosphere and forming the cathode 4030 without opening to the atmosphere. In this embodiment, the above-described film formation is made possible by using a multi-chamber type (cluster tool type) film formation apparatus.

In this embodiment, the cathode 4030 is
A laminated structure of a LiF (lithium fluoride) film and an Al (aluminum) film is used. Specifically, the organic compound layer 4029
A LiF (lithium fluoride) film having a thickness of 1 nm is formed thereon by a vapor deposition method, and an aluminum film having a thickness of 300 nm is formed thereon. Of course, a MgAg electrode which is a known cathode material may be used. The cathode 4030 is connected to the wiring 4016 in a region indicated by 4031. The wiring 4016 is a power supply line for applying a predetermined voltage to the cathode 4030, and the FPC 40 through a conductive paste material 4032.
17 is connected.

In the region indicated by 4031, the cathode 40
In order to electrically connect the wiring 30 and the wiring 3016, it is necessary to form contact holes in the interlayer insulating film 4026 and the insulating film 4028. These are at the time of etching the interlayer insulating film 4026 (at the time of forming the contact hole for the pixel electrode).
Or at the time of etching the insulating film 4028 (at the time of forming the opening before forming the organic compound layer). Further, when the insulating film 4028 is etched, an interlayer insulating film 4026 is formed.
Etching may be performed all at once. In this case, if the interlayer insulating film 4026 and the insulating film 4028 are the same resin material,
The shape of the contact hole can be made good.

The passivation film 6003 and the filler 600 cover the surface of the light emitting element thus formed.
4. The cover material 6000 is formed.

Further, the sealing material 7000 and the sealing material 7 are provided inside the substrate 4010 so as to surround the light emitting element portion.
000 is provided, and a sealing material (second sealing material) 7001 is formed outside the sealing material 7000.

At this time, the filler 6004 also functions as an adhesive for bonding the cover material 6000.
As the filler 6004, PVC (polyvinyl chloride), epoxy resin, silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. It is preferable to provide a desiccant inside the filler 6004 because a moisture absorbing effect can be maintained.

[0226] The filler 6004 may contain a spacer. At this time, the spacer may be a granular substance made of BaO or the like, and the spacer itself may have hygroscopicity.

In the case where a spacer is provided, the passivation film 6003 can reduce the spacer pressure.
Further, a resin film or the like for relaxing the spacer pressure may be provided separately from the passivation film.

As the cover member 6000, a glass plate, an aluminum plate, a stainless steel plate, FRP (Five)
rglass-Reinforced Plastic
s) plate, PVF (polyvinyl fluoride) film,
Mylar film, polyester film or acrylic film can be used. The filling material 600
When PVB or EVA is used as 4, it is preferable to use a sheet having a structure in which aluminum foil of several tens of μm is sandwiched between PVF films or Mylar films.

However, depending on the direction of light emission (the direction of light emission) from the light emitting element, the cover material 6000 needs to have a light transmitting property.

Further, the wiring 4016 is made of the sealing material 700.
0 and through the gap between the sealing material 7001 and the substrate 4010, and is electrically connected to the FPC 4017. Although the wiring 4016 has been described here, the other wiring 401
4, 4015 are similarly electrically connected to the FPC 4017 under the sealant 7000 and the sealant 7001.

In this embodiment, after the filler 6004 is provided, the cover 6000 is adhered, and the sealing material 7000 is attached so as to cover the side surface (exposed surface) of the filler 6004. Lumber 70
After attaching 00, the filler 6004 may be provided. In this case, an injection port for a filler is provided to communicate with a space formed by the substrate 4010, the cover material 6000, and the sealing material 7000. Then, the gap is vacuumed (10
^-2 Torr or less), immerse the injection port in the water tank containing the filler, and then fill the gap with the filler by setting the pressure outside the gap higher than the pressure inside the gap.

(Embodiment 9) In this embodiment, an example in which a light-emitting device having a mode different from that of Embodiment 8 is manufactured by using the present invention will be described with reference to FIGS. 23 (A) and 23 (B) denote the same parts, and a description thereof will not be repeated.

FIG. 24A is a top view of the light emitting device of this embodiment, and FIG. 24B is a cross-sectional view taken along line AA ′ of FIG.

According to Embodiment 8, a passivation film 6003 is formed to cover the surface of the light emitting element.

[0235] Further, a filler 6004 is provided so as to cover the light-emitting element. This filler 6004 is used as the cover material 6
000 also functions as an adhesive for bonding. As the filler 6004, PVC (polyvinyl chloride), epoxy resin, silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. It is preferable to provide a desiccant inside the filler 6004 because a moisture absorbing effect can be maintained.

[0236] A spacer may be contained in the filler 6004. At this time, the spacer may be a granular substance made of BaO or the like, and the spacer itself may have hygroscopicity.

In the case where a spacer is provided, the passivation film 6003 can reduce the spacer pressure.
Further, a resin film or the like for relaxing the spacer pressure may be provided separately from the passivation film.

As the cover material 6000, a glass plate, an aluminum plate, a stainless steel plate, FRP (Fiber)
rglass-Reinforced Plastic
s) plate, PVF (polyvinyl fluoride) film,
Mylar film, polyester film or acrylic film can be used. The filling material 600
When PVB or EVA is used as 4, it is preferable to use a sheet having a structure in which aluminum foil of several tens of μm is sandwiched between PVF films or Mylar films.

However, depending on the direction of light emission from the light emitting element (the direction of light emission), the cover material 6000 needs to have a light transmitting property.

Next, the cover material 6
After bonding 000, the side surface of filler 6004 (exposed surface)
Frame material 6001 is attached so as to cover. The frame material 6001 is a sealing material (functions as an adhesive)
Glued by 6002. At this time, a photocurable resin is preferably used as the sealing material 6002, but a thermosetting resin may be used as long as heat resistance of the organic compound layer is allowed. Note that the sealing material 6002 is preferably a material that does not transmit moisture or oxygen as much as possible. Further, a desiccant may be added to the inside of the sealing material 6002.

The wiring 4016 is made of a sealing material 600.
2 is electrically connected to the FPC 4017 through a gap between the substrate 2 and the substrate 4010. Note that although the wiring 4016 has been described here, the other wirings 4014 and 4015 are also electrically connected to the FPC 4017 under the sealing material 6002 in the same manner. Wiring 4014, 4 via FPC
Reference numerals 015 and 4016 are connected to a circuit group for generating a divided video signal according to the present invention.

In this embodiment, after the filling material 6004 is provided, the cover material 6000 is adhered, and the frame material 6001 is attached so as to cover the side surface (exposed surface) of the filling material 6004. Lumber 6001
And then the filler 6004 may be provided. In this case, an inlet for a filler is provided to communicate with a gap formed by the substrate 4010, the cover member 6000, and the frame member 6001. Then, the gap is evacuated (10 ^-2 Torr).
r), the filler is filled in the gap by immersing the injection port in the water tank containing the filler, and then making the pressure outside the gap higher than the pressure inside the gap.

(Embodiment 10) FIG. 25 shows a more detailed sectional structure of a pixel portion in a display panel, FIG. 26A shows a top structure thereof, and FIG. 26B shows a circuit diagram thereof. FIG.
5, common reference numerals are used in FIGS. 26 (A) and 26 (B), so that they may be referred to each other.

In FIG. 25, a switching TFT 3502 provided on a substrate 3501 is formed using an N-channel TFT manufactured by a known method. In this embodiment, a double gate structure is used. However, since there is no significant difference in the structure and the manufacturing process, the description is omitted. However,
The double gate structure has a structure in which substantially two TFTs are connected in series, and has an advantage that an off-current value can be reduced. Although the double gate structure is used in this embodiment, a single gate structure, a triple gate structure, or a multi-gate structure having more gates may be used. In addition, P-channel type T
It may be formed using FT.

The current controlling TFT 3503 is formed using an N-channel TFT manufactured by a known method. At this time, the drain wiring 35 of the switching TFT 3502 is electrically connected to the gate electrode 37 of the current controlling TFT by the wiring 36. The wiring indicated by 38 is a gate wiring for electrically connecting the gate electrodes 39a and 39b of the switching TFT 3502.

[0246] The current control TFT is an element for controlling the amount of current flowing through the light-emitting element, so that a large amount of current flows and the element has a high risk of deterioration due to heat or deterioration due to hot carriers. Therefore, the structure of the present invention in which the LDD region is provided on the drain side of the current controlling TFT so as to overlap the gate electrode via the gate insulating film is extremely effective.

In this embodiment, the current controlling TFT 35 is used.
03 is shown with a single gate structure.
A multi-gate structure in which FTs are connected in series may be used.
Further, a structure in which a plurality of TFTs are connected in parallel to substantially divide the channel formation region into a plurality of regions so that heat can be radiated with high efficiency may be employed. Such a structure is effective as a measure against deterioration due to heat.

As shown in FIG. 26A, the wiring which becomes the gate electrode 37 of the current controlling TFT 3503 has 35
In a region indicated by 04, the region overlaps with the drain wiring 40 of the current control TFT 3503 via an insulating film. At this time, 3
In the region indicated by 504, a capacitor is formed. This capacitor 3504 functions as a capacitor for holding a voltage applied to the gate of the current control TFT 3503. The drain wiring 40 is connected to a current supply line (power supply line) 3506, and a constant voltage is constantly applied.

The first passivation film 4 is formed on the switching TFT 3502 and the current control TFT 3503.
And a planarizing film 42 made of a resin insulating film thereon.
Is formed. It is very important to flatten the steps due to the TFT using the flattening film 42. Since an organic compound layer to be formed later is very thin, poor light emission may be caused by the presence of a step. Therefore, it is desirable that the organic compound layer be planarized before forming the pixel electrode so that the organic compound layer can be formed as flat as possible.

Reference numeral 43 denotes a pixel electrode (cathode of a light emitting element) made of a highly reflective conductive film.
503 is electrically connected to the drain. Pixel electrode 43
It is preferable to use a low-resistance conductive film such as an aluminum alloy film, a copper alloy film, or a silver alloy film, or a stacked film thereof. Of course, a stacked structure with another conductive film may be employed.

The light emitting layer 45 is formed in a groove (corresponding to a pixel) formed by the banks 44a and 44b formed of an insulating film (preferably resin). Although only one pixel is shown here, R (red), G (green),
Light emitting layers corresponding to each color of B (blue) may be separately formed.
As the organic compound material for the light emitting layer, a π-conjugated polymer material is used. Typical polymer-based materials include polyparaphenylenevinylene (PPV), polyvinylcarbazole (PVK), and polyfluorene.

Although there are various types of PPV-based organic compound materials, for example, H. Shenk, H. Becker, OG
elsen, E. Kluge, W. Kreuder, and H. Spreitzer, “Polymers
for Light Emitting Diodes ”, Euro Display, Proceedi
ngs, 1999, p.33-37 "and JP-A-10-92576.

As specific light-emitting layers, cyanopolyphenylenevinylene is used for a red light-emitting layer, polyphenylenevinylene is used for a green light-emitting layer, and polyphenylenevinylene or polyalkylphenylene is used for a blue light-emitting layer. Good. The film thickness is 30-150n
m (preferably 40 to 100 nm).

However, the above example is an example of an organic compound material that can be used as a light emitting layer, and it is not necessary to limit the invention to this. An organic compound layer (a layer for performing light emission and carrier movement therefor) may be formed by freely combining a light emitting layer, a charge transport layer, or a charge injection layer.

For example, in this embodiment, an example is shown in which a polymer material is used for the light emitting layer, but a low molecular organic compound material may be used. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer and the charge injection layer. Known materials can be used as the organic compound material and the inorganic material from which luminescence generated by applying these electric fields can be obtained.

In this embodiment, PEDOT is formed on the light emitting layer 45.
An organic compound layer having a layered structure provided with a hole injection layer 46 made of (polythiophene) or PAni (polyaniline). An anode 47 made of a transparent conductive film is provided on the hole injection layer 46. In the case of this embodiment, since the light generated in the light emitting layer 45 is emitted toward the upper surface side (toward the upper side of the TFT), the anode must be translucent. As the transparent conductive film, a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide can be used; however, it is possible to form after forming a light-emitting layer or a hole-injecting layer with low heat resistance. A material that can form a film at a temperature as low as possible is preferable.

When the anode 47 is formed, the light emitting element 3
505 is completed. Note that the light-emitting element 3505 here is used.
Are the pixel electrode (cathode) 43, the light emitting layer 45, the hole injection layer 4
6 and the anode 47. FIG.
As shown in (A), the pixel electrode 43 substantially matches the area of the pixel, so that the entire pixel functions as a light emitting element. Therefore, the efficiency of light emission is extremely high, and a bright image can be displayed.

In the present embodiment, a second passivation film 48 is further provided on the anode 47. Second
As the passivation film 48, a silicon nitride film or a silicon nitride oxide film is preferable. The purpose of this is to shut off the light emitting element from the outside, and has both the meaning of preventing the organic compound material from being deteriorated by oxidation and the meaning of suppressing outgassing from the organic compound material. Thereby, the reliability of the light emitting device is improved.

As described above, the display panel of the present invention has the structure shown in FIG.
And a switching TFT having a sufficiently low off-current value and a current controlling TFT resistant to hot carrier injection. Therefore, a display panel having high reliability and capable of displaying an excellent image can be obtained.

(Embodiment 11) In this embodiment, Embodiment 10 will be described.
A structure in which the structure of the light emitting element 3505 is inverted in the pixel portion shown in FIG. FIG. 27 is used for the description. The only difference from the structure shown in FIG. 25 is the light emitting element portion and the current controlling TFT, so that the other description will be omitted.

In FIG. 27, a current controlling TFT 350
3 is formed using a P-channel TFT manufactured by a known method.

In this embodiment, a transparent conductive film is used as the pixel electrode (anode) 50. Specifically, a conductive film formed using a compound of indium oxide and zinc oxide is used. Needless to say, a conductive film made of a compound of indium oxide and tin oxide may be used.

Then, banks 51a and 51b made of an insulating film are used.
Is formed, a light emitting layer 52 made of polyvinyl carbazole is formed by applying a solution. An electron injection layer 53 made of potassium acetylacetonate (denoted as acacK) and a cathode made of an aluminum alloy are formed thereon. In this case, the cathode 54 also functions as a passivation film. Thus, a light-emitting element 3701 is formed.

In the case of this embodiment, the light generated in the light emitting layer 52 is radiated toward the substrate on which the TFT is formed as indicated by the arrow.

(Embodiment 12) In this embodiment, FIG.
FIGS. 28A to 28C illustrate an example in which the pixel has a structure different from that of the circuit diagram illustrated in FIG. In this embodiment, reference numeral 3801 denotes a switching TFT 380.
2 is a source wiring, and 3803 is a switching TFT 38.
02, a gate wiring 3804, a current controlling TFT 38,
05 is a capacitor, 3806 and 3808 are current supply lines,
Reference numeral 3807 denotes a light-emitting element.

FIG. 28A shows an example in which a current supply line 3806 is shared between two pixels. That is, the feature is that two pixels are formed to be line-symmetric with respect to the current supply line 3806. In this case, the number of power supply lines can be reduced, so that the pixel portion can have higher definition.

FIG. 28 (B) shows the current supply line 380
8 is provided in parallel with the gate wiring 3803. Note that in FIG. 28B, the current supply line 3808 and the gate wiring 3803 are provided so as not to overlap with each other.
They can be provided so as to overlap with each other via an insulating film. In this case, since the power supply line 3808 and the gate wiring 3803 can share an occupied area, the pixel portion can have higher definition.

In FIG. 28C, a current supply line 3808 is provided in parallel with the gate wiring 3803 in the same manner as in the structure of FIG. 28B, and two pixels are connected to the current supply line 3808.
It is characterized in that it is formed so as to be line-symmetric with respect to.
It is also effective to provide the current supply line 3808 so as to overlap with one of the gate wirings 3803. In this case, the number of power supply lines can be reduced, so that the pixel portion can have higher definition.

(Embodiment 13) FIG. 26 shown in Embodiment 10
26A and 26B, a capacitor 3504 for holding a voltage applied to the gate of the current controlling TFT 3503 is used.
Is provided, but the capacitor 3504 can be omitted. In the case of the tenth embodiment, as the current controlling TFT 3503, an N-type TFT having an LDD region provided so as to overlap the gate electrode with the gate insulating film interposed therebetween is used.
A channel type TFT is used. In this overlapping region, a parasitic capacitance generally called a gate capacitance is formed. In the present embodiment, this parasitic capacitance is stored in the capacitor 3504.
The feature is that it is actively used instead of.

Since the capacitance of the parasitic capacitance changes depending on the area where the gate electrode and the LDD region overlap, it is determined by the length of the LDD region included in the overlapping region.

FIG. 28 (A) shown in Embodiment 12
Similarly, in the structures (B) and (C), the capacitor 3
It is possible to omit 805.

(Embodiment 14) In this embodiment, a multiplexer circuit is provided in the circuit group for generating the divided video signal shown in FIG. When a plurality of signals (distribution signals) output from the multiplexer circuit are input to a plurality of D / A conversion circuits corresponding to the respective signals, a combination of the plurality of distribution signals and the plurality of D / A conversion circuits is used. It has a configuration that changes every certain period.

The configurations of the plurality of D / A conversion circuits are theoretically all the same. However, actually, the characteristics of the individual D / A conversion circuits are not exactly the same. Even when the same digital signal is input, the potential of the analog signal output by the D / A conversion circuit may be different. The characteristics of the D / A conversion circuit depend on manufacturing errors of circuit elements included in the D / A conversion circuit and the ambient temperature of the D / A conversion circuit.

Therefore, the potential of the analog signal output from the D / A conversion circuit is always affected by the characteristics of the D / A conversion circuit. Therefore, an analog video signal output from a D / A conversion circuit having a different characteristic is different from another D / A conversion circuit.
It has a potential difference from the analog video signal output from the / A conversion circuit.

When the analog video signal having a potential difference is converted into a divided video signal for divided driving and sampled in the source signal line driving circuit, the image signal input to the pixel by sampling also has a potential difference. . Then, the potential difference of the image signal is displayed as bright and dark on the screen, and the observer visually recognizes the bright and dark fringes (divided fringes).

A circuit group for generating a divided video signal according to the present embodiment will be described with reference to FIG. Here,
A case will be described in which an active-matrix semiconductor display device driven by analog driving is divided into m units.

Reference numeral 401 denotes a control circuit, 402 denotes an A / D conversion circuit, 403 denotes a gamma correction circuit, 404 denotes a multiplexer circuit, 406 denotes a divided circuit group, and 407 denotes a replacement data circuit. The portion indicated by 408 surrounded by a dotted line is
Since the configuration is the same as that shown in FIG. 2, the description is omitted in this embodiment. Although not shown, the divided circuit group 406
It has a number of divided circuits.

The Hsync signal and the Vsync signal are input to the control circuit 401. Then, a clock signal (CK) for driving the source signal line driving circuit from the control circuit 401,
A start pulse signal (SP) and the like are input to the source signal line driving circuit. Further, from the control circuit 401, A
/ D conversion circuit 402, γ correction circuit 403, division circuit 40
6. A signal for driving each circuit is input to the replacement data circuit 407.

[0279] An analog video signal having image information is input to the A / D conversion circuit 402. The analog video signal input to the A / D conversion circuit 402
The signal is converted into a digital video signal by the conversion circuit 402 and input to the gamma correction circuit 403. γ correction circuit 403
Is input to the multiplexer circuit 404 after the γ correction.

Γ input to multiplexer circuit 404
The digital video signal after the correction is switched to a number of output terminals and distributed. And from the multiplexer circuit,
For example, a signal (distributed signal) distributed to l pieces is output. When the number of bits of the digital video signal output from the γ correction circuit is n bits, each of the l distributed signals is an n-bit digital signal.

[0281] The l distributed signals are simultaneously input to the D / A first switching circuit 409. FIG. 33 shows a detailed block diagram of a portion 405 surrounded by a dotted line. 409, a D / A first switching circuit; 410, a D / A conversion circuit group; 411, a D / A second switching circuit; and 412, a D / A switching data processing circuit. The D / A conversion circuit group 410 has at least one D / A conversion circuit (410_1 to 410_m).

The D / A first switching circuit 409 converts the input digital distribution signals (Dv1 to Dvm) into D / A
The D / A conversion circuit (410_1) receives a D / A first replacement signal input from the replacement data processing circuit 412.
To 410 — m). At this time, one digital distribution signal (Dv1 to Dvm) to be input and one D / A conversion circuit (410_1 to 410_m) correspond one-to-one. Which D / A conversion circuit among the l D / A conversion circuits is input to which D / A conversion circuit among the l digital distribution signals is D / A.
D / A input from A replacement data processing circuit 412
It is determined by the first replacement signal.

The D / A conversion circuits (410_1 to 410_
m) and l digital distribution signals (Dv1-Dv1)
Dvm) is converted into 1 analog distribution signal (Av1 to Avm) in each D / A conversion circuit, and the D / A second
It is input to the replacement circuit 411.

The D / A second exchange circuit 411 is provided with a D / A
The D / A conversion circuit (410_1) receives the D / A second replacement signal input from the replacement data processing circuit 412.
To 410 — m), and outputs the l analog distribution signals (Av1 to Avm) respectively
Input to the divided circuits. That is, one digital distribution signal (Dv1 to Dv1) is generated by the D / A first exchange signal.
m) is any of the D / A conversion circuits (410_1 to 410_1).
410_m), l D / A
L output from the conversion circuits (410_1 to 410_m)
The analog distribution signals (Av1 to Avm) are input to l predetermined dividing circuits.

[0285] The l analog distribution signals (Av1 to Avm) input to the l division circuits are converted into m divided video signals and output. The following is the same as described in the embodiment, and the description is omitted.

According to the present invention, an analog distribution signal output from a D / A conversion circuit having different characteristics can be obtained by the above configuration.
Since there is a potential difference between analog distribution signals output from other D / A conversion circuits, even if light and dark fringes (divided fringes) are displayed on the screen, they are divided every certain period. The position where the stripe is displayed moves. Therefore, even if the divisional stripes are displayed on the screen, it is difficult for the observer to visually recognize the divisional stripes.

In the present invention, digital distribution signals and D /
It is important to set a period from the time when the combination of the A conversion circuits is changed to the time when the combination is changed again to a length that makes it difficult for the observer to visually recognize the divided stripes. D
The period between the change of the combination of the / A conversion circuit and the next change of the combination is, in other words, D /
This corresponds to a period from when the information of the A first switching signal and the second switching signal changes to when the information of the D / A first switching signal and the second switching signal changes next time.

It is preferable that the period until the combination of the digital distribution signal and the D / A conversion circuit changes is shorter, and the divided stripes are more difficult to be visually recognized by the observer. In the present embodiment, a digital distribution signal and D
The setting is made so that the combination of the / A conversion circuits changes.

Therefore, in the present invention, when performing the division driving, the division stripes are not easily recognized by the observer. Even by increasing the number of pixels in the horizontal direction of the active matrix type semiconductor display device, it is possible to suppress flickering and flickering of the displayed image while suppressing the driving frequency of the source signal line driving circuit, by performing the division driving. It is possible to display a high-resolution, multi-tone image.

In addition to the configuration shown in FIGS. 32 and 33, the combination of the D / A conversion circuit and the signal is switched before input to the D / A conversion circuit, and after the signal is output from the buffer circuit. Alternatively, the replaced combination may be restored. More specifically, before the digital distribution signal output from the multiplexer circuit 404 is input to the D / A conversion circuits (410_1 to 410_m), the digital distribution signal
The analog distribution signal output from the D / A conversion circuit is rearranged by the A first replacement circuit 409 and directly input to the division circuit 406 without passing through the D / A second replacement circuit 411. The divided video signal output from the dividing circuit is directly input to the buffer circuits (109_1 to 109_m) without passing through the first switching circuit 108, and the divided video signal output from the buffer circuit is converted to the second switching circuit 11
By changing the combination at 0, the configuration may be changed back to the original.

Further, the configuration shown in this embodiment is
Compared with the configurations shown in the first embodiment and the third embodiment, it is possible to make it more difficult for an observer to visually recognize the divisional stripes.

(Embodiment 15) The present invention can be used for various semiconductor display devices (active matrix liquid crystal display, active matrix light emitting device, active matrix EC display). That is, the present invention can be applied to all semiconductor display devices incorporating such electro-optical devices as display media.

Examples of such a semiconductor display device include a video camera, a digital camera, a projector (rear or front type), a head mounted display (goggle type display), a game machine, a car navigation system,
Examples include a personal computer and a portable information terminal (a mobile computer, a mobile phone, an electronic book, or the like). Examples of these are shown in FIGS. 29, 30 and 31.

FIG. 29A shows a personal computer, which includes a main body 7001, a video input section 7002, and a display device 7.
003 and a keyboard 7004. The semiconductor display device of the present invention can be applied to the display device 7003.

FIG. 29B shows a video camera, which includes a main body 7101, a display device 7102, an audio input portion 7103, operation switches 7104, a battery 7105, and an image receiving portion 71.
06. The semiconductor display device of the present invention can be applied to the display device 7102.

FIG. 29C shows a mobile computer (mobile computer), which includes a main body 7201, a camera section 7202, an image receiving section 7203, operation switches 7204, and a display device 7205. The semiconductor display device of the present invention can be applied to the display device 7205.

FIG. 29D shows a goggle type display, which comprises a main body 7301, a display device 7302, and an arm portion 73.
03. The semiconductor display device of the present invention can be applied to the display device 7302.

FIG. 29E shows a player using a recording medium on which a program is recorded (hereinafter, referred to as a recording medium), which includes a main body 7401, a display device 7402, and a speaker 74.
03, a recording medium 7404, and operation switches 7405. This device uses a DVD (Di) as a recording medium.
A digital versatile disc), a CD, and the like can be used for music appreciation, movie appreciation, games, and the Internet. The semiconductor display device of the present invention can be applied to the display device 7402.

FIG. 30A shows a front type projector, which comprises a light source optical system, a display device 7601, and a screen 7602. The semiconductor display device of the present invention can be applied to the display device 7601.

FIG. 30B shows a rear projector, in which a main body 7701, a light source optical system and a display device 7702,
Mirror 7703, mirror 7704, screen 7705
It consists of. The semiconductor display device of the present invention is a display device 77.
02 can be applied.

[0301] FIG. 30C shows the light source optical system and the display device 760 shown in FIGS. 30A and 30B.
1 is a diagram showing an example of the structure of 7702. FIG. The light source optical system and the display devices 7601 and 7702 are
01, mirrors 7802, 7804 to 7806, dichroic mirror 7803, optical system 7807, display device 78
08, a phase difference plate 7809, and a projection optical system 7810. The projection optical system 7810 includes a plurality of optical lenses provided with a projection lens. This configuration corresponds to the display 78
It is called a three-plate type because it uses three 08s. In addition, the practitioner may appropriately place an optical lens, a film having a polarizing function, or the like on the optical path indicated by the arrow in FIG.
A film for adjusting the phase difference, an IR film, or the like may be provided.

FIG. 30D is a view showing an example of the structure of the light source optical system 7801 in FIG. 30C. In the present embodiment, the light source optical system 7801 includes a reflector 7811, a light source 7812, and lens arrays 7813 and 7813.
814, a polarization conversion element 7815, and a condenser lens 7816. Note that the light source optical system shown in FIG. 30D is an example and is not particularly limited. For example, a practitioner may appropriately provide an optical lens, a film having a polarizing function, a film for adjusting a phase difference, an IR film, or the like to the light source optical system.

FIG. 30 (C) shows an example of a three-plate type, while FIG. 31 (A) shows an example of a single-plate type. FIG.
The light source optical system and the display device illustrated in FIG. 1A include a light source optical system 7901, a display device 7902, and a projection optical system 7903. The projection optical system 7903 includes a plurality of optical lenses provided with a projection lens. The light source optical system and the display device shown in FIG.
The present invention can be applied to the display devices 7601 and 7702 in FIG. The light source optical system 7901 may use the light source optical system shown in FIG. Note that the display device 7902
Is provided with a color filter (not shown) to colorize the displayed image.

The light source optical system and display device shown in FIG. 31B is an application example of FIG. 31A, and uses a rotating color filter disk 7905 of RGB instead of providing a color filter. The display image is colorized. The light source optical system and the display device shown in FIG. 31B are the display device 760 in FIGS. 30A and 30B.
1, 7702.

The light source optical system and the display device shown in FIG. 31C are called a color filterless single plate type. In this method, a microlens array 7915 is provided on a display device 7916, and a dichroic mirror (green) 7 is provided.
912, a dichroic mirror (red) 7913, and a dichroic mirror (blue) 7914 are used to colorize the display image. The projection optical system 7917 includes a plurality of optical lenses provided with a projection lens. The light source optical system and the display device shown in FIG.
(B) Light source optical system and display devices 7601 and 7 in FIG.
702. As the light source optical system 7911, an optical system using a coupling lens and a collimator lens in addition to the light source may be used.

As described above, the applicable range of the present invention is extremely wide, and it can be applied to semiconductor display devices in all fields.

[0307]

According to the present invention, the divided video signal output from the buffer circuit having different characteristics has a potential difference between the divided video signal and the other divided video signals. Even if the divisional stripe is displayed, the position where the divisional stripe is displayed moves every certain period.
Therefore, even if the divisional stripes are displayed on the screen, it is difficult for the observer to visually recognize the divisional stripes.

Therefore, in the present invention, when performing the division driving, the division stripes are not easily recognized by the observer. Even by increasing the number of pixels in the horizontal direction of the active matrix type semiconductor display device, it is possible to suppress flickering and flickering of the displayed image while suppressing the driving frequency of the source signal line driving circuit, by performing the division driving. It is possible to display a high-resolution, multi-tone image.

[Brief description of the drawings]

FIG. 1 is a block diagram of a circuit group for generating a divided video signal according to the present invention.

FIG. 2 is a block diagram of a part of a circuit group that generates a divided video signal.

FIG. 3 is a block diagram of a replacement data circuit.

FIG. 4 is a schematic top view of an active matrix liquid crystal semiconductor display device of the present invention.

FIG. 5 is a diagram showing a method for driving an analog active matrix liquid crystal semiconductor display device of the present invention.

FIG. 6 is a circuit diagram of a source signal line driver circuit.

FIG. 7 is an equivalent circuit diagram of an analog switch and a level shift circuit.

FIG. 8 is a block diagram of a circuit group for generating a divided video signal according to the present invention.

FIG. 9 is a block diagram of a part of a circuit group for generating a divided video signal.

FIG. 10 is a block diagram of a replacement data circuit.

FIG. 11 is a schematic top view of an active matrix liquid crystal semiconductor display device of the present invention.

FIG. 12 is a circuit diagram of a source signal line driver circuit.

FIG. 13 is a block diagram of a circuit group for generating a divided video signal according to the present invention.

FIG. 14 is a block diagram of a part of a circuit group that generates a divided video signal.

FIG. 15 is a schematic top view of an active matrix liquid crystal display device of the present invention.

FIG. 16 is a perspective view of a semiconductor display device of the present invention.

FIG. 17 is a block diagram of a conventional circuit group for generating a divided video signal.

FIG. 18 is a diagram showing a manufacturing process of a TFT used in the present invention.

FIG. 19 is a diagram showing a manufacturing process of a TFT used in the present invention.

FIG. 20 is a diagram showing a manufacturing process of a TFT used in the present invention.

FIG. 21 is a diagram showing a manufacturing process of a TFT used in the present invention.

FIG. 22 is a diagram showing a manufacturing process of a TFT used in the present invention.

23A and 23B are a top view and a cross-sectional view of a light-emitting device using the present invention.

24A and 24B are a top view and a cross-sectional view of a light-emitting device using the present invention.

FIG. 25 is a cross-sectional view of a light emitting device using the present invention.

26A and 26B are a top view and a circuit diagram of a light-emitting device using the present invention.

FIG. 27 is a cross-sectional view of a light emitting device using the present invention.

FIG. 28 is a circuit diagram of a light emitting device using the present invention.

FIG. 29 is a diagram of a semiconductor display device using the present invention.

FIG. 30 is a diagram of a liquid crystal projector using the present invention.

FIG. 31 is a diagram of a single-panel liquid crystal projector using the present invention.

FIG. 32 is a block diagram of a circuit group for generating a divided video signal according to the present invention.

FIG. 33 is a block diagram of a part of a circuit group for generating a divided video signal.

[Explanation of symbols]

 Reference Signs List 101 control circuit 102 A / D conversion circuit 103 gamma correction circuit 104 D / A conversion circuit 105 division circuit 106 replacement data circuit 108 first replacement circuit 109 buffer circuit 110 second replacement circuit 111 replacement data processing circuit 112 counter circuit 113 memory circuit 115 Source signal line drive circuit 116 Gate signal line drive circuit 117 Source signal line 118 Gate signal line 119 Pixel 120 Pixel section 121 Pixel TFT 122 Liquid crystal cell 123 Storage capacity

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/20 623 G09G 3/20 623B 631 631 631Q 642 642A 680 680V 3/32 3/32 A

Claims (13)

[Claims] 1. A semiconductor display device having m buffer circuits and a source signal line drive circuit, wherein each of the m buffer circuits corresponds to each of m divided video signals that are parallel data. The m buffer circuits corresponding to each of the m divided video signals are replaced with each other every predetermined period, and the m divided video signals input to the m buffer circuits are , The m divided video signals output from the m buffer circuits and input to the source signal line driving circuit, and input to the source signal line driving circuit, are sampled, and the m divided video signals are sampled. A semiconductor display device, which is input to predetermined m source signal lines corresponding to signals. 2. A semiconductor display device comprising a division circuit, a first replacement circuit, a second replacement circuit, m buffer circuits, and a source signal line driving circuit, wherein a video signal is converted from a serial-parallel signal. M divided video signals formed by the division are output from the division circuit. The m division video signals output from the division circuit are:
The m divided video signals input to the first replacement circuit and input to the first replacement circuit are input to the corresponding m buffer circuits, respectively, and the m input video signals are input to the m buffer circuits. The divided video signals are output from the m buffer circuits and input to the second permutation circuit. The m divided video signals input to the second permutation circuit are divided into the m divided video signals. Default m corresponding to the signal
The m divided video signals input to the m divided video signal lines, respectively, are input to the source signal line driving circuit and sampled, and the m divided video signals are input to the m divided video signal lines. The m buffer circuits respectively input to the predetermined m source signal lines corresponding to the video signals and corresponding to the m divided video signals are replaced with each other at certain intervals. Semiconductor display device. 3. A semiconductor display device having a dividing circuit, a first switching circuit, m buffer circuits, and a source signal line driving circuit, wherein the source signal line driving circuit has a second switching circuit. M divided video signals formed by serial-to-parallel conversion of the video signal are output from the dividing circuit, and the m divided video signals output from the dividing circuit are:
The m divided video signals input to the first replacement circuit and input to the first replacement circuit are input to the corresponding m buffer circuits, respectively, and the m input video signals are input to the m buffer circuits. The divided video signals are output from the m buffer circuits and input to the second permutation circuit. The m divided video signals input to the second permutation circuit are sampled, and the m divided video signals are sampled. The m buffer circuits respectively input to the predetermined m source signal lines corresponding to the respective divided video signals, and the m buffer circuits corresponding to the respective m divided video signals are replaced with each other at predetermined intervals. Semiconductor display device. 4. The replacement data circuit according to claim 1, wherein replacement of the m buffer circuits corresponding to each of the m divided video signals is controlled by a replacement data circuit. Semiconductor display device. 5. The method according to claim 1, wherein the m buffer circuits corresponding to the m divided video signals are replaced with each other.
A semiconductor display device characterized by being determined in a replacement data circuit. 6. The replacement data circuit according to claim 5, further comprising a memory circuit and a counter circuit, wherein the memory circuit includes m buffer circuits corresponding to the m divided video signals, respectively. A plurality of pieces of exchange data having information on combinations of the above are stored, and one of the pieces of exchange data is stored by the counter circuit.
One of which is selected. 7. A semiconductor display device having a multiplexer circuit, one D / A conversion circuit, and one division circuit, wherein each of the one D / A conversion circuits outputs an output from the multiplexer circuit. Corresponding to each of the l digital distribution signals, and l corresponding to each of the l digital distribution signals.
The D / A conversion circuits are replaced with each other at certain intervals, and the l digital distribution signals input to the l D / A conversion circuits are converted into l analog distribution signals. And input to each of the predetermined l divided circuits corresponding thereto. 8. A semiconductor display device according to claim 1, wherein a liquid crystal is used. 9. A semiconductor display device according to claim 1, wherein a light-emitting element is used. 10. An electronic apparatus using the semiconductor display device according to any one of claims 1 to 9. 11. The electronic device according to claim 10, wherein the electronic device is a computer. 12. An electronic apparatus according to claim 10, wherein said electronic apparatus is a video camera. 13. The electronic device according to claim 10, wherein the electronic device is a DVD player.