JP5078767B2 - Semiconductor integrated circuit and electronic equipment - Google Patents

Description

  The present invention relates to an electronic apparatus having a circuit in which reverse polarity power may be input to a power input terminal. In particular, when the reverse polarity power is input, the reverse polarity power is hardly consumed. The present invention relates to an electronic device having the required circuit.

  A circuit that consumes less power at the time of reverse polarity power input in a conventional electronic device has a configuration as shown in FIG. 9 (see, for example, Patent Document 1). As shown in FIG. 9, a backflow prevention transistor 905 is provided between the plus terminal 106 and the plus electrode 102 of the load 104, and the base of the backflow prevention transistor 905 is connected to the minus electrode 103 via the resistor 108. The minus terminal 107 is connected to the minus electrode 103, and is configured to connect the power source 101 between the plus electrode 102 and the minus electrode 103.

  With the above configuration, when the power supply 101 is normally connected so that the positive electrode 102 has a higher voltage than the negative electrode 103, the backflow prevention transistor 905 is turned on, so that a voltage close to the voltage of the power supply 101 is applied to the load. When the power supply 101 is reversely connected, the reverse current prevention transistor 905 is turned off, so that the current that is going to flow from the negative electrode 103 to the positive electrode 102 via the load is reversed. Blocked by the prevention transistor 905.

Therefore, in the above configuration, when the power source 101 is normally connected, the power of the power source 101 can be used for driving the load 104 with a small loss. An electronic device having a circuit that can prevent power consumption of the power source 101 due to overcurrent flowing through the load 104 and thermal destruction of the load 104 can be realized.
Japanese Patent Laid-Open No. 5-260652 (Second Mitigation, Fig. 1)

  The problem with the circuit with low power consumption when inputting reverse polarity power in the conventional electronic device is that the load 104 is an IC with a low power consumption CMOS structure in order to reduce the power consumption of the electronic device. This is a case where a backflow prevention transistor 905 is incorporated in the IC in order to reduce the size and cost of the electronic device.

  In this case, when the backflow prevention transistor 905 is a bipolar transistor, it is a matter of course that a very complicated structure and manufacturing process are required for manufacturing the IC. However, since the base current flows in the bipolar transistor, low power consumption is achieved. There is a problem that cannot be made.

On the other hand, when the backflow prevention transistor 905 is an FET, the consumption can be reduced by the amount of current that does not flow through the gate, and the IC can be easily manufactured. However, a P-type substrate-N-type well structure with good performance of an N-channel MOSFET (hereinafter abbreviated as NMOS) has a drive capability about four times that of a PMOS to reduce the area of the IC, and is off-leakage. When an NMOS with a small amount is used for the backflow prevention transistor 905, the current from the negative electrode 103 to the positive electrode 102 cannot be cut off by the NMOS when the power supply 101 is reversely connected. Therefore, it is necessary to use a P-channel MOSFET (hereinafter abbreviated as PMOS) having an N well open as the backflow prevention transistor 905. However, the PMOS has a smaller driving capability than the NMOS and is formed in the N well. As a result, the driving capability is further reduced and off-leakage is increased. Therefore, it is necessary to increase the W length.
In addition to increasing the C chip area, the current consumption when the power supply 101 is reversely connected also increases.

  Also, in an N-type substrate-P-type well structure with good PMOS performance, the NMOS is formed in the P-type well. Therefore, if the P-type well is opened, the NMOS is advantageous in reducing the area of the IC. However, since the NMOS is formed in the P-type well, the performance is inferior to that of the P-type substrate-N-type well structure. Accordingly, the off-leakage of the NMOS increases, and as a result, the current consumption when the power supply 101 is reversely connected increases. Note that when a PMOS is used for the backflow prevention transistor 905, the current from the negative electrode 103 to the positive electrode 102 cannot be cut off by the PMOS when the power supply 101 is reversely connected.

  That is, in the above conventional circuit, if the backflow prevention transistor 905 is bipolar, the power consumption cannot be reduced. If the backflow prevention transistor 905 is an FET, the reverse current prevention transistor 905 is connected to the PMOS or the like formed in the N well. It is necessary to use the NMOS created in the P-well. Therefore, the PMOS or NMOS has a lower driving capability and an increased off-leakage than those produced directly on the substrate, so that it not only increases the area of the IC but also consumes power when the power supply 101 is reversely connected. There was a problem that the current increased.

  Therefore, in the first means of the present invention, a power source, a load composed of SOI-CMOS driven by the power of the power source and having a desired function, and an SOI-MOS formed on the same substrate as the load In the circuit, the SOI-MOS is connected in series to the current path of the load, the SOI-MOS has an open body, and the gate has the power supply normal. When connected, the SOI-MOS is turned on, the power supply is reverse-connected, and when reverse polarity power is supplied, a voltage is applied so that the SOI-MOS is turned off. Electronic equipment was used.

  With the above configuration, the backflow prevention transistor and the load are created on the same substrate, and the increase in the area of the IC, which was a problem when using the FET for the backflow prevention transistor, and the reverse connection of the power supply An increase in current consumption can be solved.

Further, in the second means of the present invention, in addition to the means of the first of the present invention, the circuit is reversely connected to the SOI-MOS substrate than when the power supply is normally connected. When an electric power of polarity is supplied, a voltage that gives a higher absolute value of the threshold voltage of the SOI-MOS is applied.
With the above configuration, the area of the IC can be further reduced as compared with the first means, and the current consumption when the power supply is reversely connected can be reduced.

  Further, in the third means of the present invention, in addition to the first and second means of the present invention, the circuit uses a fully depleted type SOI-MOS for the SOI-MOS. It was.

  With the above configuration, the area of the IC can be further reduced as compared with the first and second means, and the current consumption when the power supply 101 is reversely connected can be reduced.

According to a fourth aspect of the present invention, there is provided a digital circuit composed of a power source and SOI-CMOS that is driven by the power of the power source and has a desired function, and the digital circuit includes a current of the digital circuit. In the configuration, SOI-PMOS and SOI-NMOS are connected in series in the path, and when the power supply is normally connected, current from the power supply flows to the drain through the source of the SOI-PMOS, and the SOI The current from the drain of the PMOS is configured to flow to the source through the drain of the SOI-PMOS, and the gate of the SOI-PMOS and the gate of the SOI-NMOS are electrically connected. It was set as an electronic device.

  With this configuration, the backflow prevention transistor is not necessary for the digital circuit, so that not only can the power of the power source be efficiently used for the digital circuit, but also low cost and downsizing can be realized.

  Furthermore, in the fifth means of the present invention, in addition to the configuration of the fourth means, the digital circuit uses a fully depleted type SOI-PMOS for the SOI-PMOS and a fully depleted type SOI- for the SOI-NMOS. The electronic device is characterized by using NMOS.

  With the above configuration, not only the power of the power source can be efficiently used for the digital circuit but also low cost and downsizing can be realized by the fourth means.

  Further, in the sixth means of the present invention, in addition to the structures of the fourth and fifth means, the electronic device is further composed of SOI-CMOS driven by the power of the power source and having a desired function. And an SOI-MOS formed on the same substrate as the analog circuit, the SOI-MOS is connected in series to the current path of the analog circuit, and the body of the SOI-MOS is open. The gate is configured so that the SOI-MOS is turned on when the power supply is normally connected, and the SOI-MOS is turned off when the power supply is reversely connected and power of reverse polarity is supplied. The electronic device is characterized by being supplied with various voltages.

  With the above configuration, the SOI-MOS drive capability is reduced because the digital circuit does not require the backflow prevention transistor, so the analog circuit and the SOI-MOS formed on the same substrate are used. In addition to reducing the area of the IC, the current consumption when the power supply is reversely connected can be reduced.

  Further, in the seventh means of the present invention, in addition to the sixth means, the SOI-MOS is reversely connected to the SOI-MOS substrate from the case where the power supply is normally connected, and has a reverse polarity. The electronic device is characterized in that a voltage is applied so that the absolute value of the threshold voltage of the SOI-MOS is higher when the power is supplied.

  With the above configuration, the IC area can be further reduced as compared with the sixth means, and the current consumption when the power supply is reversely connected can be further reduced.

  According to an eighth means of the present invention, in addition to the configurations of the sixth and seventh means, the SOI-MOS is an electronic device characterized by using a fully depleted type SOI-MOS.

  With the above configuration, the area of the IC can be further reduced as compared with the sixth and seventh means, and the current consumption when the power supply is reversely connected can be further reduced.

  Furthermore, in the ninth means of the present invention, in addition to the structure of any one of the first to third means, the electronic device further has the same structure as the circuit, and the power supply is reversely connected. An electronic device is characterized in that it has a second circuit driven by electric power or electric power of reverse polarity.

  With the above-described configuration, in addition to the effects of the first to third means, even when the power source is reversely connected and power having a reverse polarity is supplied, the power of the power source is efficiently driven to achieve a desired function. A circuit that fulfills this can be realized.

  Further, in the tenth means of the present invention, in addition to the structures of the fourth and fifth means, the electronic device further has the same structure as the digital circuit, and the power when the power source is reversely connected. In addition, the electronic device includes a second digital circuit that is driven by electric power having a reverse polarity.

  By adopting the above configuration, in addition to the effects of the fourth and fifth means, even when the power source is reversely connected and power having a reverse polarity is supplied, the power of the power source is efficiently driven to achieve a desired function. A circuit that fulfills this can be realized.

  According to an eleventh means of the present invention, in addition to the configuration of any one of the sixth to eighth means, when the power source is normally connected to the digital circuit or when positive power is supplied, The electronic device is characterized in that the power source is reversely connected to the SOI-MOS or power having a reverse polarity is supplied.

  With the above configuration, in addition to the effects of any one of the sixth to eighth means, even when the power source is reversely connected and reverse polarity power is supplied, the power of the power source is efficiently driven, A circuit that performs the function can be realized.

  According to the present invention, by providing a backflow prevention transistor in an electronic device, in a circuit that consumes less power when reverse polarity power is input, the load 104 is reduced in CMOS structure in order to reduce the consumption of the electronic device. In order to further reduce the size and cost of the electronic device, when the backflow prevention transistor 105 is incorporated in the IC, the IC can be reduced in area, and the area of the IC can be reduced. Thus, current consumption when the power supply 101 is reversely connected can be reduced.

  In addition, an electronic device having a circuit that can be efficiently driven by the power of the power source can be realized regardless of whether the power source is normally connected or reversely connected.

  The semiconductor integrated circuit according to the present invention is connected between a first terminal to which a positive electrode of a power supply is connected, a second terminal to which a negative electrode of the power supply is connected, and the first and second terminals. And a load that is driven by receiving power supplied from the power source, and an NMOS transistor that controls the power supplied to the load. The NMOS transistor is connected between the second terminal and the load, and a voltage based on the voltage of the first terminal is applied to the gate electrode and the substrate electrode of the NMOS transistor. The NMOS transistor is an SOI-MOS transistor.

  The semiconductor integrated circuit according to the present invention is connected between a first terminal to which a positive electrode of a power supply is connected, a second terminal to which a negative electrode of the power supply is connected, and the first and second terminals. And a load that is driven by the supply of power from the power source, and a PMOS transistor that controls the power supplied to the load. The PMOS transistor is connected between the first terminal and the load, and a voltage based on the voltage of the second terminal is applied to the gate electrode and the substrate electrode of the PMOS transistor. The PMOS transistor is an SOI-MOS transistor.

The semiconductor integrated circuit according to the present invention is connected between a first terminal to which a positive electrode of a power supply is connected, a second terminal to which a negative electrode of the power supply is connected, and the first and second terminals. And a load that is driven by power supplied from the power source and a MOS transistor that controls the power supplied to the load. The MOS transistor is connected between the first terminal and the second terminal in series with the load, and when the power supply is reversely connected, the gate electrode of the MOS transistor includes: A voltage for turning off the MOS transistor is applied, and the MOS transistor is an SOI-MOS transistor.

  Further, the MOS transistor is a fully depleted SOI-MOS transistor.

  Further, the load is formed on the same substrate as the MOS transistor.

  Further, the MOS transistor constituting the load is a fully depleted SOI-MOS transistor.

  An electronic apparatus according to the present invention includes the semiconductor integrated circuit.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  1 to 4 show circuits that consume low power when reverse polarity power is input in an electronic apparatus according to first to fourth embodiments of the present invention.

FIG. 5 is a cross-sectional view for explaining a MOS structure using an SOI (Silicon on Insulator) structure used in the present invention.
First, the SOI-MOS structure used in the present invention will be described. As shown in FIG. 5, the SOI-MOS structure used in the present invention is provided with a buried oxide film 505 on a P-type conductivity type or N-type conductivity type support base 308, and a silicon layer on the buried oxide film 505. Is partially oxidized to form LOCOS307. Further, the LOCOS 307 is in complete contact with the buried oxide film 505, whereby the silicon layer surrounded by the LOCOS 307 can be electrically isolated from the other silicon layers. Then, the SOI-PMOS 105 or the SOI-NMOS 205 is formed in each silicon layer that is electrically separated. In other words, by using the SOI structure, it is possible to easily separate elements without forming a well as in a conventional MOS.

  In the SOI-PMOS 105, a P-type source 301 and a P-type drain 302 are provided on the silicon layer, and a gate oxide film 301 is provided on an N-type body 304 between the source 301 and the drain 302. The gate electrode 303 is provided on the film 310, and the SOI-NMOS includes an N-type source 311 and an N-type drain 312, and a gate oxide film 301 on a P-type body 314 between the source 311 and the drain 312. In addition, a gate electrode 303 is provided on the gate oxide film 301.

  Furthermore, in the present invention, a first substrate region 306 having a conductivity type different from that of the support substrate 308 is provided in the support substrate 308 so as to be in contact with the buried oxide film 505, and the buried oxide film is provided in the first substrate region 306. A second substrate region 316 having the same conductivity type as that of the support substrate 308 is provided so as to be in contact with 505, and the first substrate region 306 to the second substrate region 316 are formed on the body 304 of the SOI-PMOS 105 or the body 314 of the SOI-NMOS 205. The supporting substrate 308, the first substrate region 306, and the second substrate region 316 are electrically connected to each other silicon layer region through a region without a separate buried oxide film 505. It is a configuration to be connected.

With the above configuration, since the bottom of the source or drain of each SOI-MOS is in contact with the buried oxide film, the parasitic capacitance associated with the source or drain can be reduced. Therefore, the circuit composed of each SOI-MOS can achieve high speed operation and low consumption. Furthermore, the voltages of the support substrate, the first substrate region, and the second substrate region can be set separately by applying different output potentials to the silicon layer that is electrically connected to each region. Therefore, the characteristics of each SOI-MOS located directly above each region can be controlled separately.

  Each of the SOI layers is thickened to a certain extent, so that each of the SOI-MOSs is a partially depleted type in which the body is only partially depleted. It goes without saying that the MOS can be of a fully depleted type that completely depletes the body.

  Next, SOI-MOS symbols used in the description of the present invention will be described. The SOI-MOS symbol used in the description of the present invention is shown in FIG. 6 by taking a partial depletion type SOI-PMOS as an example. As shown in FIG. 6, there are a source 401 and a drain 402 on the left and right, a gate 403 between the source 401 and the drain 402, a downward arrow 401 on the gate 403, and an arrow 401 A capacitor 405 having a buried oxide film as an insulating film is provided below, and a substrate 406 is provided below the capacitor 405. The substrate 406 includes the support substrate 308 and the first substrate region shown in FIG. The configuration corresponds to either 306 or the second substrate region 316. In addition, the arrow 404 in FIG. 6 is directed upward in the case of a partially depleted type SOI-NMOS, and is directed downward in the case of a fully depleted type SOI-PMOS. In the case of NMOS, it is configured to face upward with a dotted arrow.

  1 to 4 are diagrams showing a circuit that consumes low power when reverse polarity power is input in the electronic apparatus according to the first to fourth embodiments using the above-described SOI-MOS symbols. This will be described.

  FIG. 1 is a schematic circuit diagram showing a circuit that consumes low power when reverse polarity power is input in the electronic apparatus according to the first embodiment of the present invention. As shown in FIG. 1, the depletion type SOI-PMOS 105 is used as the backflow prevention transistor, and the source or drain of the partial depletion type SOI-PMOS 105 is connected to the positive electrode 102 or the positive terminal 106 of the load 104. The gate of the partial depletion type SOI-PMOS 105 is connected to the negative electrode 103, the substrate is connected to the gate, the negative terminal 107 of the load 104 is connected to the negative electrode 103, and a power source is connected between the positive electrode 102 and the negative electrode 103. 101 is connected.

  With the above configuration, when the power supply 101 is normally connected so that the positive electrode 102 has a higher voltage than the negative electrode 103, the partially depleted type SOI-PMOS 105 is turned on. Although the load 104 is supplied and the load 104 operates, when the power supply 101 is reversely connected, the partially depleted type SOI-PMOS 105 is turned off, so that it tends to flow from the negative electrode 103 to the positive electrode 102 via the load. The current is interrupted by the partially depleted type SOI-PMOS 105.

  Therefore, in the above configuration, when the power source 101 is normally connected, the power of the power source 101 can be used for driving the load 104 with little loss, and when the power source 101 is reversely connected, the power of the power source 101 is hardly consumed. An electronic device having a circuit that can prevent power consumption of the power source 101 due to overcurrent flowing through the load 104 and thermal destruction of the load 104 can be realized.

  Further, while the bipolar circuit is used for the backflow prevention transistor as in the conventional circuit, the circuit of the present invention uses a partially depleted type SOI-PMOS for the backflow prevention transistor. Therefore, compared with the conventional circuit, the circuit according to the present invention can reduce power consumption because the current flowing through the bipolar base is eliminated.

  In other words, the configuration of the circuit of the present invention can solve the problem of increased current consumption in the case of using a bipolar for the backflow prevention transistor as in the conventional configuration of the circuit. .

  Also, as in the conventional circuit, when the backflow prevention transistor and the load are formed on the same substrate and the FET is used for the backflow prevention transistor, the performance is deteriorated because it is formed in the well. In contrast to the FET, the partially depleted SOI-PMOS used as the backflow prevention transistor in the circuit of the present invention does not need to be formed in the well, so that the driving capability is not lowered and the off-leakage is not increased.

  Therefore, in the circuit of the present invention, the backflow prevention transistor can be configured with a smaller area than the conventional circuit, so that the area of the IC in which the backflow prevention transistor and the load are formed on the same substrate can be reduced. Since off-leakage of the backflow prevention transistor can be reduced, current consumption when the power supply is reversely connected can be reduced.

  In other words, when the circuit configuration of the present invention is used, the backflow prevention transistor and the load are created on the same substrate as in the conventional circuit configuration, and the FET is used as the backflow prevention transistor. The increase in the area of the IC and the increase in current consumption when the power supply 101 is reversely connected can be solved.

  Furthermore, in the above circuit of the present invention, the substrate of the partial depletion type SOI-PMOS used as the backflow prevention transistor is connected to the gate. Thereby, the SOI-PMOS has the lowest absolute value of the threshold voltage because the lowest voltage is input to the substrate when the power supply is normally connected. Accordingly, since the drive capability of the SOI-PMOS increases, it becomes possible to supply the power of the power source to the load without further loss, and the SOI-PMOS so that the loss becomes the same. When the W length is set, the W length can be reduced. Further, the SOI-PMOS has the highest absolute value of the threshold voltage because the highest voltage is input to the substrate when the power supply is reversely connected. Therefore, since the off-leakage of the SOI-PMOS can be reduced, the current consumption when the power supply is reversely connected can be further reduced.

  In the above circuit of the present invention, the gate of the SOI-PMOS is connected to the negative electrode, but when the power supply is normally connected, a voltage is applied to turn on the SOI-PMOS. In addition, it goes without saying that a similar function can be realized even when a voltage is applied to turn off the SOI-PMOS when the power supply is reversely connected. In the above circuit of the present invention, the SOI-PMOS substrate is connected to the gate. However, when the power supply is normally connected, the absolute value of the threshold value of the SOI-PMOS decreases, and Needless to say, the same effect can be expected if a voltage is applied to increase the absolute value of the threshold value of the SOI-PMOS when the power supply is reversely connected.

  FIG. 2 is a schematic circuit diagram showing a circuit that consumes less power at the time of reverse polarity power input in the electronic apparatus according to the second embodiment of the present invention. As shown in FIG. 2, the backflow prevention transistor uses a partially depleted type SOI-PMOS 205, and the source or drain of the partially depleted type SOI-NMOS 205 is connected to the negative electrode 103 or the negative terminal 107 of the load 104. The gate of the partial depletion type SOI-NMOS 205 is connected to the positive electrode 102, the substrate is connected to the gate, the positive terminal 106 of the load 104 is connected to the positive electrode 102, and a power source is connected between the positive electrode 102 and the negative electrode 103. 101 is connected.

With the above configuration, not only the same function as in the first embodiment of the present invention is obtained, but also a partially depleted type SOI-PMOS used as a backflow prevention transistor in the first embodiment of the present invention. In contrast, the partially depleted SOI-NMOS used as the backflow prevention transistor in the second embodiment of the present invention has a drive capability that is about four times larger, and the off-leakage for the same drive capability is reduced. Therefore, in the second embodiment of the present invention, in addition to the effect of the first embodiment of the present invention, the backflow prevention transistor can be configured with a small area. Since the area of an IC formed on the same substrate can be reduced and the off-leakage of the backflow prevention transistor can be reduced, there is an effect of reducing current consumption when the power supply is reversely connected.

FIG. 3 is a schematic circuit diagram showing a circuit that consumes less power at the time of reverse polarity power input in an electronic apparatus according to the third embodiment of the present invention. As shown in FIG. 3, the fully-depleted type SOI-PMOS 305 is used for the backflow prevention transistor, and the source or drain of the fully-depleted type SOI-PMOS 305 is connected to the positive electrode 102 or the positive terminal 106 of the load 104. The gate of the fully depleted type SOI-PMOS 305 is connected to the negative electrode 103, the substrate is connected to the gate, the negative terminal 107 of the load 104 is connected to the negative electrode 103, and a power source is connected between the positive electrode 102 and the negative electrode 103. 101 is connected.

  With the above configuration, not only the same function as in the first embodiment of the present invention is obtained, but also a partially depleted type SOI-PMOS used as a backflow prevention transistor in the first embodiment of the present invention. In contrast, the fully-depleted SOI-PMOS used as the backflow prevention transistor in the third embodiment of the present invention reduces the off-leak when the absolute value of the threshold is the same, and the same when the off-leak is the same The absolute value of the threshold can be lowered. Therefore, for the MOS as described above, the decrease in the absolute value of the threshold value is equivalent to the improvement of the driving capability. Therefore, in the third embodiment of the present invention, the first embodiment of the present invention described above is used. In addition to the effect, the backflow prevention transistor can be configured with a small area, so that the area of the IC in which the backflow prevention transistor and the load are formed on the same substrate can be reduced, or off-leakage of the backflow prevention transistor can be reduced. The current consumption when the power supply is reversely connected can be reduced.

  FIG. 4 is a schematic circuit diagram showing a circuit that consumes low power when reverse polarity power is input in an electronic apparatus according to the fourth embodiment of the present invention. As shown in FIG. 4, the depletion type SOI-PMOS 405 is used for the backflow prevention transistor, and the source or drain of the fully depletion type SOI-NMOS 405 is connected to the negative electrode 103 or the negative terminal 107 of the load 104. The gate of the fully depleted type SOI-NMOS 405 is connected to the positive electrode 102, the substrate is connected to the gate, the positive terminal 106 of the load 104 is connected to the positive electrode 102, and a power source is connected between the positive electrode 102 and the negative electrode 103. 101 is connected.

  The above configuration not only provides the same function as the first embodiment of the present invention, but also a partially depleted type SOI-NMOS used as a backflow prevention transistor in the second embodiment of the present invention. In contrast, the fully depleted type SOI-NMOS used as the backflow prevention transistor in the fourth embodiment of the present invention reduces the off-leak when the absolute value of the threshold is the same, and the same when the off-leak is the same The absolute value of the threshold can be lowered. Therefore, for the MOS as described above, a decrease in the absolute value of the threshold value is equivalent to an improvement in driving capability. Therefore, in the fourth embodiment of the present invention, the second embodiment of the present invention described above is used. In addition to the effect, the backflow prevention transistor can be configured with a small area, so that the area of the IC in which the backflow prevention transistor and the load are formed on the same substrate can be reduced, or off-leakage of the backflow prevention transistor can be reduced. The current consumption when the power supply is reversely connected can be reduced.

  FIG. 7 is a schematic circuit diagram showing a circuit that consumes less power at the time of reverse polarity power input in an electronic apparatus according to the fifth embodiment of the present invention.

  As shown in FIG. 7, the analog circuit 701 has a positive terminal 710 connected to the positive electrode 102, a negative terminal 711 connected to the source or drain of the fully depleted type SOI-NMOS 406, and the fully depleted type SOI-NMOS 406 is connected to the drain. The source is connected to the negative electrode 103, the gate is connected to the positive electrode 102, the substrate is connected to the gate, and the digital circuit 702 has the positive terminal 714 connected to the positive electrode 102 and the negative terminal 715 connected to the negative electrode 103. The power supply 101 is connected between the plus electrode 102 and the minus electrode 103.

The analog circuit 701 includes fully depleted type SOI-PMOSs 703 and 705, and fully depleted type SOI-NMOSs 704 and 716. The fully depleted type SOI-PMOS 703 has a source connected to the positive terminal 710 and a gate connected to the source. The drain of the depletion type SOI-PMOS 705 is connected to the drain of the fully depleted type SOI-NMOS 704. The fully depleted type SOI-PMOS 705 has a source connected to the positive terminal 710 and a drain connected to the drain of the fully depleted type SOI-NMOS 706. The fully-depleted SOI-NMOS 704 has a gate connected to the first input terminal 712 and a source connected to the negative terminal 711. The SOI-NMOS 706 has a gate connected to the second input terminal 713 and a source connected to the negative terminal 711. Are connected to each other.

  On the other hand, the digital circuit 702 is composed of a fully depleted type SOI-CMOS, and a fully depleted type SOI-PMOS 707 and a fully depleted type SOI-NMOS 708 are connected in series in the current path from the minus terminal 715 to the plus terminal 714 of the digital circuit 702. In the fully depleted type SOI-PMOS 707 and the fully depleted type SOI-NMOS 708, the current from the positive terminal 714 flows to the drain through the source of the fully depleted type SOI-PMOS 707, and the current from the drain is completely depleted. It flows to the source through the drain of the type SOI-NMOS 708 and is connected so that the current from the source flows to the negative terminal 715, and the gate of the fully depleted type SOI-PMOS 707 and the gate of the fully depleted type SOI-NMOS 708 are connected. It is a configuration. In the figure, a dotted line portion between the terminals 714 and 715 means that another circuit or the like can be inserted.

  In other words, in the fifth embodiment of the present invention, the digital circuit having the above configuration is configured by SOI-CMOS, so that the backflow prevention transistor is not provided between the digital circuit and the plus electrode or the minus electrode. Even if the power supply is reversely connected, since any SOI-MOS of the digital circuit is turned off, little power is consumed. Furthermore, the digital circuit having the above configuration is further configured by a fully depleted SOI-CMOS having higher drive capability than SOI-CMOS and less off-leakage, thereby reducing the digital circuit area of the above configuration and reverse connection of the power supply. Current consumption can be further reduced.

  Further, in the case of a circuit in which the digital circuit and the analog circuit are mixed, it is only necessary to provide the backflow prevention transistor only in the current path of the analog circuit through which a current always flows. The driving capability of the backflow prevention transistor can be reduced. That is, the area of the backflow prevention transistor can be reduced as compared with the first to fourth embodiments of the present invention.

  Of course, the analog circuit, digital circuit, and backflow prevention transistor can be configured with partially depleted type SOI-MOS. Since there is no kink effect, it is more effective.

  FIG. 8 is a circuit that can operate efficiently regardless of the polarity of the power supply, using a circuit that consumes low power when the reverse polarity power is input in the electronic apparatus according to the sixth embodiment of the present invention.

  As shown in FIG. 8, a first circuit 801 using the circuit shown in the first to fifth embodiments of the present invention and a second circuit 802 are provided, and the first circuit 801 is a plus terminal 712. Is connected to the negative electrode 103, and the second circuit 802 has the positive terminal 812 connected to the negative electrode 103, the negative terminal 813 connected to the positive electrode 102, and the positive electrode 102 and the negative electrode 103. In this configuration, the power supply 101 is connected.

With the above configuration, when the power supply 101 is normally connected so that the voltage of the positive electrode 102 is higher than the voltage of the negative electrode 103, the first circuit 801 operates and the second circuit 802 In addition to stopping the operation, the power of the power supply 101 is hardly consumed. On the other hand, when the power source 101 is reversely connected so that the voltage of the negative electrode 103 is higher than the voltage of the positive electrode 102, the second circuit 802 operates, and the first circuit 801 simply stops operation. And the power supply 101 consumes little power. Therefore, a circuit that can operate efficiently with the power of the power supply 101 can be realized regardless of whether the power supply 101 is normally connected or reversely connected.
The power source 101 may be a power source that may be reversely connected, such as a battery, or a natural power source that changes the polarity of the generated power depending on how natural energy such as a temperature difference is applied, such as a thermoelectric generator. In the case of an energy power generation element, it is possible to use reverse polarity power that could not be used conventionally among the power generated by the natural energy power generation element, so that a circuit that efficiently drives with the power generated by the natural energy power generation element can be realized. .

It is a schematic circuit diagram which shows the circuit used as low consumption at the time of reverse polarity electric power input in the electronic device concerning the 1st Embodiment of this invention. It is a schematic circuit diagram which shows the circuit used as low consumption at the time of reverse polarity electric power input in the electronic device concerning the 2nd Embodiment of this invention. It is a schematic circuit diagram which shows the circuit used as low consumption at the time of reverse polarity electric power input in the electronic device concerning the 3rd Embodiment of this invention. It is a schematic circuit diagram which shows the circuit which becomes low consumption at the time of reverse polarity electric power input in the electronic device concerning the 4th Embodiment of this invention. It is sectional drawing for demonstrating the structure of MOS using the SOI (Silicon on Insulator) structure used by this invention. It is a figure for demonstrating the symbol of SOI-MOS used by description of this invention for the example of partial depletion type SOI-PMOS. It is a schematic circuit diagram which shows the circuit used as low consumption at the time of reverse polarity electric power input in the electronic device concerning the 5th Embodiment of this invention. It is a schematic circuit diagram which can operate | move efficiently even if the polarity of the power supply using the circuit used at the time of reverse polarity electric power input in the electronic device concerning the 6th Embodiment of this invention becomes low. It is a schematic circuit diagram which shows the circuit used as low consumption at the time of reverse polarity electric power input in the electronic device which concerns on a prior art.

Explanation of symbols

101 Power supply 102 Positive electrode 103 Negative electrode 104 Load 105 Partially depleted type SOI-PMOS
106 Load positive terminal 205 Partial depletion type SOI-NMOS
305 Fully depleted SOI-PMOS
405 Complete depletion type SOI-NMOS
701 Analog circuit 702 Digital circuit 801 First circuit 802 Second circuit

Claims (7)

A first terminal to which the positive electrode of the power supply is to be connected;
A second terminal to which the negative electrode of the power source is to be connected;
A load connected to the first terminal and driven by receiving power from the power source;
An NMOS transistor connected between the load and the second terminal for controlling power supplied to the load;
The NMOS transistor is an SOI-MOS transistor using an SOI structure in which a buried oxide film and a silicon layer are provided on a support substrate , and the support transistor is in contact with the buried oxide film in the support substrate. A substrate region having a conductivity type different from that of the substrate is provided, and the substrate region is disposed directly under the body between the source and drain of the SOI-MOS transistor, and the gate of the SOI-MOS transistor and the substrate region are shared. Connected, and a voltage based on the voltage of the first terminal is applied,
When the normal connection is established such that the voltage at the first terminal is higher than the voltage at the second terminal, the NMOS transistor is turned on, and the voltage at the second terminal is the voltage at the first terminal. A semiconductor integrated circuit characterized in that when the reverse connection is made to be higher than that, the NMOS transistor is turned off to prevent an abnormal current from flowing through the load . A first terminal to which the positive electrode of the power supply is to be connected;
A second terminal to which the negative electrode of the power source is to be connected;
A load connected to the second terminal and driven by receiving power from the power source;
A PMOS transistor connected between the load and the first terminal for controlling power supplied to the load;
The PMOS transistor is an SOI-MOS transistor using an SOI structure in which a buried oxide film and a silicon layer are provided on a support substrate , and the support transistor is in contact with the buried oxide film in the support substrate. A substrate region having a conductivity type different from that of the substrate is provided, and the substrate region is disposed directly under the body between the source and drain of the SOI-MOS transistor, and the gate of the SOI-MOS transistor and the substrate region are shared. Connected, and a voltage based on the voltage of the first terminal is applied,
When normally connected so that the voltage of the first terminal is higher than the voltage of the second terminal, the PMOS transistor is turned on, and the voltage of the second terminal is the voltage of the first terminal. A semiconductor integrated circuit characterized by preventing the PMOS transistor from turning off and causing an abnormal current to flow through the load when reversely connected so as to be higher .   The semiconductor integrated circuit according to claim 1, wherein the SOI-MOS transistor is a fully depleted type.   4. The semiconductor integrated circuit according to claim 3, wherein the load includes a fully depleted SOI-MOS transistor formed on the support substrate.   An electronic apparatus comprising the semiconductor integrated circuit according to claim 1. A load driven by receiving supply of power from the power source connected to the first terminal to which the positive electrode of the power source is to be connected;
An NMOS transistor connected between a second terminal to which a negative electrode of the power supply is to be connected and the load, and controlling power supplied to the load;
The NMOS transistor is an SOI-MOS transistor using an SOI structure, and a substrate region is provided so as to be in contact with the buried oxide film, and the substrate region has a body between a source and a drain of the SOI-MOS transistor. Arranged directly below, the gate of the SOI-MOS transistor and the substrate region are connected in common, and a voltage based on the voltage of the first terminal is applied,
When the normal connection is established such that the voltage at the first terminal is higher than the voltage at the second terminal, the NMOS transistor is turned on, and the voltage at the second terminal is the voltage at the first terminal. An electronic device characterized in that when the reverse connection is made to be higher than that, the NMOS transistor is turned off to prevent an abnormal current from flowing through the load . A load driven by receiving supply of power from the power source connected to the second terminal to which the negative electrode of the power source is to be connected;
Anda PMOS transistor for controlling power connected, is supplied to the load between the load and the first terminal to the positive pole of the power source is connected,
The PMOS transistor is an SOI-MOS transistor using an SOI structure, and a substrate region is provided so as to be in contact with the buried oxide film, and the substrate region has a body between a source and a drain of the SOI-MOS transistor. Arranged directly below, the gate of the SOI-MOS transistor and the substrate region are connected in common, and a voltage based on the voltage of the first terminal is applied,
When normally connected so that the voltage of the first terminal is higher than the voltage of the second terminal, the PMOS transistor is turned on, and the voltage of the second terminal is the voltage of the first terminal. An electronic device characterized in that when the reverse connection is made to be higher than that, the PMOS transistor is turned off and an abnormal current is prevented from flowing through the load .

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