JP5076912B2 - Terminal sheet manufacturing method - Google Patents

Description

The present invention is related to producing how the pin seat.

  In a semiconductor device (semiconductor package) in which a semiconductor chip and a circuit board are electrically connected via bumps such as solder balls, the difference is caused by the difference in thermal expansion between the semiconductor chip after the electrical connection and the circuit board. In order to relieve the stress that occurs, filling with an underfill of an insulating resin is widely performed.

  In recent years, a terminal sheet in which conductive particles are embedded in through holes formed at predetermined positions of an insulating resin sheet has been prepared, and this is sandwiched between a semiconductor chip and a circuit board to temporarily bond them, A technique for electrically connecting a semiconductor chip and a circuit board by reflowing and melting conductive particles has also been proposed (see, for example, Patent Document 1). In this case, the conductive particles function as bumps, and the insulating resin portion functions as underfill.

Conventionally, a technique of providing a layer for relaxing stress generated between different layers in a ceramic or metal laminate has been proposed (see, for example, Patent Documents 2 to 4).
JP 2007-122965 A JP 2004-63728 A JP 7-94633 A JP 2006-297868 A

  However, recent semiconductor devices have been reduced in size in response to the increase in the density of electronic equipment components, and the number of input / output terminals for signal processing and grounding has increased with the increase in functions. Yes. Therefore, in a semiconductor device in which a semiconductor chip and a circuit board are electrically connected by bumps, it is necessary to reduce the bump pitch.

  In order to reduce the pitch, it is necessary to reduce the individual bump diameters. In that case, electrical connection is performed using a method of filling an insulating resin after electrical connection and a terminal sheet. In any of the methods, the following problems occur.

  That is, when the bump diameter is reduced to reduce the pitch, the spatial gap between the semiconductor chip and the circuit board is reduced, and the filling rate of the insulating resin functioning as an underfill is lowered. Therefore, the stress generated due to the difference in thermal expansion between the semiconductor chip and the circuit board during the reflow heating / cooling process cannot be sufficiently relaxed by the insulating resin alone.

  In addition, when the reflow is heated, the bumps become molten and the surrounding insulating resin softens and becomes fluid, so that the molten bumps penetrate such insulating resin and adjacent bumps come into contact with each other. May cause a short circuit. Furthermore, in addition to the small bump diameter, reflow heating / cooling is performed on the semiconductor chip and the circuit board having a thermal expansion difference, so that the connection failure between the bump and the semiconductor chip or between the bump and the circuit board is eliminated. It may occur.

According to one aspect of the present invention, a step of forming a first insulating sheet having a first terminal portion made of a first conductive layer, and a second conductive layer having a melting point lower than that of the first conductive layer Forming a second insulating sheet having a second terminal portion formed by laminating a third conductive layer having a melting point higher than that of the first conductive layer, and on both sides of the second insulating sheet After disposing each of the first insulating sheets, the step of aligning the positions of the first terminal portion and the second terminal portion to bond the first insulating sheet and the second insulating sheet together A method for producing a terminal sheet is provided.

According to the terminal sheet manufactured using such a method , conduction between the front and back surfaces is ensured by the terminal portion including the first conductive layer, the second conductive layer, and the third conductive layer. At the same time, the stress relaxation function is exhibited by the multi-layered terminal portion.

According to the disclosed method, it is possible to obtain a terminal sheet that relieves stress and effectively suppresses the occurrence of connection failure and short circuit, and thus a semiconductor device with high connection reliability can be obtained.

Hereinafter, it will be described in detail with reference to the drawings.
FIG. 1 is an explanatory view of a terminal sheet, and FIGS. 2 and 3 are explanatory views of a semiconductor device using the terminal sheet.

  As shown in FIG. 1, the terminal sheet 10 has a configuration in which a plurality of terminal portions 12 are arranged at predetermined positions on the insulating resin sheet 11 with their front and back surfaces exposed. The terminal sheet 10 is disposed between the semiconductor chip 20 and the circuit board 30. A plurality of electrodes 21 and 31 for external connection are formed on the semiconductor chip 20 and the circuit board 30 at positions corresponding to each other, and the terminal portion 12 is positioned corresponding to the electrodes 21 and 31. Is arranged. As shown in FIG. 2, the semiconductor chip 20 and the circuit board 30 are temporarily bonded to the front and back surfaces of the terminal sheet 10 having such a configuration, and reflow is performed in this state, whereby the electrodes 21 and the circuit of the semiconductor chip 20 are connected. The electrode 31 of the substrate 30 is electrically connected via the terminal portion 12.

  The semiconductor chip 20 is roughly divided into a semiconductor substrate portion 20a in which transistors and the like are formed and a wiring layer portion 20b in which wirings and vias are formed. Here, for convenience, it is provided for external connection. The internal elements such as transistors, wirings, and vias other than the electrode 21 are not shown. The circuit board 30 is configured by laminating one or two or more insulating substrates and wiring layers. Here, for convenience, only one insulating substrate 30a and a wiring layer 30b formed on the surface thereof are illustrated. The case where the exposed portion of the wiring layer 30b that is not coated with the solder resist 30c is used as the electrode 31 for external connection is shown.

  Here, as the insulating resin sheet 11 of the terminal sheet 10, a sheet in which an underfill material is formed (underfill sheet) can be used. Examples of the underfill material include a resin material mainly composed of a thermoplastic polyimide resin or a fluororesin.

  Here, the terminal portion 12 of the terminal sheet 10 includes an adhesive layer 12a provided on the front and back surfaces of the terminal sheet 10, a stress relaxation layer 12b provided inside the adhesive layer 12a, and an adhesive layer 12a and a stress relaxation layer 12b. Are formed in a multilayer structure including three types of layers of the barrier layer 12c.

  The adhesive layer 12a is made of, for example, a metal material that melts at a reflow heating temperature (reflow temperature), and is bonded to the electrode 21 of the semiconductor chip 20 and the electrode 31 of the circuit board 30 through a reflow heating / cooling process. The The stress relaxation layer 12b is made of a metal material having a melting point lower than that of the adhesive layer 12a, melts faster than the adhesive layer 12a in the reflow heating process, and more than the adhesive layer 12a in the reflow cooling process. It solidifies slowly and plays a role of relieving stress applied to the terminal sheet 10 during reflow. The barrier layer 12c is made of a high melting point metal material whose melting point is higher than that of the adhesive layer 12a. The barrier layer 12c adjusts the height of the terminal portion 12 and is in a molten state during reflow and the stress relaxation layer. When 12b adheres, it plays the role of stopping the outflow to those sides.

  When such a terminal sheet 10 is disposed between the semiconductor chip 20 and the circuit board 30 and reflow is performed, stress caused by a difference in thermal expansion between the semiconductor chip 20 and the circuit board 30, mainly heat of the circuit board 30. Stress due to warpage generated by expansion is applied to the terminal sheet 10.

  At that time, in the terminal sheet 10, in the reflow heating process, the stress relaxation layer 12b having the lowest melting point of the terminal portion 12 starts to melt, and then the adhesive layer 12a having the higher melting point starts to melt. The stress applied to the terminal sheet 10 during this heating process is absorbed and relaxed by the melted stress relaxation layer 12b regardless of the direction of the stress (for example, the vertical direction or the horizontal direction in FIGS. 1 and 2). The Further, the stress applied to the terminal sheet 10 is also relaxed by the adhesive layer 12a in a molten state, and the adhesive layer 12a adheres to the electrode 21 of the semiconductor chip 20 and the electrode 31 of the circuit board 30 while relaxing the stress. It becomes like this.

  At this time, in the interface region between the adhesive layer 12a and the electrode 21 and the electrode 31, the adhesive layer 12a, the electrode 21, and the electrode 31 are diffused by the diffusion of the metal material of the adhesive layer 12a and the dissolution of the metal material of the electrode 21 and the electrode 31. Reaction (metal reaction) occurs.

  In the reflow heating process, the barrier layer 12c prevents the molten adhesive layer 12a and the stress relaxation layer 12b from flowing out to the side. Therefore, even when the insulating resin sheet 11 is softened and fluidized during this heating process, the metal material of the one terminal portion 12 penetrates the softened insulating resin sheet 11 and is adjacent thereto. It is possible to prevent the adjacent terminal portions 12 from coming into contact with each other by flowing toward the other terminal portions 12.

  In the reflow cooling process, the adhesive layer 12a and the stress relaxation layer 12b, which have been melted in the heating process, are solidified. Even in this cooling process, stress caused by a difference in thermal expansion between the semiconductor chip 20 and the circuit board 30, for example, stress generated by reducing warpage of the circuit board 30 caused by thermal expansion is applied to the terminal sheet 10. become.

  At that time, in the terminal sheet 10, the adhesive layer 12a having a high melting point first solidifies out of the adhesive layer 12a and the stress relaxation layer 12b, and then the stress relaxation layer 12b having a lower melting point solidifies. A layer (not shown) of an intermetallic compound containing a diffused / dissolved metal is formed in an interface region between the adhesive layer 12a in which the metal reaction as described above has occurred and the electrode 21 and the electrode 31. As 12a solidifies, a strong bond is formed between the electrode 21 and the electrode 31. Furthermore, the stress applied to the terminal sheet 10 during this cooling process is relaxed by the molten adhesive layer 12a and the stress relaxation layer 12b while being prevented from flowing out by the barrier layer 12c, and after the adhesive layer 12a is solidified, The stress is relaxed by the stress relaxation layer 12b that solidifies at a later timing.

During reflow (heating / cooling process), the stress applied to the terminal sheet 10 is also relaxed by the insulating resin sheet 11.
Through such reflow heating / cooling process, as shown in FIG. 3, the terminal portion 12 of the terminal sheet 10 electrically connects the semiconductor chip 20 and the circuit board 30 with deformation from the initial shape. Connect.

  By using such a terminal sheet 10 for electrical connection between the semiconductor chip 20 and the circuit board 30, stress generated during reflow can be effectively relieved regardless of the direction, and the terminal portion 12, the electrode 21, and the electrode It is possible to effectively suppress the occurrence of a connection failure with 31 and a short circuit between adjacent terminal portions 12.

  In selecting the metal materials used for the adhesive layer 12a, the stress relaxation layer 12b, and the barrier layer 12c of the terminal portion 12 provided on the terminal sheet 10, the electrical conductivity and the reflow temperature are taken into consideration, and the melting points thereof are as described above. A metal material that satisfies the relationship of stress relaxation layer 12b <adhesive layer 12a <barrier layer 12c is selected.

  For the bonding layer 12a and the stress relaxation layer 12b, for example, a metal material used as solder can be used. Such metal materials include tin-copper (Sn-Cu), tin-silver-copper (Sn-Ag-Cu), tin-zinc (Sn-Zn), tin-antimony (Sn-Sb), tin- Examples include silver (Sn-Ag), tin-bismuth (Sn-Bi), tin-zinc-bismuth (Sn-Zn-Bi), tin-bismuth-silver (Sn-Bi-Ag), and the like. A combination that satisfies the above relationship (stress relaxation layer 12b <adhesive layer 12a) is selected.

  For the barrier layer 12c, a metal material (adhesive layer 12a <barrier layer 12c) having the highest melting point in the terminal portion 12 is used. For example, a metal material mainly composed of copper (Cu) or Cu, nickel ( Ni) or a metal material mainly composed of Ni can be used. The barrier layer 12c is a layer in contact with the adhesive layer 12a and the stress relaxation layer 12b, and an intermetallic compound layer can be formed in the interface region by reflow. Therefore, in selecting a metal material for the barrier layer 12c, in addition to the melting point, the influence of the adhesive layer 12a and the stress relaxation layer 12b when the component is dissolved (change in melting point due to mixing of components, etc.) is taken into consideration.

  Table 1 shows examples of combinations of metal materials that can be used for each layer of the terminal portion 12. In Table 1, the numbers in parentheses for each metal material indicate the melting point (° C.) of each metal material.

なお、この表１には、１０種類の組合せを例示したが、端子部１２に適用可能な組合せはこれらに限定されるものではない。

In addition, although 10 types of combinations were illustrated in this Table 1, the combinations applicable to the terminal part 12 are not limited to these.

  The thickness of the terminal portion 12 is not particularly limited, but is set in a range of about 100 μm to 700 μm depending on the configuration of the semiconductor device in which the terminal sheet 10 including the terminal portion 12 is used. The thicknesses of the adhesive layer 12a, the stress relaxation layer 12b, and the barrier layer 12c constituting the terminal portion 12 are set so as to satisfy the relationship of stress relaxation layer 12b <adhesion layer 12a <barrier layer 12c. preferable.

  In that case, the thickness of the stress relaxation layer 12b may be set in consideration of the stress applied to the terminal sheet 10 during reflow, for example, the amount of deformation (warpage) of the circuit board 30 during the reflow. In particular, it should be noted that if the stress relaxation layer 12b is formed too thick, the shape of the terminal portion 12 may be greatly deformed during reflow or the barrier layer 12c may not be able to suppress the outflow to the side. . Further, the adhesive layer 12a is set to a thickness required for joining the electrode 21 and the electrode 31, and similarly to the stress relaxation layer 12b, the thickness thereof is set in consideration of the stress applied to the terminal sheet 10 during reflow. That's fine. The thickness of the barrier layer 12c may be set in consideration of the thickness of the entire terminal portion 12 and the thicknesses of the adhesive layer 12a and the stress relaxation layer 12b.

  For example, when the terminal portion 12 having a thickness of about 100 μm is formed, if the thickness of the stress relaxation layer 12 b is about 10 μm, the thickness of the adhesive layer 12 a is about 20 μm and the thickness of the barrier layer 12 c is about 25 μm. Or the thickness of the adhesive layer 12a can be about 15 μm, and the thickness of the barrier layer 12c can be about 30 μm.

  In the terminal sheet 10 as described above, the barrier layer 12c of the terminal portion 12 is not necessarily formed on both surfaces of the stress relaxation layer 12b. Thus, the barrier layer 12c is formed only on one surface side of the stress relaxation layer 12b (in this case, the adhesive layer 12a is formed on the other surface side of the stress relaxation layer 12b). However, it is possible to relieve the stress applied during reflow while suppressing the outflow of the stress relieving layer 12b and the adhesive layer 12a by the barrier layer 12c.

Hereinafter, the configuration and forming method of the terminal sheet and the semiconductor device using the terminal sheet will be described more specifically.
First, the first embodiment will be described.

  Here, the case where a terminal sheet is formed using a plating method will be described. In this case, the terminal sheet is formed by laminating these two sheet members after forming the first sheet member including the adhesive layer and the second sheet member including the barrier layer and the stress relaxation layer, respectively. Form.

  4A and 4B are explanatory views of the formation process of the first sheet member, in which FIG. 4A is a diagram illustrating a punching process of the underfill sheet, FIG. 4B is a diagram illustrating a state after punching the underfill sheet, and FIG. Is a figure which shows a protective film sticking process, (D) is a figure which shows an electroless Sn plating treatment process, (E) is a figure which shows an electrolytic Sn-Cu plating treatment process.

  Here, as the insulating resin sheet, an underfill sheet in which an epoxy, cyanate ester, polyolefin, phenol, naphthalene, and silicone resin component was blended with a thermoplastic polyimide resin was used. The underfill sheet having such a composition decreases in viscosity at a heating temperature of 200 ° C. or higher, and when the curing starts, the reaction is completed within about 5 minutes.

  First, as shown in FIG. 4A, a polyethylene terephthalate (PET) film 42 (length 100 mm × width 100 mm × thickness 0.03 mm) is bonded to one side of an underfill sheet 41 (length 100 mm × width 100 mm). I prepared a dish. The thickness of the underfill sheet 41 was set based on the thickness of the adhesive layer to be formed. The thickness of the underfill sheet 41 can be set to 0.03 mm, for example. For bonding the underfill sheet 41 and the PET film 42, an acrylic adhesive (not shown) was used, and they were bonded together by applying pressure while heating to 120 ° C.

  Thereafter, as shown in FIGS. 4A and 4B, a plurality of through holes 43 were simultaneously formed by a punching press from the PET film 42 side using a predetermined mold. Here, a total of 400 through-holes 43 having a diameter of 0.1 mm were formed at a central portion of the underfill sheet 41 in a lattice shape at a pitch of 0.3 mm. After forming the through holes 43, as shown in FIG. 4C, as a protective film, the same PET film 44 (length 100 mm × width) is also applied to the surface opposite to the surface on which the punched PET film 42 is pasted. 100 mm × thickness 0.03 mm) was attached in the same manner.

  After pasting the PET film 44, as shown in FIG. 4D, an electroless Sn plating process was performed to form an electroless Sn plating layer 45a. The thickness of the electroless Sn plating layer 45a may be, for example, about 0.5 μm to 1 μm. Here, this electroless Sn plating treatment is performed using a plating solution having a composition of stannous chloride 40 g / L, thiourea 300 g / L, tartaric acid 200 g / L, and dextrin 5 g / L, a plating solution temperature of 80 ° C., and a plating time. The test was performed for 15 minutes.

Subsequently, as shown in FIG. 4E, an electrolytic Sn—Cu plating process is performed to form an electrolytic Sn—Cu plating layer 45b on the previously formed electroless Sn plating layer 45a. The through-hole 43 was embedded. The thickness of the electrolytic Sn-Cu plating layer 45b may be set so as to be the thickness of the adhesive layer to be formed together with the underlying electroless Sn plating layer 45a, and can be, for example, about 0.03 mm. . Here, this electrolytic Sn-Cu plating treatment is carried out using 30 g / L of stannous oxide, 0.5 g / L of cupric oxide, 200 g / L of methanesulfonic acid, 6 g / L of acetylthiourea, ethylene oxide 10 of octylphenol ethoxylate. A plating solution having a composition of a molar adduct 8 g / L and catechol 1 g / L was used, and metal Sn was used for the anode under conditions of a current density of 15 A / dm ² and a plating time of 8 minutes.

  The layer (hereinafter referred to as “Sn—Cu layer”) 45 composed of the electroless Sn plating layer 45a and the electrolytic Sn—Cu plating layer 45b in the first sheet member 40 thus formed is finally a terminal sheet. It functions as an adhesive layer for the terminal part.

  5A and 5B are explanatory views of the formation process of the second sheet member, in which FIG. 5A is a view showing a punching process of the underfill sheet, FIG. 5B is a view showing a state after punching the underfill sheet, and FIG. Is a diagram showing a protective film attaching step, (D) is a diagram showing an electroless Cu plating treatment step, (E) is a diagram showing an electrolytic Cu plating treatment step, (F) is a diagram showing a protective film peeling step, ( (G) is a figure which shows a resist formation process, (H) is a figure which shows an electrolytic Sn-Zn plating process, (I) is a figure which shows a resist peeling process.

  First, as in the formation of the first sheet member 40 described above, as shown in FIG. 5A, an acrylic adhesive (not shown) is provided on one side of an underfill sheet 51 (length 100 mm × width 100 mm). ) Was applied at 120 ° C. to attach a PET film 52 (length 100 mm × width 100 mm × thickness 0.03 mm). The thickness of the underfill sheet 51 was set based on the thickness of the barrier layer and the stress relaxation layer to be formed. The thickness of the underfill sheet 51 can be set to 0.120 mm, for example.

  Thereafter, in the same manner, as shown in FIGS. 5A and 5B, the diameter of the underfill sheet 51 in the central portion of the underfill sheet 51 is measured by a punching press from the PET film 52 side using a mold. A total of 400 0.1 mm through-holes 53 with a 0.3 mm pitch were formed simultaneously. After the formation of the through-hole 53, as shown in FIG. 5C, the same PET film 54 (length 100 mm × width) is formed on the surface opposite to the surface on which the punched PET film 52 is pasted as a protective film. 100 mm × thickness 0.03 mm) was attached in the same manner.

  After pasting the PET film 54, as shown in FIG. 5D, an electroless Cu plating process was performed to form an electroless Cu plating layer 55a. The thickness of the electroless Cu plating layer 55a may be about 0.5 μm to 1 μm. Here, this electroless Cu plating treatment is performed using copper sulfate pentahydrate 10 g / L, ethylenediaminetetraacetic acid tetrasodium 30 g / L, 37% formaldehyde 3 ml / L, polyethylene glycol 2 g / L, α, α′- A plating solution having a dipyridyl composition was used under the conditions of a plating solution temperature of 60 ° C. and a plating time of 15 minutes.

Subsequently, as shown in FIG. 5E, electrolytic Cu plating treatment was performed, and an electrolytic Cu plating layer 55b was formed on the electroless Cu plating layer 55a so as to embed the through holes 53. The thickness of the electrolytic Cu plating layer 55b may be set so as to be the thickness of the barrier layer to be formed together with the underlying electroless Cu plating layer 55a, for example, about 0.11 mm. Here, this electrolytic Cu plating treatment is carried out using copper sulfate pentahydrate 225 g / L, 98% sulfuric acid 55 g / L, chlorine ions 60 mg / L, amines and glycidyl ether reaction condensate (KB12, manufactured by Kyoyo Chemical Industry). / L, a bissulfo organic compound (SO ₃ H—C ₃ H ₆ —S—S—C ₃ H ₆ —SO ₃ H) using a plating solution of 6 mg / L, using metal Cu as the anode, and current density It was performed under the conditions of 2 A / dm ² and plating time of 80 minutes.

  The layer (hereinafter referred to as “Cu layer”) 55 formed of the electroless Cu plating layer 55a and the electrolytic Cu plating layer 55b thus formed finally functions as a barrier layer of the terminal portion in the terminal sheet.

  After the formation of the Cu layer 55, the PET film 52 on one surface side of the underfill sheet 51 was peeled off as shown in FIG. Then, as shown in FIG. 5G, a resist 56 is applied on the entire surface with a thickness of about 0.015 mm to 0.02 mm so that the through hole 53 of the underfill sheet 51 has an opening. Patterned.

After performing such patterning, as shown in FIG. 5H, electrolytic Sn—Zn plating treatment is performed, and an electrolytic Sn—Zn plating layer (“Sn—Zn layer”) is formed on the Cu layer 55. ) 57 was formed. What is necessary is just to set the thickness of a Sn-Zn layer based on the thickness of the stress relaxation layer which should be formed, for example, can be about 0.01 mm. Here, this electrolytic Sn—Zn plating treatment is carried out using tin sulfate 30 g / L, phenolsulfonic acid 60 g / L, zinc sulfate 250 g / L, ammonium sulfate 30 g / L, nonionic active agent (Daiichi Kogyo Seiyaku Neugen) 6 g / Using a plating solution of composition L, the current density was 5 A / dm ² and the plating time was 30 minutes. After the treatment, the resist 56 was removed as shown in FIG.

  Note that it is also possible to form the Sn—Zn layer 57 by performing this electrolytic Sn—Zn plating treatment after the step of forming the electrolytic Cu plating layer 55b shown in FIG. However, in that case, when the thickness of the Sn—Zn layer 57 to be formed is thin, it should be noted that such a Sn—Zn layer 57 may be peeled together when the PET film 52 is peeled off.

The Sn—Zn layer 57 in the second sheet member 50 formed in this way finally functions as a stress relaxation layer of the terminal portion in the terminal sheet.
In order to form one terminal sheet, each of the first sheet member 40 and the second sheet member 50 as described above was formed, and the terminal sheet was formed by laminating them.

6A and 6B are explanatory diagrams of a process for forming a terminal sheet, in which FIG. 6A is a diagram showing the arrangement relationship between the first sheet member and the second sheet member, and FIG. 6B is a diagram showing a state after lamination.
When the terminal sheet is formed using the first sheet member 40 and the second sheet member 50, as shown in FIG. 6A, the pair of second sheet members 50 from which the PET film 54 has been peeled are Sn— The first sheet member 40 from which the PET film 42 was peeled was disposed with the Sn-Cu layer 45 opposed to the Cu layer 55 of the second sheet member 50 so that the Zn layers 57 were opposed to each other and sandwiched between them. .

  And after aligning correctly, the whole is integrated by temporarily crimping | bonding between the 2nd sheet members 50 and between the 1st sheet member 40 and the 2nd sheet member 50, FIG.6 (B) A terminal sheet 60 as shown in FIG. This temporary press-bonding can be performed by applying a pressure of 0.1 MPa to 0.5 MPa under a temperature of about 120 ° C. to 150 ° C. By such temporary pressure bonding, mainly between the first sheet member 40 and the second sheet member 50 and between the second sheet members 50 at the portions of the underfill sheet 41 and the underfill sheet 51, An integrated terminal sheet 60 was obtained. Note that in FIG. 6B, the one set of Sn—Zn layers 57 illustrated in FIG. 6A is illustrated as a single Sn—Zn layer 57, and the one set illustrated in FIG. The underfill sheet 41 and a set of underfill sheets 51 are illustrated as a single-layer underfill sheet 61.

  In this way, the terminal having the terminal portion 62 in which the Sn—Cu layer 45 as the adhesive layer, the Sn—Zn layer 57 as the stress relaxation layer, and the Cu layer 55 as the barrier layer are laminated in the underfill sheet 61. A sheet 60 was formed.

Subsequently, the printed circuit board of FR-4 and a semiconductor chip of a predetermined size were connected using the terminal sheet 60 thus obtained.
FIG. 7 is an explanatory diagram of a connection process between the terminal sheet and the printed circuit board.

  First, the Sn—Cu layer 45 that is the adhesive layer of the terminal sheet 60 from which the PET films 44 on both sides were peeled and the electrode 71 of the printed circuit board 70 were aligned. Then, adhesion was performed at room temperature from the aligned state. 7 shows the insulating substrate 70a, the wiring layer 70b, and the solder resist 70c. The exposed portion of the wiring layer 70b that is not coated with the solder resist 70c of the printed circuit board 70 is an electrode 71. .

FIG. 8 is an explanatory diagram of a connection process between the terminal sheet and the semiconductor chip after being connected to the printed circuit board.
After bonding to the printed circuit board 70, first, a flux 82 was applied on the Sn—Cu layer 45 on the surface side of the terminal sheet 60 to which the semiconductor chip 80 is bonded. Here, a semiconductor chip 80 having a size of 10 mm long × 10 mm wide × 0.5 mm thick was used. In FIG. 8, illustration of internal elements such as transistors and wirings of the semiconductor chip 80 composed of the semiconductor substrate portion 80a and the wiring layer portion 80b is omitted, and only the electrode 81 exposed to the outside is shown.

  Such a semiconductor chip 80 is aligned with the Sn-Cu layer 45 and the electrode 81 on the terminal sheet 60 after the flux 82 is applied using a chip bonder, and a load of 0.5 kg is applied at room temperature. Was bonded for 5 seconds.

FIG. 9 is a diagram illustrating a configuration example of a semiconductor device.
After the terminal sheet 60 and the semiconductor chip 80 were bonded, they were put into a reflow furnace (maximum temperature 260 ° C.) in a nitrogen (N ₂ ) atmosphere, and heated and cooled. Thereby, the Sn—Cu layer 45 of the terminal sheet 60 is joined to the electrode 71 of the printed circuit board 70 and the electrode 81 of the semiconductor chip 80, and the Cu layer 55 and the Sn—Cu layer 45 and Sn—Zn on both sides thereof are joined. The layer 57 was joined to form a semiconductor device in which the printed circuit board 70 and the semiconductor chip 80 were electrically connected.

  During this reflow, the stress caused by the difference in thermal expansion between the printed circuit board 70 and the semiconductor chip 80 is absorbed by the terminal sheet 60 and relaxed. That is, in the reflow heating process, first, the lowest melting point Sn—Zn layer 57 functioning as a stress relaxation layer starts to melt, and the stress applied to the terminal sheet 60 is relaxed at this time. The Sn—Cu layer 45 functioning as an adhesive layer starts to melt following the melting of the Sn—Zn layer 57 and causes a metal reaction between the electrode 71 and the electrode 81 while relaxing the stress. The Cu layer 55 functioning as a barrier layer does not melt in this heating process, prevents the Sn—Zn layer 57 and the Sn—Cu layer 45 from flowing out to the side, and the height of the terminal portion 62 of the terminal sheet 60. Contribute to maintenance. In the reflow cooling process, the Sn—Cu layer 45 is solidified to form a strong bond between the electrode 71 and the electrode 81. At that time, since the Sn—Zn layer 57 is solidified at a later timing, the stress generated in the cooling process is also relaxed by the Sn—Zn layer 57. During reflow, the underfill sheet 61 also contributes to stress relaxation.

  Here, the evaluation results of the semiconductor device obtained by the method of the first embodiment will be described. First, when the cross-sectional SEM observation of the obtained semiconductor device was performed, it was confirmed that no short circuit occurred between the terminal portions 62 of the terminal sheet 60, and the printed circuit board 70, the semiconductor chip 80, and the terminals of the terminal sheet 60 were confirmed. It was confirmed that there was no poor connection with the part 62. Further, when a temperature cycle test at -25 ° C to 125 ° C was conducted, an electric resistance value equivalent to the initial value was obtained even after 1000 cycles, and good results could be obtained. With the above method, it was possible to obtain a semiconductor device with high connection reliability in which connection failures and short circuits were effectively suppressed.

Next, a second embodiment will be described.
Here, the case where the terminal part of a terminal sheet is formed by laminating | stacking a thin plate is demonstrated.

  10A and 10B are explanatory views of the process of forming the terminal sheet, where FIG. 10A is a view showing a punching process of the underfill sheet, FIG. 10B is a view showing a state after the underfill sheet is punched, and FIG. The figure which shows a film sticking process, (D) is a figure which shows a 1st Sn-Ag-Cu layer filling process, (E) is a figure which shows a 1st Cu layer filling process, (F) is a Sn-Bi layer The figure which shows a filling process, (G) is a figure which shows a 2nd Cu layer filling process, (H) is a figure which shows a 2nd Sn-Ag-Cu layer filling process.

  Here, as the insulating resin sheet, an underfill sheet in which an epoxy-based resin, a cyanate ester-based resin, a polyolefin-based resin, a phenol-based resin, a naphthalene-based resin, and a silicone-based resin component are blended is used. The underfill sheet having such a composition decreases in viscosity at a heating temperature of 200 ° C. or higher, and when the curing starts, the reaction is completed within about 5 minutes.

  First, as shown in FIG. 10A, a PET film 102 (length 100 mm × width 100 mm × thickness 0.03 mm) is placed on one side of an underfill sheet 101 (length 100 mm × width 100 mm × thickness 0.29 mm). A pasted one was prepared. The underfill sheet 101 and the PET film 102 were bonded together by using an acrylic adhesive (not shown) and applying pressure while heating to 120 ° C.

  Thereafter, as shown in FIGS. 10A and 10B, a plurality of through-holes 103 were simultaneously formed by a punching press from the PET film 102 side using a mold. Here, a total of 360 through-holes 103 having a diameter of 0.2 mm were formed at a central portion of the underfill sheet 101 in a lattice shape at a pitch of 0.4 mm. After the formation of the through-hole 103, as shown in FIG. 10C, the same PET film 104 (length 100 mm × width) is formed on the surface opposite to the surface on which the punched PET film 102 is pasted as a protective film. 100 mm × thickness 0.03 mm) was attached in the same manner.

  After pasting the PET film 104, first, as shown in FIG. 10D, a thin plate-like Sn—Ag—Cu-based solder preform (referred to as “Sn—Ag—Cu layer”) having a thickness of 0.05 mm. ) 105 a was filled into the inside from the opening side (PET film 102 side) of the through-hole 103. Subsequently, as shown in FIG. 10 (E), a rolled Cu foil having a thickness of 0.08 mm punched out to a diameter of 0.2 mm (referred to as “Cu layer”) 106a is replaced with an Sn—Ag—Cu layer 105a. Was filled in the through-hole 103 filled with. Further, as shown in FIG. 10 (F), a thin plate-like Sn—Bi solder preform (referred to as “Sn—Bi layer”) 107 having a thickness of 0.03 mm is formed of an Sn—Ag—Cu layer 105a and The through-hole 103 filled with the Cu layer 106a was filled.

  Next, as shown in FIG. 10 (G), a Cu layer 106b obtained by punching a rolled Cu foil having a thickness of 0.08 mm to a diameter of 0.2 mm is filled on the Sn-Bi layer 107 in the through hole 103 again. Further, as shown in FIG. 10 (H), a thin plate-like Sn—Ag—Cu-based solder preform (Sn—Ag—Cu layer) 105 b having a thickness of 0.05 mm is placed in the through-hole 103. The Cu layer 106b was filled.

  In this way, the terminal sheet 100 having the terminal portion 108 in which the Sn—Ag—Cu layer 105a, the Cu layer 106a, the Sn—Bi layer 107, the Cu layer 106b, and the Sn—Ag—Cu layer 105b were sequentially laminated was formed. The Sn—Ag—Cu layer 105 a and the Sn—Ag—Cu layer 105 b of the terminal sheet 100 are in the outermost layer of the terminal portion 108 and function as an adhesive layer. The Cu layer 106a and the Cu layer 106b arranged on the inside function as a barrier layer. In addition, the Sn—Bi layer 107 at the center functions as a stress relaxation layer.

  Subsequently, the printed circuit board 70 and the semiconductor chip 80 were connected using the terminal sheet 100 thus obtained. Here, prior to these connections, first, a preliminary soldering process was performed on the printed circuit board 70.

FIG. 11 is an explanatory diagram of a preliminary soldering process for a printed circuit board.
On the electrode 71 of the printed circuit board 70, a Sn—Ag—Cu based paste was applied as the preliminary solder 72 using the metal mask 110.

FIG. 12 is an explanatory diagram of a connection process between the printed circuit board and the terminal sheet after preliminary solder formation.
The printed circuit board 70 in which the preliminary solder 72 was formed on the electrode 71 was connected to the terminal sheet 100. In that case, after the PET film 102 punched out of the terminal sheet 100 is peeled off, the terminal sheet 100 is placed on a predetermined stage (not shown) with the PET film 104 side down and sucked to the stage side. Fixed. Then, the preliminary solder 72 side of the printed circuit board 70 is opposed to the terminal sheet 100 on the stage, and the Sn—Ag—Cu layer 105 b of the terminal portion 108 and the preliminary solder 72 on the electrode 71 are aligned. Glued.

Thereafter, it can be performed in the same manner as shown in FIG. 8 of the first embodiment. That is, the surface of the printed circuit board 70 to which the terminal sheet 100 is bonded is turned up, and the PET film 104 remaining on the terminal sheet 100 is peeled off, and then the Sn-Ag-Cu layer 105a on the surface side to which the semiconductor chip 80 is bonded. The flux was applied on the top. Then, the Sn—Ag—Cu layer 105a and the electrode 81 of the semiconductor chip 80 were aligned, and a load of 1 kg was applied for 5 seconds at room temperature to bond the semiconductor chip 80. Then, put into a reflow furnace N ₂ atmosphere (maximum temperature 260 ° C.), was subjected to heating and cooling. Thereby, the Sn-Ag-Cu layer 105a of the terminal sheet 100 and the electrode 81 of the semiconductor chip 80, the Sn-Ag-Cu layer 105b of the terminal sheet 100, and the electrode 71 of the printed circuit board 70 are joined, and further the Cu layer 106a and Sn-Ag-Cu layer 105a and Sn-Bi layer 107, and Cu layer 106b and Sn-Ag-Cu layer 105b and Sn-Bi layer 107 are joined to electrically connect printed circuit board 70 and semiconductor chip 80. Connected semiconductor devices were formed.

  In this reflow, the Sn—Ag—Cu layer 105a and the Sn—Ag—Cu layer 105b of the terminal sheet 100 function as an adhesive layer, the Cu layer 106a and the Cu layer 106b function as a barrier layer, and Sn—Bi. The layer 107 functions as a stress relaxation layer. Therefore, the stress caused by the difference in thermal expansion between the printed circuit board 70 and the semiconductor chip 80 is effectively relieved.

  When the semiconductor device obtained by the method of the second embodiment was evaluated, a short circuit between the terminal portions 108 of the terminal sheet 100 was not confirmed in the cross-sectional SEM observation, and the printed circuit board 70 and the semiconductor chip 80 Connection failure with the terminal part 108 of the terminal sheet 100 was not confirmed. In addition, good results could be obtained even in a temperature cycle test of -25 ° C to 125 ° C. By the above method, a semiconductor device with high connection reliability in which short circuit and connection failure are effectively suppressed can be obtained.

  In the above description, regarding the terminal portion of the terminal sheet, it is possible to provide a structure in which a barrier layer is provided on both surfaces or one surface of a single stress relaxation layer, and an adhesive layer is provided on the outer side thereof. As described above, two or more stress relaxation layers may be provided. In that case, a barrier layer is also provided between the stress relaxation layers.

  In addition, the adhesive layers exposed on the front and back surfaces of the terminal portion of the terminal sheet, the stress relaxation layers in the case where two or more layers are provided in the terminal portion, and the barrier layers do not necessarily have to have the same thickness.

  Further, the adhesive layers in the terminal portions, the stress relaxation layers in the case where two or more layers are provided in the terminal portions, and the barrier layers do not necessarily have to be made of the same material. For example, the adhesive layer exposed on the front surface and the adhesive layer exposed on the back surface may be configured using materials that are optimum for each according to the form (material, etc.) of the electrodes to be joined to each. .

  In the above description, the case where a metal material is used for the adhesive layer, the stress relaxation layer, and the barrier layer constituting the terminal portion of the terminal sheet has been described as an example. A conductive material having properties and functions can be used, and for each layer, a metal material and another conductive material can be used in combination.

It is explanatory drawing of a terminal sheet. It is explanatory drawing (the 1) of the semiconductor device using a terminal sheet. It is explanatory drawing (the 2) of the semiconductor device using a terminal sheet. It is explanatory drawing of the formation process of a 1st sheet | seat member, Comprising: (A) is a figure which shows the punching process of an underfill sheet, (B) is a figure which shows the state after punching of an underfill sheet, (C) is a protective film The figure which shows an affixing process, (D) is a figure which shows an electroless Sn plating process, (E) is a figure which shows an electrolytic Sn-Cu plating process. It is explanatory drawing of the formation process of a 2nd sheet | seat member, Comprising: (A) is a figure which shows the punching process of an underfill sheet, (B) is a figure which shows the state after punching of an underfill sheet, (C) is a protective film The figure which shows an affixing process, (D) is a figure which shows an electroless Cu plating process, (E) is a figure which shows an electrolytic Cu plating process, (F) is a figure which shows a protective film peeling process, (G) is The figure which shows a resist formation process, (H) is a figure which shows an electrolytic Sn-Zn plating process process, (I) is a figure which shows a resist peeling process. It is explanatory drawing of the formation process of a terminal sheet, Comprising: (A) is a figure which shows the arrangement | positioning relationship of a 1st sheet member and a 2nd sheet member, (B) is a figure which shows the state after lamination | stacking. It is explanatory drawing of the connection process of a terminal sheet and a printed circuit board. It is explanatory drawing of the connection process of the terminal sheet and semiconductor chip after connecting to a printed circuit board. It is a figure which shows the structural example of a semiconductor device. It is explanatory drawing of the formation process of a terminal sheet, (A) is a figure which shows the punching process of an underfill sheet, (B) is a figure which shows the state after punching of an underfill sheet, (C) is a protective film affixing The figure which shows a process, (D) is a figure which shows a 1st Sn-Ag-Cu layer filling process, (E) is a figure which shows a 1st Cu layer filling process, (F) is a Sn-Bi layer filling process. The figure shown, (G) is a figure which shows a 2nd Cu layer filling process, (H) is a figure which shows a 2nd Sn-Ag-Cu layer filling process. It is explanatory drawing of the preliminary soldering process of a printed circuit board. It is explanatory drawing of the connection process of the printed circuit board after preliminary solder formation, and a terminal sheet.

Explanation of symbols

10, 60, 100 Terminal sheet 11 Insulating resin sheet 12, 62, 108 Terminal portion 12a Adhesive layer 12b Stress relaxation layer 12c Barrier layer 20, 80 Semiconductor chip 20a, 80a Semiconductor substrate portion 20b, 80b Wiring layer portion 21, 31, 71, 81 Electrode 30 Circuit board 30a, 70a Insulating board 30b, 70b Wiring layer 30c, 70c Solder resist 40 First sheet member 41, 51, 61, 101 Underfill sheet 42, 44, 52, 54, 102, 104 PET film 43, 53, 103 Through-hole 45 Sn-Cu layer 45a Electroless Sn plating layer 45b Electrolytic Sn-Cu plating layer 50 Second sheet member 55, 106a, 106b Cu layer 55a Electroless Cu plating layer 55b Electrolytic Cu plating layer 56 Resist 57 Sn-Zn layer 70 p Lint circuit board 72 Pre-solder 82 Flux 105a, 105b Sn-Ag-Cu layer 107 Sn-Bi layer 110 Metal mask

Claims (1)

  Forming a first insulating sheet having a first terminal portion made of a first conductive layer;
  A second insulation having a second terminal portion in which a second conductive layer having a melting point lower than that of the first conductive layer and a third conductive layer having a melting point higher than that of the first conductive layer are stacked. Forming a sheet;
  After disposing the first insulating sheet on each side of the second insulating sheet, the first insulating sheet and the second terminal are aligned by aligning the positions of the first terminal portion and the second terminal portion. A process of bonding the insulating sheet and
  A method for producing a terminal sheet, comprising:

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