JP5055786B2 - MOS type semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a MOS semiconductor device such as an IGBT (insulated gate bipolar transistor) having a trench gate structure, which is used in a power conversion device or the like.

  As the power consumption of power converters continues to decrease, there is a strong demand for lower power consumption of power devices themselves that play a central role in the devices. Among such power devices, in particular, the use of insulated gate bipolar transistors (IGBT), which can achieve a low on-voltage due to the conductivity modulation effect and can be easily gate-controlled by voltage drive, has been increasing in recent years.

  As for the IGBT, a well-known planar gate type IGBT in which a gate electrode is provided along the substrate surface of the wafer, and a trench in which a trench (groove) is formed vertically from the substrate surface and the gate electrode is embedded through an oxide film therein. There is a trench type IGBT having a gate structure. In the latter trench type IGBT, since channels are formed on both side walls of the trench formed perpendicular to the substrate surface, the channel density can be increased and the on-voltage can be further reduced as compared with the planar gate type IGBT. There are benefits. Therefore, in recent years, the number of trench type IGBTs employing a trench gate structure has increased.

  FIG. 9 shows a conventional trench gate structure IGBT (hereinafter referred to as a trench type IGBT), a part of the (cell region) active region 12 located in the center of the chip, a carrier discharge region 17 surrounding the active region 12, and a peripheral structure portion 13. FIG. FIG. 10 shows a conventional trench IGBT having no island-shaped IGBT unit cell region between parallel stripe-shaped trenches without a carrier discharge region, and the emitter electrode 9 covered on the surface of the cell region 12. The schematic plan view drawn to see through is shown. FIG. 11 is a schematic cross-sectional view of the vicinity of the surface at A-A ′ in FIG. 10.

The structure, operation, on-voltage characteristics and improvement method of the above-described trench type IGBT will be described with reference to FIG. 9, FIG. 10, and FIG. FIG. 9 shows an n-channel IGBT chip having a trench gate structure having a stripe-like planar shape, and the periphery of the chip including the cell region (active region) 12, the carrier discharge region 17, and the peripheral structure portion 13 is formed as a trench gate. It is the schematic sectional drawing which cut | disconnected the stripe-shaped planar shape of this at right angle direction. In FIG. 9, a p-type base region 3 is formed on the surface of the silicon substrate composed of the high impurity concentration p-type collector region 1 and the low impurity concentration n-type drift region 2 on the drift region 2 side, and the surface of the p-type base region 3 is formed. An n ⁺ emitter region 4 is selectively formed. Further, a trench (groove) 5 that penetrates the p-type base region 3 perpendicularly from the surface of the n ⁺ emitter region 4 and reaches the n-type drift region 2 is formed. The trench 5 is filled with a gate electrode 7 made of polycrystalline silicon with a gate oxide film 6 interposed therebetween. The gate electrode 7 is connected to a gate pad (not shown) on the chip surface by a gate wiring 14. An interlayer insulating film 8 is formed immediately above the gate electrode 7 and further insulated from the emitter electrode 9 formed thereon. The emitter electrode 9 is coated so as to be in common contact with the surface of the n ⁺ emitter region 4 and the surface of the p-type base region 3. Further, a nitride film or an amorphous silicon film as a passivation film may be formed on the emitter electrode 9, but this is omitted in this figure. Further, the collector electrode 10 is covered on the front surface (back surface) on the p-type collector region 1 side. The peripheral structure 13 is formed in the periphery surrounding the cell region 12 constituting the active region of the chip, and the silicon surface is protected by an insulating film 15 so that the breakdown voltage can be maintained with high reliability, and a guard for ensuring a high breakdown voltage. A ring 16 structure is formed. The carrier discharge region 17 has a structure in which the n emitter region 4 adjacent to the trench 5 is not provided in the p base region 3, so that carriers are concentrated in the cell region 12 in the vicinity of the boundary with the peripheral structure portion 13 at the time of turn-off. However, it has a function to prevent the current from being interrupted.

  Next, the operation for turning on the trench IGBT will be described.

The emitter electrode 9 is normally grounded to ground, and a voltage higher than the threshold voltage is applied to the gate electrode 7 via a gate resistance from a gate drive circuit (not shown) while a voltage higher than that of the emitter electrode 9 is applied to the collector electrode 10. Is added, the IGBT is turned on and turned off at a voltage lower than the threshold. When a voltage higher than the threshold value is applied to the gate electrode 7, first, charges start to be accumulated in the gate electrode 7, and at the same time as the charges are accumulated in the gate electrode 7, The portion facing the electrode 7 is inverted to n-type to form a channel portion. As a result, an electron current is injected from the emitter electrode 9 through the n ⁺ emitter region 4 and the channel region of the p-type base region 3 into the n-type drift region 2. The injected electrons cause a forward bias between the p-type collector region 1 and the n-type drift region 2, and holes are injected from the collector electrode 10 to be turned on. The voltage drop between the emitter electrode 9 and the collector electrode 10 of the IGBT in the on state is the on voltage. In particular, the on-voltage between the collector and the emitter when a rated current is passed is referred to as a saturation voltage Vce (sat).

  Next, in order to switch the IGBT from the on state to the off state, the voltage between the emitter electrode 9 and the gate electrode 7 is set to a threshold value or less so that the charge accumulated in the gate electrode 7 is passed through the gate resistance to the gate drive circuit. Is discharged. At that time, the channel region that has been inverted to the n-type returns to the p-type, and the supply of electrons stops when the channel region disappears. This eliminates the injection of holes, so that the electrons and holes accumulated in the n-type drift region 2 are discharged to the collector electrode 10 and the emitter electrode 9, respectively, or recombined with each other, thereby causing the current to flow. It disappears and the IGBT is turned off.

In order to reduce the on-voltage of the trench IGBT, a known improvement method that has been carried out is described below. The IEGT (INJECTION ENHANCED GATE BIPOLOR TRANSISTOR) described in the following Patent Document 1 is improved so that a limit ON voltage characteristic close to a forward voltage drop characteristic of a diode can be obtained. In this method, the n ⁺ emitter region and the p-type base region are partially covered with an insulating layer so that the emitter electrode does not contact the surface of the covered region. The operation of this IEGT is basically the same as that of a conventional trench IGBT, but the holes under the p-type base region where the n ⁺ emitter region and the p-type base region are not in contact with the emitter electrode are Since it is difficult to be discharged to the emitter electrode, it accumulates under the p-type base region. As a result, the carrier concentration distribution in the n-type drift region reaches close to that of the diode, and can be lowered from the on-voltage of a normal trench IGBT. However, as described above, when the carrier concentration in the region close to the p base region in the n-type drift region is increased, the high-speed switching property is deteriorated. That is, in the trench type IGBT and IEGT, since the trench structure is formed at a high density, the on-voltage is reduced, but the capacitance between the gate electrode and the emitter electrode is increased, and the switching loss (particularly the turn-off loss) is increased. To do. However, since the power device actually has not only low on-voltage characteristics but also high-speed switching characteristics, the aforementioned switching characteristics are not preferable. In other words, the generated loss of the power device occurs as the sum of the steady loss determined by the on-voltage and the switching loss during the on-operation and off-operation, so it is not enough to reduce the on-voltage, which is the cause of the switching loss. That is, it is necessary to reduce the capacitance between the gate electrode and the emitter electrode. Here, there is room for further improvement of the conventional trench IGBT and IEGT, and this is a problem to be improved.

  One specific method for reducing the capacitance between the gate electrode and the emitter electrode described above has already been suggested in Patent Document 2 below. The same figure as FIG. 1 described in Patent Document 2 is replaced with a common reference numeral having the same function as that of FIG. In FIG. 12, by covering the p region 11 with the interlayer insulating film 8 so as not to contact the emitter electrode 9, it becomes difficult for holes to be discharged to the emitter electrode 9. As a result, the carrier concentration distribution in the n-type drift region 2 is close to that of the diode. Further, the surface of the p region 11 is entirely covered with the interlayer insulating film 8 and, of course, does not include the trench gate structure portions 5, 6, and 7. Therefore, the capacitance between the gate electrode 7 and the emitter electrode 9 is correspondingly increased. Thus, the charge / discharge time is shortened and the switching loss is reduced (Patent Document 2). In other symbols, 4 indicates an emitter region, 1 indicates a p collector region, and 10 indicates a collector electrode.

  On the other hand, in the trench IGBT, when minority carrier holes are discharged to the emitter electrode in the turn-off process, it is necessary to discharge holes existing in the n-type drift region 2 below the peripheral structure portion. As the current increases, the concentration of carriers is likely to occur in the active region closest to the peripheral structure, and the parasitic npn transistor structure in the neighboring cell region is likely to be conducted. It was a problem. As a measure for preventing the reduction of the cutoff current, a p-type region (side diffusion region) that does not form an n-type source region is provided in the cell region closest to the peripheral structure portion, and a parasitic npn transistor is provided in that region There is known a method of promoting minority carrier discharge at the time of turn-off by connecting to the emitter electrode without forming a layer (Patent Document 3). Incidentally, the carrier discharge region 17 described in the trench type IGBT shown in FIG. 9 has an effect of improving the cutoff current similar to that of the side diffusion region described in Patent Document 3.

Furthermore, by selectively forming the p-type base region of the trench IGBT not over the entire surface of the wafer, the area where holes injected into the n-drift region flow out of the emitter electrode is reduced, and the n-drift region The method of suppressing the decrease in the carrier concentration accumulated on the emitter electrode side and reducing the on-voltage (saturation voltage: Vce (sat)) has already been disclosed (Patent Document 4).
JP-A-5-243561 (FIG. 101) JP 2001-308327 A (FIG. 1) Japanese Patent Laid-Open No. 9-270512 JP 2000-228519 A

  In consideration of the above-mentioned problems, the trench type IGBT having the selective p base region described in Patent Document 4 is further improved so as to achieve both improvement in switching characteristics and reduction in on-voltage. The resulting structure is a trench IGBT having an island-shaped cell region shown by the plan view of the relevant part in FIG. 10 and the cross-sectional view of the relevant part in FIG. This trench IGBT has an IGBT unit cell 12-1 region divided into islands in a region sandwiched between parallel trenches 5 formed on the surface of the active region 12 and having a striped planar pattern. In FIG. 10, there is a peripheral structure portion (not shown) on the right side of the figure, and the right end thereof is a chip end. The left side in the figure is the direction of the center of the chip.

  However, according to the trench type IGBT, the p base region 3 is manufactured in an island shape (cell shape), and the effective discharge area of injected minority carriers (the emitter electrode 9 and the p type base region 3 are in contact with each other). The total area of the contact holes 18) is reduced, so that both the reduction of the on-voltage and the improvement of the switching characteristics can be obtained. However, the conventional IGBT having the p-type base region 3 formed on the entire surface, or the p-type base region Minority carrier concentration is more likely to occur near the peripheral structure 13 side in the active region 12 than the conventional trench IGBT in which 3 is formed in a stripe shape along the longitudinal direction of the trench, and the interruptable current is reduced. I found out that

  On the other hand, as described above, the carrier discharge region described in FIG. 9 and Patent Document 3 having the effect of improving the interruptable current is an annular region surrounding the cell region which is the active region. However, since this annular carrier discharge region is originally an ineffective region as the function of the IGBT, if the area is increased in order to improve the cutoff current improvement effect by the annular region, the area of the IGBT cell region (active (Area area) tends to be relatively small, and the saturation voltage (Vce (sat)) in the ON state increases rapidly, so there is a limit to simply increasing the carrier discharge area.

  The present invention has been made in view of the above-described points, and the object of the present invention is to suppress an increase in on-state voltage in the on-state without deteriorating switching characteristics and to improve an interruptable current. The present invention provides a trench type MOS semiconductor device that can be measured.

According to the first aspect of the present invention, the first conductivity type first semiconductor layer, the second conductivity type second semiconductor layer stacked on the first semiconductor layer, and the first conductivity type Two grooves formed in a vertical direction having a parallel stripe-like planar pattern on the surface of the semiconductor layer, and the parallel adjacent to the surface of the second semiconductor layer located between the adjacent parallel grooves A plurality of first-conductivity-type third semiconductor regions that are in contact with both sides of the trench and are spaced apart from each other and are shallower than the depth of the trench, and a surface of the third semiconductor region, A fourth semiconductor region of a second conductivity type that is in contact with an adjacent parallel groove on one side and is opposed to each other; a gate electrode embedded in the groove with an insulating film; and the third semiconductor In contact with both the surface of the region and the surface of the fourth semiconductor region, on the gate electrode In a MOS type semiconductor device having an emitter electrode film covered via an inter-layer insulating film, a collector electrode film in contact with the surface of the first semiconductor layer, and a peripheral structure portion arranged so as to surround the stripe-shaped groove Formed on the surface of the second semiconductor layer located between the parallel grooves, is in contact with both sides of the adjacent parallel grooves on the side surface, and is separated between third semiconductor regions located between the same parallel grooves. A fifth semiconductor region of the first conductivity type is disposed,
The arrangement of the fifth semiconductor region is between the grooves located from the peripheral structure part to 50 μm or more and 300 μm or less toward the center part of the chip, and the third semiconductor area and the fifth semiconductor area are alternately arranged, In addition, the object of the present invention is achieved by providing a MOS semiconductor device in which the fifth semiconductor region is in conductive contact with the emitter electrode film.

According to the invention described in claim 2 of the claim, the MOS type semiconductor device according to claim 1 wherein the impurity concentration of the fifth semiconductor region is higher than that of the third semiconductor region. It is preferable to do.

According to the third aspect of the present invention, the diffusion depth of the fifth semiconductor region is equal to or greater than that of the third semiconductor region. The MOS semiconductor device according to Item 1 or 2 may be used.

According to a fourth aspect of the present invention, the MOS semiconductor device according to the first or second aspect, wherein the diffusion depth of the fifth semiconductor region is shallower than that of the third semiconductor region. Is preferable.

According to the invention of claim 5 , the sixth semiconductor region having a higher impurity concentration than the third semiconductor region in the third semiconductor region and the fifth semiconductor region. More preferably, the MOS semiconductor device according to any one of claims 1 to 4 is used.

According to the invention of claim 6 , a concentration higher than that of the second semiconductor layer is provided between the first conductive type first semiconductor layer and the second conductive type second semiconductor layer. It is more preferable to provide the MOS semiconductor device according to any one of claims 1 to 5, which includes a seventh semiconductor layer of the second conductivity type.

According to a seventh aspect of the present invention, in the method for manufacturing a MOS semiconductor device according to the first aspect of the present invention, the fifth semiconductor region and the third semiconductor region are formed in the same step. The manufacturing method of the MOS type semiconductor device can be made.

In a trench IGBT in which IGBT cells are divided and arranged in the longitudinal direction of the trench, a p-type semiconductor region (hereinafter referred to as a dummy cell) that does not have an n-type source region inside from the peripheral structure portion is divided and arranged. The range in which the dummy cells are arranged is desirably 50 μm or more and 300 μm or less from the peripheral structure portion. Alternatively, a p ⁺ type well region having a higher impurity concentration than the p type base region may be formed. Further, when a p-type semiconductor region having a diffusion depth shallower than that of the p-type base region is formed, an increase in Vce (sat) can be suppressed.

  According to the present invention, it is possible to provide a trench type MOS semiconductor device capable of suppressing an increase in ON voltage in an ON state and improving a cutoff current without deteriorating switching characteristics.

  Hereinafter, a method for manufacturing a semiconductor device according to the present invention will be described in detail with reference to the drawings. The present invention is not limited to the description of the examples described below unless it exceeds the gist.

  FIG. 1 is a plan view of an essential part of a trench type IGBT according to the present invention. 2 is a cross-sectional view taken along the line B-B 'of FIG. FIG. 3 is a plan view of an essential part of a different trench type IGBT according to the present invention. 4 is a cross-sectional view of an essential part of C-C ′ in FIG. 3. FIG. 5 is a plan view of an essential part of still another trench IGBT according to the present invention. FIG. 6 is a cross-sectional view of an essential part of D-D ′ in FIG. 5. FIG. 7 is a graph showing the relationship between Vce (sat) and the carrier discharge area width according to the present invention. FIG. 8 is a relationship diagram between the interruptable current and the carrier discharge region width.

  The plan view of the trench type IGBT according to the first embodiment of the present invention shown in FIG. 1 corresponds to the plan view (FIG. 10) of the conventional IGBT and shows a plan view of the active region (cell region) 32. . FIG. 2 is a sectional view according to the present invention corresponding to FIG. The difference between the present invention figure and the conventional figure is that the dummy cell 32-2 in the p-type region is located between the IGBT unit cells 32-1 between the stripe-like grooves (trench) 25 arranged in parallel near the peripheral structure portion. Is provided. Reference numeral 26 denotes a gate oxide film, 27 denotes a polysilicon gate electrode, 28 denotes an interlayer insulating film, and 29 denotes an emitter electrode. Reference numeral 38 denotes a contact hole in contact with the emitter electrode and the silicon substrate surface. In FIG. 1, there is a peripheral structure 33 (not shown) on the right side. In FIG. 1, the left side is the center direction of the chip.

The dummy cell 32-2 includes a p-type base region 23-1 and a p ⁺ -type contact region 23-2 having an impurity concentration higher than that of the p-type base region, and the n-type source region 24 is not formed. Since the dummy cell 32-2 does not have the n-type source region 24, electrons are not injected into the n-type drift region 22 in the ON state, and minority carriers (holes) accumulated in the n-type drift region 22 are emitted from the emitter electrode. It is also an area that has only the function of discharging to 29 and does not function as an IGBT. Since the conventional carrier discharge region (reference numeral 17 in FIG. 9) is formed so as to continuously surround the IGBT cell region in an annular shape, the invalid region as a function of the IGBT becomes large, and the on-voltage tends to increase. However, in Example 1, since the carrier discharge region is island-shaped, the area can be made smaller than that of the conventional annular carrier discharge region, and the rise of the on-voltage can be reduced.

  As shown in the relationship diagram between the saturation voltage Vce (sat) of FIG. 7 and the conventional annular carrier discharge region width and dummy cell arrangement width, when considering the same chip size, the dummy cell arrangement width according to the present invention and the conventional annular When the width of the carrier discharge region (FIG. 9) is the same, it can be seen that the conventional carrier discharge region width has a larger Vce (sat).

  As shown in FIG. 8, the width in which the dummy cell 32-2 is arranged from the peripheral structure portion 33 toward the center of the chip is less than 50 μm and less than 300 μm, and contributes little to the increase in current that can be cut off, and more than 50 μm and less than 300 μm. Then, it was confirmed that the increase amount increased.

It is preferable that the p ⁺ -type contact layer 23-2 is formed in the dummy cell 32-2, since the effect of discharging carriers is higher, but the impurity concentration of the p-type base layer 23 or 23-1 is sufficiently high, and the emitter If the contact resistance with the electrode does not substantially cause a problem, it is not always necessary to form the electrode. The same applies to the presence or absence of the p ⁺ -type contact layer 23-3 in the IGBT unit cell 32-1.

  The length Y in the trench longitudinal direction of the p-type base region 23-1 of the dummy cell 32-2 and the contact hole 38 affects the Vce (sat) and the cutoff current. The longer the length in the longitudinal direction, the larger the interruptable current, but the Vce (sat) also increases. Therefore, the length in the Y direction may be designed as appropriate so that the necessary Vce (sat) and breakable current can be obtained.

  Further, if the p-type semiconductor region of the dummy cell is formed in the same process as the p-type base region as in this example, the dummy cell can be efficiently formed without increasing the process.

FIG. 3 shows a plan view of a main part of a trench type IGBT according to Example 2 of the present invention, and FIG. 4 shows a schematic cross-sectional view taken along the line CC ′ in FIG. The p-type region 43-1 of the dummy cell 52-2 has a higher impurity concentration than the p-type base region 43 of the IGBT unit cell 52-1, and has a diffusion depth equal to or deeper than that of the p-type base region 43. Have. In a state in which a negative voltage is applied to the gate electrode 47 with respect to the emitter electrode 49 in the turn-off process, the storage layer 50 is formed in the p ⁺ type base region 43 on the side wall of the trench 45. Therefore, a higher carrier discharge effect than that of Example 1 can be expected. However, in the ON state, on the contrary, the increase in Vce (sat) is slightly larger than that in the first embodiment due to the influence of the high carrier discharge effect.

  FIG. 5 shows a plan view of the main part of a trench IGBT according to Example 3 of the present invention, and FIG. 6 shows a schematic cross-sectional view taken along the line D-D ′ in FIG. Example 3 is characterized in that the p-type region 63-1 of the dummy cell 72-2 has a shallower diffusion depth than the p-type base layer 63 of the IGBT unit cell 72-1. Although the carrier discharging effect is slightly reduced, an increase in Vce (sat) can be reduced. Other areas are the same as in the first and second embodiments.

  Table 1 shows the effect of the impurity concentration of the p-type semiconductor region in the dummy cell on Vce (sat) and the cutoff current, and Table 2 shows the diffusion depth of the p-type semiconductor region in the dummy cell on Vce (sat) and the cutoff current. The effects of are shown together.

ダミーセル７２−２内のｐ型領域６３−１は上記表１、２の効果を考え合わせ、最適に設計する必要がある。

The p-type region 63-1 in the dummy cell 72-2 needs to be optimally designed in consideration of the effects shown in Tables 1 and 2 above.

It is a principal part top view of trench type IGBT concerning the present invention. It is B-B 'sectional drawing of FIG. It is a principal part top view of different trench type IGBT concerning this invention. FIG. 4 is a cross-sectional view of a main part of C-C ′ in FIG. 3. It is a principal part top view of further different trench type IGBT concerning this invention. FIG. 6 is a cross-sectional view of an essential part of D-D ′ in FIG. 5. It is a relationship figure of Vce (sat) concerning this invention, and carrier discharge area width. FIG. 5 is a relationship diagram between a current that can be interrupted and a carrier discharge region width. It is a schematic sectional drawing of the chip periphery of the conventional trench type IGBT. It is a schematic plan view of the conventional trench type IGBT. It is a schematic sectional drawing of the surface vicinity in A-A 'in FIG. 2 is a cross-sectional view of an IGBT corresponding to FIG. 1 described in Patent Document 2. FIG.

Explanation of symbols

22 ... n drift layer 23, 43, 63 ... p base layer 24 ... n emitter layer 25, 45 ... trench
26 ... Gate oxide film 27, 47 ... Polysilicon gate electrode 28 ... Interlayer insulating film 29, 49 ... Emitter electrode 32, 52, 72 ... IGBT unit cell region 33 ... Peripheral structure part.

Claims (7)

A first semiconductor layer of a first conductivity type;
A second semiconductor layer of a second conductivity type stacked on the first semiconductor layer;
A groove formed in a vertical direction on the surface of the second semiconductor layer with a parallel stripe-like planar pattern;
Formed on the surface of the second semiconductor layer located between the adjacent parallel grooves, in contact with both sides of the adjacent parallel grooves on the side surfaces and spaced apart from each other, and shallower than the depth of the grooves. A plurality of first-conductivity-type third semiconductor regions,
A fourth semiconductor region of a second conductivity type disposed on the surface of the third semiconductor region, in contact with an adjacent parallel groove on one side surface on one side and oppositely spaced from each other;
A gate electrode embedded in the trench through an insulating film;
An emitter electrode film in contact with both the surface of the third semiconductor region and the surface of the fourth semiconductor region and covering the gate electrode with an interlayer insulating film;
In a MOS semiconductor device having a collector electrode film in contact with the surface of the first semiconductor layer and a peripheral structure portion arranged so as to surround the stripe-shaped groove,
Between the third semiconductor regions formed on the surface of the second semiconductor layer located between the adjacent parallel grooves, in contact with both sides of the adjacent parallel grooves on the side surfaces and between the same parallel grooves A fifth semiconductor region of the first conductivity type is disposed apart from
The arrangement of the fifth semiconductor region is between the grooves located from the peripheral structure part to 50 μm or more and 300 μm or less toward the center part of the chip, and the third semiconductor area and the fifth semiconductor area are alternately arranged, A MOS semiconductor device, wherein the fifth semiconductor region is in conductive contact with the emitter electrode film. 2. The MOS semiconductor device according to claim 1, wherein an impurity concentration of the fifth semiconductor region is higher than that of the third semiconductor region. The diffusion depth of the fifth semiconductor region, equivalent to the third semiconductor region or,, MOS-type semiconductor device according to claim 1 or 2, characterized in that with more diffusion depth. MOS type semiconductor device according to claim 1 or 2 diffusion depth of said fifth semiconductor region is equal to or shallower than the third semiconductor region. The third semiconductor region and fifth semiconductor region, MOS-type semiconductor according to any one of claims 1 to 4, characterized in that it has a sixth semiconductor region having a higher impurity concentration than the third semiconductor region apparatus. A seventh conductivity type seventh semiconductor layer having a higher concentration than the second semiconductor layer is provided between the first conductivity type first semiconductor layer and the second conductivity type second semiconductor layer. MOS type semiconductor device according to any one of claims 1 to 5,. 2. The method of manufacturing a MOS semiconductor device according to claim 1, wherein the fifth semiconductor region and the third semiconductor region are formed in the same step.

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