JP2003197912A - Insulated gate semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a low breakdown voltage insulated gate semiconductor device in which the channel resistance and the ON voltage are decreased. <P>SOLUTION: The insulated gate semiconductor device 100 comprises a first conductivity type first base layer 110, a second conductivity type second base layer 120 formed on the surface thereof, a second conductivity type collector layer 140 formed on the rear surface side of the first base layer, a trench type gate electrode 160 having a plurality of first gate electrode parts 160a extending substantially in parallel on the surface of the second base layer and a plurality of second gate electrode parts 160b interconnecting the adjacent first gate electrode parts, a first conductivity type emitter layer 180 formed in an arbitrary base surface region surrounded by the first and second gate electrode parts on the surface of the second base layer, and an emitter electrode 195 connected with the base surface region having the emitter layer. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate semiconductor device.

[0002]

2. Description of the Related Art FIG. 8 shows a conventional insulated gate semiconductor device (hereinafter referred to as an IGBT (Insulated Gate Bipolar Transistor).
It is also a perspective sectional view of r)). The insulated gate semiconductor device 600 includes an n base layer 610 made of an n type semiconductor.
And p formed on the surface 612 of the n base layer 610.
A p-type base layer 620 made of a type semiconductor. On the back surface 614 of the n base layer 610 opposite to the surface 612,
An n buffer layer 630 made of an n-type semiconductor having a higher impurity concentration than the n base layer 610 is formed. The insulated gate semiconductor device 600 has a collector layer 640 made of a p-type semiconductor on the back surface 634 of the n buffer layer 630, and further has a collector electrode 650 made of metal on the back surface 644 of the collector layer 640.

In addition, the insulated gate semiconductor device 600 is
A trench type gate electrode 660 is further provided which penetrates the p base layer 620 from the surface 622 of the p base layer 620 and reaches the n base layer 610. The trench type gate electrode 660 is formed by the gate insulating layer 670.
10 and p base layer 620. The insulated gate semiconductor device 600 further includes an n-type emitter layer 680 selectively formed in the p base layer 620.

Further, an insulating layer 690 is selectively formed on the surface 622 of the p base layer 620. An emitter electrode 695 electrically connected to the emitter layer 680 is formed on the insulating layer 690.

FIG. 9 shows the trench type gate electrode 660 and the emitter layer 6 on the surface 622 of the p base layer 620.
It is a top view which shows 80. The plurality of trench type gate electrodes 660 extend substantially parallel to each other and are formed in a stripe pattern.

Adjacent gate electrodes 66 are formed on the surface 622.
Base surface region 6 with emitter layer 680 present between 0
22a and base surface regions 622b where the emitter layer 680 does not exist between the adjacent gate electrodes 660 are alternately formed.

An emitter electrode 695 is connected to the emitter layer 680 in the base surface region 622a. In FIG. 9, a contact region 695a of the emitter electrode 695
Is indicated by a broken line. On the other hand, the base surface area 622b
The emitter electrode 695 is not connected to.

As described above, the insulated gate semiconductor device having the base surface region to which the emitter electrode is not connected, of the base surface region between the adjacent gate electrodes and accumulating carriers to realize the injection promotion effect, is In particular, IEGT
It is called (Injection Enhanced Gate Bipolar Transistor).

[0009]

In the insulated gate semiconductor device 600 (hereinafter, also referred to as IEGT 600), the emitter layer 6 is formed by applying a voltage to the gate electrode 660.
A channel is formed in the p base layer 620 between 80 and the n base layer 610. Carriers flow to the p base layer 620 by this channel, the IEGT 600 is turned on, and a current flows between the collector electrode 650 and the emitter electrode 695.

The emitter electrode 695 is not connected to the base surface region 622b. Therefore, IEGT600
High resistance base surface area 622b when is on.
Carriers are accumulated in the n-base layer 610 and the p-base layer 620 below. Thereby, the n base layer 610
And the carrier concentration of the p base layer 620 becomes high, and n
The resistances of the base layer 610 and the p base layer 620 decrease. Therefore, the on-voltage of the IEGT 600 is reduced.

However, since no current flows in the base surface region 622b, the IEGT 600 has a smaller total channel width than an IGBT having an emitter layer in the entire base surface region. Therefore, the IEGT 600 has a channel resistance of I with an emitter layer over the entire base surface area.
It becomes higher than the channel resistance of GBT.

In the IEGT having a relatively low breakdown voltage of 1200 V or less, the thickness of the n base layer 610 is relatively thin, or the impurity concentration of the n base layer 610 is relatively high. The ratio of the channel resistance to the resistance from the emitter to the emitter 695 is large.

Therefore, in particular, the IEGT having a withstand voltage of 1200 V or less
In the above, the deterioration of the on-voltage due to the increase of the channel resistance becomes a problem.

Therefore, an object of the present invention is to provide an insulated gate semiconductor device having a relatively low breakdown voltage between the collector and the emitter, in which the channel resistance and the on-voltage are reduced.

[0015]

An insulated gate semiconductor device according to a first embodiment of the present invention is formed on a first base layer of a first conductivity type and a surface of the first base layer. Second conductive type second base layer and a second conductive type collector layer formed on the back surface side of the first base layer opposite to the front surface of the first base layer. And the first
Is insulated from the base layer and the second base layer, and penetrates the second base layer from the surface of the second base layer to reach the first base layer. Having a plurality of first gate electrode portions extending substantially parallel to each other on the surface of the substrate and a plurality of second gate electrode portions connecting between the first gate electrode portions adjacent to each other. A gate electrode and a surface of the second base layer, a base surface region surrounded by the first gate electrode portion and the second gate electrode portion is selectively formed in an arbitrary base surface region. It is provided with a formed first conductivity type emitter layer and an emitter electrode connected to a base surface region having the emitter layer.

In the insulated gate semiconductor device according to the second embodiment of the present invention, the emitter electrode is connected only to the base surface region of the base surface region where the emitter layer is formed. A reference electrode for applying a reference potential is connected to the base surface region where the emitter layer is not formed.

A high resistance layer having a higher resistance than that of the emitter layer is formed in a base surface area of the base surface area where the emitter layer is not formed, and the emitter electrode is formed through the high resistance layer. It may be connected to the base surface region where the emitter layer is not formed.

In the insulated gate semiconductor device according to the third embodiment of the present invention, the emitter layer is formed in all the base surface regions, and the emitter electrodes are formed in the base surface regions. It is configured so that it is connected to the selected base surface region and is not connected to other base surface regions.

On the surface of the second base layer, of the adjacent first gate electrode portions, the second gate electrode portion is present and the second gate electrode is not present. The parts and the parts may be alternately formed.

On the surface of the second base layer, the first gate electrode portion and the second gate electrode portion may be formed in a ladder pattern.

In the insulated gate semiconductor device according to the fourth and fifth embodiments of the present invention, the plurality of second gate electrode portions are substantially parallel to each other on the surface of the second base layer. Extending and orthogonal to the first gate electrode portion, the first gate electrode portion and the second gate electrode portion.
The gate electrode part of 1 is formed with a mesh pattern.

The area ratio per unit area on the surface of the second base layer between the base surface area to which the emitter electrode is connected and the base surface area to which the emitter electrode is not connected is the area ratio of the second base layer. It may be formed so as to be substantially constant over the surface.

Preferably, the area of the base surface region to which the emitter electrode is connected and the area of the base surface region to which the emitter electrode is not connected may be set at an arbitrary ratio on the surface of the second base layer. it can.

Preferably, the breakdown voltage between the emitter and collector of the insulated gate semiconductor device is 1200 V or less.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. The present embodiment does not limit the present invention. In addition, the present embodiment has the effect of the present invention even if the conductivity type of the semiconductor is changed from n-type to p-type and vice versa.

FIG. 1 is a perspective sectional view of an insulated gate semiconductor device 100 according to the first embodiment of the present invention. The insulated gate semiconductor device 100 includes an n base layer 110 made of an n type semiconductor and a surface 11 of the n base layer 110.
P base layer 12 made of p-type semiconductor formed in No. 2
With 0 and.

An n buffer layer 130 made of an n-type semiconductor having an impurity concentration higher than that of the n base layer 110 is formed on a back surface 114 of the n base layer 110 opposite to the front surface 112. The insulated gate semiconductor device 100 includes a collector layer 140 made of a p-type semiconductor on the back surface 134 of the n-buffer layer 130. That is, the insulated gate semiconductor device 100 includes the collector layer 140 on the back surface 114 side of the n base layer 110. Further, the collector layer 140
A collector electrode 150 made of metal is formed on the back surface 144 of the.

In addition, the insulated gate semiconductor device 100 is
A trench type gate electrode 160 penetrating the p base layer 120 from the surface 122 of the p base layer 120 to reach the n base layer 110 is further provided. Trench type gate electrode 1
60 is an n-base layer 110 formed by the gate insulating layer 170.
And is insulated from the p base layer 120. The insulated gate semiconductor device 100 further includes an n-type emitter layer 180 selectively formed in the p base layer 120.
The trench type gate electrode 160 is also insulated from the emitter layer 180.

Further, an insulating layer 190 is selectively formed on the surface 122 of the p base layer 120. Insulation layer 1
An emitter electrode 195 electrically connected to the emitter layer 180 is formed on the surface 90.

FIG. 2 is a plan view of the surface 122 of the p base layer 120. The configuration of the insulated gate semiconductor device 100 will be further described with reference to FIGS. 1 and 2.
The trench type gate electrode 160 connects a plurality of vertical gate electrode portions 160a extending substantially parallel to each other and a plurality of vertical gate electrode portions 160a adjacent to each other on the surface 122 of the p base layer 120. Lateral gate electrode portion 160b. Between the adjacent vertical gate electrode portions 160a, there are a portion 122a in which the horizontal gate electrode portion 160b is not formed and a portion 122b in which the horizontal gate electrode pattern 160b is formed. 122a for copy and 1 for copy
22b are formed alternately on the surface 122.

In this embodiment, the vertical gate electrode portions 160a are formed substantially parallel to each other, and the surface 12
2 is formed in a striped pattern.
The lateral gate electrode portions 160b are also formed substantially parallel to each other and extend in a direction substantially perpendicular to the vertical gate electrode portion 160a. Therefore, the horizontal gate electrode portion 160b and the vertical gate electrode portion 160a are formed in a ladder pattern on the surface 122.
Here, the width between the horizontal gate electrode portions 160b and the width between the vertical gate electrode portions 160a are not particularly limited and may be set arbitrarily.

A region of the surface 122 surrounded by the vertical gate electrode portion 160a and the horizontal gate electrode portion 160b is referred to as a base surface region 165. Base surface area 1
65 has a connection base surface region 165a connected to the emitter electrode 195 and a non-connection base surface region 165b not connected to the emitter electrode 195. In the present embodiment, emitter layer 180 is formed in connection base surface region 165a, and emitter layer 180 is not formed in non-connection base surface region 165b. Since the width between the horizontal gate electrode portions 160b and the width between the vertical gate electrode portions 160a can be set arbitrarily, the areas of the connection base surface region 165a and the non-connection base surface region 165b can be set. Can also be set arbitrarily.

The connection base surface region 165a and the non-connection base surface region 165b are the surface 1 of the p base layer 120.
22 is selectively formed. In the present embodiment, the connection base surface region 165a and the non-connection base surface region 165b are alternately formed in the portion 122b.

On the other hand, in the p base layer 120 of the portion 122a where the lateral gate electrode portion 160b is not formed, the emitter layer 180 is formed almost entirely on the portion 160b along the vertical gate electrode 160a. . Therefore, almost the entire base surface area of the portion 122a is the connection base surface area 165a.

An emitter electrode 195 is connected to the emitter layer 180 in the connection base surface region 165a. In FIG. 2, the contact region 19 of the emitter electrode 195
5a is indicated by a broken line. On the other hand, since the insulating layer 190 covers the non-connection base surface region 165b, no electrode is connected to the non-connection base surface region 165b.
In FIG. 1, the emitter electrode 195 and the insulating film 1
Only 90 of those 90 are shown, and the other parts are omitted.

Next, the effect of the insulated gate semiconductor device 100 will be described while explaining the operation thereof.

In the insulated gate semiconductor device 100, the emitter layer 1 is formed by applying a voltage to the gate electrode 160.
A channel (not shown) is formed in the p base layer 120 between 80 and the n base layer 110. Due to this channel, electrons passing through the emitter layer 180 are transferred to the n base layer 11
Injected to zero. The injected electrons cause a forward bias between the collector layer 150 and the n base layer 110, so holes are injected from the collector layer 150 to the n base layer 110. Therefore, the insulated gate semiconductor device 1
00, collector electrode 150 and emitter electrode 19
An electric current flows between and.

The emitter electrode 195 is not connected to the unconnected base surface region 165b. Therefore, when the insulated gate semiconductor device 100 is turned on, carriers are accumulated in the n base layer 110 and the p base layer 120 below the unconnected base surface region 165b. As a result, the carrier concentration of the n base layer 110 and the p base layer 120 increases, and the resistance of the n base layer 110 and the p base layer 120 decreases. Therefore, the on-voltage of the insulated gate semiconductor device 100 decreases. That is, the insulated gate semiconductor device 100 also has the same effect as the IEGT 600. On the other hand, the area of the non-connection base surface region 165b of the insulated gate semiconductor device 100 is larger than that of the conventional IEGT60.
It is smaller than the area of the base surface region 622b of 0.
Therefore, the effect of lowering the on-voltage by the unconnected base surface region is lower than that of the conventional IEGT 600.

However, the connection base surface region 165a is formed not only in the part 122a but also in the part 122b. Therefore, the total sum of the channel widths of the insulated gate semiconductor device 100 becomes larger than the total sum of the channel widths of the conventional IEGT 600. Since the channel resistance depends on the channel width, the channel resistance of the insulated gate semiconductor device 100 is higher than the channel resistance of the IGBT having the emitter layer over the entire base surface region, but the conventional IE.
It is lower than the GT channel resistance. Therefore, by increasing the connection base surface region 165a, the channel resistance of the insulated gate semiconductor device 100 is lowered, and the ON voltage thereof is also lowered. That is, in the IEGT, there is a trade-off relationship between the effect of lowering the ON voltage by increasing the non-connection base surface region and the effect of decreasing the ON voltage by increasing the connection base surface region.

In general, among IEGTs, a product having a relatively low withstand voltage of 1200 V or less between the collector and the emitter has a collector withstand voltage higher than that of a product with a relatively high withstand voltage of 1200 V or more. The ratio of the channel resistance to the resistance from the electrode to the emitter electrode is large. Therefore, particularly for a low breakdown voltage IEGT having a breakdown voltage between the collector and the emitter of 1200 V or less, the connection base surface region is increased more than the effect of lowering the ON voltage by increasing the non-connection base surface region. By doing so, the effect of lowering the on-voltage may be greater.

That is, the area ratio of the connection base surface region 165a and the non-connection base surface region 165b that minimizes the on-voltage of the insulated gate semiconductor device depends on the breakdown voltage between the collector and the emitter of the insulated gate semiconductor device. To do.

Therefore, the area ratio of the connection base surface region 165a and the non-connection base surface region 165b can be determined by the breakdown voltage between the collector and the emitter. The change of the area ratio of the connection base surface region 165a and the non-connection base surface region 165b is achieved by changing the width of the part 122a and the part 122b.

Since the connection base surface region 165a is provided, the non-connection base surface region 165 is formed.
Since b is reduced, the total number of carriers accumulated in the p base layer 120 and the n base layer 110 is reduced. Therefore, the insulated gate semiconductor device 100 also has an effect of reducing the tail current at the time of switching.

FIG. 3 and FIG. 4 respectively show an insulated gate semiconductor device 20 according to the second embodiment of the present invention.
0 is a perspective sectional view of 0 and a plan view of a surface 122 of the p base layer 120. In the following embodiments, the same components as those of the insulated gate semiconductor device 100 are designated by the same reference numerals.

In this embodiment, the reference base surface area 1 is formed in the area corresponding to the non-connection base surface area 165b.
65c is provided, which is different from the first embodiment. Further, the insulated gate semiconductor device 200 is different from that of the first embodiment in that it further includes a reference electrode 197 connected to the reference base surface region 165c. Figure 3
In FIG. 4 and FIG. 4, the contact region 197a connected to the reference electrode 197 is indicated by a broken line. In FIG. 3, the reference electrode 197, like the emitter electrode 195,
Only a portion thereof is shown and the other portions are omitted.

The reference electrode 197 maintains the p base layer 180 and the n base layer 110 below the reference base surface region 165c at a reference potential, eg, ground potential. Therefore, since the potentials of the p base layer 180 and the n base layer 110 below the unconnected base surface region 165b are determined, the operation of the insulated gate semiconductor device 200 is performed by the insulated gate semiconductor device according to the first embodiment. 10
It is stable compared to 0. For example, according to the present embodiment, control of breakdown voltage between collector electrode 195 and emitter electrode 150 becomes relatively easy.

Further, a high resistance layer having a higher resistance than the emitter layer 180 may be formed in the base surface region 165c, and the emitter electrode 195 may be connected to the high resistance layer. In this case, the high resistance layer is formed at the position 197a in FIG. By connecting the emitter electrode 195 to the high resistance layer, as in the case where the reference electrode 197 is connected,
The operation of the insulated gate semiconductor device 200 is relatively stable. Further, since the base surface region 165c is formed to have a higher resistance than the base surface region 165a, carriers are accumulated in the base surface region 165c. Therefore, the insulated gate semiconductor device 200 is
The effect as T is not lost. Further, it is not necessary to change the design of the mask used when forming the contact hole to the base surface region. Therefore, an existing IGBT mask can be used.

Since the reference electrode or the emitter electrode 195 maintains the connection, an impurity diffusion layer (not shown) having a lower concentration than the emitter layer 180 is formed in the contact region 197a.
May be formed in.

FIG. 5 is a plan view of surface 122 of p base layer 120 in insulated gate semiconductor device 300 according to the third embodiment of the present invention. According to the present embodiment, emitter layer 180 is formed in almost all of base surface region 165. Therefore, the present embodiment is different from the first embodiment in that the emitter layer 180 is also formed in the non-connection base surface region 165b.

However, the emitter electrode 195 is connected to the selected connection base surface region 16 of the base surface region 165.
5a and not to any other unconnected base surface area 165b.

Therefore, the insulated gate semiconductor device 300 according to the present embodiment can obtain the same effect as the insulated gate semiconductor device 100 according to the first embodiment. Incidentally, in FIG. 5, the contact region 195a to which the emitter electrode 195 is connected is shown by a broken line.

Generally, the IGBTs other than the IEGT are often provided with emitter layers on both sides thereof along almost all the gate electrodes. Therefore, in the step of forming the emitter layer, a mask having an emitter layer pattern on both sides of almost all gate electrode patterns is used. In the insulated gate semiconductor device 300 according to the present embodiment, the emitter layer 180 is formed on both sides of almost all the vertical gate electrode portions 160a except the portion where the horizontal gate electrode portion 160b is connected. Therefore, in the step of forming the emitter layer of the present embodiment, the conventional mask can be used without changing the design.

FIG. 6 is a plan view of surface 122 of p base layer 120 in insulated gate semiconductor device 400 according to the fourth embodiment of the present invention. In the present embodiment, the horizontal gate electrode portions 160b extend substantially parallel to each other and are substantially orthogonal to the vertical gate electrode portions 160a. That is, on the surface 122 of the p base layer 120, the vertical gate electrode portion 160a and the horizontal gate electrode portion 160b form a mesh pattern.

Each base surface area 165 is divided by this mesh-shaped pattern. Connection base surface area 165a or non-connection base surface area 16
5b can be arbitrarily selected from the base surface region 165.
Further, the distance between the vertical gate electrode portions 160a and the distance between the horizontal gate electrode portions 160b can be arbitrarily selected. Therefore, the mesh-shaped pattern can be set more finely by narrowing the space between the vertical gate electrode portions 160a and the space between the horizontal gate electrode portions 160b.

By setting this mesh-like pattern more finely and selecting a desired connecting base surface region 165a from the base surface region 165, the surface 122 of the connecting base surface region 165a and the non-connecting base surface region 165b is formed. The area ratio can be set arbitrarily. Therefore, according to the breakdown voltage between the collector and the emitter of the insulated gate semiconductor device 400, the connection base surface region 165a is formed.
The area ratio of the non-connecting base surface region 165b on the surface 122 can be set.

FIG. 7 is a plan view of surface 122 of p base layer 120 in insulated gate semiconductor device 500 according to the fifth embodiment of the present invention. In the present embodiment, in the fourth embodiment in FIG. 6, the area ratio per unit area on the surface of the p base layer 120 between the connection base surface region 165a and the non-connection base surface region 165b is the p base layer 120. It is an embodiment that is substantially constant over the surface.

In the insulated gate semiconductor device 500,
Connection base surface area 165a and non-connection base surface area 1
65b are formed so as to be adjacent to each other. That is, the connection base surface region 165a and the non-connection base surface region 165b form a checkered pattern on the surface 122. Therefore, the distribution of the connection base surface region 165a and the non-connection base surface region 165b on the surface 122 is uniform. That is, the ratio of the area occupied by the connection base surface region 165a and the area occupied by the non-connection base surface region 165b per unit area of the surface 122 is
It is substantially constant across the surface 122. In the present embodiment, connection base surface region 165a and non-connection base surface region 165b are evenly distributed on surface 122 at an area ratio of approximately 1: 1.

Therefore, according to the present embodiment, the current flowing through insulated gate semiconductor device 500 flows uniformly on surface 122 without being partially biased. As a result, the breakdown voltage between the collector and the emitter does not decrease, and the reliability of the insulated gate semiconductor device improves.

The connection base surface region 165a and the non-connection base surface region 165b may be uniformly distributed on the surface 122 at an area ratio other than 1: 1.

Also in this embodiment, the interval between the vertical gate electrode portions 160a and the horizontal gate electrode portion 16 are set.
The interval of 0b can be arbitrarily selected. By making the distance between the vertical gate electrode portions 160a and the distance between the horizontal gate electrode portions 160b smaller, the uniformity of the current flowing through the insulated gate semiconductor device 500 on the surface 122 can be further improved. Note that the above-described embodiment describes the punch-through type insulated gate semiconductor device including the n buffer layer 130. But,
The n buffer layer 130 is not always necessary. That is, n
Even in a non-punch through type insulated gate semiconductor device having no buffer layer 130, the effects of the present invention and this embodiment are not lost.

[0061]

According to the insulated gate semiconductor device according to the present invention, in the insulated gate semiconductor device having a relatively low breakdown voltage between the collector and the emitter, the channel resistance and the on-voltage can be reduced more than ever before. You can

[Brief description of drawings]

FIG. 1 is a perspective sectional view of an insulated gate semiconductor device 100 according to a first embodiment of the invention.

FIG. 2 is a plan view of a surface 122 of a p base layer 120.

FIG. 3 is a perspective sectional view of an insulated gate semiconductor device 200 according to a second embodiment of the present invention.

FIG. 4 is a plan view of a surface 122 of a p base layer 120 in an insulated gate semiconductor device 200 according to a second embodiment of the present invention.

FIG. 5 is a plan view of a surface 122 of a p base layer 120 in an insulated gate semiconductor device 300 according to a third embodiment of the present invention.

FIG. 6 is a plan view of a surface 122 of a p base layer 120 in an insulated gate semiconductor device 400 according to a fourth embodiment of the present invention.

FIG. 7 is a plan view of a surface 122 of a p base layer 120 in an insulated gate semiconductor device 500 according to a fifth embodiment of the present invention.

FIG. 8 is a perspective sectional view of a conventional insulated gate semiconductor device.

FIG. 9 is a plan view showing a trench type gate electrode 660 and an emitter layer 680 on a surface 622 of a p base layer 620.

[Explanation of symbols]

100, 200, 300, 400, 500 Insulated gate type semiconductor device 110 n Base layer 120 p Base layer 130 n Buffer layer 140 Collector layer 150 Collector electrode 160 Trench type gate electrode 165 Base surface region 170 Gate insulating layer 180 Emitter layer 190 Insulation Layer 195 Emitter electrode 197 Reference electrode (high resistance layer)

Claims (10)

[Claims] 1. A first conductive type first base layer, a second conductive type second base layer formed on a surface of the first base layer, and a back surface of the first base layer. A collector layer of the second conductivity type formed on the side of the first base layer and the surface of the second base layer, penetrating the second base layer to reach the first base layer, and A trench type gate electrode insulated from a base layer and the second base layer, which is adjacent to a plurality of first gate electrode portions extending substantially parallel to each other on the surface of the second base layer. A trench-type gate electrode including a plurality of second gate electrode portions connecting between the first gate electrode portions that match each other; and a first gate electrode portion on the surface of the second base layer. Base surrounded by the second gate electrode portion An insulated gate semiconductor including an emitter layer of a first conductivity type selectively formed in an arbitrary base surface region of the surface region and an emitter electrode connected to the base surface region having the emitter layer. apparatus. 2. A reference for applying a reference potential to a base surface region of the base surface region, wherein the emitter electrode is connected only to the base surface region where the emitter layer is formed, and the base surface region where the emitter layer is not formed. The insulated gate semiconductor device according to claim 1, wherein electrodes are connected. 3. A high resistance layer having a higher resistance than that of the emitter layer is formed in a base surface area of the base surface area where the emitter layer is not formed, and the emitter electrode has the high resistance layer interposed therebetween. 2. The insulated gate semiconductor device according to claim 1, wherein the insulated gate semiconductor device is connected to a base surface region where the emitter layer is not formed. 4. The emitter layer is formed in the base surface region, and the emitter electrode is connected only to a selected base surface region of the base surface region. Insulated gate type semiconductor device according to. 5. A portion of the surface of the second base layer in which the second gate electrode portion is present and a portion of the portion of the first gate electrode portion which are adjacent to each other, The insulated gate semiconductor device according to any one of claims 1 to 4, wherein portions that do not exist are alternately formed. 6. The surface of the second base layer, wherein the first gate electrode portion and the second gate electrode portion form a ladder pattern. The insulated gate semiconductor device according to claim 4. 7. A plurality of the second gate electrode portions extend substantially parallel to each other on a surface of the second base layer and are orthogonal to the first gate electrode portion, the first gate electrode. The insulated gate semiconductor device according to claim 1, wherein the portion and the second gate electrode portion form a mesh pattern. 8. The area ratio per unit area on the surface of the second base layer between the base surface region to which the emitter electrode is connected and the base surface region to which the emitter electrode is not connected is the second base. 8. The insulated gate semiconductor device according to claim 7, wherein the surface is substantially constant over the surface of the layer. 9. The area of the base surface region to which the emitter electrode is connected and the area of the base surface region to which the emitter electrode is not connected can be set at an arbitrary ratio on the surface of the second base layer. The insulated gate type semiconductor device according to claim 7. 10. The insulated gate semiconductor device according to claim 1, wherein the breakdown voltage between the emitter and the collector of the insulated gate semiconductor device is 1200 V or less.