JP5049253B2 - Semiconductor element - Google Patents

Description

  The present invention relates to a semiconductor element.

  Conventionally, a semiconductor element formed using a semiconductor substrate has been provided. Such semiconductor elements include acceleration sensors, pressure sensors, infrared sensors, BAW (Bulk Acoustic Wave) filters, electrostatic transducers, and the like. These are formed by using a micromachining technique or the like, and have a functional portion that is thinner than the peripheral portion at the center. For example, in a piezoresistive acceleration sensor or pressure sensor, a piezoresistor is formed at an appropriate position of the functional unit. In the infrared sensor, at least a part of the infrared detection unit is formed in the functional unit. In the BAW filter, a resonator composed of a lower electrode, a piezoelectric layer, and an upper electrode is formed in the functional part. Further, in the electrostatic transducer, one electrode of a pair of electrodes constituting a capacitor is formed on the functional portion, and the other electrode of the pair of electrodes is formed on a thin plate portion disposed to face the functional portion. Yes.

  By the way, when the semiconductor element as described above is mounted on a mounting substrate (for example, a glass epoxy resin substrate having a connection terminal formed on one surface side of an insulating base made of glass epoxy resin), the semiconductor element is used. There is a possibility that the stress due to the difference in linear expansion coefficient between the semiconductor substrate and the mounting substrate is generated in the functional part of the semiconductor element, and the characteristics of the semiconductor element are deteriorated.

Therefore, a technique for forming a groove in a semiconductor substrate has been proposed in order to suppress deterioration of characteristics of the semiconductor element due to such stress. For example, in the technique disclosed in Patent Document 1, a plurality of cut grooves having a V-shaped cross section are formed on the main surface and the back surface of the support portion of the sensor chip so as to be separated along the circumferential direction of the support portion. In this case, the support portion is easily deformed by the cut groove having a V-shaped cross section. That is, when the support portion is deformed by the stress caused by the difference in linear expansion coefficient between the semiconductor substrate and the mounting substrate, the stress is suppressed from occurring in the bent portion as the functional portion.
JP 2000-187040 A

  However, in the above-mentioned Patent Document 1, there is a limit to the amount of deformation of the support portion, and the stress caused by the difference in linear expansion coefficient between the semiconductor substrate and the mounting substrate cannot be sufficiently relaxed.

  The present invention has been made in view of the above-described reasons, and an object thereof is to provide a semiconductor element that can further relieve stress generated in a functional part due to a difference in linear expansion coefficient between a semiconductor substrate and a mounting substrate. There is to do.

  According to a first aspect of the present invention, there is provided a semiconductor substrate in which a thin functional portion is formed in a central portion as compared with a peripheral portion, a circuit portion formed in the functional portion on one surface side of the semiconductor substrate, and the semiconductor substrate An external connection electrode provided on the other surface side, a through-hole wiring for penetrating the semiconductor substrate in the thickness direction to electrically connect the circuit portion and the external connection electrode, and the one surface of the semiconductor substrate In the semiconductor element provided with a connection portion that is provided on a side and electrically connects the through-hole wiring and the circuit portion, the through-hole is formed on either the one surface side or the other surface side of the semiconductor substrate. A first groove formed on the center side of the semiconductor substrate with respect to the wiring, and on the outer peripheral side of the semiconductor substrate with respect to the through-hole wiring on the other side of the one surface side and the other surface side of the semiconductor substrate. Formed second Characterized in that it comprises a groove.

  According to the present invention, the first groove is formed on the center side of the semiconductor substrate with respect to the through-hole wiring on either the one surface side or the other surface side of the semiconductor substrate, and the semiconductor substrate A second groove is formed on the outer peripheral side of the semiconductor substrate with respect to the through-hole wiring on the other of the one surface side and the other surface side of the semiconductor substrate, and the first groove portion and the first groove in the semiconductor substrate are formed. The portion between the two groove portions is a portion that is easily deformed. Therefore, the stress generated in the functional portion due to the difference in linear expansion coefficient between the semiconductor substrate and the mounting substrate can be sufficiently relaxed by the deformation of the portion. Further, since the through-hole wiring is arranged in the portion, even if the first groove and the second groove are formed, the circuit portion on the one surface side of the semiconductor substrate and the circuit The external connection electrode on the other surface side of the semiconductor substrate can be electrically connected.

  According to a second aspect of the present invention, in the first aspect of the invention, the connection portion is formed on the one surface side of the semiconductor substrate on the center side of the semiconductor substrate with respect to the through-hole wiring, and the external connection electrode is It is formed on the outer surface side of the semiconductor substrate from the through hole wiring on the other surface side of the semiconductor substrate.

  According to the present invention, it is possible to increase the distance between the functional part and the connection part and the external connection electrode in a plane whose normal direction is the thickness direction of the semiconductor substrate. A portion between the first groove portion and the second groove portion in the semiconductor substrate is interposed between the connection portion and the external connection electrode. Therefore, the stress generated in the functional part of the semiconductor element due to the difference in linear expansion coefficient between the semiconductor substrate and the mounting substrate can be further relaxed.

  According to a third aspect of the invention, in the second aspect of the invention, the first groove is formed on the other surface side of the semiconductor substrate, and the second groove is formed on the one surface side of the semiconductor substrate. It is characterized by being.

  According to this invention, the said through-hole wiring intervened between the said connection part electrically connected mutually and the said external connection electrode can be made into one. Therefore, the wiring structure can be simplified. In addition, electrical reliability between the connection portion and the external connection electrode can be improved.

  According to a fourth aspect of the present invention, in any one of the first to third aspects, the inner bottom surface of each of the first groove portion and the second groove portion is a concave curved surface.

  According to this invention, the inner bottom surface and inner circumference of the first groove portion and the second groove portion are compared with the case where the inner bottom surfaces of the first groove portion and the second groove portion are formed in a planar shape. It is possible to prevent stress from being concentrated near the boundary with the surface. Therefore, damage to the semiconductor substrate can be prevented.

  According to a fifth aspect of the present invention, in any one of the first to fourth aspects, the first groove portion and the second groove portion are the first groove portion and the second groove portion in the semiconductor substrate. Each of the formation scheduled regions is formed by dry etching.

  According to the present invention, the aspect ratio of the first groove portion and the second groove portion is higher than that in the case of forming the first groove portion and the second groove portion by wet etching or using a dicing saw. The ratio can be increased. Therefore, the formation area of each of the first groove and the second groove can be narrowed.

  The present invention has an effect that stress generated in the functional part due to the difference in linear expansion coefficient between the semiconductor substrate and the mounting substrate can be further relaxed.

  As shown in FIGS. 1 and 2, a semiconductor element (semiconductor chip) 1 according to an embodiment of the present invention cooperates with a sensor unit 1a having a movable unit provided with a sensing unit, which will be described later, and the sensor unit 1a. This is an acceleration sensor chip in which an IC portion 1b and a bonding region portion 1c are integrated. In the semiconductor element 1 of the present embodiment, the IC part 1b is formed so as to surround the sensor part 1a. Further, the bonding region 1c is formed so as to surround the IC portion 1b. In short, in the semiconductor element 1, the sensor unit 1 a, the IC unit 1 b, and the bonding region part are so formed that the IC part 1 b surrounds the sensor part 1 a located at the center in plan view and the bonding part 1 c surrounds the IC part 1 b. The layout of 1c is designed.

  The semiconductor element 1 is formed by processing the semiconductor substrate 10. The semiconductor substrate 10 is an SOI wafer, a support substrate 10a made of a silicon substrate, an insulating film (embedded oxide film) 10b formed on the support substrate 10a, and an n-type silicon formed on the insulating film 10b. Layer (active layer) 10c. In the semiconductor substrate 10 according to the present embodiment, the thickness of the support substrate 10a is about 300 μm to 500 μm, the thickness of the insulating film 10b is about 0.3 μm to 1.5 μm, and the thickness of the silicon layer 10c is about 4 μm to 10 μm. It is said. These numerical values are merely examples, and the semiconductor substrate 10 in the present embodiment is not intended to be limited to the above. The surface of the silicon layer 10c, which is the main surface of the SOI wafer, is a (100) plane.

  The sensor unit 1a includes a frame-shaped frame portion 11 (in this embodiment, a rectangular frame shape), a weight portion 12 disposed inside the frame portion 11, and a flexible strip-shaped weight portion 12. And a bending portion 13 that connects the frame portion 11 to each other. The weight portion 12 is swingably supported by the frame portion 11 via four flexure portions 13 on one surface side (the upper surface side in FIG. 1) of the semiconductor substrate 10. In other words, in the semiconductor element 1, the weight portion 12 disposed inside the frame-shaped frame portion 11 is swingably supported by the frame portion 11 via the four bent portions 13 extending from the weight portion 12 in all directions. ing. Here, the frame portion 11 is formed using the support substrate 10a, the insulating film 10b, and the silicon layer 10c. On the other hand, the bending part 13 is formed using the silicon layer 10 c and is sufficiently thinner than the frame part 11.

  The weight portion 12 includes a rectangular parallelepiped core portion 12a and four rectangular parallelepiped accompanying portions 12b. The core portion 12 a is supported by the frame portion 11 via the four bending portions 13. That is, the other end portion of each bending portion 13 having one end portion connected to the inner side surface of the frame portion 11 is connected to the outer surface of the core portion 12a. The four associated parts 12b are continuously and integrally connected to the four corners of the core part 12a when viewed from the one surface side of the semiconductor substrate 10. As a result, the accompanying portion 12b is formed integrally with the core portion 12a and is disposed in a space between the core portion 12a and the frame portion 11. More specifically, each associated portion 12b is a space surrounded by two flexible portions 13 and 13 extending in a direction orthogonal to the frame portion 11 and the core portion 12a when viewed from the one surface side of the semiconductor substrate 1. Is arranged. Here, a slit 14 is formed between each of the accompanying portions 12 b and the frame portion 11. In addition, the interval between the accompanying portions 12 b that are adjacent to each other with the bending portion 13 interposed therebetween is longer than the width dimension of the bending portion 13.

  The core portion 12a described above is formed using the support substrate 10a, the insulating film 10b, and the silicon layer 10c. Each accompanying portion 12b is formed by using the support substrate 10a. Therefore, on the one surface side of the semiconductor substrate 10, the surface of each associated portion 12 b is located away from the plane including the surface of the core portion 12 a toward the other surface side (lower surface side in FIG. 1) of the semiconductor substrate 10. Yes.

  Note that the frame portion 11, the weight portion 12, and each bending portion 13 of the semiconductor element 1 may be formed using a lithography technique and an etching technique.

  By the way, as shown in the lower right of each of FIGS. 1 and 2, in this embodiment, one direction along one side of the frame portion 11 in a plane parallel to the one surface of the semiconductor substrate 10 is the positive direction of the x axis. One direction along the side perpendicular to the one side is defined as the positive direction of the y-axis, and one direction of the thickness direction of the semiconductor element 1 is defined as the positive direction of the z-axis.

  In this case, the weight part 12 is extended in the x-axis direction and includes a pair of bending parts 13 and 13 that sandwich the core part 12a, and the pair of bending parts that extend in the y-axis direction and sandwiches the core part 12a. It is supported by the frame part 11 via the parts 13 and 13. In the orthogonal coordinates defined by the three axes of the above-described x-axis, y-axis, and z-axis, the origin is the center position of the weight portion 12 on the surface of the semiconductor element 1 formed by the silicon layer 10c.

  In the bending portion 13 (the right-side bending portion 13 in FIG. 2) extending from the core portion 12a of the weight portion 12 in the positive direction of the x-axis, a pair of piezoresistors Rx2 and Rx4 are formed in the vicinity of the core portion 12a. Thus, one piezoresistor Rz2 is formed in the vicinity of the frame portion 11. In the bent portion 13 (left bent portion 13 in FIG. 2) extending from the core portion 12a of the weight portion 12 in the negative direction of the x-axis, a pair of piezoresistors Rx1 and Rx3 are formed in the vicinity of the core portion 12a. Thus, one piezoresistor Rz3 is formed in the vicinity of the frame portion 11. In the bent portion 13 (the upper bent portion 13 in FIG. 2) extending from the core portion 12a of the weight portion 12 in the positive direction of the y-axis, a pair of piezoresistors Ry1 and Ry3 are formed in the vicinity of the core portion 12a. Thus, one piezoresistor Rz1 is formed in the vicinity of the frame portion 11. In the bent portion 13 (the lower bent portion 13 in FIG. 2) extended from the core portion 12a of the weight portion 12 in the negative direction of the y-axis, a pair of piezoresistors Ry2 and Ry4 are provided in the vicinity of the core portion 12a. One piezoresistor Rz4 is formed in the vicinity of the frame portion 11 side.

  Four piezoresistors Rx1, Rx2, Rx3, and Rx4 are formed to detect acceleration in the x-axis direction. The planar shapes of these piezoresistors Rx1 to Rx4 are all elongated rectangles. Further, these piezoresistors Rx1 to Rx4 are formed so that the longitudinal direction thereof coincides with the longitudinal direction of the bending portion 13. These piezoresistors Rx1 to Rx4 are connected so as to constitute the left bridge circuit Bx in FIG. Wirings (not shown) connecting these piezoresistors Rx1 to Rx4 are diffusion layer wirings formed on the semiconductor substrate 10, metal wirings, and the like. Note that these piezoresistors Rx1 to Rx4 are formed in a stress concentration region where stress is concentrated in the bent portion 13 when acceleration in the x-axis direction is applied.

  Four piezoresistors Ry1, Ry2, Ry3, and Ry4 are formed to detect acceleration in the y-axis direction. The planar shapes of these piezoresistors Ry1 to Ry4 are all elongated rectangular shapes. The piezoresistors Ry <b> 1 to Ry <b> 4 are formed so that the longitudinal direction coincides with the longitudinal direction of the bending portion 13. These piezoresistors Ry1 to Ry4 are connected so as to constitute a central bridge circuit By in FIG. Wirings (not shown) connecting these piezoresistors Ry1 to Ry4 are diffusion layer wirings formed on the semiconductor substrate 10, metal wirings, and the like. Note that these piezoresistors Ry to Ry4 are formed in a stress concentration region where stress is concentrated in the bent portion 13 when acceleration in the y-axis direction is applied.

  Four piezoresistors Rz1, Rz2, Rz3, and Rz4 are formed to detect acceleration in the z-axis direction. These piezoresistors Rz1 to Rz4 are connected so as to constitute a bridge circuit Bz on the right side in FIG. Wirings (not shown) connecting these piezoresistors Rz1 to Rz4 are diffusion layer wirings formed on the semiconductor substrate 10, metal wirings, and the like. Here, the piezoresistors Rz1 and Rz4 formed in one set of the bent portions 13 and 13 of the two bent portions 13 and 13 are set so that the longitudinal direction thereof coincides with the longitudinal direction of the bent portions 13 and 13. Is formed. On the other hand, the piezoresistors Rz2 and Rz3 formed in the other set of bending portions 13 and 13 are formed such that the longitudinal direction coincides with the width direction (short direction) of the bending portions 13 and 13.

  The piezoresistors Rx1 to Rx4, Ry1 to Ry4, Rz1 to Rz4, and the diffusion layer wirings are formed by doping p-type impurities with appropriate concentrations at respective formation sites in the silicon layer 10c.

  Here, an example of the operation of the sensor unit 1a in the semiconductor element 1 will be described. Assume that acceleration is applied to the semiconductor element 1 in the positive direction of the x-axis with no acceleration applied to the semiconductor element 1. In this case, the weight part 12 is displaced with respect to the frame part 11 by the inertial force of the weight part 12 acting in the negative direction of the x axis. As a result, the bending portions 13 and 13 having the longitudinal direction in the x-axis direction are bent, and the resistance values of the piezoresistors Rx1 to Rx4 formed in the bending portions 13 and 13 change. At this time, the piezoresistors Rx1 and Rx3 are subjected to tensile stress, and the piezoresistors Rx2 and Rx4 are subjected to compressive stress. In general, a piezoresistor has a characteristic that a resistance value (resistivity) increases when subjected to a tensile stress and a resistance value (resistivity) decreases when subjected to a compressive stress. Therefore, the resistance values of the piezo resistors Rx1 and Rx3 are increased, and the resistance values of the piezo resistors Rx2 and Rx4 are decreased. Therefore, if a constant DC voltage is applied from the external power supply between the pair of input terminals VDD and GND shown in FIG. 3, the potential difference between the output terminals X1 and X2 of the bridge circuit Bx is the magnitude of the acceleration in the x-axis direction. It changes according to the height. Similarly, when the acceleration in the y-axis direction is applied to the semiconductor element 1, the potential difference between the output terminals Y1 and Y2 of the bridge circuit By changes according to the magnitude of the acceleration in the y-axis direction. Similarly, when an acceleration in the z-axis direction is applied to the semiconductor element 1, the potential difference between the output terminals Z1 and Z2 of the bridge circuit Bz changes according to the magnitude of the acceleration in the z-axis direction.

  Therefore, by detecting a change in the output voltage of each of the bridge circuits Bx to Bz of the semiconductor element 1, it is possible to detect accelerations in the x-axis direction, the y-axis direction, and the z-axis direction that act on the semiconductor element 1. it can. In this embodiment, the weight part 12 and each bending part 13 comprise the movable part. Moreover, each bending part 13 is formed in the center part of the semiconductor substrate 10, and comprises the thin functional part compared with the surrounding part. In addition, the piezoresistors Rx1 to Rx4, Ry1 to Ry4, Rz1 to Rz4 constitute a sensing unit in the semiconductor element 1. And in the bending part 13 which is a function part of the semiconductor substrate 10, the circuit part which consists of bridge circuit Bx-Bz which has the said sensing part is formed.

  The IC unit 1b includes an integrated circuit (CMOS IC) using CMOS. The integrated circuit of the IC unit 1b is an integrated circuit that cooperates with the piezo resistors Rx1 to Rx4, Ry1 to Ry4, and Rz1 to Rz4 that are the sensing units. The integrated circuit of the IC unit 1b performs signal processing such as amplification, offset adjustment, temperature compensation and the like on the output signals of the bridge circuits Bx, By, Bz, and outputs data used in the signal processing circuit. The stored EEPROM is integrated.

  Further, in the IC part 1b, the occupied area of the IC part 1b in the semiconductor element 1 is reduced by using a multilayer wiring technique. In the present embodiment, an insulating film 16 is formed on the surface of the silicon layer 10c opposite to the insulating film 10b (on the upper surface side in FIG. 1). This insulating film 16 is a laminated film of a silicon oxide film and a silicon nitride film on the silicon oxide film. In the IC portion 1b, a multilayer structure portion 41 having an interlayer insulating film, a passivation film, and the like is formed on the surface side of the insulating film 16. A plurality of electrodes 42 are exposed by removing appropriate portions of the passivation film of the multilayer structure 41.

  A plurality of external connection electrodes 17 and a plurality of through-hole wirings 18 are provided in the bonding region portion 1c. The external connection electrode 17 is an electrode for connecting to an external circuit such as an electric circuit provided on the mounting substrate (mother substrate) 2. The plurality of external connection electrodes 17 are arranged on the other surface side of the semiconductor substrate 1 so as to be separated from each other in the circumferential direction of the bonding region 1 c. The external connection electrode 17 is formed on the outer peripheral side of the semiconductor substrate 10 with respect to the through hole wiring 18 on the other surface side of the semiconductor substrate 10. In the present embodiment, the outer peripheral shape of each external connection electrode 17 is rectangular. On the other surface side of the semiconductor substrate 10, a plurality of surface wirings 19 a that electrically connect the external connection electrodes 17 and the through-hole wirings 18 are formed. In the present embodiment, the material of the external connection electrode 17 and the material of the surface wiring 19 a are the same metal material (for example, Au), and the surface wiring 19 a is formed in a form continuous with the external connection electrode 17.

  In the external connection electrode 17, a Ti film is interposed as an adhesion layer for improving adhesion between the bonding film made of the Au film and the insulating film 10b. In other words, the external connection electrode 17 is composed of a laminated film of a Ti film formed on the insulating film 10b and a bonding film formed on the Ti film. Here, in the external connection electrode 17, the thickness of the Ti film is set to 15 to 50 nm, and the thickness of the bonding film is set to 500 nm. However, these numerical values are examples and are not particularly limited. Further, the material of each Au film is not limited to pure gold, and may be one added with impurities. In the above example, a Ti film is exemplified as the adhesion layer, but the material of the adhesion layer is not limited to Ti, and may be, for example, Cr, Nb, Zr, TiN, TaN, or the like. The bonding film is not limited to the Au film but may be an Al film.

  The through-hole wiring 18 is for electrically connecting the circuit portion and the external connection electrode 17 and penetrates the semiconductor substrate 10 in the thickness direction (vertical direction in FIG. 1). Here, when forming the through-hole wiring 18, before forming the insulating layer 10 b on the support substrate 10 a, the through-hole wiring 18 is formed in the thickness direction (vertical direction in FIG. 1) in each region where the through-hole wiring 18 is to be formed. A through-hole 10d is formed in advance. Thus, the insulating film 10b is formed across one surface (upper surface in FIG. 1), the other surface (lower surface in FIG. 1), and the inner surface of the hole 10d. Thereafter, by appropriately forming the silicon layer 10c and the insulating film 16, the through hole 10e shown in FIG. 1 is obtained. Such a hole 10d is formed using an anisotropic etching technique using, for example, an inductively coupled plasma (ICP) type dry etching apparatus. In this case, the aspect ratio of the hole 10d can be increased as compared with the case where the hole 10d is formed using a general RIE apparatus. As a result, for example, the through-hole wiring 18 having a diameter of 100 μm or less can be formed. Thereby, the area of the through-hole wiring 18 on each of the one surface and the other surface of the semiconductor substrate 10 can be reduced. The through-hole wiring 18 is formed using a plating method. Here, as the material of the through-hole wiring 18, Cu, Ni, or the like can be adopted.

  A connection portion 43 for electrically connecting the through-hole wiring 18 and the circuit portion is provided on the one surface side of the semiconductor substrate 10. The connection part 43 is made of a lead wiring that connects the electrode 42 of the IC part 1 b to the through-hole wiring 18. The connection portion 43 is formed on the center side (center side) of the semiconductor substrate 10 with respect to the one surface side of the semiconductor substrate 10 than the through-hole wiring 18. The connecting portion 43 is electrically connected to the through-hole wiring 18 by the surface wiring 19b formed on the one surface side of the semiconductor substrate 10. That is, on the one surface side of the semiconductor substrate 10, a plurality of surface wirings 19 b that electrically connect the connection portions 43 and the through-hole wirings 18 are formed. In the present embodiment, the material of the connection portion 43 and the material of the surface wiring 19b are the same metal material (for example, Au), and the connection portion 43 and the surface wiring 19b are formed continuously. The plurality of electrodes 42 formed in the IC portion 1b are electrically connected to the circuit portion through the signal processing circuit and electrically connected to the circuit portion without passing through the signal processing circuit. There is something to be done. In any case, the connection part 43 is electrically connected to the circuit part.

  The semiconductor element 1 of this embodiment is mounted on a mounting substrate 2 as shown in FIG. Here, the mounting substrate 2 includes an insulating base material 20 made of glass epoxy resin or the like. A plurality of connection terminals (conductor patterns) 21 that are electrically connected to the respective external connection electrodes 17 of the semiconductor element 1 are formed on one surface side (the upper surface side in FIG. 1) of the insulating substrate 20. Yes. FIG. 1 shows an example in which a semiconductor element 1 is mounted on a mounting substrate 2 by a flip chip mounting method. In the example shown in FIG. 1, the external connection electrode 17 and the connection terminal 21 of the mounting substrate 2 are connected by the joint portion 50. Here, the bonding portion 50 is formed by a bump such as an Au bump. In addition, what is necessary is just to set joining temperature to about 100-400 degreeC, when joining part 50 is formed by Au bump.

  By the way, the semiconductor element 1 of this embodiment includes the first groove portion 31 formed on the center side of the semiconductor substrate 10 with respect to the other surface side of the semiconductor substrate 10 and the one surface of the semiconductor substrate 10. And a second groove 32 formed on the outer peripheral side of the semiconductor substrate 10 with respect to the through-hole wiring 18 on the side. In particular, in the present embodiment, the second groove portion 32 is formed so as to be positioned between the external connection electrode 17 and the through-hole wiring 18.

  In the semiconductor element 1 of the present embodiment, a portion of the semiconductor substrate 10 between the second groove portion 32 and the first groove portion 31 is subjected to stress (that is, transmitted from the mounting substrate 2 to each bent portion 13 of the semiconductor element 1 (that is, In addition, the external connection electrode 17 and the connection terminal 21 of the mounting substrate 2 become a stress relaxation portion that relieves stress generated in the bending portion 13 when the joint portion 50 made of solder is joined.

  In the present embodiment, each of the first groove portion 31 and the second groove portion 32 is formed in a rectangular ring shape along the arrangement direction of the through-hole wirings 18. As shown in FIG. 2, the first groove portion 31 is located inside the second groove portion 32 in the projection view. In addition, a plurality of through-hole wirings 18 are arranged in a portion between the second groove portion 32 and the first groove portion 31 in the semiconductor substrate 10.

  In the present embodiment, the depth dimension of each of the first groove part 31 and the second groove part 32 is set to be larger than half the thickness dimension of the semiconductor substrate 10. Such deep groove first groove portion 31 and second groove portion 32 may be formed using an anisotropic etching technique using, for example, an ICP type dry etching apparatus. If the first groove portion 31 and the second groove portion 32 are formed using an ICP type dry etching apparatus, the width of the first groove portion 31 and the second groove portion 32 can be reduced to 100 μm or less. The thickness of the thin portion between the inner bottom surface of the first groove portion 31 and the one surface of the semiconductor substrate 10 and the thin portion between the inner bottom surface of the second groove portion 32 and the other surface of the semiconductor substrate 10 Each thickness can be reduced to about 50 μm.

  Here, as the thickness of each thin-walled portion described above is thinner, the stress relaxation portion is more easily deformed. Therefore, it becomes easy to suppress stress propagation and the stress relaxation effect is enhanced. However, care should be taken because the mechanical strength deteriorates if the thin portion becomes too thin.

  In the present embodiment, the grooves 31 and 32 are formed after the insulating film 10b is formed. However, the insulating film 10b may be formed after the grooves 31 and 32 are formed. In this case, the insulating film 10b is also formed on the inner surfaces of the groove portions 31 and 32. In any case, the first groove portion 31 and the second groove portion 32 are formed by dry-etching the respective planned formation regions of the first groove portion 31 and the second groove portion 32 in the semiconductor substrate 10. Therefore, the aspect ratio of the first groove portion 31 and the second groove portion 32 can be increased as compared with the case where the first groove portion 31 and the second groove portion 32 are formed by wet etching or a dicing saw. Therefore, the formation area of each of the first groove portion 31 and the second groove portion 32 can be narrowed.

  In the semiconductor element 1 of the present embodiment described above, the first groove portion 31 is formed on the other surface side of the semiconductor substrate 10 on the center side of the semiconductor substrate 10 than the through-hole wiring 18, and A second groove 32 is formed on the outer peripheral side of the semiconductor substrate 10 with respect to the through-hole wiring 18 on one surface side. As a result, the stress relaxation, which is a portion between the first groove portion 31 and the second groove portion 32 in the semiconductor substrate 10, between the portion where the external connection electrode 17 is formed in the semiconductor substrate 10 and the bent portion 13. Part is interposed. The stress relaxation portion is a portion that has a sufficiently small width dimension and is easily deformed as compared with the semiconductor substrate 10. Therefore, the stress generated in the bending portion 13 due to the difference in linear expansion coefficient between the semiconductor substrate 10 and the mounting substrate 2 can be sufficiently relaxed by the deformation of the stress relaxation portion. Further, since the through-hole wiring 18 is arranged in the stress relaxation portion, the circuit portion on the one surface side of the semiconductor substrate 10 even if the first groove portion 31 and the second groove portion 32 are formed. And the external connection electrode 17 on the other surface side of the semiconductor substrate 10 can be electrically connected.

  Here, the stress relaxation portion is more easily deformed as its width is narrower. Therefore, the narrower the width of the stress relaxation portion, the easier the stress propagation is suppressed and the stress relaxation effect is enhanced. However, if the width of the stress relaxation portion becomes too narrow, it is difficult to form the through-hole wiring 18 and the mechanical strength deteriorates, so care must be taken.

  Furthermore, in the semiconductor element 1 of the present embodiment, the connection portion 43 is formed on the one surface side of the semiconductor substrate 10 on the center side of the semiconductor substrate 10 than the through-hole wiring 18, and the external connection electrode 17 is connected to the semiconductor substrate 10. The other surface side of the semiconductor substrate 10 is formed on the outer peripheral side of the through-hole wiring 18. That is, the circuit portion and the bending portion 13 processed by the wafer process are located on the center side of the semiconductor substrate 10, and the external connection electrode 17 where stress propagates when mounted on the mounting substrate 2 is on the outer peripheral side of the semiconductor substrate 10. positioned. Therefore, it is possible to increase the distance between the bending portion 13 and the connection portion 43 and the external connection electrode 17 in the plane having the thickness direction of the semiconductor substrate 10 as the normal direction, and the bending portion 13 and the connection portion 43 and the outside. The stress relieving part is interposed between the connection electrodes 17. Therefore, the stress generated in the bent portion 13 of the semiconductor element 1 due to the difference in linear expansion coefficient between the semiconductor substrate 10 and the mounting substrate 2 can be further relaxed. In particular, in the semiconductor element 1 of the present embodiment, the external connection electrode 17 is formed on the outer peripheral side of the semiconductor substrate 10 with respect to the second groove portion 32, so that the linear expansion coefficient difference between the semiconductor substrate 10 and the mounting substrate 2. Due to this, it is possible to further relax the stress generated in the bent portion 13 of the semiconductor element 1.

  By the way, in the semiconductor element 1 of the present embodiment, the first groove portion 31 is formed on the other side of the semiconductor substrate 10 on the center side of the semiconductor substrate 10 than the through-hole wiring 18. Further, the second groove portion 32 is formed on the outer peripheral side of the semiconductor substrate 10 with respect to the through hole wiring 18 on the one surface side of the semiconductor substrate 10.

  However, the first groove portion 31 may be formed not on the other surface side of the semiconductor substrate 10 but on the center side of the semiconductor substrate 31 on the one surface side. In this case, the second groove portion 32 is formed not on the one surface side of the semiconductor substrate 10 but on the outer peripheral side of the semiconductor substrate 10 on the other surface side.

  However, in the latter case, as shown in FIG. 4, three through-hole wirings 18 are required to electrically connect the connection portion 43 and the external connection electrode 17. In this case, it is necessary to add two surface wirings 19c and 19d. Here, the surface wiring 19c is a wiring for electrically connecting the through-hole wiring 18 (the right-side through-hole wiring 18 and the central through-hole wiring 18 in FIG. 4) to each other on the other surface side of the semiconductor substrate 10. is there. On the other hand, the surface wiring 19d is a wiring for electrically connecting the through-hole wirings 18 (the central through-hole wiring 18 and the left-side through-hole wiring 18 in FIG. 4) on the one surface side of the semiconductor substrate 10. .

  On the other hand, in the former case (that is, in the case of the present embodiment), as shown in FIG. That is, in the former case, as compared with the latter case, the number of through-hole wirings 18 interposed between the connection portion 43 and the external connection electrode 17 that are electrically connected to each other can be reduced. Therefore, there is an advantage that the wiring structure can be simplified. Moreover, there is an advantage that the electrical reliability between the connection portion 43 and the external connection electrode 17 can be improved.

  Further, in the semiconductor element 1 of the present embodiment, as shown in FIG. 5, the inner bottom surface 31a of the first groove portion 31 and the inner bottom surface 32a of the second groove portion 32 may be formed in a concave curved surface shape. In this way, stress concentrates near the boundary between the inner bottom surface 31a and the inner peripheral surface of the first groove portion 31 as compared with the case where the inner bottom surface 31a of the first groove portion 31 is formed in a planar shape. This can be prevented. Similarly, stress is prevented from concentrating near the boundary between the inner bottom surface 32a of the second groove portion 32 and the inner peripheral surface, compared to the case where the inner bottom surface 32a of the second groove portion 32 is formed in a planar shape. can do. Thereby, damage to the semiconductor substrate 10 can be prevented. In addition, the 1st groove part 31 and the 2nd groove part 32 in which the inner bottom surfaces 31a and 32a became concave curved surface as shown in FIG. 5 are the time of forming the 1st groove part 31 and the 2nd groove part 32. It can be easily formed by appropriately setting the etching conditions.

  By the way, in this embodiment, the example which mounted the semiconductor element 1 in the mounting board | substrate 2 by the flip chip mounting method is shown. Here, the semiconductor element 1 may be mounted on the mounting substrate 2 by a wire bonding mounting method instead of the flip chip mounting method. In this case, a bonding metal layer (not shown) is provided on the semiconductor element 1. The bonding metal layer is formed on the insulating film 16 in the bonding region 1c. Such a bonding metal layer is composed of, for example, a laminated film of a Ti film formed on the insulating film 16 and an Au film formed on the Ti film.

  When the semiconductor element 1 is mounted on the mounting substrate 2 by the wire bonding mounting method, the semiconductor element 1 is bonded to the insulating base material 20 of the mounting substrate 2 using the bonding metal layer, and bonding wires (FIG. The external connection terminal 17 may be electrically connected to the connection terminal 21 of the mounting substrate 2 through a not-shown).

  Moreover, although the semiconductor element 1 demonstrated the acceleration sensor provided with the IC part 1b in this embodiment, the acceleration sensor which is not provided with the IC part 1b may be sufficient. In each of the above embodiments, a piezoresistive acceleration sensor is exemplified as the semiconductor element 1. However, the semiconductor element 1 is not limited to a piezoresistive acceleration sensor. For example, a pressure sensor, an infrared sensor, a BAW filter, An electrostatic transducer may be used.

It is a schematic sectional drawing which shows the usage condition of the semiconductor element of one Embodiment of this invention. It is a schematic plan view of a semiconductor element same as the above. It is a principal part circuit diagram of a semiconductor element same as the above. It is a principal part schematic sectional drawing of the other structural example of a semiconductor element same as the above. It is a principal part schematic sectional drawing of another structural example of a semiconductor element same as the above.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor element 10 Semiconductor substrate 13 Bending part (functional part)
17 External connection electrode 18 Through-hole wiring 31 1st groove part 31a inner bottom face 32 2nd groove part 32a inner bottom face 43 connection part

Claims (5)

A semiconductor substrate in which a thin functional portion is formed in the center compared to the peripheral portion, a circuit portion formed in the functional portion on one surface side of the semiconductor substrate, and provided on the other surface side of the semiconductor substrate An external connection electrode; a through-hole wiring for passing through the semiconductor substrate in the thickness direction and electrically connecting the circuit portion and the external connection electrode; and the through-hole provided on the one surface side of the semiconductor substrate In a semiconductor element comprising a wiring and a connection part for electrically connecting the circuit part,
A first groove formed on the center side of the semiconductor substrate rather than the through-hole wiring on either the one surface side or the other surface side of the semiconductor substrate;
A semiconductor element comprising: a second groove formed on an outer peripheral side of the semiconductor substrate with respect to the through-hole wiring on the other one of the one surface side and the other surface side of the semiconductor substrate. . The connecting portion is formed on the center side of the semiconductor substrate from the through-hole wiring on the one surface side of the semiconductor substrate,
2. The semiconductor element according to claim 1, wherein the external connection electrode is formed on an outer peripheral side of the semiconductor substrate with respect to the through hole wiring on the other surface side of the semiconductor substrate. The first groove is formed on the other surface side of the semiconductor substrate,
3. The semiconductor device according to claim 2, wherein the second groove is formed on the one surface side of the semiconductor substrate.   The semiconductor element according to claim 1, wherein the inner bottom surfaces of the first groove portion and the second groove portion each have a concave curved surface shape.   The first groove portion and the second groove portion are formed by dry-etching respective formation regions of the first groove portion and the second groove portion in the semiconductor substrate. Item 5. The semiconductor element according to any one of Items 1 to 4.

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