JP5045692B2 - Operation mode control circuit and microcomputer - Google Patents

Description

  The present invention is a microcomputer that performs processing according to a control program, and includes an operation mode control circuit that controls an operation mode of the input / output circuit in a microcomputer incorporating an input / output circuit having a plurality of operation modes, and The present invention relates to a microcomputer incorporating an operation mode control circuit.

  A microcomputer system or the like is required to have a monitoring function by a watchdog timer and to operate stably even in a poor environment. And a microcomputer for controlling the system by a control program (hereinafter, a general microcomputer, a micro control system, or a semiconductor control device, for example, a DSP (digital signal processor) or the like is collectively referred to as a microcomputer). For a microcomputer incorporating an input / output circuit having the above operation mode, it is required by the control program that the operation mode of the input / output circuit set when the microcomputer is initialized is stable. This is because the input / output signals of the microcomputer have a great influence on other devices of the microcomputer system that operate according to the input / output signals, and as a result, the entire operation of the microcomputer system is also affected. is there.

  Therefore, there has been a demand for a circuit that is built in the microcomputer so as to control the operation mode once the operation mode of the input / output circuit is set.

  A conventional example related to stable operation of a microcomputer system using an input / output circuit operation control in a microcomputer or a watchdog timer will be described below with reference to FIGS.

  The vehicle LAN microcomputer system shown in FIG. 16 includes a microcomputer 602, a watchdog timer 605, which is an external LSI that monitors the operation of the microcomputer, a power supply circuit 603, a ROM 606, an input I / F circuit 601, and a VCCION. / OFF circuit 607, VCCI 613, VCCII 614, low voltage reset circuit 608, communication LSI 609, delay circuit 604, and multi-input AND circuit 615.

In the vehicle LAN microcomputer system, a watchdog timer (hereinafter referred to as “watchdog”) 605 for monitoring the operation of the microcomputer 602 is mounted on the system, and when the microcomputer 602 is in a runaway state for some reason, By detecting that the signal from the monitoring signal generation circuit mounted on the microcomputer 602 is interrupted, the microcomputer is reset to prevent malfunction (for example, Patent Document 1).
The data processing apparatus shown in FIG. 17 is a single-chip microcomputer, and includes a central processing unit CPU 701, a system controller SYSC 702, an interrupt controller INT 704, a read only memory ROM 705, a random access memory RAM 706, and a timer 708. And functional blocks of a serial communication interface SCI 707, first to eighth input / output ports IOP8 (709) to 1 (716), and a clock oscillator CPG 703.

The data processing apparatus has a system controller SYSC 702 that holds operation mode information inside a single chip microcomputer, and automatically reads information stored in a ROM 705 that is a nonvolatile storage device in an initialization operation. The system controller SYSC 702 that holds the operation mode information is set by a control signal that is not controlled by software. Furthermore, the operation mode information of the system controller SYSC 702 that holds the operation mode information is erroneously changed to an operation mode that is not rewritten by software of the CPU (central processing unit) 701 in the operation after the initialization operation. To prevent rewriting (for example, Patent Document 2).
18 includes a CPU 801, a memory 802, a protection control register 804, an address decoder 811 to 814, logic elements 805 to 810, a protection control circuit 830 having a logic element 827, and a control register 815. The clock generation circuit 819 includes a peripheral unit A 820 having a control register 816, a peripheral unit B 821 having a control register 817, and a peripheral unit C 822 having a control register 818.

  The microcomputer holds information on whether to allow or prohibit writing of data to the control registers 815 to 818 for each control register, and the protection control register 804 stores the information when a write operation occurs. The control register that is the target is specified, and the protection control circuit 830 controls the write signal according to the information in the protection control register 804, so that the control register caused by a program runaway or the like is controlled. Incorrect writing is prevented (for example, Patent Document 3).

JP-A-5-32142 JP-A-8-63445 JP-A-8-233503

  In a microcomputer that performs processing by a control program, when the microcomputer has an input / output circuit having a plurality of operation modes, the operation mode is determined only by the control program. Reconfiguration may occur. On the other hand, there is a problem that flexibility and expandability are lost when the operation mode is determined only by the microcomputer hardware so that the operation mode is not reset as described above.

  For example, in a conventional data processing apparatus, it is possible to prevent the operation mode and the like from being rewritten by an instruction caused by the CPU software during a malfunction of the microcomputer, but the operation mode information is obtained by a control signal that is not controlled by the software. Since the register means to be held is controlled, the operation mode can be set only by information stored in the nonvolatile storage device, and there is a problem that flexibility and expandability are lost.

  Further, in a conventional microcomputer, a protection control circuit for selecting whether to allow or prohibit writing to a control register for determining an operation mode and a protection control circuit for selecting a control register for determining an operation mode are large-scale. There was a problem that required hardware. Furthermore, in the microcomputer described above, rewriting of the control register that determines the operation mode due to microcomputer runaway can be prevented by the protect circuit, but the protect control register can be rewritten by an instruction caused by software. The protection control register is rewritten with an instruction caused by software when the microcomputer runs out of control, and as a result, the control register for determining the operation mode can be rewritten and set to an unintended operation mode.

  Further, the microcomputer built in the microcomputer system switches the input / output attributes of the input / output circuit (for example, switching between the input mode and the output mode), the A / D converter, or the 16-bit length interval according to an instruction derived from the control program. Of the built-in peripheral functions such as a timer, it is possible to switch which built-in peripheral function outputs the output signal to the outside of the microcomputer system. On the other hand, if the microcomputer runs out of control, the monitoring signal generated spontaneously by the microcomputer is interrupted, so a reset signal is output from the watchdog built into the microcomputer system that detected the disconnection of the monitoring signal, causing the microcomputer system to malfunction. Is prevented.

  Therefore, if a runaway microcomputer command causes the output signal of the built-in peripheral function to be output to the outside of the microcomputer system, and a watchdog signal is output instead of the monitor signal, the watchdog Does not detect the interruption of the monitoring signal, and does not generate a reset signal that stops the microcomputer from running away.

  Then, there is a problem that the malfunction of the microcomputer system is not prevented while the watchdog monitoring function is incorporated.

  In addition, when the microcomputer is operating normally, and the microcomputer generates a command to generate it due to noise inside the microcomputer (including when it occurs in response to external noise). However, when a command related to the setting of the operation mode occurs, as a result, the mode of the output circuit that outputs the monitoring signal to the watchdog is reset, and the reset signal is output from the watchdog when the monitoring signal is interrupted. Even if the microcomputer is normal, there is a problem that the microcomputer is reset.

  Therefore, the present invention is a microcomputer that performs processing by a control program, and when the microcomputer incorporates an input / output circuit having a plurality of operation modes, while maintaining the flexibility and expandability of the operation modes, An operation mode control circuit that suppresses unintended resetting of the operation mode and a microcomputer incorporating the operation mode control circuit are provided.

According to one aspect of the present invention, at least a control signal generator and a second output signal from the control signal generator in response to the first output signal from the control signal generator, A write inhibit circuit for generating a write signal according to the logic value of the signal, a third output signal from the control signal generator in response to the write signal, and a control according to the logic value of the held signal An operation mode control circuit comprising a control circuit for generating a signal is provided . The write signal, when the logic value of the signal write inhibition circuit has held a one logic value is a signal whose logic value is fixed, the logical value other logic value of the signal write inhibition circuit is held Is a buffer signal of the first output signal from the control signal generation unit, and the control signal is a signal generation circuit that transmits a signal to the outside from a plurality of signal generation circuits including at least a data register circuit. It is supplied to the selection circuit to select.
According to the above configuration, when there are a plurality of peripheral circuits connected to one input / output control circuit through the selection circuit in the microcomputer, the write inhibit circuit operates to bring the selection circuit into a predetermined state. After the selection signal is set, the setting cannot be rewritten by the computer itself, so that the setting of the selection circuit is maintained regardless of the state of the microcomputer (for example, even in a runaway state).

The present invention has the following effects.
In the microcomputer, the operation mode of the microcomputer, for example, the setting of the connection between the peripheral function circuit and the I / O (Input / Output) buffer, the setting of the operation mode of the I / O buffer, etc. are set during the operation mode setting period. According to the microcomputer control program, there is an effect that it can be set according to the situation.

  On the other hand, the setting of the operation mode set during the operation mode setting period depends on the effect of the operation mode control circuit inside the microcomputer until the microcomputer is reset from the outside (for example, even in a runaway state). There is an effect that it cannot be reset regardless.

Therefore, the operation mode is compared with the setting of the connection between the monitoring signal generation circuit for the watchdog timer which is a kind of peripheral function circuit and the I / O buffer of the monitoring signal output port, and the operation mode of the I / O buffer. When the control circuit is applied, the setting set in the operation mode setting period is maintained until it is reset by an external reset signal regardless of the state of the microcomputer.
As a result, the watchdog timer is effective in detecting the runaway state of the microcomputer with high reliability.

It is the schematic of the whole microcomputer circuit which concerns on 1st Embodiment. It is a control program schematic diagram of the microcomputer concerning a 1st embodiment. It is a flowchart schematic diagram of a control program concerning a 1st embodiment. It is a flowchart schematic diagram of the mode setting routine concerning a 1st embodiment. It is the whole microcomputer schematic circuit diagram concerning a 2nd embodiment. It is the schematic of 3rd Embodiment. It is an operation | movement waveform diagram of the write-inhibition circuit of 3rd Embodiment. It is the schematic of 4th Embodiment. It is an operation | movement waveform diagram of the write-inhibition circuit of 4th Embodiment. It is the schematic of 5th Embodiment. It is an operation | movement waveform diagram of the write-inhibition circuit of 5th Embodiment. It is the schematic of 6th Embodiment. It is an operation | movement waveform diagram of the write-inhibition circuit of 6th Embodiment. It is the schematic of 7th Embodiment (outline | summary of the whole microcomputer circuit). It is the schematic of 8th Embodiment (control system). It is the schematic of the prior art example 1 (vehicle microcomputer system). It is the schematic of the prior art example 2 (data processing apparatus). It is the schematic of the prior art example 3 (microcomputer).

  A microcomputer according to an embodiment for carrying out the invention (hereinafter referred to as a general microcomputer, a micro control system, or a semiconductor control device such as a DSP (digital signal processor)) will be described below. . The microcomputer includes a CPU (central processing unit) including a control signal generator, an output data register, an operation mode control circuit, a timer, a selector, and an I / O buffer having a plurality of operation modes. ing. The operation mode control circuit includes an OR circuit, a peripheral selection register, an input / output control register, and a write inhibit circuit.

  The CPU controls other control circuits by a microcomputer control program. In addition, the CPU sets a write signal to registers related to the operation mode setting, such as an input / output control register and a peripheral selection register, in order to set the operation mode through the control signal generator by the operation mode setting routine in the control program. Is generated.

  The output data register is a temporary storage location for data output from the CPU through the I / O buffer to the outside of the microcomputer.

  The timer is a specific example of the peripheral function circuit, and generates a signal indicating a certain interval for the microcomputer to control the external device.

  The selector is a circuit that selects one of the output of the output data register or the output from the timer according to the logical value of the signal from the peripheral selection register and connects it to the I / O buffer.

  The operation mode control circuit controls selection of the selector through the peripheral selection register. The operation mode of the I / O buffer is controlled through the input / output control register and the OR circuit. The circuits constituting the operation mode control circuit operate as follows.

  The peripheral selection register outputs a signal for connecting the output of the output data register to the I / O buffer in response to the write signal to the selector and the OR circuit.

  The input / output control register outputs a signal for setting an operation mode of the I / O buffer to the OR circuit.

  The output of the peripheral selection register and the output of the input / output register are input to the OR circuit. The OR circuit outputs a logical value “0” when the logical value of the signal from the peripheral selection register is “0”, while the logical value of the signal from the peripheral selection register is “1”. In some cases, a logical value similar to the signal of the input / output control register is output.

  The write inhibit circuit outputs a signal of logical value “0” for the peripheral selection register to connect the output of the output data register to the I / O buffer to the selector and the OR circuit, and the OR circuit After the signal of logical “0” is output from the I / O buffer and the operation mode of the I / O buffer is set, the operation mode of the input / output circuit is reset until it is reset by an external reset signal. Deter.

  The I / O buffer having the plurality of operation modes inputs / outputs a signal to / from the outside of the microcomputer according to an operation mode set by a logical value of a signal from the OR circuit. Here, the operation mode corresponding to the logical value “0” is the output mode, and the operation mode corresponding to the logical value “1” is the input mode.

  According to the mode for carrying out the invention, while the operation mode setting routine in the control program of the CPU is operating, the setting for connecting the output of the output data register to the I / O buffer, and the I / O buffer The operation mode can be set by software. However, after completion of the operation mode setting routine, due to the effect of the operation mode control circuit and the write inhibit circuit constituting the operation mode control circuit, the I / O buffer is not reset until reset by an external reset signal. Resetting the operation mode setting and the connection setting between the output data register and the I / O buffer is inhibited. Therefore, even if unexpected software operates as a result of CPU runaway, the above setting is maintained.

(First embodiment)
The first embodiment will be described with reference to FIGS.

  First, the microcomputer 850 shown in FIG. 1 includes a CPU (Central Processing Unit) 860 including a control signal generator 861, a RAM (Random Access Memory) 851, a ROM (Read Only Memory) 852, and an operation mode detection circuit 853. An output data register 855, a reset circuit 870, an operation mode control circuit 862, a timer 854, a selector 856, an input buffer 864, an I / O (Input / Output) buffer 867, a data bus 863, A reset signal 871, an operation mode setting port 865, a monitor signal output port 866, and a reset signal receiving port 869 are provided. The operation mode control circuit 862 includes an OR circuit 868, a peripheral selection register 857, an input / output control register 858, and a write inhibit circuit 859.

  The monitoring signal output port 866 is a port for outputting a monitoring signal from the microcomputer 850 to the watchdog timer. Here, the watchdog timer monitors the output timing of the monitoring signal, that is, the interval between the monitoring signals, the number of outputs per unit time, etc., and whether the CPU 860 in the microcomputer 850 is operating normally. This is an external circuit for determining whether or not.

  Next, the operation mode setting port 865 is a port for receiving an external input signal for determining the operation mode from the outside of the microcomputer 850 during the period for determining the operation mode of the microcomputer 850.

  Next, the reset signal receiving port 869 is a port for receiving a reset signal generated when the watchdog timer determines that the CPU 860 in the microcomputer 850 is malfunctioning or running out of control. The port is also a port for receiving a reset signal from the outside of the microcomputer 850 (hereinafter referred to as “reset signal from the outside of the microcomputer 850”), which is input to initialize the microcomputer 850. That is, the “reset signal from the outside” includes a “reset signal from the watchdog timer” and a “reset signal from the outside of the microcomputer 850” that is input to initialize the microcomputer 850.

  The CPU 860 is a central processing unit that controls the entire microcomputer 850 by a control program of the microcomputer 850. The control signal generation unit 861 is a signal generation unit that controls the internal circuit of the microcomputer 850 and determines the operation mode of circuits other than the CPU 860 in the CPU 860.

  The RAM 851 and the ROM 852 serve as, for example, a storage location for control programs and setting conditions and a temporary storage location for data passed between functional circuits in the microcomputer 850.

  In addition, the data bus 863 is a bus through which data passed between functional circuits in the microcomputer 850 passes. Here, the data bus 863 includes a so-called common bus to which the CPU 860 is connected, but also includes a bus that is not connected to the CPU 860 and exists between functional circuits other than the CPU 860.

  In addition, the reset circuit 870 is an internal reset signal 904 or a reset signal to a circuit inside the microcomputer 850 in response to “a reset signal from the watchdog timer” or “a reset signal from the outside of the microcomputer 850”. 871 is generated, and each related circuit in the microcomputer 850 is reset. Here, the reset signal 871 is connected to a related circuit that needs to be reset in addition to the CPU 860.

  Further, the operation mode detection circuit 853 is a circuit for determining an input state given to the operation mode setting port 865 during a period for determining the operation mode after the operation of the microcomputer 850.

  Next, the I / O buffer 867 includes an output circuit that outputs data to the outside of the microcomputer 850 and an input circuit that receives data from the outside of the microcomputer 850. For example, in either the input mode or the output mode, Can have a plurality of input / output modes such as a non-existing mode, but has an operation mode setting terminal, and when it receives a signal of logical value “0”, it receives an output mode, and when it receives logical value “1” In this embodiment, it is desirable to set the input mode.

  In addition, the output data register 855 is a temporary storage location for data output from the CPU 860 to the outside of the microcomputer 850 through the I / O buffer 867. The output data register 855 delivers the stored data to the I / O buffer 867 at a predetermined timing. Therefore, when the I / O buffer 867 is connected to the monitor signal output port 866 that outputs data from the microcomputer 850 to the watchdog timer, the output data register 855 is connected to the watchdog timer from the microcomputer 850. Data is temporarily stored, and the CPU 860 controls to form a predetermined timing that provides evidence that the CPU 860 is operating normally.

  Next, the timer 854 is a specific example of a peripheral function circuit, and is a circuit that generates a signal indicating a certain interval for the microcomputer 850 to control an external device.

  Further, the selector 856 selects one of the output from the output data register 855 or the output from the timer 854 according to the logical value of the signal from the peripheral selection register 857, and sends it to the I / O buffer 867. It is a circuit to be connected. That is, when the logical value of the signal from the peripheral selection register 857 is “0”, the output from the output data register 855 is selected, and when the logical value of the signal from the peripheral selection register 857 is “1”. , The output from the timer 854 is selected.

  In addition, the operation mode control circuit 862 is a circuit for controlling the input / output mode of the I / O buffer 867 and instructing selection to the selector 856. The circuit constituting the operation mode control circuit 862 is as follows. Behaves like

  The input / output control register 858 is a circuit that holds a signal for setting an input / output mode, and outputs a signal indicating the same logical value as the held signal to the OR circuit 868.

  The peripheral selection register 857 is a circuit that holds a signal instructing the selector 856 to select, and outputs the same signal as the held signal to the selector 856 and the OR circuit 868.

  Further, the write inhibit circuit 859 is a peripheral selection register for a signal that instructs the selector 856 to select until it is reset by a “reset signal from the outside of the microcomputer 850” or “a reset signal from the watchdog timer”. Rewriting to 857 is inhibited.

  In addition, the OR circuit 868 selects the output signal from the output data register 855 when the selection instructing signal from the peripheral selection register 857 to the selector 856 is the logical value “0”. When it is, a signal of logical value “0” is output. As a result, the I / O buffer 867 is set to the output mode.

  On the other hand, the OR circuit 868 has a logical value “1” for the selection instruction from the peripheral selection register 857 to the selector 856, that is, when the selector 856 selects the output signal from the timer 854. A logical value corresponding to the signal from the input / output control register 858 is output. As a result, the I / O buffer 867 is set to the input / output mode corresponding to the logical value of the signal from the input / output control register 858.

  Therefore, the operation mode control circuit 862 described above is configured to connect the output signal from the output data register 855 to the I / O buffer 867 and the connected I / O during the operation mode setting period of the microcomputer 850. The operation mode of the O buffer 867 is set. Then, the operation of the write inhibit circuit 859 constituting the operation mode control circuit 862 causes the operation mode control circuit 862 to connect the output of the output data register 855 to the I / O buffer 867 and change the operation mode of the I / O buffer. After the output mode is set, the above setting is prevented from being reset until it is reset by the “reset signal from the outside of the microcomputer 850” or the “reset signal from the watchdog timer”.

  The input buffer 864 is a signal buffer circuit that transmits a signal input to the operation mode setting port 865 to the operation mode detection circuit 853.

  Next, the control program of the microcomputer 850 shown in FIG. 2 corresponds to the initialization module 903, the mode setting module 909, the display control module 910, the watchdog timer module 905, the task control module 907, and peripheral functions. The peripheral function 1 module 906 and the peripheral function 2 module 908 are provided at least. The control module of the microcomputer 850 is reset in response to the input of “an external reset signal 900 input from the outside of the microcomputer 850” or “a reset signal 902 from the watchdog timer”. The monitoring signal 901 is a signal generated as a result of the operation of the watchdog timer module 905. Further, the internal reset signal 904 is a signal generated from the watchdog timer module 905 because the initialization module 903 is activated.

  Each module of the control program corresponds to a group of routines executed by the CPU 850.

  Therefore, during the execution of the mode setting module 909 which is a part of the control program, for example, the setting signal from the operation mode setting port 865 is detected by the operation mode detection circuit 853 and the operation mode control is performed by the control from the CPU 860. The circuit 862 sets the selection of the selector 856 and the operation mode of the I / O buffer 867.

  Further, during execution of the watchdog timer module 905 that is a part of the control program, for example, the output data register 885 receives data from the CPU 860, and the I / O buffer 867 outputs the output from the output data register 855, The monitoring signal 901 is output from the monitoring signal output port 866 of the microcomputer 850. When the microcomputer 850 receives the reset signal 902 from the watchdog timer, the microcomputer 850 generates an internal reset signal 904 and activates the initialization module 903.

  In other words, if the CPU 860 is operating normally, a predetermined signal is output as the monitoring signal 901 at a predetermined timing. Therefore, when the predetermined signal is not output at all, or the predetermined signal is If it is not output at the timing, it can be recognized that the CPU 860 is malfunctioning.

  Here, in the first embodiment, it is assumed that the “reset signal 902 from the watchdog timer” and the “reset signal 900 from the outside of the microcomputer 850” are received by the reset signal receiving port 869. The reset circuit 870 makes a distinction between the “reset signal 902 from” and the “reset signal 900 from outside the microcomputer 850” according to the characteristics of each signal. In that case, the generated internal reset signal 904 and the reset signal 871 shown in FIG. 1 are supplied to similar related circuits including the CPU 860. However, the “reset signal 902 from the watchdog timer” and the “reset signal 900 from the outside of the microcomputer 850” may be input to the microcomputer 850 from different ports. Furthermore, it is not necessary to distinguish between “reset signal 902 from the watchdog timer” and “reset signal 900 from the outside of the microcomputer”. In this case, the entry point shown in the flowchart schematic diagram of the control program in FIG. A reset 915 and reset entry 916 from a watchdog timer will be integrated and connected to the watchdog timer module 918 of FIG. In FIG. 2, the “reset signal 900 from the microcomputer 850” and the “reset signal 902 from the watchdog timer” input to the initialization module 903 are input to the watchdog timer module 905 of FIG. Integrated into the “reset signal from the outside”.

  Further, during execution of the task control module 907, which is a part of the control program, the timing for executing various modules is determined by a predetermined algorithm.

  In addition, the initialization module 903, which is a part of the control program, is executed first when the “reset signal 900 from the outside of the microcomputer 850” is input, and sets the state of the microcomputer 850 to a predetermined initial state. To do.

  During execution of the display module 910 which is a part of the control program, the microcomputer 850 controls the state of the device inside the microcomputer 850 or the device controlled by the microcomputer 850 on the external display device to be controlled. A signal indicating a predetermined state is generated.

  In addition, the peripheral function circuit such as the timer 854 in the microcomputer 850 is operated during the execution of the modules related to the peripheral functions such as the peripheral function 1 module 906 and the peripheral function 2 module 908 which are a part of the control program.

  Next, FIG. 3 shows an outline of a flowchart of a control program of the microcomputer 850. When the program operates normally, if the “reset signal 900 from the outside of the microcomputer 850” is input, the control program of the microcomputer 850 enters the reset entry 916, and after executing the initialization module 917 and the mode setting module 923. The task control module 921 is executed. Also, the peripheral function control module 925 and the watchdog timer module 918 are executed by a predetermined algorithm during the execution of the task control module 921. On the other hand, when the control program does not operate normally, that is, when the CPU 860 runs away, the control program does not operate according to a predetermined algorithm, for example, the state where the watchdog timer module 918 stops operating at a predetermined timing, or at all The watchdog timer module 918 becomes inoperative. In this case, the watchdog timer module 918 is activated from the reset entry 915 from the watchdog timer by the “reset signal 902 from the watchdog timer”.

  Next, FIG. 4 shows an outline of a flowchart of the mode setting module 923 constituting the control program of the microcomputer 850. That is, the mode setting module 923 recognizes the input state for mode setting, outputs data to the peripheral selection register 857, holds data in the peripheral selection register 857, and data to the input / output control register 858 , And at least a step of holding data to the input / output control register 858 is shown. Then, after the inhibition of the write inhibition circuit 859 is released by the “reset signal from the outside of the microcomputer 850” or the “reset signal from the watchdog timer”, the operation recognized in the step of recognizing the input state for mode setting. Corresponding to the mode, by holding predetermined data in the peripheral selection register 857 and the input / output control register 858, the operation mode of the microcomputer 850 is set, and suppression is started by the function of the write suppression circuit 859. To do.

  Therefore, the microcomputer 850 of the first embodiment sets the operation mode of the microcomputer 850 regardless of the state of the CPU 860 (for example, even if it is in a runaway state), and then “reset signal from the outside of the microcomputer 850”. 900 ”or“ reset signal 902 from the watchdog timer ”in order to prevent the peripheral selection register 857 from rewriting a signal for instructing the selection of the peripheral function until the function is canceled. The setting of the signal for selecting the peripheral function 857 and the setting of the operation mode of the I / O buffer 867 are not reset.

  That is, during the operation mode setting period of the microcomputer 850, the CPU 860 controlled by the control program connects the output data register 855 to the monitoring signal output port 866 through the I / O buffer 867, and the I After the input / output mode of the / O buffer 855 is set to the output mode, the operation mode of the microcomputer 850 is fixed.

  Therefore, even when the CPU 860 goes into a runaway state, the peripheral selection register 857 does not hold a signal for instructing selection so that the output from the timer 854 is connected to the I / O buffer 867, and the microcomputer 850 The watch signal from the watchdog timer to the watchdog timer is not replaced with a signal from the timer 854 similar to the normal watch signal.

  As a result, a signal reflecting the state of the CPU 860 is always output from the monitoring signal output port 866 to the outside of the microcomputer 850, so that the watchdog timer can detect the runaway state of the CPU 860 with high reliability. it can.

(Second Embodiment)
First, the microcomputer 880 shown in FIG. 5 includes a CPU (central processing unit) 890 including a control signal generator 891, a RAM 881, a ROM 882, an operation mode detection circuit 883, an output data register 885, and a reset circuit 889. , An operation mode control circuit 886, a peripheral function circuit 884, an input buffer 893, an output buffer 899, an I / O buffer 897, a peripheral function circuit port 895, an operation mode setting port 894, and a monitor signal output A port 896, a reset signal receiving port 898, a data bus 892, and a reset signal 879 are provided. Further, the operation mode control circuit 886 includes an input / output control register 887 and a write inhibit circuit 888.

  Here, compared with the microcomputer 850 of the first embodiment, the microcomputer 880 according to the second embodiment has a general peripheral including a timer 854 instead of the timer 854 which is a specific example of the peripheral function circuit. The function circuit 884 is a constituent element, the output from the peripheral function circuit 884 is output from the peripheral function circuit port 895 to the outside of the microcomputer, the selector 856 is not included in the constituent element, and the I for the output data register 885 The / O buffer 897 and the output buffer 899 for the peripheral function circuit 884 exist separately, and the peripheral selection register 857 is not a component of the operation mode control circuit 886.

  Here, the peripheral function circuit port 895 is a port for outputting a signal from the peripheral function circuit 884 included in the microcomputer 880.

  The peripheral function circuit 884 is a circuit that generates a signal for the microcomputer 880 to control a device outside the microcomputer 880, and includes, for example, an interval timer and a 16-bit A / D converter.

  The operation mode control circuit 886 is a circuit that controls the input / output mode of the I / O buffer 897. The input / output control register 887 is a circuit that holds a signal for setting the input / output mode. The write inhibit circuit 888 is a signal for setting the input / output mode for the input / output control register 887 until it is reset by the “reset signal from the outside of the microcomputer 880” or the “reset signal from the watchdog timer”. This circuit suppresses rewriting. Therefore, the operation mode control circuit 886 sets the operation mode of the I / O buffer 897 to which the output data register 885 is connected during the operation mode setting period of the microcomputer 880. After the above setting, the operation mode control circuit 886 performs the “reset signal from the outside of the microcomputer 880” or the “watchdog timer” by the operation of the write suppression circuit 888 constituting the operation mode control circuit 886. By the “reset signal from”, the setting is prevented from being reset until it is reset.

  The input buffer 893 is a signal buffer circuit that transmits a signal from the operation mode setting port 894 to the operation mode detection circuit 883.

Further, the output buffer 899 is a signal buffer circuit for transmitting a signal from the peripheral function circuit 884 to the peripheral function circuit port 895.
On the other hand, regarding the other components of the microcomputer 880, the CPU 890, the control signal generator 891, the RAM 881, the ROM 882, the operation mode detection circuit 883, the output data register 885, the reset circuit 889, and the I / O buffer 897, The circuit has the same function as the circuit shown in the first embodiment. In addition, the monitoring signal output port 896 and the reset signal receiving port 898 are also ports having the same role as in the first embodiment. Further, the data bus 892 and the reset signal 879 are also buses or signals having the same role as in the first embodiment.

  Further, the control program for the microcomputer that controls the CPU 890 also has the same function as the control program for the microcomputer 880 in the first embodiment, and the task control module, operation mode setting module, and initialization module that constitute the control program. The watchdog timer control module and the peripheral function control module have similar functions.

  Therefore, in the microcomputer 880 of the second embodiment, the signal for setting the input / output mode is erroneously written to the input / output control register 887 by the operation of the operation mode control circuit 886 of the second embodiment. After setting the operation mode of the microcomputer 880 so that the function is canceled, the input / output mode is set until the function is canceled by the “reset signal from the outside of the microcomputer 880” or the “reset signal from the watchdog timer”. This has the effect of inhibiting the writing of signals to the input / output control register 887.

  That is, when the I / O buffer 897 is connected to the monitoring signal output port 896, the operation mode is fixed after the microcomputer 880 is set to the output mode during the operation mode setting period.

  Therefore, although the CPU 890 is normal, the microcomputer 880 does not erroneously write a signal for setting the input / output mode to the input / output control register 887 due to noise inside the microcomputer 880. A monitoring signal to the watchdog timer is always output. As a result, since the monitoring signal that always reflects the operation state of the CPU 890 reaches the watchdog timer, the watchdog timer can continue to monitor the state of the CPU 890 with high reliability.

(Third embodiment)
The third embodiment will be described with reference to FIGS. 6 and 7. The third embodiment relates to the operation mode control circuit of the second embodiment and will be described in more detail.

  First, FIG. 6 shows an operation mode control circuit 20 including a write inhibit circuit 10, an output data register 2 and input / output I / O3 controlled by the operation mode control circuit 20, and output signals from the input / output I / O3. Represents the terminal 8 from which is output. Here, the input / output I / O 3 has, for example, an operation mode in which no output signal is output, an operation mode in which an output signal is output, and the like, and the operation mode can be changed. On the other hand, the output data register 2 latches output data output from the input / output I / O 3.

  The operation mode control circuit 20 receives the write pulse generator 1 and the first input / output control register write signal 12 from the write pulse generator 1 and outputs a buffer signal of the input / output control register write signal 12. It comprises a write inhibit circuit 10 and an input / output control register 4 that receives the buffer signal of the input / output control register write signal 12 and latches data from the data bus 14. Further, the write pulse generator 1 supplies output data to the output data register 2 through the data bus 14 and supplies the output data register write signal 11 to the output data register 2 to latch the output data. The output of the Q terminal of the input / output control register 4 is supplied to the input / output I / O 3 and the operation mode of the input / output I / O 3 is determined according to the logical value of the output of the Q terminal.

  Further, the write inhibit circuit 10 includes an AND circuit 5 that receives the input / output control register write signal 12 at one input terminal, and a flip-flop (hereinafter referred to as “FF”) 6 that uses the output of the AND circuit 5 as a data capture signal. The buffer 7 receives the output of the FF 6 as an input and outputs it to the other input terminal of the AND circuit 5.

  Then, in response to the second and subsequent input / output control register write signal 12 input to the write inhibit circuit 10, the write inhibit circuit 10 sends the input / output control register write signal 12 to the input / output control register 4. Since the transmission of the buffer signal is suppressed, the operation mode control circuit 20 maintains the first operation mode setting value latched in the input / output control register 4 after initialization.

  Therefore, since the first operation mode setting value latched in the input / output control register 4 determines the operation mode of the input / output I / O 3, the output data register write signal 11 output from the write pulse generator 1 is received. The data from the data bus 14 latched in the output data register 2 is set by the first input / output control register write signal 12, and thereafter, the input / output does not change due to microcomputer runaway or noise in the microcomputer. There is an effect that the data is output according to the operation mode of I / O3.

  In the above description, it is assumed that the write pulse generation unit 1 generates a pulse signal. However, even if the signal changes in state, the write suppression circuit 10 does not receive the first input from the write pulse generation unit 1. If a pulse signal is generated only from the output control register write signal 12, only the first write is performed in the input / output control register 4, and the operation mode control circuit 20 is similarly initialized. It is possible to maintain the first operation mode setting value later.

  Here, in order to clarify the operation of the write inhibit circuit 10, a description will be given below with reference to FIG.

  First, when the reset signal 15 is input to the R terminal, the FF 6 is reset, and the FF 6 outputs “0” from the Q terminal. Here, the reset signal 15 is a signal for resetting the entire circuit of the system or microcomputer including the operation mode control circuit 20. As a result, the buffer 7 outputs “1”, the AND circuit 5 receives the output signal “1” of the buffer 7 at one terminal, and the AND circuit 5 is in a state of passing the signal from the other terminal.

  Next, when the input / output control register write signal 12 as a pulse signal is input to the other terminal of the AND circuit 5 and a pulse signal is transmitted from the output of the AND circuit 5 to the CK terminal of the FF 6, the D terminal is always supplied to the D terminal. Since the VCC power supply 9, that is, the signal of the logical value “1” is input, the FF 6 outputs “1” from the Q terminal. On the other hand, the output of the AND circuit 5 is also transmitted to the input / output control register as the write inhibit signal 10, and takes in data from the data bus 14 and latches the data.

  Next, the output “1” of the Q terminal of the FF 6 is input to the buffer 7, and the output of the buffer 7 is inverted to “0”. The output of the buffer 7 is input to one terminal of the AND circuit 5 to block the second input / output control register write signal 12. At this stage, the output states of the buffer 7, the AND circuit 5, and the FF 6 are maintained until the next reset signal 15 is received, so that the second and subsequent input / output control register write signals 12 are input to the input / output control register 4. On the other hand, it has no effect.

  That is, the write inhibit circuit 10 generates a pulse signal in response to the input / output control register write signal, but the outputs of the FF 6 and the buffer 7 are latched by the input / output control register write signal 12, so that The generation of pulses in the write inhibit circuit 10 is inhibited.

  According to the write inhibit circuit 10 and the operation mode control circuit 20 according to the third embodiment shown in FIG. 6, the write inhibit circuit 10 causes the input / output control register 4 to respond to the first input / output control register write signal. Since the set set value is maintained even if there is a microcomputer runaway or internal noise, there is an effect that the operation mode is not changed by an unintended software instruction.

  In the above description, the operation mode related to the input / output I / O has been described as an example. However, the input / output control register 4 is the operation mode control register, and the input / output control register write signal 12 is the operation mode control register. In the case of an embedded signal, the operation mode control circuit 20 and the write inhibit circuit 10 can also control a general operation mode, and have the same effect as described above.

(Fourth embodiment)
The fourth embodiment will be described with reference to FIGS. 8 and 9. In the fourth embodiment, the operation mode control circuit of the second embodiment is described in more detail.

  First, FIG. 8 shows an operation mode control circuit 130 including a write inhibit circuit 120, an output data register 102 and input / output I / O 103 controlled by the operation mode control circuit 130, and output signals from the input / output I / O 103. Represents a terminal 113 from which is output. Here, the output data register 102 and the input / output I / O 103 have the same functions as the corresponding output data register 2 and input / output I / O 3 in the third embodiment of FIG.

  On the other hand, in the third embodiment of FIG. 6, the write inhibit circuit 10 permits writing of the operation mode setting value of the input / output I / O 3 to the input / output register 4 only once after initialization. In contrast, in the second embodiment of FIG. 5, the write inhibit circuit 120 causes the input register 104 when the write inhibit circuit 120 receives two or more consecutive decodes from the write pulse generator 101. Is different in that writing of the setting value of the operation mode of the input / output I / O 3 is permitted.

  Further, the operation mode control circuit 130 includes a write pulse generation unit 101, a write inhibit circuit 120 that receives the input / output control register write signal 122 from the write pulse generation unit 101 and generates a pulse signal, and the write The input / output control register 104 is configured to receive a pulse signal from the inhibition circuit 120 and latch data from the data bus 124. Further, the write pulse generator 101 supplies output data to the output data register 102 through the data bus 124, and supplies the output data register write signal 121 to the output data register 102 to latch the output data. The output of the Q terminal of the input / output control register 104 is supplied to the input / output I / O 103, and the operation mode of the input / output I / O 103 is determined according to the logical value of the output of the Q terminal.

  Further, when receiving data “55” or data “AA” from the data bus 124, the write inhibit circuit 120 corresponds to the decoder 105 that generates a decode signal corresponding to each data and the data “AA”. The AND circuit 106 that receives the decode signal as one input, the flip-flop (hereinafter referred to as “FF”) 107 that receives the output of the AND circuit 106 by the input / output control register write signal 122, and the output and data “55” of the FF 107 The AND circuit 108 that receives the corresponding decode signal as an input, the FF 109 that receives the output of the AND circuit 108 by the input / output control register write signal 122, the output of the FF 109 as an input, and one input of the AND circuit 106 The buffer 110 to output and the write inhibit signal 123 that is the output of the FF 109 are Input from square pin, output control register write signals 122 and an AND circuit 111. inputted from the other terminal.

  Then, by successively decoding with the data “55” and the data “AA”, the input / output control register write signal 122 is received from the write pulse generation unit 101, and the write inhibition to the AND circuit 111 as a pass permission signal. The signal 123 is generated, and the AND circuit 111 outputs a signal obtained by buffering the input / output control register write signal 122. In the input / output control register 104, a value corresponding to the operation mode of the input / output I / O 103 is set.

  On the other hand, when the decoding by the data “55” and the data “AA” is completed, when the write inhibit circuit 120 receives the input / output control register write signal 122, the write inhibit signal is sent to the AND circuit 111 as a passage inhibit signal. 123 is generated to prevent the input / output control register write signal 122 from being transmitted to the input / output control register 104. As a result, the operation mode control circuit 130 can maintain the first operation mode setting value after initialization.

  In the above description, it is assumed that the input / output control register write signal 122 is a pulse signal, but a plurality of decode signals (here, data “55” and data “AA”) are continuously input. Only when the write inhibit circuit 120 generates a pulse signal from the input / output control register write signal 122 output from the write pulse generator 101, the operation mode is written to the input / output control register 104. Therefore, the operation mode control circuit 130 can similarly maintain the operation mode set value.

  Therefore, the write inhibit circuit 120 continuously decodes the data latched in the output data register 102 in response to the output data register write signal 121 output from the write pulse generator 101, and the input / output control register write signal. There is an effect that the data is output from the input / output I / O 103 in accordance with the operation mode set by 122.

  In addition, even if the microcomputer runs out of control, there is a low probability that continuous decoding by specific data will occur. Therefore, the operation mode set by the I / O control register write signal 122 is not changed by the microcomputer running out of control. .

  Here, in order to clarify the operation of the write inhibit circuit 120, it will be described below with reference to FIG.

  First, the FF 107 and the FF 109 are reset by the reset signal 112, and the output from the output terminal Q of each FF is set to “0”. Next, in response to the data “AA”, the decoder 105 generates a signal “1” corresponding to the data “AA”. Next, the AND circuit 106 receives the output signal “1” of the buffer 110 and the signal “1” corresponding to the data “AA”, and the AND circuit 106 outputs the signal “1”. Next, the FF 107 receives and latches the output “1” of the AND circuit 106 in response to the input / output control register write signal 122 which is a pulse signal, and outputs “1” from the Q terminal.

  Next, when the decoding by the data “AA” is canceled and the decoder 105 receives the decoding by the data “55”, the AND circuit 108 outputs the signal “1” corresponding to the output “1” from the FF 107 and the data “55”. In response, a signal “1” is output. Next, the FF 109 takes in the output “1” of the AND circuit 108 by the input / output control register write signal 122 and outputs “1” as the write inhibit signal 123. As a result, the AND circuit 111 buffers and outputs the input / output control register write signal 122 to the input / output control register 104, and the input / output control register 104 latches data from the data bus 124.

  Thereafter, when the decoding of the data “55” is stopped, a “0” signal is output from the decoder 105. When the input / output control register write signal 122 is output from the write pulse generation unit 101 in this state, the FF 109 The “0” signal is output as the write inhibit signal 123. As a result, since the write inhibit signal 123 of the “0” signal is inputted to one input terminal of the AND circuit 111, the AND circuit 111 buffers and outputs the input / output control register write signal 122. Is suppressed.

  That is, only when the write inhibit circuit 120 receives continuous decode with different decode signals, the write inhibit circuit 120 buffers the input / output control register write signal 122 and outputs it to the input / output control register 104. When not performed or when continuous decoding is not performed, the input / output control register write signal 122 is buffered and not output to the input / output control register 104.

  According to the write inhibit circuit 120 and the operation mode control circuit 130 according to the fourth embodiment of FIG. 8, even if the microcomputer runs out of control, the probability of continuously outputting “55” and “AA” data is Since it is low, the operation mode of the input / output I / O set at the time of continuous decoding is maintained. Therefore, the operation mode is not changed by the output of the control register write signal 122 and the decode signal due to an unintended software instruction or internal noise.

  In the above description, the operation mode setting related to input / output I / O has been described as an example. However, the input / output control register 104 is an operation mode control register, and the input / output control register write signal 122 is an operation mode control register. In the case of an embedded signal, the operation mode control circuit 130 and the write inhibit circuit 120 can also control a general operation mode, and have the same effects as described above.

(Fifth embodiment)
The fifth embodiment will be described with reference to FIGS. 10 and 11. The fifth embodiment describes the operation mode circuit of the first embodiment in more detail.

  First, FIG. 10 shows an operation mode control circuit 230 including a write inhibit circuit 220, an output data register 204 and input / output I / O 205 controlled by the operation mode control circuit 230, a selector 203, and an input / output I / O 205. 2 represents a terminal 212 from which an output signal is output and a timer circuit. Here, the timer 202 outputs a clock signal having a fixed period. The selector 203 is a circuit for selecting an output signal from the timer 202 or an output signal from the output data register 204. When the logical value “1” is set, the selector 203 selects the output signal from the timer 202, and the logical value When “0” is set, an output signal from the output data register 204 is selected. Further, the output data register 204 is a circuit that receives and latches output data from the write pulse generation circuit 201 through the data bus 221.

  In the third embodiment of FIG. 6, the write inhibit circuit 10 permits writing of the operation mode set value of the input / output I / O 3 to the input / output register 4 only once after initialization. On the other hand, in the fifth embodiment of FIG. 10, the write inhibit circuit 220 sends a predetermined data signal to the write inhibit circuit 220 after initialization and is used by the selector 203 only during the period until it is latched. This is different in that writing of the selected set value of the peripheral selection register 207 is permitted.

  The operation mode control circuit 230 includes a write pulse generation unit 201, a write suppression circuit 220 that receives the peripheral selection register write signal 223 from the write pulse generation unit 201 and generates a write suppression signal 224, The input / output control register write signal 222 from the write pulse generator 201 is received, the input / output control register 208 that latches data on the data bus 221 and the write inhibit signal 224 from the write inhibit circuit 220 are received, Peripheral selection register 207 that latches data on data bus 221; OR 206 that receives an output from the Q terminal of input / output control register 208 and an output from the Q terminal of peripheral selection register 207 at the input terminal and takes a logical sum; It is composed of

  The output from the Q terminal of the peripheral selection register 207 is supplied to the selector 203 and functions as a selection signal. Here, when the selection signal is “1”, the signal from the timer 202 is selected, and the logical value equivalent to the logical value of the selection signal is also output from the OR 206. Therefore, the input / output I / O 205 It operates in the operation mode corresponding to the logical value “1”. On the other hand, when the selection signal is “0”, the signal from the output data register 204 is selected, but the OR 206 outputs a logic signal similar to the output from the Q terminal of the input / output control register. The output I / O 205 operates in an operation mode corresponding to the output from the Q terminal of the input / output control register.

  The write inhibit circuit 220 receives a data from the data bus 221 and a flip-flop (hereinafter referred to as “FF”) that latches the output of the buffer 210 with a peripheral selection register write signal 223 from the write pulse generator 201. 209 and an AND circuit 211 that receives the peripheral selection register write signal 223 from the write pulse generation unit 201 and the output signal from the FF 209 as inputs. Here, the data bus 221 is a data bus including at least a signal for the output data register 204, a signal for the peripheral selection register 207, a signal for the input / output control register 208, and a signal for the FF 209.

  Then, by inputting the reset signal 213 to the R terminal, the XQ terminal of the FF 209 of the write inhibit circuit 220 is set to “1”, and then the signal for the FF 209 of the data bus 221 is set to “0”. As a result of the FF 209 being latched by the peripheral selection register write signal 223, “0” set as the signal for the FF 209 of the data bus 221 until the XQ terminal of the FF 209 changes to “0” (hereinafter “AND”). The AND circuit 211 outputs the peripheral selection register write signal 223 as the write inhibition signal 224 as it is. In other words, after the XQ terminal of the FF 209 of the write inhibit circuit 220 is set to “1” by the reset signal, the peripheral selection register is set while the “1” signal is set as the signal for the FF 209 of the data bus 221. Each time the write signal 223 is generated, the peripheral select register 207 has an effect of latching a signal for the peripheral select register 207 of the data bus 221 by the write inhibit signal 224. On the other hand, during the period other than the AND circuit 211 open period, “0” is set to the XQ terminal of the FF 209. As a result, the write inhibit signal 224, which is the output signal of the AND circuit 211, becomes a fixed signal of logical value “0”. The latch of the selection register 207 is suppressed.

  Here, in order to clarify the operation of the write inhibit circuit 220, it will be described below with reference to FIG.

  First, by inputting the reset signal 213 to the R terminal, the FF 209 is reset, and the XQ terminal of the FF 209 is set to “1”. Next, when the peripheral selection register write signal 223 is generated from the write pulse generator 201, the AND circuit 211 outputs the peripheral selection register write signal 223 as it is as the write inhibition signal 224, and the FF 209 outputs the write inhibition signal 224. In response, the signal for the FF 209 of the data bus 221 is latched.

  At this time, when the data signal for the FF 209 of the data bus 221 is set to “1”, the XQ terminal of the FF 209 maintains “1”. Therefore, the AND circuit 211 also passes the next peripheral selection register write signal 223 as the write inhibit signal 224.

  However, when the data signal for the FF 209 of the data bus 221 is set to “0”, the XQ terminal of the FF 209 changes to “0”. As a result, the AND circuit 211 outputs a fixed “0” signal as the write inhibit signal 224, so that writing to the peripheral selection register 207 and the FF 209 is inhibited.

  Further, when the output of the XQ terminal of the FF 209 is “0”, the output of the AND circuit 211 is maintained at “0”. Therefore, unless the FF 209 is reset by the reset signal 213, writing to the peripheral selection register 207 and the FF 209 is performed. The deterrence state is maintained.

  In the above description, it is assumed that the peripheral selection register write signal 223 is a pulse signal. However, even if the peripheral selection register write signal 223 is a state change signal, the write suppression circuit 220 generates a write pulse. If the peripheral selection register write signal 223 from the unit 201 is received and a pulse signal is generated, the same effect can be obtained. In order to generate a pulse signal, it is desirable to include a circuit that receives a state change signal and generates a pulse immediately after the AND circuit 211 in the write inhibit circuit 220.

  Therefore, the operation mode control circuit 230 outputs the setting value of the peripheral selection register 207 to the selector 203 and the setting value of the input / output control register 208 set by the input / output control register write signal 224 to the input / output I / O 205. However, after the write inhibition circuit 220 inhibits the write signal to the peripheral selection register 207, the output is fixed.

  As a result, when the output of the peripheral selection register 207 is “0”, the selector 203 sets not the output from the timer 202 but the output of the output data register 204 according to the set value of the input / output control register 208. There is an effect that the data is output from the input / output I / O 205 according to the operation mode.

  Further, since the output of the AND circuit 211 is fixed to “0” because the set value of the peripheral selection register 207 is maintained even if the microcomputer runs away or internal noise, the output from the timer 202 is always output. The output of the output data register 213 is output.

  In the above description, the operation mode setting related to input / output I / O has been described as an example. However, the input / output control register 208 is an operation mode control register, and the input / output control register write signal 222 is an operation mode control register. In the case of an embedded signal, the operation mode control circuit 230 and the write inhibit circuit 220 can also control a general operation mode, and have the same effect as described above.

(Sixth embodiment)
The sixth embodiment will be described with reference to FIGS. 12 and 13. In the sixth embodiment, the operation mode control circuit of the second embodiment is described in more detail.

  First, FIG. 12 shows an operation mode control circuit 320 including a write inhibit circuit 310, an output data register 302 and input / output I / O 304 controlled by the operation mode control circuit 320, and output signals from the input / output I / O 304. An output terminal 309 is shown. Here, the output data register 302 and the input / output I / O 304 have the same functions as the corresponding output data register 2 and input / output I / O 3 in the third embodiment of FIG.

  On the other hand, in the third embodiment of FIG. 6, the write inhibit circuit 10 writes the operation mode setting value of the input / output I / O 3 to the input / output control register 4 only once after initialization. On the other hand, in the sixth embodiment of FIG. 12, the write inhibit circuit 310 is in the execution state in the initialization routine while the predetermined initialization routine is being executed, to the input / output control register 303. This is different in that writing of the setting value of the operation mode of the input / output I / O 304 is permitted.

  Further, the operation mode control circuit 320 receives the write pulse generation unit 301 and the input / output control register write signal 313 from the write pulse generation unit 301, and outputs an initialization program as to whether to output as a buffer or to suppress it. The write inhibit circuit 310 is determined according to the execution state, and the input / output control register 303 receives the buffer signal of the input / output control register write signal 313 and latches data from the data bus 317.

  The write inhibition circuit 310 according to the sixth embodiment includes an initialization routine execution display circuit (hereinafter referred to as “display circuit”) 305 that generates an initialization routine state signal 311 indicating that the initialization program is being read. An execution state in an initialization routine that generates a state signal in a predetermined region (hereinafter referred to as “predetermined state signal”) 312 of the initialization routine indicating that the sequence currently being executed of the initialization program is after the predetermined sequence Determination circuit (hereinafter referred to as “determination circuit”) 306, an AND circuit 316 that receives the predetermined internal state signal and the initialization routine state signal, and a set / reset flip-flop (hereinafter referred to as “the determination circuit”) that latches the output of the AND circuit 316. SRFF ") 307 and one input terminal accepts the input / output control register write signal, the other From the input terminal and an AND circuit 308 for outputting a write inhibit signal it receives the output signal from the SRFF307.

  If the sequence currently being executed of the initialization program is before the predetermined sequence, the write inhibit circuit 310 buffers and passes the input / output control register write signal 313 output from the write pulse generation unit 301. Thus, when the sequence currently being executed of the initialization program is a sequence after a predetermined sequence, there is an effect of blocking the passage of the input / output write signal.

  Further, the operation mode control circuit 320 prevents the input / output control register signal from the write pulse generation unit 301 from being suppressed after the predetermined sequence of the initialization program, so that even if the microcomputer runs out of control. There is an effect of maintaining the set value relating to the operation mode set in the input / output control register 303.

  As a result, there is an effect that the input / output I / O 304 outputs the data fetched into the output data register 302 according to the operation mode set by the operation mode control circuit 320.

  Here, in order to clarify the operation of the write inhibit circuit 310, it will be described below with reference to FIG.

  First, the output of the output terminal Q of the SRFF 307 is set to “1” by the reset signal 318. Here, the reset signal means a signal for resetting a system or microcomputer circuit including the operation mode control circuit 320 and the write inhibit circuit 310.

  Next, when an initialization routine for initializing the microcomputer is started, an initialization routine status signal 311 whose logical value is “1” is output from the display circuit 305. On the other hand, from the determination circuit 306, the logical value is initially “1”, but when the initialization routine proceeds and the sequence of the initialization routine goes out of a predetermined area, the logical value changes to “0”. A predetermined internal state signal 312 is output. As a result, the AND circuit 316 outputs “1” after the initialization routine is started and within the predetermined area of the initialization routine. However, when the predetermined area is exceeded, the AND circuit 316 outputs “0”. Output.

  Next, when the output of the AND circuit 316 changes from “0” to “1” and further changes from “1” to “0”, the SRFF 307 changes the output terminal Q from “1” to “0”.

  Therefore, when the input / output control register write signal 313 is output from the write pulse generation unit 301 after the initialization routine is started and within the predetermined area of the initialization routine, the input / output control register write is performed. The signal 313 is buffered by the AND circuit 308 and output to the input / output control register 303.

  On the other hand, when the initialization program is not executed and when the initialization routine is outside the predetermined area, the output terminal of the SRFF 307 is “0”, so the input / output control register write signal 313 is suppressed by the AND circuit 308. .

  According to the operation mode control circuit 320 and the write inhibit circuit 310 of FIG. 12, the initialization program is stored in the input / output control register 303 in the operation mode control circuit 320 during execution of a stage before a predetermined initialization routine. The set operation mode is caused by internal noise or microcomputer runaway because writing to the input / output control register 303 is inhibited by the write inhibiting circuit 310 that is not controlled by software other than the initialization program. It has the effect of not being changed by unintended software.

(Seventh embodiment)
The seventh embodiment will be described with reference to FIG.

  A microcomputer 400 according to the seventh embodiment includes a CPU 401 (central processing unit), a ROM (Read Only Memory) 405, a RAM (Random Access Memory) 404, a timer 403, a write inhibit circuit 402, an address Input / output control register & address register 406 for input / output I / O, input / output control register & control signal register 415 for control signal I / O, input / output control register & data register for data input / output I / O 409, address input / output I / O 1 (407), address input / output I / O 2 (408), data input / output I / O 410, control signal I / O 411, selector 417, and peripheral selection register 416 The write inhibit circuit 402 is a write inhibit circuit according to the first to fourth embodiments, and the write inhibit circuit A road 402, and the input and output registers, peripheral selection register constitutes the operation mode control circuit according to the third embodiment. A CPU (central processing unit) 401 functions as a write pulse generation unit in the first to fourth embodiments.

  Here, the peripheral functions such as the timer 403 in the microcomputer 400 and the input / output functions such as respective registers for storing control signals, data, and addresses necessary for input / output to / from the outside of the microcomputer are data or signals. When outputting to the outside of the microcomputer, the same input / output I / O may be shared. For example, FIG. 14 shows that a part of the address input / output I / O 1 (407) is shared with the output of the timer 403.

  In this case, the CPU (central processing unit) 401 sends a setting value indicating which function is output to the input / output I / O, sends a peripheral selection register write signal, and sends data through the data bus. Thus, in the peripheral selection register 416, which input / output I / O has what operation mode is set in the input / output control register in the same manner as the peripheral selection register 416. The selector 417 selects which function to output a signal from among a plurality of functions based on the signal output based on the setting value of the peripheral selection register 416, and based on the setting value of the input / output control register. With the output signal, the input / output I / O selects the output operation mode.

  Further, the write inhibit circuit 402 sets the values set in the peripheral selection register 416 and each input / output control register to a signal from the CPU (central processing unit) by the functions shown in the third to sixth embodiments. In response to this, it has a role of preventing rewriting by a method other than setting by a predetermined setting method.

  Therefore, according to the microcomputer 400 according to the seventh embodiment, the control register for determining the output attribute related to the important input / output I / O, such as the monitoring signal to the watchdog, in the write inhibiting circuit 402. Since the set value can be secured even if the microcomputer runs away, the microcomputer can be reliably dealt with when the microcomputer runs away. On the other hand, even during the normal operation of the microcomputer, it is output by the software command of the microcomputer. Depending on the output signal, the output attribute related to the input / output I / O does not change, so even if there is an error in the software instruction, it can be reliably determined whether or not the microcomputer is out of control. Therefore, when the microcomputer according to the fifth embodiment is used in the system, there is an effect that the system can be made highly safe.

(Eighth embodiment)
The eighth embodiment will be described with reference to FIG.

  The control system 500 according to the eighth embodiment includes a peripheral function circuit such as a timer 502, an output data register 503 related to a monitoring signal, an output from the peripheral function circuit such as the timer 502, or an output from the output data register 503. A selector 507 for selecting one of the outputs, an I / O buffer 508 for outputting the output from the selector 507, a monitoring signal output port 511 for outputting a monitoring signal, and a peripheral selection register 504 for controlling the selector 507 , An input / output control register 505 for controlling the input / output mode of the I / O buffer 508, a write inhibition circuit 506 for inhibiting data writing to the peripheral selection register 504 or the input / output control register 505, and a CPU 510 (central Processing device), RAM 516, ROM 517, reset circuit 509, my A microcomputer 501 comprising a reset signal receiving port 512 for receiving a reset signal for resetting the entire computer and a monitor signal 514 from the microcomputer 501 are received, and a reset signal 515 is generated when the signal is interrupted. At least a watch dog 513 is included. Here, the write inhibit circuit 506 is the write inhibit circuit of the first to fourth embodiments. The write inhibit circuit 506, the input / output control register 505, and the peripheral selection register 504 are the same as those in the fifth embodiment. The operation mode control circuit shown in the embodiment is configured.

  According to the control system 500 according to the eighth embodiment, the microcomputer 501 included in the control system 500 runs out of control for some reason while the control system 500 controls the apparatus incorporating the control system 500. When the monitoring signal output port 511 interrupts the monitoring signal output port 511, the watch dog 513 detects the interruption of the signal, the watch dog 513 generates a reset signal 515 for the microcomputer 501, and the microcomputer 501 Because it is reset, it can automatically recover from the runaway state. On the other hand, even during the normal operation of the control system 500, the output attribute related to the I / O buffer 508 of the microcomputer 501 does not change depending on the signal output by the software instruction of the microcomputer 501 in the control system. In addition, even if the monitoring signal output port with the watchdog has an error in the software instruction, the output from the output data register 503 for outputting the monitoring signal is not switched to the output of the timer 502. It can be reliably determined whether or not the computer 501 is running away. Therefore, there is an effect that the apparatus using the control system 500 according to the eighth embodiment can be a highly safe apparatus.

(Appendix 1)
A microcomputer that is reset by an external reset signal and performs processing by a control program,
An input / output circuit having a plurality of operation modes;
A control signal generator;
A control circuit;
With a deterrent circuit,
The control signal generation unit generates a write signal by an operation mode setting routine in the control program,
The control circuit sets an operation mode of the input / output circuit according to the write signal,
The inhibition circuit inhibits resetting the operation mode of the input / output circuit until it is reset by the external reset signal after the control circuit sets the operation mode,
The microcomputer according to claim 1, wherein the input / output circuit inputs / outputs a signal to / from the outside of the microcomputer according to an operation mode set by the control circuit.
According to the microcomputer according to appendix 1, the operation mode set by the control circuit can be set by the control signal generation unit based on the control program. However, after that, until the reset signal is reset, the operation mode cannot be reset by the write signal from the control signal generator or the write signal generated by the internal noise due to the action of the suppression circuit. There is. As a result, since the operation mode of the input / output circuit is maintained, when the input / output circuit outputs a monitoring signal to the watchdog timer, the microcomputer status, for example, normal, runaway, etc. There is an effect of outputting a monitoring signal reflecting the state as it is.
(Appendix 2)
A write inhibit circuit for generating a buffer signal for the first output signal only from the first first output signal from the control signal generator after initialization, and the write inhibit circuit; A control circuit for holding a second output signal from the control signal generator in response to the buffer signal from
The control circuit sets an operation mode of an external signal input / output control circuit based on the held second output signal.
According to the operation mode control circuit according to appendix 2, the signal held in the control circuit cannot be rewritten by the microcomputer itself due to the action of the write inhibit circuit, so that the microcomputer state (for example, in the runaway state) Regardless of this, the operation mode of the circuit that controls input / output of signals to / from the outside is effectively maintained.
(Appendix 3)
An operation mode control circuit described in appendix 2,
The operation mode control circuit according to claim 1, wherein the first output signal is a pulse signal.
(Appendix 4)
An operation mode control circuit described in appendix 2,
The write inhibit circuit is
Buffer means for outputting a buffer signal of the first output signal or a fixed logic signal in response to the first output signal from the control signal generator;
Holding means for holding by the first output signal from the control signal generator and outputting a status signal indicating a holding state;
The buffer means further has an input terminal for receiving the state signal from the holding means, and outputs the fixed logic value signal when the state signal indicates the holding state, and holds the holding signal. An operation mode control circuit that outputs the buffer signal when a state is not indicated.
The operation mode control circuit according to appendix 4 also has the same effect as the operation mode control circuit according to appendix 2.
(Appendix 5)
An operation mode control circuit described in appendix 2,
The write inhibit circuit is
An AND circuit that receives the first output signal from the control signal generator at one of the inputs;
A flip-flop circuit that outputs a signal of a logical value “1” when an output of the AND circuit is connected to a holding terminal and a pulse signal is input to the holding terminal;
In response to a signal from the flip-flop circuit, a buffer circuit that outputs a signal obtained by inverting a logical value to the other input of the AND circuit,
The AND circuit takes an AND of the first output signal from the control signal generator and a signal obtained by inverting the logic value.
(Appendix 6)
At least the operation mode control circuit described in any one of appendix 2 to appendix 5,
The input / output control circuit for controlling input / output of signals with the outside;
A data register circuit for holding a data signal from the operation mode control circuit by a data register write signal from the operation mode control circuit;
The microcomputer according to claim 1, wherein the data register circuit outputs a signal corresponding to the data signal to the input / output control circuit.
In the microcomputer according to appendix 6, since the signal for setting the operation mode of the input / output control circuit held in the control circuit cannot be rewritten by the microcomputer itself by the action of the write inhibit circuit. The operation mode of the circuit that controls the input / output of signals to / from the outside is maintained regardless of the state (for example, even in a runaway state).
(Appendix 7)
A control signal generator;
A document that generates a buffer signal obtained by buffering the first output signal from the control signal generator only when the first decode signal and the second decode signal from the control signal generator are successively received. A deterrence circuit,
A control circuit for holding a second signal from the control signal generator in response to the buffer signal from the write inhibit circuit;
The control circuit sets an operation mode of an external signal input / output control circuit based on the held second output signal.
According to the operation mode control circuit according to appendix 7, the signal held in the control circuit has a low probability of continuous decoding by the code designated to the write inhibit circuit. As a result of the possibility of rewriting depending on the computer itself, the operation mode of the circuit that controls the input / output of signals to / from the outside is maintained regardless of the state of the microcomputer (for example, even in a runaway state). There is an effect.
(Appendix 8)
An operation mode control circuit according to appendix 7,
The operation mode control circuit according to claim 1, wherein the first output signal is a pulse signal.
(Appendix 9)
A control signal generator;
A write inhibit circuit that generates a buffer signal obtained by buffering the first output signal from the control signal generator only when a predetermined plurality of decode signals are continuously received from the control signal generator;
A control circuit for holding a second signal from the control signal generator in response to the buffer signal from the write inhibit circuit;
The control circuit sets an operation mode of an external signal input / output control circuit based on the held second output signal.
(Appendix 10)
An operation mode control circuit according to appendix 7,
The write inhibit circuit is
A decoder circuit for outputting a first selection state signal and a second selection state signal in response to the first decode signal and the second decode signal from the control signal generator;
A first AND circuit that receives the first selection state signal at one input terminal;
A second AND circuit receiving the second selection state signal at one input terminal;
A third AND circuit;
In response to the first output signal from the control signal generator, the output signal of the first AND circuit is held, and the first data is output to the other input terminal of the second AND circuit. A first flip-flop circuit that
In response to the first output signal from the control signal generator, the output signal of the second AND circuit is held, and the second data is output to one input terminal of the third AND circuit. A second flip-flop circuit that
A buffer circuit that outputs a third output signal obtained by logically inverting the second data to the other input of the first AND circuit;
The first AND circuit ANDs the first selection state signal and the third output signal,
The second AND circuit ANDs the second selection state signal and the first data,
The third AND circuit ANDs the second data and the first output signal,
The control circuit includes a third flip-flop circuit that holds the second output signal from the control signal generator in response to an output signal from the third AND circuit. Operation mode control circuit.
Note that Supplementary Note 10 has the same effect as Supplementary Note 7.
(Appendix 11)
At least the operation mode control circuit described in any one of appendix 7 to appendix 10;
The input / output control circuit for controlling input / output of signals with the outside;
A data register circuit for holding a data signal from the operation mode control circuit by a data register write signal from the operation mode control circuit;
The microcomputer according to claim 1, wherein the data register circuit outputs a signal corresponding to the data signal to the input / output control circuit.
In the microcomputer according to appendix 11, the signal that sets the operation mode of the input / output control circuit held in the control circuit cannot be rewritten by the microcomputer itself by the action of the write inhibit circuit. The operation mode of the circuit that controls the input / output of signals to / from the outside is maintained regardless of the state (for example, even in a runaway state).
(Appendix 12)
At least a control signal generator;
In response to the first output signal from the control signal generator, the second output signal from the control signal generator is held and a write signal is generated according to the logical value of the held signal A control circuit for holding a third output signal from the control signal generator in response to the write signal and generating a control signal according to the logical value of the held signal in response to the write signal;
One of the write signals corresponding to the logic value of the second output signal from the control signal generator is a signal whose logic value is fixed, and the other is the first output from the control signal generator. A buffer signal of the signal,
The operation mode control circuit, wherein the control signal is supplied to a selection circuit that selects a signal generation circuit that transmits a signal to the outside from a plurality of signal generation circuits including at least a data register circuit.
According to the operation mode control circuit of Supplementary Note 12, when there are a plurality of peripheral circuits connected to one input / output control circuit through a selection circuit in the microcomputer, the operation of the write inhibit circuit causes a predetermined After setting the selection signal to the selection circuit in the state, since the setting cannot be rewritten by the computer itself, the setting of the selection circuit is not limited regardless of the state of the microcomputer (for example, even in a runaway state). The effect is maintained.
(Appendix 13)
At least a control signal generator;
In response to the first output signal from the control signal generator, the second output signal from the control signal generator is held and a write signal is generated according to the logical value of the held signal A first control circuit for holding a third output signal from the control signal generator and generating a first control signal corresponding to the logical value of the held signal in response to the write signal; When,
In response to the fourth output signal from the control signal generation unit, the fifth output signal from the control signal generation unit is held, and a second control signal corresponding to the logical value of the held signal is generated. A second control circuit;
An OR circuit that takes a logical sum of the first control signal and the second control signal and outputs an operation mode setting signal as a result;
One of the write signals corresponding to the logic value of the second output signal from the control signal generator is a signal whose logic value is fixed, and the other is the first output from the control signal generator. A buffer signal of the signal,
The first control signal is supplied to a selection circuit that selects a signal generation circuit for transmitting a signal to the outside from a plurality of signal generation circuits including at least a data register circuit.
The operation mode control circuit is characterized in that the operation mode setting signal is supplied to a circuit for controlling an input / output signal to / from the outside in order to set an operation mode of the circuit.
(Appendix 14)
An operation mode control circuit described in appendix 12,
The write inhibit circuit is
Buffer means for outputting a buffer signal of the first output signal or a fixed signal in response to the first output signal from the control signal generator;
Holding means for holding the second output signal from the control signal generator in response to the buffer signal and outputting a logic signal corresponding to the logic value of the second output signal;
The buffer means receives a logic signal from the holding means, outputs the fixed signal according to one logic value, and outputs the buffer signal according to the other logic value. circuit.
The operation mode control circuit according to Supplementary Note 14 has the same effect as the operation mode control circuit according to Supplementary Note 12.
(Appendix 15)
An operation mode control circuit described in appendix 12,
The write inhibit circuit is
An AND circuit that receives the first output signal from the control signal generator at one input terminal;
A buffer circuit that outputs a buffer signal obtained by logically inverting the second output signal from the control signal generator;
A buffer circuit that receives the buffer signal at a data terminal, holds the buffer signal in response to an output of the AND circuit, and generates a logic signal corresponding to a logic value of the buffer signal;
The AND circuit performs an AND operation on the logic signal and the first output signal.
(Appendix 16)
At least the operation mode control circuit described in appendix 12 to appendix 15,
An input / output control circuit for controlling input / output of signals with the outside;
A data register circuit that holds a data signal from the operation mode control circuit in response to a data register write signal from the operation mode control circuit;
A timer circuit capable of generating one or more periodic clocks;
A selection circuit that selects the data register circuit or the timer circuit in response to the first control signal from the operation mode control circuit;
The microcomputer according to claim 1, wherein the data register circuit outputs a signal corresponding to the data signal to the input / output control circuit.
When the microcomputer according to appendix 16 includes a data register circuit and a timer circuit for controlling input / output signals in the microcomputer, the operation mode control circuit supplies the selection circuit with the data register circuit and timer circuit. The set value can be rewritten by the microcomputer itself by the action of the write inhibit circuit. Therefore, there is an effect that the output of the data register circuit is always connected to the input / output control circuit regardless of the state of the microcomputer (for example, even in a runaway state).
(Appendix 17)
A control signal generator;
After executing the initialization program, when a stage before a predetermined initialization routine is being executed, a buffer signal obtained by buffering the first output signal from the control signal generator is output, and otherwise, A write inhibit circuit for outputting a fixed signal;
A control circuit for holding a second output signal from the control signal generator in response to an output signal from the write inhibit circuit;
The control circuit sets an operation mode of an external input / output control circuit in accordance with the held second output signal.
According to the operation mode control circuit of Supplementary Note 17, since the signal held in the control circuit during the initialization routine cannot be rewritten by the microcomputer itself by the action of the write inhibit circuit, the microcomputer state ( For example, the operation mode of the circuit that controls the input / output of signals to / from the outside is maintained regardless of whether it is in a runaway state.
(Appendix 18)
An operation mode control circuit described in appendix 17,
The operation mode control circuit according to claim 1, wherein the first output signal from the control signal generator is a pulse signal.
(Appendix 19)
An operation mode control circuit described in appendix 17,
The write inhibit circuit is
A first state signal generating circuit for generating a first state signal indicating that the initialization program is being executed;
A second state signal generating circuit for generating a second state signal indicating that a stage before a predetermined initialization routine is being executed;
A first AND circuit that ANDs the first state signal and the second state signal;
In the reset state, the logic value “1” is output, the output from the first AND circuit is received, and the logic value “0” is output when the output from the first AND circuit is a predetermined signal. A set / reset flip flip circuit,
An operation mode control circuit comprising: a second AND circuit that performs an AND operation on the first signal from the control signal generator and an output signal of the set / reset flip-flip circuit.
(Appendix 20)
At least the operation mode control circuit described in any one of appendix 17 to appendix 19,
The input / output control circuit for controlling input / output of signals with the outside;
A data register circuit for holding a data signal from the operation mode control circuit by a data register write signal from the operation mode control circuit;
The microcomputer according to claim 1, wherein the data register circuit outputs a signal corresponding to the data signal to the input / output control circuit.
In the microcomputer according to appendix 20, since the signal for setting the operation mode of the input / output control circuit held in the control circuit cannot be rewritten by the microcomputer itself by the action of the write inhibit circuit, the microcomputer The operation mode of the circuit that controls the input / output of signals to / from the outside is maintained regardless of the state (for example, even in a runaway state).
(Appendix 21)
And at least a watchdog and the microcomputer described in Appendix 6, Appendix 11, Appendix 16 or Appendix 20,
The microcomputer further includes a monitoring signal output port for outputting a monitoring signal to the watchdog, a reset signal receiving port for receiving a first reset signal from the watchdog, and the microcomputer according to the first reset signal. A reset circuit for generating a second reset signal to the predetermined circuit of
The output from the input / output control circuit is the monitoring signal to the watchdog,
The control system, wherein the watch dog outputs the first reset signal to the microcomputer.
According to the control system described in appendix 21, since the monitoring signal output from the microcomputer to the watchdog is always generated due to the operation of the microcomputer main body, the interruption or continuation of the generation of the monitoring signal is always performed. There is an effect that reflects the state of the microcomputer body. Therefore, there is an effect that monitoring by the watchdog of the microcomputer is properly performed, the microcomputer is prevented from runaway reliably, and the malfunction of the entire control system is prevented. Further, when the microcomputer is normal, the monitoring signal is not output to the watch dock due to internal noise of the microcomputer (including a case induced from the outside).

  An operation mode control circuit of a microcomputer according to the present invention sets an input / output register for determining an input / output attribute of an I / O buffer and a peripheral selection register for selecting a peripheral function by a predetermined setting method. There is an effect of inhibiting writing so as not to be rewritten by other methods, and the operation mode set in the operation mode setting period is not reset regardless of the state of the microcomputer until it is reset by an external reset signal. The resetting of the operation mode is prevented.

Therefore, the setting of the I / O buffer of the port that outputs the monitoring signal for the watchdog timer and the setting of connecting the monitoring signal generation circuit for the watchdog timer to the I / O buffer are performed by the microcomputer itself for a predetermined period. Since the resetting is not performed, the monitoring signal indicating the microcomputer state can be continuously sent to the watchdog timer regardless of the state of the microcomputer.
Therefore, the watchdog timer can continue to monitor the state of the microcomputer (for example, a runaway state) with high reliability.

  As a result, according to the present invention, it is possible to provide an operation mode control circuit that prevents rewriting of the operation mode, a microcomputer that can operate stably, and a control system that uses the microcomputer.

1 Write Pulse Generation Unit 2 Output Data Register 3 Input / Output I / O
4 I / O control register 5 AND circuit 6 FF
7 buffer 8 terminal 9 VCC power supply 10 write inhibit circuit 11 output data register write signal 12 input / output control register write signal 13 write inhibit signal 14 data bus 15 reset signal 20 operation mode control circuit 101 write pulse generator 102 output Data register 103 Input / output I / O
104 I / O control register 105 Decoder 106 AND circuit 107 FF
108 AND circuit 109 FF
110 Buffer 111 AND circuit 112 Reset signal 113 Terminal 120 Write inhibit circuit 121 Output data register write signal 122 Input / output data register write signal 124 Data bus 130 Operation mode control circuit 201 Write pulse generator 202 Timer 203 Selector 204 Output data Register 205 I / O I / O
206 OR 207 Peripheral selection register 208 I / O control register 209 FF
210 Buffer 211 AND circuit 212 Terminal 213 Reset signal 220 Write inhibit circuit 221 Data bus 222 Input / output control register write signal 223 Peripheral selection register write signal 225 Output data register write signal 230 Operation mode control circuit 301 Write pulse generator 302 Output data register 303 Input / output control register 304 Input / output I / O
305 Initialization routine execution display circuit 306 Execution state determination circuit in initialization routine 307 SRFF
308 AND circuit 309 Terminal 310 Write inhibit circuit 311 Initialization routine state signal 312 Initial state routine predetermined state signal 313 Input / output control register write signal 314 Output data register write signal 316 AND circuit 317 Data bus 318 Reset signal 320 Operation Mode Control Circuit 400 Microcomputer 401 CPU (Central Processing Unit)
402 Write inhibit circuit 403 Timer 404 RAM
405 ROM
406 Input / output control register & address register 407 Address input / output I / O1
408 Address input / output I / O2
409 Input / output control register & data register 410 Data input / output I / O
411 Control signal I / O
413 Control signal 414 Data bus 415 Input / output control register & control signal register 416 Peripheral selection register 500 Control system 501 Microcomputer 502 Timer 503 Output data register 504 Peripheral selection register 505 Input / output control register 506 Write inhibit circuit 507 Selector 508 I / O buffer 509 Reset circuit 510 CPU (central processing unit)
511 Monitoring signal output port 512 Reset signal receiving port 513 Watchdog 514 Monitoring signal 515 Reset signal 516 RAM
517 ROM
518 Data bus 601 Input I / F circuit 602 Microcomputer 603 Power supply circuit 604 Delay circuit 605 Watchdog timer 606 ROM
607 VCCION / OFF circuit 608 Low voltage reset circuit 609 Communication LSI
610 Sleep / wake-up signal 611 RUN signal 612 RESET signal 613 VCCI
614 VCCII
615 Multi-input AND circuit 701 CPU (central processing unit)
702 SYSC
703 CPG
705 ROM
706 RAM
707 SCI
708 Timer 709 IOP8
710 IOP7
711 IOP6
712 IOP5
713 IOP4
714 IOP3
715 IOP2
716 IOP1
717 Internal bus 718 Write request signal 801 CPU
802 Memory 803 Address decoder 804 Protect control register 805 Logic element 806 Logic element 807 Logic element 808 Logic element 809 Logic element 810 Logic element 811 Address decoder 812 Address decoder 813 Address decoder 814 Address decoder 815 Control register 816 Control register 817 Control register 818 Control Register 819 Clock generation circuit 820 Peripheral unit A
821 Peripheral unit B
822 Peripheral unit C
823 Internal bus 824 ALE
825 SPCWR
826 WR
827 Logic element 830 Protection control circuit 850 Microcomputer 851 RAM
852 ROM
853 Operation mode detection circuit 854 Timer 855 Output data register 856 Selector 857 Peripheral selection register 858 Input / output control register 859 Write inhibit circuit 860 CPU (central processing unit)
861 Control signal generator 862 Operation mode control circuit 863 Data bus 864 I / O buffer 865 Operation mode setting port 866 Monitoring signal output port 867 I / O buffer 868 OR circuit 869 Reset signal receiving port 870 Reset circuit 871 Reset signal 879 Reset signal 880 Microcomputer 881 RAM
882 ROM
883 Operation mode detection circuit 884 Peripheral function circuit 885 Output data register 886 Operation mode control circuit 887 Input / output control register 888 Write inhibit circuit 889 Reset circuit 890 CPU (central processing unit)
891 Control signal generator 892 Data bus 893 I / O buffer 894 Operation mode setting port 895 Peripheral function circuit port 896 Monitoring signal output port 897 I / O buffer 898 Reset signal receiving port 899 I / O buffer 900 External reset signal 901 Monitoring Signal 902 Reset signal from the watchdog timer 903 Initialization module 904 Internal reset signal 905 Watchdog timer module 906 Peripheral function 1 module 907 Task control module 908 Peripheral function 2 module 909 Mode setting module 910 Display control module 915 From the watchdog timer Reset 916 Reset entry 917 Initialization module 918 Watchdog timer control module 921 Task control module 923 Mode setting module 925 Peripheral function control module

Claims (3)

A operation mode control circuit incorporated in the microcomputer that performs processing by a the control program a microcomputer to have a selection circuit for selecting the signal generating circuit for transmitting a signal to the outside from a plurality of signal generating circuit ,
At least a control signal generator;
In response to the first output signal from the control signal generator, the second output signal from the control signal generator is held and a write signal is generated according to the logical value of the held signal A deterrent circuit;
A control circuit that holds a third output signal from the control signal generator in response to the write signal and generates a control signal according to the logical value of the held signal;
Before Kishokomi signal, when the logic value of a signal the write inhibit circuit has held a one logic value is a signal whose logic value is fixed, the logic value of a signal the write inhibit circuit is held When the other logical value is the buffer signal of the first output signal from the control signal generator,
The operation mode control circuit is characterized in that the control signal is supplied to the selection circuit that selects a signal generation circuit for transmitting a signal to the outside from the plurality of signal generation circuits including at least a data register circuit. . An operation mode control circuit according to claim 1,
A buffer means for outputting a buffer signal of the first output signal or a fixed signal in response to the first output signal from the control signal generator;
Holding means for holding the second output signal from the control signal generator in response to the buffer signal and outputting a logic signal corresponding to the logic value of the second output signal;
The buffer means receives a logic signal from the holding means, outputs the fixed signal according to one logic value, and outputs the buffer signal according to the other logic value. circuit. At least an operation mode control circuit according to claim 1 or claim 2;
A signal input / output control circuit for controlling input / output of signals with the outside;
A data register circuit that holds a data signal from the operation mode control circuit in response to a data register write signal from the operation mode control circuit;
A timer circuit capable of generating one or more periodic clocks;
A selection circuit that selects the data register circuit or the timer circuit in response to the control signal from the operation mode control circuit;
The microcomputer, wherein the data register circuit outputs a signal corresponding to the data signal to the signal input / output control circuit.

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