JPH0792793B2 - Micro computer - Google Patents

Description

DETAILED DESCRIPTION [Outline] A microcomputer that incorporates a circuit that initializes an output port when a clock is stopped facilitates a fail-safe design when the clock is stopped.

[Industrial application field]

The present invention relates to a microcomputer including a circuit that initializes an output port when a clock is stopped.

[Conventional technology]

A microcomputer with a built-in output port (generally a one-chip microcomputer) initializes the output port at the same time as the registers when the external reset signal turns on. FIG. 2 is a partial configuration diagram of this type of microcomputer. 1 is one output port, 2 is an input terminal for reset signal ▲ ▼, 3 is an oscillation circuit, 4 is a system clock generation circuit, and 5 to 7 are D type. Flip-flops (FF) and 8 are externally attached oscillators.

The state of output port 1 depends on the state of FFT9. Normally FET9
It is generally turned off to have high impedance. FIG. 3 is an explanatory view of this. The system clocks φ ₁ and φ ₂ are obtained by dividing the output of the oscillator circuit 3, and φ ₁ is F
F5 is used to latch the external reset signal ▲ ▼, and φ ₂ is used to latch the output of FF6 in FF7. FF6 is for outputting internal data to output port 1 by an output command, but its set terminal SE
When an inverted version of the internal reset signal enters T, the Q output is forcibly fixed at H level. Therefore, at the next φ ₂ timing, the Q output of FF7 becomes H, and the inverted signal turns off FET9.

Such a reset function is important as a countermeasure against malfunction of the microcomputer. In this case, for example, a watchdog timer (WDT) is a circuit that externally generates the reset signal (). This is because a pulse signal is always output from a certain output port of the microcomputer, and when the microcomputer falls into an infinite loop due to the destruction of stack data, the above pulse signal disappears. ▲
In this method, ▼ is temporarily turned on (set to L).

[Problems to be solved by the invention]

However, since the conventional reset method it is assumed that the clock in the microcomputer is occurring normally, clock phi ₁ for some hardware failures, phi ₂
If the same is stopped, the reset is not performed and the output port 1 is held in the state immediately before.

Since this type of microcomputer is used for various controls, it may not be preferable depending on the state in which the output port 1 is held. The present invention is intended to enhance a fail-safe function by incorporating a circuit for holding an output port in a desired state when the clock is stopped, in a microcomputer.

[Means for solving problems]

The present invention relates to a clock stop detection circuit (10) for monitoring output changes of a clock generation circuit (4) and detecting stop of a clock.
The clock stop detection circuit holds the output port (1) in a predetermined state when it is detected that the output of the clock generation circuit is stopped. .

[Action]

The clock stop detection circuit (10) is a clock generation circuit (4)
Monitor the output change and detect the stop of the clock in the microcomputer. Then, when the stop of the clock is detected, the output port (1) is kept in a preferable state for fail-safe. This can be realized by setting such a hardware configuration in advance.

〔Example〕

FIG. 1 is a configuration diagram of a main part showing an embodiment of the present invention, in which a clock stop detection circuit 10 within a dotted frame is added to the configuration of FIG. The clock stop detection circuit 10 of this example includes a prescaler 11 that divides the system clock φ ₂ , an F / V converter 12 that converts an output frequency F of the system clock φ ₂ into a DC voltage V, and the DC voltage V as a reference value E. Comparing, a comparator 13 that keeps the output at H while V> E and inverts the output to L when V ≦ E,
When the output of the comparator 13 becomes L, the AND gate 14 forcibly turns off the FET 9.

This gate 14 is always open and allows the output of FF7 to pass while the clock φ ₂ is generated. Therefore, the output port 1 can be changed by the internal data, or the output port 1 can be set to high impedance by the reset signal from the WDT. On the other hand, when the clock φ ₂ is stopped, the output of the gate 14 becomes L, so that the FET 9 is turned off and the output port 1 becomes high impedance. In this case, high impedance is considered to be preferable for safety.

The fixing of the output port 1 by the clock stop detection circuit 10 does not require any operation clock. Therefore, unlike the external reset by the WDT or the like, the output port 1 can be surely kept in a safe state for control even if a hardware-related clock stop failure occurs. Further, since the detection circuit 10 is built in, there is no need for a terminal (port) for outputting the clock to the outside and inputting the detection result to the inside.

〔The invention's effect〕

As described above, according to the present invention, there is an advantage that the output port can be surely kept in a preferable state for safety when the internal clock which makes the microcomputer inoperable by hardware is stopped.

[Brief description of drawings]

 FIG. 1 is a configuration diagram of a main part showing an embodiment of the present invention, FIG. 2 is a partial configuration diagram of a conventional microcomputer, and FIG. 3 is an operation waveform diagram of each part of FIG.

Claims (1)

[Claims] 1. A clock stop detection circuit (1) for monitoring a change in output of a clock generation circuit (4) and detecting stop of a clock.
0), wherein the clock stop detection circuit holds the output port (1) in a predetermined state when the output of the clock generation circuit is detected to stop. Computer.