JPH1166030A - Semiconductor integrated circuit and micro-computer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To input/output data to/from the data register of a port circuit from the outer terminal of the port circuit in asynchronizintg with an inner bus cycle by accessing first data register means from first outer terminals in synchronism with control signals supplied from a second input terminal. SOLUTION: A first control logic means 9 enables the first data register means 22-25 and a second data register means 26 to read/write data in synchronism with access from a central processing unit. A second control logic means 28 enables the first outer terminals P1(0)-P1(7) to access the first data register means 22-25 in synchronism with the control signals supplied from the second outer terminals P2(0)-P2(7). Control information deciding an input/output operation by the first control logic means 9 or that by a second control logic means 8 is given to a control register means 27 from the central processing unit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a semiconductor integrated circuit,
Further, the present invention relates to a port circuit of a microcomputer, and relates to a technology effective when applied to multifunctional or general-purpose port circuits.

[0002]

2. Description of the Related Art Microcomputers have data terminals for inputting and outputting data to and from the outside. Some microcomputers have a port circuit in addition to the data terminals. The port circuit has a data register connected to the internal bus, and each bit of the data register has one-to-one correspondence with an external terminal (port terminal) of the port circuit. The data register of the port circuit holds data output from the port terminal to the outside, and holds data input from the port terminal. Further, a control register is provided for input / output control of the port terminal. When the central processing unit (CPU) sets control information in this control register, the input, output or input / output function of the port circuit is determined, and the type of input / output signal is determined.

There is also a device in which terminals other than terminals that are always used, such as addresses and data, are also used as port terminals so that the number of terminals of the entire microcomputer does not increase. For example, a port terminal is also used as an external interface terminal of a specific peripheral circuit.

As an example of a document describing a port circuit of a microcomputer, see "H8 / 3398, H8 / 3337, H8 / 3334 Hardware Manual", published by Hitachi, Ltd. in September 1994, page 113. ~ 149 pages.

[0005]

However, in the conventional port circuit, only one bit of the data register corresponds to one port terminal. In other words, for example, only one 1-byte data register corresponds to a set of port terminals such as 1 byte. For this reason, the diversification of the input / output functions of the port circuit has only increased the number of terminals that can also be used as port terminals. The external input / output timing of the data register of the port circuit is CP
It was only synchronized with the U bus cycle. Therefore, when data is externally input to the port circuit, the external circuit must operate in synchronization with the bus cycle of the CPU built in the microcomputer.

An object of the present invention is to provide a semiconductor integrated circuit and a microcomputer which can diversify data input / output functions for external terminals of a port circuit.

Another object of the present invention is to provide a microcomputer capable of inputting and outputting data from an external terminal of a port circuit to a data register of the port circuit asynchronously with an internal bus cycle.

Another object of the present invention is to improve the data input / output function of a port circuit without increasing the number of external terminals of the port circuit. That is, a plurality of units of data of the number of parallel input / output data bits determined by the number of external terminals of the port circuit are held so that input / output is possible.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, in the semiconductor integrated circuit according to the present invention, the bus access control means (3, 4) is provided on the semiconductor substrate.
And an internal bus (5, 6, 7) connected to the bus access control means, and a port circuit (8A) connected to the internal bus and capable of interfacing with the outside of the semiconductor substrate. The port circuit (8A) has a first
Data register means (22 to 25), second data register means (26), and first external terminals (P1 (0) to (P1 (0)) assigned to external input / output of data with respect to the first data register means. P1 (7)) and second external terminals (P2 (0) to P2 (7)) assigned to external input / output of data to and from the second data register means, and synchronized with access from the internal bus. A first register control means (9) for making the first data register means and the second data register means readable and writable, and a control signal supplied from the second input terminal. Second register control means (27, 28) for making the first data register means accessible from the first external terminal.

According to the above means, the data input / output operation with respect to the first data register means can be externally controlled via the second external terminal. That is, the first data register means can be externally accessed asynchronously with the bus cycle by the bus access control means inside the semiconductor integrated circuit.

A microcomputer according to another aspect of the present invention includes a central processing unit (3) and a port circuit (8A) accessed by the central processing unit and interfaced with the outside. The port circuit includes first data register means (22 to 25) and second data register means (22 to 25).
Data register means (26), first external terminals (P1 (0) to P1 (7)) assigned to external input / output of data to and from the first data register means, and the second data register means A second external terminal (P2 (0) to P2 (7)) assigned to external input / output of data to / from the means, and the first data register means and the second data register means synchronized with access from the central processing unit. A first control logic means (9) for making the data register means readable / writable, and the first data register means in synchronization with the control signal supplied from the second external terminal. The second control logic means (28) which can be accessed from an external terminal, and the control information for determining whether the input / output operation by the first control logic means or the input / output operation by the second control logic means is the central control means. Depending on the processing equipment Given control register means includes a (27).

According to the above means, the data input / output operation with respect to the first data register means can be externally controlled via the second external terminal. That is, the first data register means can be externally accessed asynchronously with the bus cycle inside the microcomputer. Whether the access control to the first data register means is synchronized with the bus cycle inside the microcomputer or the signal supplied from the second external terminal can be determined by the CPU via the control register means. .

The control register means includes first control information (CNT) for designating an input / output operation by the first control logic means or an input / output operation by the second control logic means.
By having the storage area of R), which of the interface synchronization types is adopted for the port circuit depends on the CPU.
Can be arbitrarily determined according to the operation program described above, and can be changed at any time.

The first data register means includes a plurality of data registers (22 to 2) whose operations are selected by the first control logic means and the second control logic means, respectively.
5). Therefore, a data register arbitrarily selected from a plurality of data registers can be connected to the first external terminal, so that the data input / output function of the port circuit can be improved without increasing the number of external terminals of the port circuit. it can. In other words, data of the number of parallel input / output data bits determined by the number of external terminals of the port circuit can be held in a plurality of data registers in a plurality of units, or data held in a plurality of units can be selected and output. In a sense different from simply increasing the number of terminals that can also be used as port terminals, a high-performance port circuit can be realized.

The second control logic means selects a data register included in the first register means in accordance with register designation information (sel0 to sel3) included in a control signal supplied from the second external terminal. A read / write operation for the data register is selected in accordance with read / write designation information (EX / IN) included in a control signal supplied from the second external terminal, and a control supplied from the second external terminal is selected. The read / write operation can be performed on the data register in synchronization with the timing information (ST) included in the signal.

The second control logic means can switch the selection of the data register for each specific state of the first external terminal in place of the register designation information. At this time, the control register means:
The second control information (MD0, MD1) for instructing the second control logic means whether to select a register based on the register designation information or to switch for each specific state of the first external terminal. It can have a storage area.

[0019]

FIG. 6 is a block diagram of a microcomputer according to an embodiment of the present invention. Although not particularly limited, the microcomputer shown in FIG. 1 is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique such as CMOS.

In the microcomputer shown in FIG. 1, a CPU 3 has an address and data input / output function for an address bus 1 and a data bus 2. Also,
The bus state controller 4 has an address and data input / output function with respect to the address bus 1, the data bus 2, the peripheral address bus 6, and the peripheral data bus 7. CPU3
And bus state controller 4 share address bus 1 and data bus 2. Further, port circuits 8A and 8B are connected to the peripheral address bus 6 and the peripheral data bus 7 as an example of a peripheral circuit. The CPU 3
Fetches an instruction from a program memory (not shown) connected to the peripheral address bus 6 and the peripheral data bus 7, and decodes and executes the fetched instruction. For example, when the CPU 3 executes a load instruction or a store instruction, and the access target area is on a peripheral circuit connected to the peripheral address bus 6 and the peripheral data bus 7, the access target area is described according to the access address on the address bus 1 at that time. The bus state controller 4 starts a bus cycle using the peripheral address bus 6 and the peripheral data bus 7.

The port circuit 8B has a general port circuit configuration, and the port circuit 8A is a multifunctional port circuit, each of which constitutes an input / output port module.

First, the configuration of the port circuit 8B will be described with reference to FIG. Although not particularly limited, the port circuit 8B
Constitutes port 3 and port 4. The port 3 has eight port terminals P3 (0) to P3 (7), a terminal control logic 15, a data register 13, and a control register 12, although not particularly limited. Port 4 is not particularly limited,
It has eight port terminals P4 (0) to P4 (7), terminal control logic 19, data register 17, and control register 18. The control registers 12, 18 and the data register 1
Reference numerals 3 and 17 are connected to the data latch circuit 10 via the data bus 11 in the module.

The decoder 9 selects the registers for the control registers 12 and 18 and the data registers 13 and 17. The decoder 9 decodes an address signal supplied from the peripheral address bus 6 and decodes the control register 12, 1
8 and one of the data registers 13 and 17 is exclusively selected. The selected register is connected to the peripheral data bus 7 via the data bus 11 in the module and the data latch circuit 10. The control register 12,
Instructions such as read / write 18 and data registers 13 and 17 are given from the bus state controller 4 via the peripheral control bus 5. The bus state controller 4 outputs control signals such as a write signal, a read signal, and an access size signal to the peripheral control bus 5 when activating a bus cycle using the peripheral buses 6 and 7. Thereby, the data registers 13, 17
The control registers 12 and 18 are freely accessed by the CPU 3. At the time of register write, data output from the data latch circuit 10 is written to a register selected by the decoder 9. When reading the register,
The data of the register selected by the decoder 9 is sent to the data latch circuit 10, and the data latch circuit 1
0 to the bus state controller 4 through the peripheral data bus 7.

The port terminals P3 (0) to P3 of the port 3
(7) is connected to the signal line 14 and the data register 13 via the terminal control logic 15. According to this example, 8
The signal line 14 and the data register 13 each have an 8-bit configuration corresponding to the bit port terminals P3 (0) to P3 (7). The terminal control logic 15 outputs the data of the signal line 14 from the port terminals P3 (0) to P3 (7) in accordance with the control information given from the control register 12, and outputs the value of the data register 13 to the port terminal P3 (0 ) -P3 (7), output from port terminals P3 (0) -P3 (7) to signal line 14, port terminal P3
(0) to P3 (7) to supply the input signal to the data register 13 or to disable any of the input / output operations of the port terminals P3 (0) to P3 (7). select.

Similarly, the port terminal P4 of the port 4
(0) to P4 (7) are connected to the signal line 2 via the terminal control logic 19.
1 and the data register 17. According to this example, the signal line 21 and the data register 17 each have an 8-bit configuration corresponding to the 8-bit port terminals P4 (0) to P4 (7). The terminal control logic 19 controls the signal line 2 according to the control information given from the control register 18.
1 data is output from the port terminals P4 (0) to P4 (7), and the value of the data register 17 is changed from the port terminals P4 (0) to P4 (0).
Output from P4 (7), port terminals P4 (0) to P4
(7) is supplied to the signal line 21, the input signals from the port terminals P4 (0) to P4 (7) are supplied to the data register 17, or the port terminals P4 (0) to P4
Either of the states in which the input / output operation of (7) is invalidated is selected.

The signal lines 14 and 21 are connected to other internal modules other than ports, not shown. That is, the port terminals P3 (0) to P3 (7) also serve as terminals of the signal line 14. Similarly, the port terminals P4 (0) to P4 (7) also serve as terminals of the signal line 21.

As is clear from the above, the port circuit 8B
Then, the port terminals P3 (0) to P3 (7), P4 (0) to P4 (7)
In the data input / output operation via the
The selection of 3, 17 is synchronized with the address output operation that the bus state controller 4 outputs to the peripheral address bus 6,
The instruction of the read / write operation to the data registers 13 and 17 is synchronized with the control signal output from the bus state controller 4 to the peripheral control bus 5, and the data transfer between the data registers 13 and 17 and the peripheral data bus 7 is performed. Are synchronized with the bus cycle activated by the bus state controller 4. Therefore, the data input / output operation of the port circuit 8B is basically performed only in synchronization with the bus cycle inside the microcomputer.

Next, an example of the port circuit 8A will be described with reference to FIG. Although not particularly limited, the port circuit 8A configures the port 1 and the port 2. Although the port 1 is not particularly limited, eight port terminals P1 (0) to P1
(7), terminal control logic 16, data registers 22-2
5 and a control register 32. The port 2 includes, but is not limited to, eight port terminals P2 (0) to P2 (7), a terminal control logic 20, a data register 26, and a control register 38. The control registers 32 and 38 and the data registers 22 to 25 and 26 are connected to a latch circuit 33 via a data bus 31 in the module. Although not particularly limited, each of the data registers 22 to 26 and 26 and the control registers 32 and 38 has an 8-bit configuration.

In the port circuit 8A, the port terminal P1
When the data input / output operation via (0) to P1 (7) and P2 (0) to P2 (7) is performed in synchronization with the bus cycle inside the microcomputer as in the case of the port circuit 8B, the first input / output operation is performed. The control mode or the second input / output from the port terminals P1 (0) to P1 (7) in synchronization with a timing signal or the like externally supplied via the port terminals P2 (0) to P2 (7). The input / output control mode is configured to be selectable.

First, in order to realize the first input / output control mode, a decoder 34 for selecting the control registers 32 and 38 and the data registers 22 to 26 is provided. The decoder 34 is connected to the peripheral address bus 6
And exclusively selects one register from the control registers 32 and 38 and the data registers 22 to 26. In particular, there are two modes for selecting the data registers 22 to 25, which will be described later. The selected register is connected to the peripheral data bus 7 via the module data bus 31 and the data latch 33. Instructions such as read / write for the control registers 32 and 38 and the data registers 22 to 26 are given via the peripheral control bus 5. Thus, the control registers 32 and 38 and the data registers 22 to 26 can be freely accessed by the CPU 3.
At the time of register write, data output from the data latch circuit 33 is written to a register selected by the decoder 34. At the time of register reading, the data of the register selected by the decoder 34 is sent to the data latch circuit 33, and further sent from the data latch circuit 33 to the bus state controller 4 through the peripheral data bus 7.

Port terminals P1 (0) to P1 of the port 1
(7) is connected to the signal line 14 and the data registers 22 to 25 via the terminal control logic 16. The terminal control logic 16 transfers the data of the signal line 14 to the port terminal P in accordance with the control information given from the control register 32.
1 (0) to output from P1 (7), data register 22
25, a state in which the value of one data register selected from among the data terminals is output from the port terminals P1 (0) to P1 (7), and the input signal from the port terminals P1 (0) to P1 (7) is , The state where the input signals from the port terminals P1 (0) to P1 (7) are supplied to one data register selected from the data registers 22 to 25, or the state where the port terminal P1
One of the states (0) to P1 (7) in which the input / output operation is invalidated is selected.

Similarly, the port terminal P2 of the port 2
(0) to P2 (7) are connected to the signal line 21 and the data register 26 via the terminal control logic 20. The terminal control logic 20 outputs the data of the signal line 21 from the port terminals P2 (0) to P2 (7) according to the control information given from the control register 38.
6, the state where the value of 6 is output from the port terminals P2 (0) to P2 (7), the state where the input signals from the port terminals P2 (0) to P2 (7) are supplied to the signal line 21, the state where the port terminal P2 (0) ＰP2 (7) is supplied to the data register 26, or the input / output operation of the port terminals P2 (0) 〜P2 (7) is disabled. .

As is clear from the above description, this port circuit 8A is provided with four data registers 22 to 25 for a set of port terminals P1 (0) to P1 (7).
As a result, a set of port terminals P1 (0) is stored in a data register selected from the plurality of data registers 22 to 25.
~ P1 (7) can be connected, and the data input / output function of the port circuit can be improved without increasing the number of external terminals of the port circuit. In other words, data of the number of parallel input / output data bits determined by the number of external terminals of the port circuit can be held in a plurality of data registers in a plurality of units, or data held in a plurality of units can be selected and output.

In order to realize the second input / output control mode in the port circuit 8A, a control logic circuit 28 and an enable register 27 are provided. The control logic circuit 28 responds to a control signal supplied from the port terminals P2 (0) to P2 (7) to control the first data register 2
It has control logic for making 2 to 25 accessible from the first port terminals P1 (0) to P1 (7). The enable register 27 is a register in which at least control information for controlling the first input / output control mode or the second input / output control mode is set by the CPU 3. The enable register 27 is provided in the control register 3
Control information is set via the decoder 34 and the latch 33 in the same manner as in (2).

FIG. 2 shows the specifications of the control information (control signal) supplied to the control logic circuit 28 from the port terminals P2 (0) to P2 (7) via the terminal control logic 20 in the second input / output state. Is shown. In FIG.
It should be understood that 0 to D7 correspond to, for example, port terminals P2 (0) to P2 (7). In order to select a data register to be accessed from the data registers 22 to 25,
D7 to D4 are register designation information (register selection signal) s
el3 to sel0. Register selection signal sel3
Ｓsel0 is a logical value “1” or a high level “H”
Indicates selection, and a logical value “0” or a low level (“L”) indicates non-selection. D3 is the data register 22 to 25
When accessing the read / write operation, read / write designation information (read / write signal) E indicating a read operation or a write operation
X / IN. The read / write signal EX / IN is
A logical value “1” indicates a register write operation (terminal input operation), and a logical value “0” indicates a register write operation (terminal output operation). Although not particularly limited, if the CPU 3 attempts to write to the same data register during the terminal input operation, the terminal input operation has priority and the CPU 3
The write operation of No. 3 is ignored. Conversely, if the CPU 3 attempts to write to the same data register during the terminal output operation, the write operation of the CPU 3 is prioritized, so that the write data output from the data latch circuit 10 is written to the data register. And the port terminal P1
Write data output from the data latch circuit 10 is output to (0) to P1 (7). D2 is the register selection signal s
The strobe signal ST indicates the validity of data input / output from the port terminals P1 (0) to P1 (7) in parallel with the input of control signals such as el3 to sel0. Although not particularly limited, the logic value “0” of the strobe signal ST means that data is valid. The strobe signal ST is positioned as a timing signal when actually performing a read / write operation on the data registers 22 to 25.

FIG. 3 shows an example of the data specification of the enable register 27. D7 is a control bit ON / O
When the logical value “1” is set to the bit ON / OFF, the data register 22 of the port 1
To 25 are made valid (that is, selectable), and only one of the data registers 22 to 25 of the port 1 is made valid by the logical value “0” of the bit ON / OFF. The instruction by the control bit ON / OFF is not particularly limited, but is given from the control signal line 39 to the decoder 34 via the control logic circuit 28. Bit D6 is set as control bit CNTR. Control bit CNT
R designates a terminal control mode by a logical value “1” and a CPU control mode by a logical value “0”. The terminal control mode is an operation mode for realizing the second input / output control mode.
The CPU control mode is an operation mode for realizing the first input / output control mode. Although not particularly limited, in the terminal control mode, in the terminal output operation, the CPU 3 controls the data register (data registers 22 to 25 when ON / OFF = "1", and the data register 22 when ON / OFF = "0"). ) Can be written. On the other hand, in the terminal input operation in the terminal control mode, selection of the data registers 22 to 25 by the decoder 34 via the signal line 39 is suppressed, and the CPU 3 cannot perform writing to the data registers 22 to 25.

D5 and D4 of the enable register 27 are
These are setting bits for manual mode and automatic detection mode for the selection of the data registers 22 to 25 in the terminal control mode. In manual mode, data register 2
Selection of 2 to 25 is performed by the selection signals sel3 to sel0. When the automatic detection mode is set, the port terminals P1 (0) to P1 (7) are set to a specific state (for example, a logical value “1” and a logical The selection state of the data registers 22 to 25 is automatically switched sequentially each time the value is set to an intermediate level of the value "0". When the automatic detection mode is set, the control logic circuit 28 switches the selection state of the data register to the next data register every time the intermediate level is recognized by the detection signal 41 output from the state detection circuit 40. . The order of switching the data registers is not particularly limited, but is the order of the data registers 22 to 25. At this time, when the control bit CONT of the enable register 27 has the logical value "0", the automatic switching of the data registers in the automatic detection mode is sequentially completed from the data registers 22 to 25. When the control bit CONT is a logical value "1", the control bit
The automatic switching of the data register in the automatic detection mode is repeated.

FIG. 4 shows the control bit ON / OFF =
The terminal control mode using the four data registers 22 to 25 is set by “1” and CNTR = “1”.
An example of an operation timing chart of the port 1 when the manual mode is set according to = “1” and MD0 = “0” is shown.

In FIG. 4, φ is a microcomputer bus clock. Port 2 port terminal P2 (0) ~
Select signals sel0-sel3 and signal E from P2 (7)
The X / IN and the strobe signal ST are supplied asynchronously with the bus clock φ. At this time, the selection signal sel
Data H'12 is supplied from the port terminals P1 (0) to P1 (7) in synchronization with the logical value "1" of 0 (selection of the data register 22) (asynchronous with the bus clock φ), and the strobe signal ST The data is written to the register 22 in synchronization with the low level period. Hereinafter, the port terminals P1 (0) to P1 (P) are sequentially synchronized with the low level period of the strobe signal ST.
The data H'56 input from 1 (7) is written to the data register 23, and the data H'9A is stored in the data register 24.
To the port terminal P1 (0), and the data H'DE is output from the data register 25 from the port terminals P1 (0) to P1 (7).

Next, the operation of the port circuit 8A of FIG. 1 will be described generally. When the control bit ON / OFF of the enable register 27 is set to “0”, the port 1
Indicates that only the data register 22 is valid and the port circuit 8
Ports 1 and 2 of A realize the same functions as ports 3 and 4 of the port circuit 8B. Therefore, at this time,
Port 1 data registers 23-25 are not used.

Control bit ON of enable register 27
When / OFF is "1", an arbitrary register can be selected from the data registers 22 to 25 and used. At this time, when the terminal control mode is selected by the control bit CNTR of the enable register 27, the selection signals sel3 to sel0 input from the port terminals P2 (0) to P2 (7) of the port 2 are transmitted to the control logic circuit 28. Can decode and select the data registers 22 to 25, and read or write to the selected data register in synchronization with an external strobe signal ST. Therefore, in this terminal control mode, CP
The data registers 22 to 25 can be externally read or written asynchronously with the bus cycle of U3.

When the control information ON / OFF is set to "1" and the CPU control mode is set in the enable register 27, the terminal control logics 16 and 20 are set according to the set values of the control registers 32 and 38. Are controlled, and the data registers 22 to 25 and 26 are read / written according to the bus cycle of the CPU 3.

When the automatic detection mode is selected by the control bits MD0 and MD1 of the enable register 27, for example, after the data register 22 is accessed via the port terminals P1 (0) to P1 (7). When the end of the register access is recognized by the detection signal 41, the data register 2 is accessed at the next register access.
3 is automatically selected. Similarly, automatic switching is performed up to the data register 25 in the same manner. At this time, when the automatic detection mode is set to end in one cycle by the control bit CONT of the enable register 27,
This function automatically returns to the manual mode. When it is set to repeat indefinitely, the access destination automatically returns to the data register 22 further.

Although the invention made by the inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited to the embodiments and can be variously modified without departing from the gist of the invention. No.

For example, the number of bits of a set of port terminals and the number of bits of a data register are not limited to 8 bits.
It is also possible to adopt a bit number such as 16 bits or 32 bits. Further, the number of data registers as shown in the port 1 is not limited to four, and an appropriate number such as two, six, or eight can be adopted. The selection signal supplied from the outside in the terminal control mode is
The register selection signal is not limited to 10 to sel3, and may be 2 bits, which may be decoded inside the control logic circuit to form a register selection signal. Although the port circuits are connected to the peripheral buses 6 and 7 in FIG. 6, the port circuits may be connected to the address bus 1 and the data bus 2 directly connected to the CPU 3. Further, the automatic switching of the selection state of the data register is not limited to the case where the selection is performed by detecting an intermediate level state between the high level and the low level of the port terminal. The state to be detected can be variously changed according to the definition of the signal logic value or the driving form of the signal line.

In the above description, the case where the invention made by the present inventor is mainly applied to a microcomputer which is a field of application as a background has been described. However, the present invention is not limited to this, and a microprocessor, a communication protocol control, and the like. The present invention can be widely applied to various semiconductor integrated circuits such as dedicated logic LSIs used for such purposes.

[0047]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, according to the control information supplied from the second external terminal, the data register of the port circuit is stored in the first register.
Data can be read / written from the external terminal of Therefore, data input / output can be performed by accessing the data register of the port circuit in synchronization with the internal bus cycle of the microcomputer or the semiconductor integrated circuit and asynchronously with the internal bus cycle.

Further, by providing a plurality of data registers for the first external terminal, a data register arbitrarily selected from the plurality of data registers can be connected to the first external terminal. The data input / output function of the port circuit can be improved without increasing the number of external terminals of the circuit. In other words, data of the number of parallel input / output data bits determined by the number of external terminals of the port circuit can be held in a plurality of data registers in a plurality of units, or data held in a plurality of units can be selected and output.

An operation of individually selecting a desired data register for the plurality of data registers using an address signal or selection information similar thereto, and a specific state such as an intermediate level state of the first external terminal. An operation of automatically switching the selection state of the data register can be selected every time.

As described above, it is possible to realize a high-performance port circuit in a sense different from simply increasing the number of terminals that can also be used as port terminals.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example of a port circuit having a CPU control mode and a terminal control mode.

FIG. 2 is an explanatory diagram showing an example of specifications of control information (control signal) supplied to a control logic circuit from a port terminal in a terminal control mode.

FIG. 3 is an explanatory diagram showing an example of data specifications of an enable register.

FIG. 4 is a timing chart showing an example of an input / output operation in a terminal control mode.

FIG. 5 is an explanatory diagram of an example of a port circuit having no terminal control mode.

FIG. 6 is a block diagram of a microcomputer according to one embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Address bus 2 Data bus 3 CPU 4 Bus state controller 5 Peripheral control bus 6 Peripheral address bus 7 Peripheral data bus 8A, 8B Port circuit P1 (0) -P1 (7), P2 (0) -P2 (7) port terminal 16 terminal control logic 20 terminal control logic 22 to 25 data register 27 enable register 26 data register 28 control logic circuit 32 control register 34 decoder 38 control register 40 state detection circuit sel3 to sel0 selection signal EX / IN read / write signal ST strobe signal

Claims (7)

[Claims] 1. A semiconductor substrate comprising: a bus access control means; an internal bus connected to the bus access control means; and a port circuit connected to the internal bus and capable of interfacing with the outside of the semiconductor substrate. Wherein the port circuit comprises: first data register means;
A data register means, a first external terminal assigned to external input / output of data to the first data register means, and a second external terminal assigned to external input / output of data to the second data register means. External terminals,
First register control means for making the first data register means and second data register means readable / writable in synchronization with access from the internal bus, and control supplied from the second input terminal A second register control means for making the first data register means accessible from the first external terminal in synchronization with a signal. 2. A central processing unit, and a port circuit accessed by the central processing unit and interfaced with the outside, the port circuit comprising: first data register means;
A data register means, a first external terminal assigned to external input / output of data to the first data register means, and a second external terminal assigned to external input / output of data to the second data register means. External terminals,
First control logic means for making the first data register means and second data register means readable / writable in synchronization with access from the central processing unit; and supplied from the second external terminal. A second control logic means for making the first data register means accessible from the first external terminal in synchronization with a control signal; and an input / output operation by the first control logic means or the second control And a control register means provided with control information for determining whether the input / output operation is performed by the logic means by the central processing unit. 3. The control register means has a storage area for first control information for designating an input / output operation by the first control logic means or an input / output operation by the second control logic means. 3. The microcomputer according to claim 2, wherein: 4. The first data register means has a plurality of data registers whose operations are selected by the first control logic means and the second control logic means, respectively. The microcomputer according to claim 2. 5. The second control logic means selects a data register included in the first register means according to register designation information included in a control signal supplied from the second external terminal, and selects the data register. A read / write operation for the data register is selected in accordance with read / write designation information included in a control signal supplied from the second external terminal, and synchronized with timing information included in the control signal supplied from the second external terminal 5. The microcomputer according to claim 4, wherein said microcomputer performs a read / write operation on said data register. 6. The second control logic means is capable of sequentially switching the selection of the data register for each specific state of the first external terminal in place of the register designation information. The microcomputer according to claim 5, wherein: 7. The control register means instructs the second control logic means whether to select a register based on the register designation information or to switch over for each specific state of the first external terminal. 7. The microcomputer according to claim 6, comprising a storage area for second control information.