JPH10255490A - Reset control circuit of memory cell device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid such situation that writing is interrupted by input of a reset signal during write-in operation to a memory cell, and data of a memory cell is made unstable, in a memory cell device. SOLUTION: In the memory cell device having an EEPROM cell 304, a write-in circuit 306 performing writing data for this EEPROM cell 304, a reset terminal 101 to which a reset signal for reset-operating a device including the EEPROM cell is inputted, the device is provided with a reset signal reservation circuit 308 which can reserve a reset signal inputted to the reset terminal 101. The reset signal reservation circuit 308 has constitution in which an internal reset signal 103 is outputted based on a state of a power-on-clear signal and a write-in signal from the EEPROM cell write-in circuit 306, and performs reset of a memory device by the internal reset signal 103.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory cell device for writing and resetting data in a memory cell, and more particularly to a reset control circuit for preventing a malfunction due to a reset.

[0002]

2. Description of the Related Art As a conventional memory cell device of this kind,
The configuration of a device incorporating an EEPROM cell will be described with reference to the block diagram of FIG. This memory cell device has a CPU
302, an EEPROM cell 304, and an EEPROM
Read (read) circuit 305 and EEPROM W
It is composed of a write (write) circuit 306 and an internal bus 401 connecting each of them. The CPU 302 incorporates an interrupt control circuit 303 and detects an interrupt request from the EEPROM writing circuit 306. EEPROM
The writing circuit 306 has a built-in writing time counter 307 for counting the writing time to the EEPROM cell 304. Further, the internal reset signal 103 input from the RESET (reset) terminal 101 is input to all the components, and the initialization is executed asynchronously by inputting “1” to the reset terminal 101.

The EEPROM reading circuit 305 has a C
EEPROM cell 3 based on the instruction executed by PU 302
Read the data from the data buffer 04. EEPROM
The write circuit 306 writes data to the EEPROM cell 304 based on the instruction executed by the CPU 302. The EEPROM writing circuit 306 is a CPU 30
2, the operation of the write time counter 307 is started at the same time as the execution of the write command, and thereafter, the write process to the EEPROM cell 304 is executed with the time counted by the write time counter 307 regardless of the operation of the CPU 302. The write time counter 307 stops the operation of the EEPROM write circuit 306 at the end of the count, and at the same time, the EEPROM write end interrupt signal 105
To notify the CPU 302 that the writing to the EEPROM cell 304 has been completed.

Next, the operation of the conventional example will be described with reference to a timing chart of FIG. In this conventional example, since the input from the reset terminal 101 is the highest control in the memory cell device, when "1" is input to the reset terminal 101, regardless of the internal operation state at that time, the memory cell device Is initialized. That is, E
When “1” is input to the reset terminal 101 while writing to the EPROM cell 304 is being executed, EE
The operation of the PROM write circuit 306 also stops and the EEPROM
Writing to the M cell 304 is interrupted. EEPROM
If the writing to the cell 304 is interrupted and the writing time is insufficient, the data of the cell where the writing has been performed remains undefined. This indeterminate EEPRO
When the data of the M cell 304 is read after initialization,
There is a possibility that the CPU 302 malfunctions and the entire memory cell device runs away.

[0005]

As described above, in the conventional circuit configuration, since the input to the reset terminal is the highest control, the reset signal input to the reset terminal causes E
It is inevitable that the writing being performed on the EPROM cell is interrupted halfway and the data of the cell becomes indefinite. Therefore, when the indefinite data held in the EEPROM cell is read out after the initialization accompanying the reset, the CPU may malfunction and cause a runaway in a memory cell device or a so-called logic circuit device such as a microcomputer including the same. is there.

SUMMARY OF THE INVENTION It is an object of the present invention to prevent a data in a memory cell from becoming unstable when a reset signal is inputted, and to prevent a malfunction of the device even by initialization by reset. To provide a reset control circuit.

[0007]

According to the present invention, a memory cell, a write circuit for writing data to the memory cell, and a reset signal for resetting a device including the memory cell are input. And a reset signal holding circuit capable of holding a reset signal input to the reset terminal. The reset signal holding circuit includes a means for outputting a signal for inhibiting writing to the memory cell based on the reset signal, a delay means for delaying the reset signal for a predetermined time, and a signal for outputting the delayed reset signal when the power is turned on. Means for outputting an internal reset signal for resetting the memory cell device based on each state of the clear signal and the write signal from the memory cell write circuit.

In this case, the means for outputting the internal reset signal is configured to suspend the output of the internal reset signal when the memory cell write signal is a signal indicating a write state. Further, a configuration may be provided that includes second delay means for delaying the clear signal and the memory cell write signal, and latch means for latching the delayed reset signal based on an output of the second delay means.

[0009]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a first embodiment of the present invention. In the figure, the memory cell device is C
PU 302, EEPROM cell 304, EEPROM
M read circuit 305 and EEPROM write circuit 3
06, an internal bus 401 for connecting them, and a reset signal holding circuit 308. The CPU 3
Reference numeral 02 includes an interrupt control circuit 303 and detects an interrupt request based on the interrupt signal 105 from the EEPROM writing circuit 306. EEPROM writing circuit 3
Reference numeral 06 incorporates a write time counter 307 that counts the write time to the EEPROM cell 304. The write time counter 307 outputs the EEPROM write signal 102 which becomes "1" during the count operation. Also,
The reset signal holding circuit 308 is connected to the reset terminal 101.
And the logic level of the reset signal input to
Based on the logical level of the M write signal 102, the internal reset signal 103, the EEPROM Inactive
(Prohibition) The signal 104 is output. The EEPROMI inhibit signal 104 is a signal for preventing contention between the initialization operation by the internal reset signal 103 and the write operation to the EEPROM cell 304.

FIG. 2 is a diagram showing the internal configuration of the reset signal holding circuit 308. Power On Clear
An r (power-on-clear) circuit 301 and an EEPROM write signal 102 are input to the NAND circuit 201,
Further, the reset signal of the reset terminal 101 is
07 and is input to the AND circuit 204 together with the output of the NAND circuit 201. This AND circuit 204
Is an internal reset signal 103 for resetting the memory cell device. Also, the reset terminal 101
Is connected to a reset rising edge detection circuit 309, the output of which is the EEPROM inhibition signal 104.

Here, the power-on-clear circuit 301
Is a circuit which outputs "0" immediately after power-on and outputs "1" when the power supply voltage exceeds the inversion level of the power-on-clear circuit 301. The power-on-clear circuit 301 is indeterminate immediately after power-on until the reset terminal 101 and the internal reset signal 103 are initialized.
NAN reliably without being affected by the ROM write signal 102
It has a role of fixing the output of the D circuit 201 to “1”. The reset rising edge detection circuit 309 detects the rising edge of the reset signal at the reset terminal 101,
EEPROM for inhibiting the start of writing to EEPROM cells
The OM inhibit signal 104 is output. The delay circuit 207 has a delay time from the rising edge of the reset terminal 101 to the time when the EEPROM inhibition signal 104 inhibits the start of writing to the EEPROM cell 304, and the CPU 302
EE after executing a write instruction to ROM cell 304
This circuit has a delay equal to or longer than the total delay time until "1" is output to the PROM write signal 102.

Next, the operation of the memory cell device having the inside of the reset signal holding circuit 308 will be described with reference to FIGS. FIG. 3 shows a timing chart immediately after the power is turned on. Since the power-on-clear circuit 301 outputs “0” immediately after power-on and fixes the output of the NAND circuit 201 to “1”, the “1” level input to the reset terminal 101 is delayed after a delay by the delay circuit 207. , Are output to the internal reset signal 103. The internal reset signal 103 initializes the inside of the memory cell device, so that the EEPROM write signal 102 is determined to be “0”. Thereafter, when the power supply voltage exceeds the inversion level of the power-on-clear circuit 301, the power-on-clear circuit 301 outputs "1", and thereafter the NAND circuit 201
Is determined by the input to the EEPROM write signal 102.

FIG. 4 shows that "1" is applied to the reset terminal 101 while writing to the EEPROM cell 304 is being executed.
9 shows a timing chart in the case where is input.
When a write command to the EEPROM cell 304 is executed by the CPU 302, the EEPROM write circuit 3
06 immediately starts the write process to the EEPROM cell 304, and the write time counter 307 starts counting the write time and outputs "1" to the EEPROM write signal 102 at the same time. As a result, the output of the NAND circuit 201 is fixed at “0”, and the internal RESET signal 103 is also fixed at “0”. Therefore, even if "1" is input to the reset terminal 101 in this state, nothing is output to the internal reset signal 103.

Therefore, as shown in FIG.
While the EPROM write signal 102 is "1", that is, E
If the reset terminal 101 becomes “0” while writing to the BPROM cell is being executed, the EEPR
The initialization of the memory cell device after the data of the OM cell is determined is not executed. Further, as shown in FIG.
If the input to the reset terminal 101 remains "1" until the writing to the EPROM cell is finished,
After the data of the EPROM cell is determined, the initialization of the memory cell device is executed. That is, in both operations of FIG. 4, the data of the EEPROM cell 304 is always determined.

FIG. 5 shows a timing chart in the case where the writing to the EEPROM cell 304 and the input of "1" to the reset terminal 101 conflict. Reset terminal 1
When "1" is input to the counter 01, the reset rising edge detection circuit 309 detects the rising edge and detects EEP.
A ROM inhibition signal 104 is output. When this signal is "1", the EEPROM inhibit signal 104
This signal prohibits the start of the write operation to the M cell. As shown in FIG. 5A, when the start of writing to the EEPROM cell is slightly earlier than the EEPROM inhibition signal 104, the EEPROM inhibition signal 104 does not operate. Also, due to the delay of the delay circuit 207, the “1” input to the reset terminal 101 is more E
The AND circuit 20 is operated by the EPROM write signal 102
Since the output of the internal reset signal 103, i.e., the internal reset signal 103 is fixed to "0" earlier, the writing to the EEPROM cell is executed as it is, and the initialization of the memory cell device is suspended. On the other hand, as shown in FIG.
When the start of writing to the EEPROM cell is slightly later than the EEPROM inhibition signal 104, the operation of the EEPROM inhibition signal 104 does not start the writing to the EEPROM cell. Further, “1” input to the reset terminal 101 is output to the internal reset signal 103, and initialization of the memory cell device is executed. That is, the data in the EEPROM cell 304 does not become unstable in either operation of FIG.

FIG. 6 shows a timing chart when writing to the EEPROM cell 304 is not executed. At this timing, the reset terminal 101
Is input to the internal reset signal 103 as it is via the delay time of the delay circuit 207.

FIG. 7 is a diagram showing another configuration example of the reset signal holding circuit 308 in the reset control circuit of the present invention. In this embodiment, in addition to the configuration of the reset signal holding circuit 308 shown in FIG.
3. Addition of inverter circuits 205 and 206 and delay circuit 208 constitute a holding circuit (latch) for inputting "1" to reset terminal 101 when a write operation is performed on the EBPROM cell.

FIG. 8 shows that "1" is applied to the reset terminal 101 while writing to the EBPROM cell 304 is being executed.
9 shows a timing chart in the case where is input.
When the write operation to the EEPROM cell is being executed, that is, when the EEPROM write signal 102 is “1”
When "1" is input to the RESET terminal 101 in the case of
“1” is held at the output of the D circuit 203. Next, EE
When the writing to the PROM cell is completed and the output of the EEPROM write signal 102 becomes “0”, “1” held in the NAND circuit 203 is output to the internal reset signal 103 regardless of the level of the reset terminal 101 at this time. Initialization of the memory cell device is performed.

Therefore, as shown in FIG.
If the reset terminal 101 is already "0" when "0" is output to the EPROM write signal 102, the output of the NAND circuit 203 becomes "1" when the output of the delay circuit 208 becomes "1". 0 ". That is, the signal output as the internal reset signal 103 is a pulse having the maximum delay time of the delay circuit 208. As shown in FIG. 8B, when "0" is output to the EEPROM write signal 102, the reset terminal 101
Remains at "1", the signal output as the internal reset signal 103 is a pulse having the maximum width until the reset terminal 101 becomes "0". Also in this configuration,
The data in the EEPROM cell 304 does not become unstable. If a reset input occurs during the write operation to the EEPROM cell 304, the memory cell device is always initialized and is not ignored.

In the above embodiment, an example is described in which an EEPROM is used as a memory cell.
The present invention can be similarly applied to any memory cell device that includes a readable memory cell and is initialized by reset.

[0021]

As described above, in the reset control circuit of the present invention, by providing the reset signal holding circuit, when a reset signal is input during execution of writing to a memory cell, the reset signal is written. Is completed without interruption, and the value of the memory cell is definitely determined. Alternatively, when the start of writing to the memory cell and the reset signal input conflict, the writing to the memory cell is not executed, or the reset signal is suspended and the writing is executed to definitely determine the value of the memory cell.
A circuit in which data of a memory cell does not become unstable can be realized. Thereby, the data storage in the memory cell is not affected by the reset input, and it can be guaranteed that the data is always normal, so that malfunction and runaway of the memory cell device can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram of a memory cell device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a reset signal holding circuit of the memory cell device of FIG. 1;

FIG. 3 is a timing chart immediately after power-on.

FIG. 4 is a timing chart showing a reset operation during writing to an EEPROM cell.

FIG. 5 is a timing chart showing a reset operation when writing to an EEPROM cell and reset signal input conflict.

FIG. 6 is a timing chart showing a reset operation when writing to an EEPROM cell is not executed;

FIG. 7 is a circuit diagram showing another configuration example of the reset signal holding circuit of the present invention.

FIG. 8 is a timing chart for explaining the operation of FIG. 7;

FIG. 9 is a block diagram of an example of a conventional memory cell device.

FIG. 10 is a timing chart for explaining the operation of FIG. 9;

DESCRIPTION OF SYMBOLS 101 RESET terminal 102 EEPROM write signal 103 Internal reset signal 104 EEPROM inhibit signal 105 is EEPROM write end interrupt signal 201, 202, 203 NAND circuit 204 AND circuit 205, 206 Inverter circuit 207, 208 Delay circuit 301 Power on Clear circuit 302 CPU 303 Interrupt control circuit 304 EEPROM cell 305 EEPROM read circuit 306 EEPROM write circuit 307 Write time counter 308 Reset signal hold circuit 309 Reset rising edge detection circuit

Claims (4)

[Claims] 1. A memory cell device comprising: a memory cell; a write circuit for writing data to the memory cell; and a reset terminal to which a reset signal for resetting a device including the memory cell is input. 2. The reset control circuit according to claim 1, further comprising a reset signal holding circuit capable of holding a reset signal input to the reset terminal. A reset signal holding circuit configured to output a signal prohibiting writing to the memory cell based on the reset signal; a delay unit configured to delay the reset signal for a predetermined time; 2. The reset control according to claim 1, further comprising: means for outputting an internal reset signal for resetting the memory cell device based on each state of a clear signal output when power is turned on and a write signal from the memory cell write circuit. circuit. 3. The reset control circuit according to claim 2, wherein said means for outputting said internal reset signal suspends output of said internal reset signal when said memory cell write signal is a signal indicating a write state. 4. A semiconductor device comprising: a second delay means for delaying the clear signal and the memory cell write signal; and a latch means for latching the delayed reset signal based on an output of the second delay means. 2 reset control circuit.