JP5041686B2 - Method for peeling thin film integrated circuit and method for manufacturing semiconductor device - Google Patents

Description

  The present invention relates to a method for peeling a thin film integrated circuit capable of recording a large amount of information, and a method for manufacturing a semiconductor device using the peeling method.

  In recent years, technological development of an IC chip (also referred to as an IC tag, an ID tag, an RF tag (Radio Frequency), a wireless tag, or an electronic tag) using a thin film integrated circuit formed over a glass substrate has been advanced. In such a technique, the thin film integrated circuit formed on the glass substrate needs to be separated from the glass substrate which is a support substrate after completion. Therefore, various techniques have been considered so far as a method for separating a thin film integrated circuit provided on a supporting substrate.

  For example, there are a method of thinning the substrate by grinding and polishing to take out a thin film integrated circuit, a method of removing the support substrate by a chemical reaction, a method of peeling the support substrate and the thin film integrated circuit, and the like.

As a method of peeling a thin film integrated circuit provided on a supporting substrate, a separation layer made of amorphous silicon (or polysilicon) is specifically provided, and the substrate is passed through and irradiated with laser light to form amorphous silicon. There is a technique in which a support substrate is separated by generating a void by releasing hydrogen contained in (see Patent Document 1). In addition, a peeling layer containing silicon is provided between the thin film integrated circuit and the supporting substrate, and the peeling layer is removed using a gas containing halogen fluoride, so that the thin film integrated circuit is separated from the supporting substrate. There is a technology (see Patent Document 2). As described above, there are many methods for separating the thin film circuit provided on the support substrate.
Japanese Patent Laid-Open No. 10-125929 JP-A-8-254686

  However, in the method of removing the support substrate by grinding, polishing or dissolution, it is very difficult to reuse the substrate once used, and there is a problem that the cost increases.

  In the case of a method for separating a thin film integrated circuit provided on a support substrate by removing a release layer provided between the thin film integrated circuit and the support substrate, it is important to remove the release layer. In other words, the time required for removing the release layer, the state of the thin film integrated circuit after removal, and the like depend on the selection of the material and the etching agent used for the release layer. As a result, the process of peeling the support substrate and the thin film integrated circuit greatly affects the production efficiency and the overall cost. In the peeling process using the peeling layer, when the thin film integrated circuit provided on the support substrate is separated, the thin film integrated circuit is distorted due to stress or the like, and it is difficult to maintain the original shape. is there.

  In view of the above problems, an object of the present invention is to provide a method for peeling a thin film integrated circuit with low cost and high production efficiency, and a method for manufacturing a semiconductor device using the peeling method.

  The present invention forms a release layer made of a film containing a metal on a substrate, forms a plurality of thin film integrated circuits on the release layer, and forms a resin film on each of the plurality of thin film integrated circuits. A gas or liquid containing halogen fluoride is introduced into the substrate, the peeling layer is removed, and the substrate and the thin film integrated circuit are peeled off. The film containing a metal may be any film as long as it contains a metal, for example, a film containing any of tungsten (W), molybdenum (Mo), niobium (Nb), titanium (Ti), and the like. Can be used. Further, an oxide of the metal film may be formed on the surface of the metal film. Specifically, a film containing WOx on W, a film containing Mox on Mo, a film containing Nbx on Nb, a film containing TiOx on Ti (x = 2 to 3), or the like can be formed. .

  As another structure of the present invention, a release layer made of a film containing a metal is formed on a substrate, a plurality of thin film integrated circuits are formed on the release layer, and a resin film is formed on each of the plurality of thin film integrated circuits. Forming and introducing a gas or a liquid containing halogen fluoride into the peeling layer, removing at least a part of the peeling layer located below the thin film integrated circuit, and bonding the substrate with a part of the peeling layer; A plurality of thin film integrated circuits are separated using physical means (physical force). The physical means is a means recognized not by chemistry but by physics. Specifically, it means a mechanical means or a mechanical means having a process that can be applied to the laws of mechanics. It refers to a means of changing energy (mechanical energy). In other words, peeling using physical means means, for example, by applying an impact (stress) from the outside using a human hand, a wind pressure of a gas blown from a nozzle, a load using an ultrasonic wave or a wedge-shaped member, or the like. Say to peel.

  Further, as another structure of the present invention, a peeling layer made of a film containing a metal is formed over a substrate, a part of the peeling layer is selectively removed, and a plurality of openings are formed in the peeling layer. A thin film integrated circuit is formed over the layer and the opening, a resin film is formed over the thin film integrated circuit, a gas or liquid containing halogen fluoride is introduced into the peeling layer, the peeling layer is removed, and adhesion is performed at the opening The substrate and the thin film integrated circuit are peeled off using physical means.

  As another structure of the present invention, a peeling layer made of a film containing a metal is formed on a substrate, a thin film integrated circuit is formed on the peeling layer, and a convex portion is formed on at least a part of the surface on the thin film integrated circuit. A gas film or a liquid containing halogen fluoride is introduced into the peeling layer, and at least a part of the peeling layer located below the convex portion of the resin film is removed to remove a part of the peeling film. The substrate and the thin film integrated circuit bonded by the layers are peeled off using physical means.

In the present invention, the etching agent for removing the release layer is preferably the above-described gas or liquid containing halogen fluoride, but is not limited thereto. Any material can be used as long as it reacts with the release layer, and CF ₄ , SF ₆ , NF ₃ , F ₂ , TMAH, or the like can also be used as an etching agent.

  The resin film preferably covers the entire top surface of the thin film integrated circuit, but it is sufficient that it covers at least a part of the thin film integrated circuit. In addition to the upper surface of the thin film integrated circuit, the side surfaces may be covered with a resin film.

  Note that the thin film integrated circuit of the present invention may have any configuration, and includes, for example, all kinds of integrated circuits such as an LSI (Large Scale Integrated Circuit), a CPU (Central Processing Unit), a memory, or a microprocessor. One of thin film integrated circuits that can be formed using the peeling method of the present invention is an IC chip. An IC chip is a semiconductor device capable of transmitting and receiving data wirelessly, and its practical use is being promoted in various fields. The IC chip is also called a wireless tag, an RFID (Radio frequency identification) tag, an IC tag, or an ID chip.

  A semiconductor device formed using the peeling method of the present invention includes an integrated circuit using a thin film transistor. In addition, a semiconductor device using the manufacturing method of the present invention can have a mode having an antenna in addition to the integrated circuit. The integrated circuit operates using an alternating voltage generated at the antenna, and modulates the alternating voltage applied to the antenna, thereby transmitting a signal to the reader / writer. Note that the antenna may be formed together with the integrated circuit, or may be formed separately from the integrated circuit and electrically connected later.

  By using the present invention, the shape of the thin film integrated circuit can be maintained even after the thin film integrated circuit provided over the substrate is peeled from the substrate. Further, by selecting the combination of the release layer and the etchant shown in the present invention, the process of peeling the thin film integrated circuit from the substrate can be performed in a short time, and the production efficiency is improved in the manufacture of the semiconductor device. . Furthermore, by using the present invention, a substrate on which a thin film integrated circuit is formed can be reused, so that cost reduction can be achieved.

  Embodiments of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in the structures of the present invention described below, the same reference numerals are used in common in different drawings.

  The present invention relates to a method for peeling a thin film integrated circuit formed over a substrate, and the peeled thin film integrated circuit can be used for a semiconductor device or the like capable of transmitting and receiving data wirelessly.

  In the present invention, as a method of peeling a thin film integrated circuit from the substrate after the thin film integrated circuit is formed on the substrate, a means is provided in which a peeling layer is provided at the boundary between the substrate and the thin film integrated circuit and peeling is performed at that portion. Specifically, a thin film integrated circuit is once formed over a substrate through a separation layer, and then the thin film integrated circuit is separated from the substrate. Therefore, since the thin film integrated circuit can be reused after the thin film integrated circuit is peeled from the substrate, the thin film integrated circuit can be manufactured and peeled at low cost. For example, even when a quartz substrate having a higher cost than a glass substrate is used as the substrate, the cost can be reduced by reusing.

  In the present invention, the peeling process is important. That is, the longer the removal of the release layer is possible, the longer the processing time and the higher the production efficiency. Therefore, it is necessary to select the combination of a peeling layer formed between the substrate and the thin film integrated circuit and an etching agent for removing the peeling layer, with sufficient consideration.

  In addition, after the thin film integrated circuit is peeled from the substrate, the shape of the thin film integrated circuit may be distorted due to stress or the like. Therefore, in the present invention, in order to maintain the shape of the thin film integrated circuit after peeling, a protective film is formed in advance on the thin film integrated circuit before peeling. By forming the protective film and reinforcing the thin film integrated circuit, it is possible to prevent the thin film integrated circuit from being damaged or destroyed by stress or the like even when physically peeling.

  In the present invention, in order to separate the substrate and the thin film integrated circuit manufactured over the substrate, the practitioner may select an optimal material for the release layer and an etching agent as appropriate. In addition, the thin film integrated circuit includes, for example, an LSI (Large Integrated Circuit), a CPU (Central Processing Unit), a memory, or the like, and can be used by being mounted on an article after peeling.

  Hereinafter, a method for peeling a substrate and a thin film integrated circuit formed over the substrate and a method for manufacturing a semiconductor device will be specifically described with reference to the drawings.

(Embodiment 1)
In this embodiment, a method for separating a substrate and a thin film integrated circuit provided over the substrate will be described. Here, a case where a plurality of integrated circuits are provided over a substrate and then the plurality of integrated circuits are separated from the substrate will be described with reference to the drawings.

  First, as illustrated in FIG. 1A, a substrate 100 is prepared, and a separation layer 101 is provided over the substrate 100. Specifically, for example, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a quartz substrate, a ceramic substrate, or the like can be used as the substrate 100. Alternatively, a metal substrate containing stainless steel or a semiconductor substrate with an insulating film formed on the surface thereof may be used. A substrate made of a synthetic resin having flexibility such as plastic generally tends to have a lower heat resistant temperature than the above substrate, but can be used as long as it can withstand the processing temperature in the manufacturing process. . The surface of the substrate 100 may be planarized by polishing such as a CMP method.

The separation layer 101 is formed using a metal such as tungsten (W), molybdenum (Mo), niobium (Nb), or titanium (Ti), or a film containing silicon. The crystal structure of the film containing silicon may be any of amorphous, microcrystalline, and polycrystalline. In this embodiment, a metal film containing W is used as the separation layer 101. Note that a method for forming W can be formed by a CVD method, a sputtering method, an electron beam, or the like. Here, the W is formed by a sputtering method. In the case where the substrate and the thin film integrated circuit are physically separated in a later step, an oxide (for example, WO _x ) may be formed over a film containing a metal (for example, W) or silicon. In addition to W, Mo and MoOx, Nb and NbOx, Ti and TiOx, or the like (X = 2 to 3) can be used as a combination of a metal film and a metal oxide film.

  In FIG. 1, the peeling layer 101 is formed directly on the substrate 100, but a base film may be formed between the substrate 100 and the peeling layer 101. The base film is a single insulating film containing oxygen or nitrogen, such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) (x> y), or the like. A layer structure or a stacked structure thereof can be used. In particular, when there is a concern about contamination from the substrate, a base film is preferably formed between the substrate 100 and the peeling layer 101.

  Next, a layer 102 having an integrated circuit formed of a thin film transistor (TFT) (hereinafter referred to as a TFT layer 102) is formed over the separation layer 101 (FIG. 1B). The TFT layer 102 may have any configuration, and for example, an LSI, a CPU, a memory, or the like can be provided.

  Note that the semiconductor film included in the TFT layer 102 has a thickness of 0.2 μm or less, typically 40 nm to 170 nm, preferably 50 nm to 150 nm. Since such a very thin semiconductor film is used, the integrated circuit can be made thinner than a chip formed from a silicon wafer.

  Next, a protective film 103 is formed over the TFT layer 102 (FIG. 1C). When the TFT layer 102 is separated from the substrate 100, the TFT layer 102 may warp due to stress or the like, and the thin film transistor included in the TFT layer may be destroyed. In particular, as the TFT layer 102 is formed thinner, the risk of the TFT layer 102 warping becomes more prominent. Therefore, warping of the TFT layer 102 after peeling can be prevented by forming a protective film on the TFT layer 102 and reinforcing it before peeling the TFT layer 102 from the substrate 100. Note that a schematic diagram of a top view of FIG. 1C is illustrated in FIG. 3A illustrates the case where twelve thin film integrated circuits are formed over the substrate 100, and a cross-sectional view taken along line AB corresponds to FIG.

  As the protective film 103, a resin material such as an epoxy resin, an acrylic resin, a phenol resin, a novolac resin, a melamine resin, a urethane resin, or a silicon resin can be used. In addition, organic materials such as benzocyclobutene, parylene, flare, and polyimide, siloxane (a skeleton structure is formed by a bond of silicon (Si) and oxygen (O), and an organic group containing at least hydrogen as a substituent (for example, an alkyl group) Group, aromatic hydrocarbon), or a fluoro group as a substituent, or an organic group containing at least hydrogen and a fluoro group as a substituent. It may be formed using a compound material made by the above, a composition material containing a water-soluble homopolymer and a water-soluble copolymer, and the like. The protective film 103 can be formed by a screen printing method or a droplet discharge method. The droplet discharge method is a method in which droplets (also referred to as dots) of a composition containing a material such as a conductive film or an insulating film are selectively discharged (jetted) and formed at an arbitrary location. Is also called an inkjet method. In the case where the etching agent is resistant, an inorganic material may be used without being limited to the resin material.

  Further, although the case where the protective film 103 is formed on the upper surface of the TFT layer 102 is shown in FIG. 1, the protective film 103 may be formed so as to cover the side surface simultaneously with the upper surface of the TFT layer 102. In this case, when the TFT layer 102 is peeled from the substrate 100, damage or destruction of the TFT layer 102 can be prevented more effectively. However, in this case, care must be taken not to completely close the opening 104 for introducing the etching agent later.

Subsequently, an etchant is introduced into the opening 104, and the separation layer 101 is removed (FIG. 1D and FIG. 3B). In this embodiment mode, the release layer and the etching agent are chemically reacted to remove the release layer. As the etchant, a gas or liquid containing halogen fluoride (interhalogen compound) that easily reacts with the release layer can be used. In this embodiment mode, chlorine trifluoride gas (ClF ₃ ) that reacts well with W used for the separation layer 102 is used. In addition, CF ₄ , SF ₆ , NF ₃ , F ₂ or the like may be used, and the practitioner may select as appropriate.

  After removing the release layer 101, the substrate 100 is separated. In this embodiment mode, since the separation layer 101 is completely removed, the substrate 100 and the TFT layer 102 can be separated without using physical means (FIG. 1E).

  The TFT layer 102 separated from the substrate 100 may be mounted on an article as it is because the protective film 103 for reinforcement is provided, or may be mounted in a state of being transferred to a separate transfer substrate. A flexible substrate is preferably used as the transfer substrate. As the flexible substrate, a substrate made of plastic such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or polyethersulfone (PES), or a synthetic resin having flexibility such as acrylic is used. Can do.

  Further, as an adhesive for bonding the peeled TFT layer 102 and the flexible substrate, an adhesive such as a thermosetting resin, an ultraviolet curable resin, an epoxy resin adhesive, a resin additive, or a double-sided tape can be used. .

  When the TFT layer 102 is transferred to a flexible substrate after peeling, the breaking strength of the thin film integrated circuit can be increased. Further, as compared with a thin film integrated circuit formed over an insulating substrate, light weight and thin film can be achieved, and flexibility can be increased. Further, the TFT layer 102 may be sealed by a laminating process using a flexible substrate.

  Further, the peeled substrate 100 can be reused. As a result, cost reduction can be achieved in manufacturing a semiconductor device using a substrate. Therefore, cost reduction can be achieved even when a quartz substrate having a higher cost than a glass substrate is used. Note that when the substrate is reused, it is desirable to control the substrate so that scratches are not generated in the peeling process. However, even when scratches are generated, planarization may be performed by forming an organic resin or inorganic resin film by a coating method or a droplet discharge method, or by grinding or polishing.

  As described above, when a thin film integrated circuit is formed over a substrate having an insulating surface, the shape of the base substrate is not limited as compared with a chip manufactured using a silicon wafer in which the chip is extracted from a circular silicon wafer. Therefore, the productivity of semiconductor devices can be increased and mass production can be performed. Furthermore, since the insulating substrate can be reused, the cost can be reduced.

(Embodiment 2)
In this embodiment, a method for separating a substrate and a thin film integrated circuit provided over the substrate by a method different from that in Embodiment 1 is described with reference to FIGS.

  In this embodiment mode, the steps up to FIG. 1C can be performed in the same manner as in Embodiment Mode 1. Therefore, the materials and structures described in Embodiment Mode 1 are used up to FIG.

After that, in this embodiment mode, an etchant is introduced into the opening 104 (FIG. 2A), and at least a part of the peeling layer located below the TFT layer 102 is left without completely removing the peeling layer 101. (FIG. 2 (B)). The amount of the release layer remaining can be controlled by setting the etching flow rate and the reaction time in consideration of the reaction between the release layer and the etching agent. As the release layer, any of the materials described in Embodiment Mode 1 can be used. Note that this embodiment mode also shows a case where a metal film containing W is used as a peeling layer and ClF ₃ is used as an etchant.

  Subsequently, the substrate 100 and the TFT layer 102 are peeled off. In this embodiment mode, the substrate 100 and the TFT layer 102 are separated using physical means. Here, an auxiliary substrate 105 for peeling is provided on the upper surface of the protective film 103 formed to reinforce the TFT layer 102 (FIG. 2C). As an adhesive used to bond the protective film 103 and the auxiliary substrate 105, an adhesive such as a thermosetting resin, an ultraviolet curable resin, an epoxy resin adhesive, a resin additive, or a double-sided tape can be used. As the auxiliary substrate 105, a flexible substrate is preferably used. For example, a sheet material in which an adhesive is provided on a flexible film such as polyester can be used.

  In this embodiment mode, the substrate 100 and the TFT layer 102 are separated using physical means. Therefore, the weaker the interface at the interface between the release layer 101 and the TFT layer 102, the easier the release and the less damage to the TFT layer. Therefore, it is preferable to previously form a layer that easily peels (here, the peeling layer 101) between the substrate 100 and the TFT layer 102. In addition, as described in Embodiment Mode 1, a metal oxide may be provided over a metal film used as a peeling layer. For example, when W or Mo is used as a release layer, after forming SiOx on W or Mo, WOx or MoOx (X = 2 to 3) is formed on the surface of W or Mo by heat treatment or the like, respectively. To do. Thus, by forming the WOx and MoOx metal oxide films on the W and Mo metal films, respectively, the adhesion between the release layer and the SiOx is reduced and the film is easily peeled off, and the release layer is not completely removed. However, the substrate and the thin film integrated circuit can be easily separated.

  Subsequently, the TFT layer 102 is physically peeled from the substrate 100 using the auxiliary substrate 105 (FIG. 2D). The auxiliary substrate 105 may be anything as long as it is rigid, but it is preferable to use a flexible substrate, for example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polyethersulfone (PES). A substrate made of plastic or synthetic resin such as acrylic can be used. As an adhesive used to bond the protective film 103 and the auxiliary substrate 105, an adhesive such as a thermosetting resin, an ultraviolet curable resin, an epoxy resin adhesive, a resin additive, or a double-sided tape can be used. In addition, the auxiliary substrate 105 can be bonded to the protective film 103 using a flexible film or tape having an adhesive surface on one surface in advance.

  Through the above steps, the TFT layer 102 can be peeled from the substrate 100. By using the method shown in this embodiment mode, the TFT layer 102 after peeling can be obtained in a regularly arranged state as before peeling. That is, since the peeling is performed without completely removing the peeling layer 101, the TFT layer adhered to the auxiliary substrate 105 can be obtained in the same arrangement as before peeling.

In addition, after the TFT layer 102 is peeled from the substrate 100, the auxiliary substrate 105 can be selectively cut by dicing, scribing, or laser cutting, and each TFT layer 102 can be taken out. For example, it can be cut using a laser that is absorbed by the glass substrate, for example a CO ₂ laser.

  In addition, when the strength of the TFT layer is not sufficient, the TFT layer 102 may be separately transferred to the transfer substrate. As the transfer substrate, a flexible substrate is preferable. As the flexible substrate, a substrate made of plastic such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or polyethersulfone (PES), or a synthetic resin having flexibility such as acrylic is used. Can do. In addition, when there is a problem with the strength of the TFT layer 102, it is preferable to perform a process such as laminating.

  Further, the peeled substrate 100 can be reused. As a result, cost reduction can be achieved in manufacturing a semiconductor device using a substrate. Therefore, cost reduction can be achieved even when a quartz substrate having a higher cost than a glass substrate is used. Note that when the substrate is reused, it is desirable to control the substrate so that scratches are not generated in the peeling process. However, even when scratches are generated, an organic resin or inorganic resin film may be formed by a coating method or a droplet discharge method, and planarization may be performed.

  As described above, when a thin film integrated circuit is formed over a substrate having an insulating surface, the shape of the base substrate is not limited as compared with a chip manufactured using a silicon wafer in which the chip is extracted from a circular silicon wafer. Therefore, the productivity of thin film integrated circuits can be increased and mass production can be performed. Furthermore, since the insulating substrate can be reused, the cost can be reduced.

  Note that this embodiment mode can be freely combined with the above embodiment modes.

(Embodiment 3)
In this embodiment, a method for separating a substrate and a thin film integrated circuit provided over the substrate by a method different from that in the above embodiment is described with reference to drawings. Specifically, a thin film integrated circuit is formed over a substrate through a peeling layer having an opening, and the peeling layer is removed to physically connect the substrate and the thin film integrated circuit directly bonded in the opening. The case where peeling is performed using means will be described.

  First, as shown in FIG. 1, the separation layer 101 is provided over the substrate 100 (FIG. 4A).

  Next, using a photolithography technique, the peeling layer 101 is etched to form a pattern including a plurality of openings 106 (FIG. 4B). In addition, a pattern may be formed by forming a resist by etching a droplet and etching it. The droplet discharge method is a method in which droplets (also referred to as dots) of a composition containing a material such as a conductive film or an insulating film are selectively discharged (jetted) and formed at an arbitrary location. Is also called an inkjet method. Note that the opening 106 is preferably provided in a portion of the TFT layer to be formed later, where a region where a transistor is to be formed is avoided.

  Next, a layer 102 (hereinafter referred to as a TFT layer 102) having an integrated circuit formed using a thin film transistor (TFT) is selectively formed so as to cover the separation layer 101 and the opening 106 (FIG. 4C). ). The TFT layer may have any configuration. For example, a large scale integrated circuit (LSI), a central processing unit (CPU), or a memory may be provided.

  Note that the semiconductor film in the TFT layer 102 has a thickness of 0.2 μm or less, typically 40 nm to 170 nm, preferably 50 nm to 150 nm. Since such a very thin semiconductor film is used, the integrated circuit can be made thinner than a chip formed from a silicon wafer.

  Next, a protective film 103 is formed over the TFT layer 102 (FIG. 4D). When the TFT layer 102 is separated from the substrate 100, the TFT layer 102 may warp due to stress or the like, and the TFT may be destroyed. In particular, as the TFT layer 102 is formed thinner, the risk of the TFT layer 102 warping becomes more prominent. Therefore, warping of the TFT layer 102 after peeling can be prevented by forming and reinforcing a protective film on the TFT layer 102 before peeling. A top view at this time is shown in FIG. 6A illustrates the case where 12 thin film integrated circuits are formed over the substrate 100, and a cross-sectional view taken along line AB corresponds to FIG.

  In FIG. 4, the protective film 103 is formed on the upper surface of each TFT layer 102. However, the protective film 103 may be formed so as to cover the side surface simultaneously with the upper surface. In this case, it works as a more sufficient protective film when the integrated circuit is peeled off. However, in this case, care must be taken not to block the opening 104 for introducing an etching agent used for removing the peeling layer later.

Subsequently, an etchant is introduced into the opening 104 (FIG. 4E), and the peeling layer 101 is removed (FIGS. 5A and 6B). In this embodiment mode, the peeling layer 101 and the etching agent are chemically reacted to remove the peeling layer 101. As the etchant, a gas or liquid containing halogen fluoride (interhalogen compound) that easily reacts with the release layer can be used. In this embodiment mode, chlorine trifluoride gas (ClF ₃ ) that reacts well with W used for the separation layer 102 is used. In addition, a gas containing fluorine such as CF ₄ , SF ₆ , NF ₃ , and F ₂ may be used as a plasma, or a strong alkali solution such as tetraethylammonium hydroxide (TMAH) may be used. Good.

  After removing the peeling layer 101, the substrate 100 is peeled off. In this embodiment mode, the semiconductor layer 102 formed in the portion of the opening 106 is partially connected to the substrate 100 even after the separation layer is completely removed (FIG. 5A). Therefore, the substrate 100 and the TFT layer 102 are separated using physical means. Here, an auxiliary substrate 105 for peeling is provided on the upper surface of the protective film 103 formed to reinforce the TFT layer 102 (FIG. 5B).

  The auxiliary substrate 105 may be anything as long as it is rigid, but it is preferable to use a flexible substrate, for example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polyethersulfone (PES). A substrate made of plastic or synthetic resin such as acrylic can be used. As an adhesive used to bond the protective film 103 and the auxiliary substrate 105, an adhesive such as a thermosetting resin, an ultraviolet curable resin, an epoxy resin adhesive, a resin additive, or a double-sided tape can be used. In addition, the auxiliary substrate 105 can be formed by adhering to the protective film 103 using a flexible film or tape having an adhesive surface on one surface in advance.

  Subsequently, the TFT layer 102 is physically peeled from the substrate 100 using the auxiliary substrate 105 (FIG. 5C). Through the above steps, the TFT layer 102 can be peeled from the substrate 100. By using the method shown in this embodiment, the TFT layer 102 does not fall apart even after being peeled off and can be obtained in a regularly arranged state as before peeling.

  After that, the TFT layer 102 separated from the substrate 100 may be mounted on an article as it is because the reinforcing protective film 103 is provided, or may be mounted on a transfer substrate separately. As the transfer substrate, a flexible substrate is preferable. As the flexible substrate, a substrate made of plastic such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or polyethersulfone (PES), or a synthetic resin having flexibility such as acrylic is used. Can do.

  As an adhesive for adhering the flexible substrate, an adhesive such as a thermosetting resin, an ultraviolet curable resin, an epoxy resin adhesive, a resin additive, or a double-sided tape can be used.

  When transferred to a flexible substrate, the breaking strength of the thin film integrated circuit can be increased. Further, as compared with a thin film integrated circuit formed over an insulating substrate, light weight and thin film can be achieved, and flexibility can be increased.

  Further, the peeled substrate can be reused. As a result, cost reduction can be achieved in manufacturing a semiconductor device. In the case of reuse, it is desirable to control so as not to generate scratches on the substrate in the peeling process. However, even when scratches are generated, an organic resin or inorganic resin film may be formed by a coating method or a droplet discharge method, and planarization may be performed.

  As described above, when a thin film integrated circuit is formed over a substrate having an insulating surface, the shape of the base substrate is not limited as compared with a chip manufactured using a silicon wafer in which the chip is extracted from a circular silicon wafer. Therefore, the productivity of thin film integrated circuits can be increased and mass production can be performed. Furthermore, since the insulating substrate can be reused, the cost can be reduced.

  Note that this embodiment mode can be freely combined with the above embodiment modes.

(Embodiment 4)
In this embodiment, a method for separating a substrate and a thin film integrated circuit provided over the substrate by a method different from that in the above embodiment is described with reference to drawings.

  First, as illustrated in FIG. 7A, a substrate 2000 is prepared, and a peeling layer 2010 is provided thereover. Specifically, any of the substrate materials described in Embodiment 1 can be used for the substrate 2000. Further, the surface of the substrate 2000 may be planarized in advance by polishing such as a CMP method.

The peeling layer 2010 is formed using a metal such as tungsten (W), titanium (Ti), niobium (Nb), or molybdenum (Mo), or a film containing silicon (Si). The crystal structure of the film containing silicon may be any of amorphous, microcrystalline, and polycrystalline. In this embodiment, a metal film containing W is used as the peeling layer 2010. Note that a method for forming W can be formed by a CVD method, a sputtering method, an electron beam method, or the like. Here, the W is formed by a sputtering method. In the case where the substrate is physically peeled off in a later step, an oxide (for example, WO _x ) may be formed on the film (for example, W). In addition, as a combination of a film and an oxide film, Mo and MoOx, Nb and NbOx, Ti and TiOx, or the like (X = 2 to 3) can be used. Further, as described above, a base film may be formed between the substrate 2000 and the peeling layer 2010 in order to prevent contamination due to diffusion of impurities.

  Next, a layer 2020 having an integrated circuit formed using a thin film transistor (TFT) (hereinafter referred to as a TFT layer 2020) is selectively formed over the separation layer 2010 (FIG. 7B). The TFT layer may have any configuration. For example, a large scale integrated circuit (LSI), a central processing unit (CPU), or a memory may be provided.

  Note that the semiconductor film in the TFT layer 2020 has a thickness of 0.2 μm or less, typically 40 nm to 170 nm, preferably 50 nm to 150 nm. Since such a very thin semiconductor film is used, the integrated circuit can be made thinner than a chip formed from a silicon wafer.

  Next, a protective film 2030 is formed over the TFT layer 2020 (FIG. 7C). When the TFT layer 2020 is separated from the substrate 2000, the TFT layer 2020 may warp due to stress and the TFT may be destroyed. In particular, as the TFT layer 2020 is formed thinner, the risk of the TFT layer 2020 warping becomes more prominent. Therefore, warping of the TFT layer 2020 after peeling can be prevented by forming a protective film on the TFT layer 2020 and reinforcing it before peeling.

  In this embodiment, a thick portion (convex region 2040) is selectively formed on at least part of the upper surface of the protective film 2030. The convex region 2040 is preferably provided in a portion of the previously formed TFT layer that is located outside the region where the transistor is formed. In the present embodiment, four convex regions 2040 are formed at the corners of the protective film 2030, but any number may be formed at any portion. A top view at this time is shown in FIG. FIG. 9A illustrates the case where twelve thin film integrated circuits are formed over the substrate 2000, and a cross-sectional view taken along line EF corresponds to FIG.

  As the protective film 2030, a resin material such as an epoxy resin, an acrylic resin, a phenol resin, a novolac resin, a melamine resin, a urethane resin, or a silicon resin can be used. Also formed using organic materials such as benzocyclobutene, parylene, flare, polyimide, compound materials made by polymerization of siloxane materials such as siloxane resins, composition materials containing water-soluble homopolymers and water-soluble copolymers, etc. May be. The protective film 2030 can be formed by a screen printing method or a droplet discharge method.

  In FIG. 7, the protective film 2030 is formed on the upper surface of the TFT layer 2020. However, the protective film 2030 may be formed so as to cover the side surface simultaneously with the upper surface. In this case, it works as a more sufficient protective film when the integrated circuit is peeled off. However, in this case, it is necessary to prevent the opening 2050 for introducing an etching agent for removing the peeling layer later from being blocked.

Subsequently, an etchant is introduced into the opening 2050 (FIG. 7D), and the peeling layer 2010 is removed (FIGS. 7E and 9B). In this embodiment mode, the release layer 2010 is removed by chemically reacting the release layer 2010 with an etchant. As the etchant, a gas or liquid containing halogen fluoride (interhalogen compound) that easily reacts with the release layer can be used. In this embodiment mode, chlorine trifluoride gas (ClF ₃ ) that reacts well with W used for the release layer 2020 is used. In addition to this, a gas containing fluorine such as CF ₄ , SF ₆ , NF ₃ , and F ₂ may be used as a plasma, or a strong alkali solution such as tetraethylammonium hydroxide (TMAH) may be used. Good.

  At this time, in the release layer 2010, the progress of the etching of the release layer located below the convex region 2040 is delayed as compared with the other release layer portions. In the configuration of the present invention, the rate of progress of the peeling layer etching is inversely proportional to the thickness of the protective film formed on the peeling layer. That is, the thicker the protective film, the slower the etching progress rate.

Therefore, by providing a thick portion (convex region 2040) over the protective film 2030 and adjusting the etching time, the peeling layer below the convex region remains (FIG. 7E). That is, the TFT layer 2020 and the substrate 2000 are bonded by the remaining portion 2060 of the peeling layer.

  Next, the substrate 2000 and the TFT layer 2020 are separated using physical means. Here, an auxiliary substrate 2070 for peeling is provided on the upper surface of the protective film 2030 formed to reinforce the TFT layer 2020 (FIG. 8A). The auxiliary substrate 2070 may be anything as long as it is rigid, but it is preferable to use a flexible substrate, for example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polyethersulfone (PES). A substrate made of plastic or synthetic resin such as acrylic can be used. As an adhesive used for bonding the protective film 2030 and the auxiliary substrate 2070, an adhesive such as a thermosetting resin, an ultraviolet curable resin, an epoxy resin adhesive, a resin additive, or a double-sided tape can be used. In addition, the auxiliary substrate 2070 can be bonded to the protective film 2030 using a flexible film or tape having an adhesive surface on one surface in advance.

  Note that in this embodiment mode, the substrate 2000 and the TFT layer 2020 are separated using physical means. Therefore, the weaker the adhesion at the interface between the peeling layer 2010 and the TFT layer 2020, the easier the peeling and the less damage to the TFT layer. A metal oxide may be formed on the metal film. For example, when W or Mo is used as a release layer, after forming SiOx on W or Mo, WOx or MoOx (X = 2 to 3) is formed on the surface of W or Mo by heat treatment or the like, respectively. To do. Thus, by forming the WOx and MoOx metal oxide films on the W and Mo metal films, respectively, the adhesion between the release layer and the SiOx is reduced and the film is easily peeled off, and the release layer is not completely removed. However, the substrate and the thin film integrated circuit can be easily separated.

  Subsequently, the TFT layer 2020 is peeled off from the substrate 2000 using a physical means using the auxiliary substrate 2070 (FIG. 8B). In the case where a peeling layer is attached to the TFT layer 2020 after peeling, it is preferably removed again using an etching agent.

  Through the above steps, the TFT layer 2020 formed on the substrate 2000 can be peeled off. By using the method described in this embodiment mode, the TFT layer 2020 after peeling can be obtained in a state of being arranged in the same manner as before peeling without being separated.

  After that, the TFT layer 2020 separated from the substrate 2000 may be mounted on the article as it is because the reinforcing protective film 2030 is provided, or may be mounted on the transfer substrate separately. As the transfer substrate, a flexible substrate is preferable. As the flexible substrate, a substrate made of plastic such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or polyethersulfone (PES), or a synthetic resin having flexibility such as acrylic is used. Can do.

  As an adhesive for adhering the flexible substrate, an adhesive such as a thermosetting resin, an ultraviolet curable resin, an epoxy resin adhesive, a resin additive, or a double-sided tape can be used.

  When transferred to a flexible substrate, the breaking strength of the thin film integrated circuit can be increased. Further, as compared with a thin film integrated circuit formed over an insulating substrate, light weight and thin film can be achieved, and flexibility can be increased.

  Further, the peeled substrate can be reused. As a result, cost reduction can be achieved in manufacturing a semiconductor device. In the case of reuse, it is desirable to control so as not to generate scratches on the substrate in the peeling process. However, even when scratches are generated, an organic resin or inorganic resin film may be formed by a coating method or a droplet discharge method, and planarization may be performed.

  As described above, when a thin film integrated circuit is formed over a substrate having an insulating surface, the shape of the base substrate is not limited as compared with a chip manufactured using a silicon wafer in which the chip is extracted from a circular silicon wafer. Therefore, the productivity of semiconductor devices can be increased and mass production can be performed. Furthermore, since the insulating substrate can be reused, the cost can be reduced.

  Note that this embodiment mode can be freely combined with the above embodiment modes.

  In this example, a more specific structure of the peeling method described in Embodiment Mode 1 and Embodiment Mode 2 will be described with reference to the drawings.

  First, as illustrated in FIG. 10A, the separation layer 201 is formed over the substrate 200. Specifically, for example, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a quartz substrate, a ceramic substrate, or the like can be used as the substrate 200. Alternatively, a metal substrate containing stainless steel or a semiconductor substrate with an insulating film formed on the surface thereof may be used. A substrate made of a synthetic resin having flexibility such as plastic generally tends to have a lower heat resistant temperature than the above substrate, but can be used as long as it can withstand the processing temperature in the manufacturing process. . The surface of the substrate 200 may be planarized by polishing such as a CMP method. In this embodiment, a quartz substrate is used as the substrate 200.

  As the peeling layer 201, W formed by sputtering and having a thickness of 30 nm to 1 μm, preferably 30 nm to 50 nm is used. In addition to the sputtering method, W can be formed by a CVD method. In this example, a metal film containing W is used for the peeling layer 201, but other materials described in the above embodiments may be used.

  An insulating film is selectively formed in a region where a thin film integrated circuit is formed over the separation layer 201 (FIG. 10B). The insulating film can be formed with a single-layer structure or a stacked structure. In this embodiment, the insulating film is formed with a stacked structure including the first insulating film 202 and the second insulating film 203. For example, a silicon oxide film is used as the first insulating film, and a silicon oxynitride film is used as the second insulating film. In addition, a three-layer structure including a silicon oxide film as the first insulating film, a silicon nitride oxide film as the second insulating film, and a silicon oxynitride film as the third insulating film may be formed. Note that in the case where peeling is performed using physical means in a later step, it is preferable to use a silicon oxide film as the first insulating film 202 which is in direct contact with the peeling layer 201.

  Next, a thin film transistor is formed over the insulating film 203 (FIG. 10C). The thin film transistor is provided with at least gate electrodes 214 and 215 formed through semiconductor films 211 and 212 patterned into a desired shape and an insulating film (gate insulating film) 213 functioning as a gate insulating film.

  The semiconductor films 211 and 212 are amorphous semiconductors, SAS (Semi Amorphous Semiconductor) in which an amorphous state and a crystalline state are mixed, and crystal grains of 0.5 nm to 20 nm can be observed in the amorphous semiconductor. It may have any state selected from a microcrystalline semiconductor and a crystalline semiconductor.

  If a substrate that can withstand the film formation temperature, for example, a quartz substrate is used, a crystalline semiconductor film may be formed on the substrate by a CVD method or the like.

  In this embodiment, an amorphous semiconductor film is formed, and a crystalline semiconductor film crystallized by heat treatment is formed. The heat treatment can be performed using a heating furnace, laser irradiation, irradiation of light emitted from a lamp instead of laser light (lamp annealing), or a combination thereof.

When laser irradiation is used, a continuous wave laser (CW laser) or a pulsed laser (pulse laser) can be used. Lasers include Ar laser, Kr laser, excimer laser, YAG laser, Y ₂ O ₃ laser, YVO ₄ laser, YLF laser, YAlO ₃ laser, glass laser, ruby laser, alexandride laser, Ti: sapphire laser, copper vapor One or a plurality of lasers or gold vapor lasers can be used. By irradiating the fundamental wave of such a laser and the second to fourth harmonics of the fundamental wave, a crystal having a large grain size can be obtained. For example, a second harmonic (532 nm) or a third harmonic (355 nm) of an Nd: YVO ₄ laser (fundamental wave 1064 nm) can be used. In this case, a laser power density is about 0.01 to 100 MW / cm ² (preferably 0.1 to 10 MW / cm ²⁾ is required. Then, irradiation is performed at a scanning speed of about 10 to 2000 cm / sec.

  At this time, for example, an optical system as shown in FIG. 18A is used and crystallization is performed using a CW laser. First, the CW laser beam emitted from the laser oscillator 290 is elongated by the optical system 291 and processed into a linear shape. Specifically, a cylindrical lens or a convex lens included in the optical system 291 can be processed into a linear shape when the laser beam passes. At this time, it is good to process so that the length of the long axis of a spot may be set to 200-350 micrometers.

  Thereafter, the linearly processed laser beam is incident on the semiconductor film 124 via the galvanometer mirror 293 and the fθ lens 294. At this time, the linear laser is adjusted so as to form a laser spot 282 having a predetermined size on the semiconductor film. Further, the fθ lens 294 can make the shape of the laser spot 282 constant on the surface of the irradiated object regardless of the angle of the galvanometer mirror.

  At this time, the device (control device) 296 that controls the vibration of the galvanometer mirror vibrates the galvanometer mirror, that is, the angle of the mirror changes, and the laser spot 282 is in one direction (for example, the X-axis direction in the figure). ) For example, when a galvanometer mirror vibrates in a half cycle, the laser beam is adjusted so as to move a certain width in the X-axis direction on the semiconductor film (outward path).

  Then, the semiconductor film is moved in the Y-axis direction by the XY stage 295. Similarly, the laser spot moves in the X-axis direction on the semiconductor film by the galvanometer mirror (return path). Using such a reciprocating motion of the laser beam, the laser spot moves along the path 283, and laser annealing is performed.

  At this time, as shown in FIG. 18B, the thin film transistor performs laser annealing so that the carrier moving direction 284 and the moving direction (scanning direction) 283 to the major axis of the laser beam are aligned. For example, in the case of the semiconductor film 230 having the shape shown in FIG. 18B, a source region 230 (s) formed in the semiconductor film so as to be parallel to the moving direction (scanning direction) of the laser beam to the long axis, A channel formation region 230 (c) and a drain region 230 (d) are disposed. As a result, since the grain boundaries crossed by carriers can be reduced or eliminated, the mobility of the thin film transistor can be increased.

  Furthermore, the incident angle of the laser may be θ (0 ° <θ <90 °) with respect to the semiconductor film. As a result, laser interference can be prevented.

  Note that continuous wave fundamental laser light and continuous wave harmonic laser light may be emitted, or continuous wave fundamental laser light and pulsed harmonic laser light are emitted. You may do it. Energy can be supplemented by irradiating a plurality of laser beams.

  In addition, it is a pulse oscillation type laser that oscillates laser light at an oscillation frequency that can irradiate the laser light of the next pulse after the semiconductor film is melted by the laser light and solidifies in the scanning direction. Crystal grains grown continuously can be obtained. That is, a pulse beam in which the lower limit of the oscillation frequency is determined so that the period of pulse oscillation is shorter than the time from when the semiconductor film is melted until it is completely solidified.

  The oscillation frequency of the pulse beam that can be actually used is 10 MHz or more, and a frequency band that is significantly higher than the frequency band of several tens to several hundreds Hz that is normally used is used.

  Note that laser light may be irradiated in an inert gas atmosphere such as a rare gas or nitrogen. Thereby, roughness of the semiconductor surface due to laser light irradiation can be suppressed, and variation in threshold value caused by variation in interface state density can be suppressed.

Alternatively, a microcrystalline semiconductor film may be formed using SiH ₄ and F ₂ , or SiH ₄ and H ₂ , and then crystallized by performing laser irradiation as described above.

  As another heat treatment, when a heating furnace is used, the amorphous semiconductor film is heated at 500 to 550 ° C. for 2 to 20 hours. At this time, the temperature may be set in multiple stages in the range of 500 to 550 ° C. so that the temperature gradually increases. In the first low-temperature heating step, hydrogen or the like of the amorphous semiconductor film comes out, so that so-called hydrogen dipping that reduces film roughness during crystallization can be performed. Furthermore, it is preferable to form a metal element that promotes crystallization, such as Ni, on the amorphous semiconductor film because the heating temperature can be reduced. Even crystallization using such a metal element may be heated to 600 to 950 ° C.

  However, when a metal element is formed, there is a concern that the electrical characteristics of the semiconductor element may be adversely affected. Therefore, it is necessary to perform a gettering step for reducing or removing the metal element. For example, a process may be performed so as to capture a metal element using an amorphous semiconductor film as a gettering sink.

Alternatively, a crystalline semiconductor film may be formed directly on the surface to be formed. In this case, a crystalline semiconductor film is directly formed on the surface to be formed using heat or plasma using a fluorine-based gas such as GeF ₄ or F ₂ and a silane-based gas such as SiH ₄ or Si ₂ H _6. Can be formed. In the case where a crystalline semiconductor film is directly formed as described above and high temperature treatment is required, a quartz substrate with high heat resistance is preferably used.

  Thus, it is thought that there is an influence of heating on the peeling layer by the process of heating the semiconductor film. For example, when heat treatment is performed using a furnace, or when laser irradiation is performed using a wavelength of 532 nm, energy may reach the release layer.

  On the other hand, in order to efficiently crystallize the semiconductor film, the structure of the base film can be selected so that the energy of the laser does not reach the release layer. For example, the material, film thickness, and stacking order of the base film are selected.

A semiconductor film formed by any one of the means described above has more hydrogen than a chip formed from a silicon wafer. Specifically, hydrogen can be formed so as to have 1 × 10 ¹⁹ to 1 × 10 ²² / cm ³ , preferably 1 × 10 ^{19 to} 5 × 10 ²⁰ / cm ³ . This hydrogen can provide a so-called defect termination effect that alleviates defects in the semiconductor film. In addition, the flexibility of the thin film integrated circuit can be increased by hydrogen.

  Furthermore, by setting the ratio of the area occupied by the patterned semiconductor film in the thin film integrated circuit to 1 to 30%, the breakdown and peeling of the thin film transistor due to bending stress can be prevented.

  The gate insulating film 213 is formed so as to cover the semiconductor films 211 and 212. The gate insulating film 213 can be formed by stacking a single layer or a plurality of films using, for example, silicon oxide, silicon nitride, silicon nitride oxide, or the like. As a film formation method, a plasma CVD method, a sputtering method, or the like can be used. Here, a sputtering method is used to form an insulating film containing silicon with a thickness of 30 nm to 200 nm.

  The gate electrodes 214 and 215 are formed by forming a first conductive layer on the gate insulating film 213 and a second conductive layer thereon, and patterning the first conductive layer and the second conductive layer. Can do. In this embodiment, tantalum nitride (TaN) is used as the first conductive layer and tungsten (W) is used as the second conductive layer. Both the TaN film and the W film may be formed by sputtering, the TaN film may be formed in a nitrogen atmosphere using a Ta target, and the W film may be formed using a W target.

  In this embodiment, the first conductive layer is TaN and the second conductive layer is W. However, the present invention is not limited to this, and the first conductive layer and the second conductive layer are both Ta, W, Ti, You may form with the element chosen from Mo, Al, Cu, Cr, Nd, or the alloy material or compound material which has the said element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. Further, an AgPdCu alloy may be used. Furthermore, the combination may be selected as appropriate. The film thickness may be in the range of 20 to 100 nm for the first conductive layer and 100 to 400 nm for the second conductive layer. In this embodiment, a two-layer structure is used, but a single layer may be used, or a three-layer or more structure may be used.

  Next, an impurity imparting n-type or p-type conductivity is selectively added to the semiconductor films 211 and 212 using a gate electrode or a resist pattern formed and patterned as a mask. The semiconductor films 211 and 212 include a channel formation region and an impurity region (including a source region, a drain region, a GOLD region, and an LDD region), and an n-channel TFT 204 or a p-channel type depending on the conductivity type of the added impurity element. It can be distinguished from the TFT 205.

  In FIG. 10, an n-channel TFT 204 has a sidewall on the side wall of the gate electrode 214, and a source region, a drain region, and an LDD region in which an impurity imparting n-type conductivity is selectively added to the semiconductor film 211. Is formed. In the p-channel TFT 205, a source region and a drain region to which an impurity imparting p-type conductivity is selectively added are formed in the semiconductor film 212. Here, a structure in which sidewalls are formed on the sidewalls of the gate electrodes 214 and 215 and an LDD region is selectively formed in the n-channel TFT 204 is shown; however, the present invention is not limited to this structure. A region may be formed, or the p-channel TFT 205 may not be provided with a sidewall.

  Alternatively, a CMOS structure in which the n-channel TFT 204 and the p-channel TFT 205 are combined with each other may be formed. Note that an impurity element (boron, phosphorus, or the like) may be added in advance to the channel region of the semiconductor film located below the gate electrode by doping or the like. By adding an impurity element to the channel region of the semiconductor film, a thin film transistor with excellent characteristics can be obtained by suppressing variation in threshold value and the like.

  Next, an interlayer insulating film 206 is formed (FIG. 10D). As the interlayer insulating film 206, an inorganic insulating film or an organic insulating film can be used. As the inorganic insulating film, a silicon oxide film or a silicon oxynitride film formed by a CVD method, a silicon oxide film applied by an SOG (Spin On Glass) method, or the like can be used. As an organic insulating film, polyimide, A film made of polyamide, BCB (benzocyclobutene), acrylic, positive photosensitive organic resin, negative photosensitive organic resin, or the like can be used. Alternatively, a stacked structure of an acrylic film and a silicon oxynitride film may be used.

  A siloxane material such as a siloxane resin can be used for the interlayer insulating film. A siloxane material corresponds to a material including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent.

  Siloxane materials can be classified according to their structure into, for example, silica glass, alkylsiloxane polymers, alkylsilsesquioxane polymers, hydrogenated silsesquioxane polymers, hydrogenated alkylsilsesquioxane polymers, and the like. Alternatively, the interlayer insulating film may be formed using a material containing a polymer (polysilazane) having a Si—N bond.

  By using the above material, an interlayer insulating film having sufficient insulation and flatness can be obtained even when the film thickness is reduced. In addition, since the above material has high heat resistance, an interlayer insulating film that can withstand reflow processing in a multilayer wiring can be obtained. Further, since the hygroscopic property is low, an interlayer insulating film with a small amount of dehydration can be formed.

  In this embodiment, a siloxane material is formed as the interlayer insulating film 206. With the interlayer insulating film 206, unevenness due to the TFT formed on the substrate can be reduced and planarized. In particular, since the interlayer insulating film 206 has a strong meaning of planarization, it is preferable to use an insulating film made of a material that is easily planarized.

In addition, a first passivation film may be formed before the interlayer insulating film 206 is formed. As the passivation film, an insulating film containing silicon is formed to a thickness of 100 to 200 nm. As a film forming method, a plasma CVD method or a sputtering method may be used. In addition, a silicon oxynitride silicon film formed from SiH ₄ , N ₂ O, and H ₂ may be used as a passivation film. Of course, the passivation film can be formed as a single layer structure or a stacked structure.

  Further, after forming the interlayer insulating film 206, a second passivation film made of a silicon nitride oxide film or the like may be formed. The film thickness may be approximately 10 to 200 nm, and moisture can be prevented from entering and leaving the interlayer insulating film 206 by the second passivation film. In addition, a silicon nitride film, an aluminum nitride film, an aluminum oxynitride film, a diamond-like carbon (DLC) film, and a carbon nitride (CN) film can be used as the second passivation film.

  Next, the interlayer insulating film 206 is etched to form contact holes reaching the source and drain regions. Subsequently, wirings 207a to 207c that are electrically connected to the source and drain regions are formed. As the wirings 207a to 207c, a single layer or a laminated structure made of one kind of element selected from Al, Ni, C, W, Mo, Ti, Pt, Cu, Ta, Au, and Mn or an alloy containing a plurality of such elements is used. Can be used. Here, it is preferable to form a metal film containing Al. In this embodiment mode, a laminated film of a Ti film and an alloy film containing Al and Ti is formed by patterning. Of course, not only a two-layer structure but also a single-layer structure or a laminated structure of three or more layers may be used. Further, the wiring material is not limited to the laminated film of Al and Ti. For example, the wiring may be formed by forming an Al film or a Cu film on the TaN film and then patterning a laminated film formed with a Ti film.

  Subsequently, an insulating film 208 is formed so as to cover the wirings 207a to 207c. As the insulating film 208, an insulating material containing oxygen or nitrogen such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) (x> y), or the like. A film can be used, but typically, silicon nitride oxide (SiNxOy) is preferably used. Alternatively, a resin film may be used.

  Next, as illustrated in FIG. 11A, a protective film 209 is formed over the insulating film 208. As a material for the protective film 209, a resin material such as an epoxy resin, an acrylic resin, a phenol resin, a novolac resin, a melamine resin, a urethane resin, or a silicon resin can be used. Also, organic materials such as benzocyclobutene, parylene, flare, permeable polyimide, compound materials made by polymerization of siloxane materials such as siloxane resins, composition materials containing water-soluble homopolymers and water-soluble copolymers, etc. You may form using. The protective film 209 can be formed by a screen printing method or a droplet discharge method. In this embodiment, an epoxy resin formed by a screen printing method is used as the protective film 209.

  By providing the protective film 209, the TFT layer 102 can be prevented from warping due to stress when the TFT layer 102 is separated from the substrate 200.

Thereafter, the release film 201 is completely removed. In this embodiment, the release layer and the etching agent are chemically reacted to remove the release layer. As shown in FIG. 21, the release layer is removed by introducing a gas or liquid containing halogen fluoride as an etchant. Here, the vacuum means as shown in FIG. 21, using the device 89 with pressing means, the temperature control means, using ClF ₃ (chlorine trifluoride) as the etchant, the temperature: room temperature to 150 DEG ° C., flow rate : The peeling layer is removed under the conditions of 50 sccm and atmospheric pressure: 9 Torr (about 1200 Pa), but is not limited to these conditions. In addition, the apparatus shown in FIG. 21 includes a bell jar 91 that can process a plurality of substrates 200. Then, ClF ₃ 115 is introduced from the gas introduction pipe, and unnecessary gas is exhausted from the exhaust pipe 92. Further, a heating means such as a heater 91 may be provided on the side surface of the apparatus.

As shown in FIG. 11, a gas or liquid containing halogen fluoride is introduced into the opening 104. At this time, the reaction rate can be increased by setting the treatment temperature to 100 ° C. to 300 ° C. by the heating means. As a result, the amount of ClF ₃ gas used can be reduced and the processing time can be shortened.

At this time, an etching agent, a gas flow rate, a temperature, and the like are set so that each layer of the TFT layer 102 is not etched. Since ClF ₃ used in this embodiment has a characteristic of selectively etching W, it selectively removes W as a peeling layer. Therefore, a layer made of a metal film containing W is used for the peeling layer, and an insulating film containing oxygen or nitrogen is used for the base film. Since the difference in reaction rate, that is, the selectivity is high, the peeling layer can be easily removed while protecting the TFT layer 102. In this embodiment, the TFT layer 102 is not etched by ClF ₃ by the end portions of the insulating films provided above and below the TFT layer, the interlayer insulating film exposed on the side surfaces, the gate insulating film, the wiring, and the like.

Note that ClF ₃ can be produced through a process of Cl ₂ (g) + 3F ₂ (g) → 2ClF ₃ (g) by reacting chlorine with fluorine at 200 ° C. or higher. Further, ClF ₃ may be a liquid depending on the temperature of the reaction space (boiling point: 11.75 ° C.), and wet etching can be employed at that time.

As another gas containing halogen fluoride, a gas in which nitrogen is mixed with ClF ₃ or the like may be used.

Further, an etchant that etches the release layer and does not etch the base film is not limited to ClF ₃ , and is not limited to halogen fluoride. For example, a gas containing fluorine such as CF ₄ , SF ₆ , NF ₃ , F _2, etc. can be used as plasma. As another etching agent, a strong alkaline solution such as tetraethylammonium hydroxide (TMAH) may be used.

Further, in the case of chemical removal with a gas containing halogen fluoride such as ClF ₃ , if the condition that a material that is selectively etched is used as a peeling layer and a material that is not etched is used as a base film, the peeling layer and The combination of the base films is not limited to the above materials.

  Next, after removing the peeling layer 201, the substrate 200 is peeled off. When the separation layer 201 is completely removed, the substrate 100 and the TFT layer 102 can be separated without using physical means (FIG. 11B).

  On the other hand, FIGS. 12 and 13 show a method for separating the substrate 200 and the TFT layer 102 without completely removing the peeling layer.

  In FIG. 12A, after forming in the same manner as in FIG. 11A, an etchant is introduced into the opening 104, and the peeling layer 201 is not completely removed, and a part of the peeling layer 221 is left. The amount of the release layer 221 remaining is controlled by adjusting the flow rate of the etchant for peeling and the reaction time.

  After that, an auxiliary substrate 222 is provided over the protective film 209 (FIG. 12B). As the auxiliary substrate 222, a quartz substrate or a flexible substrate is used. In the case of using a flexible substrate, the protective film 209 can be bonded using a flexible film having an adhesive on one surface. In this case, as an adhesive used for bonding the protective film 209 and the auxiliary substrate 222, an adhesive such as a thermosetting resin, an ultraviolet curable resin, an epoxy or acrylic resin adhesive, a resin additive, a tape, or the like can be used. .

  Subsequently, the TFT layer 102 is physically peeled from the substrate 200 using the auxiliary substrate 221 (FIG. 12C). Through the above steps, the TFT layer 102 can be peeled from the substrate 100. By using this method, since the TFT layer can be peeled from the substrate without completely removing the peeling layer, the processing time of the peeling step is improved. Further, the TFT layer 102 after peeling is obtained in a regularly arranged state as before peeling. That is, since the peeling is performed without completely removing the peeling layer 101, the TFT layer bonded to the auxiliary substrate 105 can be obtained in the same arrangement as before peeling. Therefore, the processing time can be improved in the subsequent steps.

  After that, the TFT layer 102 peeled from the substrate 100 may be mounted on an article as it is because the reinforcing protective film 209 is provided, or may be mounted on a transfer substrate separately. FIG. 13 shows a case where a transfer substrate is separately transferred.

  As shown in FIG. 13A, the peeled TFT layer 102 is attached to the transfer substrate 223. As the transfer substrate 223, a flexible substrate is preferably used. As the flexible substrate, a substrate made of plastic such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or polyethersulfone (PES), or a synthetic resin having flexibility such as acrylic is used. Can do. In addition, when there is a problem with the strength of the TFT layer 102, it is preferable to perform a process such as laminating.

Thereafter, the auxiliary substrate 222 is peeled off, and the transfer substrate 223 is selectively cut by dicing, scribing, or laser cutting (FIG. 13B) to separate each thin film integrated circuit (FIG. 13C). ). Here, cutting is performed using a CO ₂ laser absorbed by the glass substrate. Further, an organic resin such as an epoxy resin may be provided around the side surface of the TFT layer 102 for reinforcement. As a result, the TFT layer 102 is protected from the outside, and the mechanical strength can be further improved.

  Further, the peeled substrate 200 can be reused. As a result, cost reduction can be achieved in manufacturing a semiconductor device using a substrate. For example, a quartz substrate has advantages such as excellent flatness and high heat resistance, but has a problem of high cost. However, by reusing the substrate, cost reduction can be achieved even when a quartz substrate having a higher cost than the glass substrate is used.

  FIG. 31 shows a photograph of the semiconductor device shown in this example. FIG. 31A is a photograph showing a semiconductor device manufactured by sealing a thin film integrated circuit peeled from a substrate. The thin film integrated circuit was peeled by completely removing the peeling layer. That is, the semiconductor device shown here was manufactured by using the method described in Embodiment Mode 1. Since the semiconductor device has a structure in which a semiconductor layer and a protective film are formed as described in the above embodiment mode, the semiconductor device can have a curved shape as illustrated in FIG.

  Note that this embodiment can be freely combined with the above embodiment modes.

  In this example, a more specific structure of the peeling method shown in Embodiment Mode 3 and Embodiment Mode 4 will be described with reference to the drawings.

  First, regarding the peeling method shown in Embodiment Mode 3, a more specific structure and a peeling method are shown in FIGS.

  First, as illustrated in FIG. 14A, a separation layer 301 is formed over a substrate 300. Specifically, as the substrate 300, for example, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a quartz substrate, a ceramic substrate, or the like can be used. Alternatively, a metal substrate containing stainless steel or a semiconductor substrate with an insulating film formed on the surface thereof may be used. A substrate made of a synthetic resin having flexibility such as plastic generally tends to have a lower heat resistant temperature than the above substrate, but can be used as long as it can withstand the processing temperature in the manufacturing process. . The surface of the substrate 300 may be planarized by polishing such as a CMP method. In this embodiment, a glass substrate is used as the substrate 300.

  As the peeling layer 301, W formed by a sputtering method and having a thickness of 30 nm to 1 μm, preferably 30 nm to 50 nm is used. In addition to the sputtering method, W can be formed by a CVD method. In this example, a metal film containing W is used for the peeling layer 301; however, other materials described in the above embodiments may be used.

  Next, the peeling layer 301 is selectively etched to form a pattern (FIG. 14B). The pattern can be formed using photolithography, droplet discharge method, or the like. In this embodiment, the peeling layer 301 is etched by photolithography to form a pattern including a plurality of openings 306 (FIG. 14B). Alternatively, a pattern may be formed using a droplet discharge method, in which case a resist can be formed directly and a mask is not necessary. Note that the opening 306 is preferably provided in a portion of a TFT layer to be formed, where a region where a transistor is to be formed is avoided.

  Subsequently, a semiconductor layer is formed over the separation layer 301 (FIG. 14C). The semiconductor layer includes at least an insulating film, a semiconductor film, a gate insulating film, a gate electrode, an interlayer insulating film, and a wiring. A specific peeling method will be described below.

  First, an insulating film is selectively formed in a region where a thin film integrated circuit is formed over the separation layer 301. The insulating film can be formed with a single-layer structure or a stacked structure. In this embodiment, the insulating film is formed with a stacked structure including the first insulating film 302 and the second insulating film 303. For example, a silicon oxide film is used as the first insulating film, and a silicon oxynitride film is used as the second insulating film. Alternatively, a three-layer structure including a silicon oxide film as the first insulating film, a silicon nitride oxide film as the second insulating film, and a silicon oxynitride film as the third insulating film may be formed. Note that in the case where peeling is performed using physical means in a later step, it is preferable to use a silicon oxide film as the first insulating film that is in direct contact with the peeling layer 301. In addition, the first insulating film 302 is in direct contact with the substrate 300 in the opening 306 at this time.

  Next, a thin film transistor is formed over the insulating film 303. The thin film transistor is provided with gate electrodes 314 and 315 formed through semiconductor films 311 and 312 etched into at least a desired shape and an insulating film (gate insulating film) 313 functioning as a gate insulating film.

  The semiconductor films 311 and 312 are an amorphous semiconductor, a SAS in which an amorphous state and a crystalline state are mixed, a microcrystalline semiconductor capable of observing crystal grains of 0.5 nm to 20 nm in the amorphous semiconductor, and It may have any state selected from crystalline semiconductors.

  If a substrate that can withstand the film formation temperature, for example, a quartz substrate is used, a crystalline semiconductor film may be formed on the substrate by a CVD method or the like.

  In this embodiment, an amorphous semiconductor film is formed, and a crystalline semiconductor film crystallized by heat treatment is formed. The heat treatment can be performed using a heating furnace, laser irradiation, irradiation of light emitted from a lamp instead of laser light (lamp annealing), or a combination thereof.

When laser irradiation is used, a continuous wave laser (CW laser) or a pulsed laser (pulse laser) can be used. Lasers include Ar laser, Kr laser, excimer laser, YAG laser, Y ₂ O ₃ laser, YVO ₄ laser, YLF laser, YAlO ₃ laser, glass laser, ruby laser, alexandride laser, Ti: sapphire laser, copper vapor One or a plurality of lasers or gold vapor lasers can be used. By irradiating the fundamental wave of such a laser and the second to fourth harmonics of the fundamental wave, a crystal having a large grain size can be obtained. For example, a second harmonic (532 nm) or a third harmonic (355 nm) of an Nd: YVO ₄ laser (fundamental wave 1064 nm) can be used. In this case, a laser power density is about 0.01 to 100 MW / cm ² (preferably 0.1 to 10 MW / cm ²⁾ is required. Then, irradiation is performed at a scanning speed of about 10 to 2000 cm / sec.

  At this time, crystallization can be performed using an optical system as shown in FIG.

  As another heat treatment, when a heating furnace is used, the amorphous semiconductor film is heated at 500 to 550 ° C. for 2 to 20 hours. At this time, the temperature may be set in multiple stages in the range of 500 to 550 ° C. so that the temperature gradually increases. In the first low-temperature heating step, hydrogen or the like of the amorphous semiconductor film comes out, so that so-called hydrogen dipping that reduces film roughness during crystallization can be performed. Furthermore, it is preferable to form a metal element that promotes crystallization, such as Ni, on the amorphous semiconductor film because the heating temperature can be reduced. Even crystallization using such a metal element may be heated to 600 to 950 ° C.

  However, when a metal element is formed, there is a concern that the electrical characteristics of the semiconductor element may be adversely affected. Therefore, it is necessary to perform a gettering step for reducing or removing the metal element. For example, a process may be performed so as to capture a metal element using an amorphous semiconductor film as a gettering sink.

Alternatively, a crystalline semiconductor film may be formed directly on the surface to be formed. In this case, a crystalline semiconductor film is directly formed on the surface to be formed using heat or plasma using a fluorine-based gas such as GeF ₄ or F ₂ and a silane-based gas such as SiH ₄ or Si ₂ H _6. Can be formed. In the case where a crystalline semiconductor film is directly formed as described above and high temperature treatment is required, a quartz substrate with high heat resistance is preferably used.

  Thus, it is thought that there is an influence of heating on the peeling layer by the process of heating the semiconductor film. For example, when heat treatment is performed using a furnace, or when laser irradiation is performed using a wavelength of 532 nm, energy may reach the release layer.

  On the other hand, in order to efficiently crystallize the semiconductor film, the structure of the base film can be selected so that the energy of the laser does not reach the release layer. For example, the material, film thickness, and stacking order of the base film are selected.

A semiconductor film formed by any one of the means described above has more hydrogen than a chip formed from a silicon wafer. Specifically, hydrogen can be formed so as to have 1 × 10 ¹⁹ to 1 × 10 ²² / cm ³ , preferably 1 × 10 ^{19 to} 5 × 10 ²⁰ / cm ³ . This hydrogen can provide a so-called defect termination effect that alleviates defects in the semiconductor film. In addition, the flexibility of the thin film integrated circuit can be increased by hydrogen.

  Furthermore, by setting the ratio of the area occupied by the semiconductor film etched into a desired shape in the thin film integrated circuit to 1 to 30%, the thin film transistor can be prevented from being broken or peeled off due to bending stress.

  The gate insulating film 313 is formed so as to cover the semiconductor films 311 and 312. The gate insulating film 313 can be formed by stacking a single layer or a plurality of films using, for example, silicon oxide, silicon nitride, silicon nitride oxide, or the like. As a film formation method, a plasma CVD method, a sputtering method, or the like can be used. Here, a sputtering method is used to form an insulating film containing silicon with a thickness of 30 nm to 200 nm.

  The gate electrodes 314 and 315 are formed by forming a first conductive layer on the gate insulating film 313 and a second conductive layer thereon, and patterning the first conductive layer and the second conductive layer. Can do. In this embodiment, tantalum nitride (TaN) is used as the first conductive layer and tungsten (W) is used as the second conductive layer. Both the TaN film and the W film may be formed by sputtering, the TaN film may be formed in a nitrogen atmosphere using a Ta target, and the W film may be formed using a W target.

  In this embodiment, the first conductive layer is TaN and the second conductive layer is W. However, the present invention is not limited to this, and the first conductive layer and the second conductive layer are both Ta, W, Ti, You may form with the element chosen from Mo, Al, Cu, Cr, Nd, or the alloy material or compound material which has the said element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. Further, an AgPdCu alloy may be used. Furthermore, the combination may be selected as appropriate. The film thickness may be in the range of 20 to 100 nm for the first conductive layer and 100 to 400 nm for the second conductive layer. In this embodiment, a two-layer structure is used, but a single layer may be used, or a three-layer or more structure may be used.

  Next, an impurity imparting n-type or p-type conductivity is selectively added to the semiconductor films 311 and 312 using a gate electrode or a selectively formed resist as a mask. The semiconductor films 311 and 312 have a channel formation region and an impurity region (including a source region, a drain region, a GOLD region, and an LDD region), and an n-channel TFT 304 or a p-channel type depending on the conductivity type of the added impurity element. It can be distinguished from the TFT 305.

  In FIG. 14, an n-channel TFT 304 has a sidewall on the side wall of the gate electrode 214, and a source region, a drain region, and an LDD region in which an impurity imparting n-type conductivity is selectively added to the semiconductor film 311 Is formed. In the p-channel TFT 305, a source region and a drain region in which an impurity imparting p-type conductivity is selectively added to the semiconductor film 312 are formed. Here, a structure in which sidewalls are formed on the sidewalls of the gate electrodes 314 and 315 and an LDD region is selectively formed in the n-channel TFT 204 is shown; however, the present invention is not limited to this structure. A region may be formed, or the p-channel TFT 205 may not be provided with a sidewall.

  Alternatively, a CMOS structure in which an n-channel TFT 304 and a p-channel TFT 305 are combined in a conservative manner may be used. Note that an impurity element may be added in advance to the channel region of the semiconductor film by doping or the like. By adding an impurity element to the channel region of the semiconductor film, a thin film transistor with excellent characteristics can be obtained by suppressing variation in threshold value and the like.

  Next, an interlayer insulating film 307 is formed. As the interlayer insulating film 307, an inorganic insulating film or an organic insulating film can be used. As the inorganic insulating film, a silicon oxide film, silicon oxynitride formed by a CVD method, a silicon oxide film applied by a SOG (Spin On Glass) method, or the like can be used. As an organic insulating film, polyimide, polyamide, or the like can be used. A film of BCB (benzocyclobutene), acrylic or positive photosensitive organic resin, negative photosensitive organic resin, or the like can be used. Alternatively, a stacked structure of an acrylic film and a silicon oxynitride film may be used.

  Further, as the interlayer insulating film, a siloxane material such as a siloxane resin may be used.

  Siloxane materials can be classified according to their structure into, for example, silica glass, alkylsiloxane polymers, alkylsilsesquioxane polymers, hydrogenated silsesquioxane polymers, hydrogenated alkylsilsesquioxane polymers, and the like. Alternatively, the interlayer insulating film may be formed using a material containing a polymer (polysilazane) having a Si—N bond.

  By using the above material, an interlayer insulating film having sufficient insulation and flatness can be obtained even when the film thickness is reduced. In addition, since the above material has high heat resistance, an interlayer insulating film that can withstand reflow processing in a multilayer wiring can be obtained. Further, since the hygroscopic property is low, an interlayer insulating film with a small amount of dehydration can be formed.

  In this embodiment, a siloxane material is formed as the interlayer insulating film 307. By the interlayer insulating film 307, unevenness due to the TFT formed over the substrate can be relaxed and planarized. In particular, since the interlayer insulating film 307 has a strong meaning of planarization, it is preferable to use an insulating film made of a material that is easily planarized.

In addition, a first passivation film may be formed before the interlayer insulating film 307 is formed. As the passivation film, an insulating film containing silicon is formed to a thickness of 100 to 200 nm. As a film forming method, a plasma CVD method or a sputtering method may be used. In addition, a silicon oxynitride silicon film formed from SiH ₄ , N ₂ O, and H ₂ may be used as a passivation film. Of course, the passivation film can be formed as a single layer structure or a stacked structure.

  In addition, after forming the interlayer insulating film 307, a second passivation film made of a silicon nitride oxide film or the like may be formed. The film thickness may be approximately 10 to 200 nm, and moisture can be prevented from entering and leaving the interlayer insulating film 206 by the second passivation film. In addition, a silicon nitride film, an aluminum nitride film, an aluminum oxynitride film, a diamond-like carbon (DLC) film, and a carbon nitride (CN) film can be used as the second passivation film.

  Next, the interlayer insulating film 307 is etched to form contact holes reaching the source and drain regions (FIG. 14D). Subsequently, wirings 308a to 308c that are electrically connected to the source and drain regions are formed. As the wirings 308a to 308c, a single layer or a multilayer structure made of one kind of element selected from Al, Ni, C, W, Mo, Ti, Pt, Cu, Ta, Au, and Mn or an alloy containing a plurality of such elements is used. Can be used. Here, it is preferable to form a metal film containing Al. In this embodiment mode, a stacked film of a Ti film and an alloy film containing Al and Ti is formed by etching into a desired shape. Of course, not only a two-layer structure but also a single-layer structure or a laminated structure of three or more layers may be used. Further, the wiring material is not limited to the laminated film of Al and Ti. For example, an Al film or a Cu film may be formed on the TaN film, and a laminated film formed with a Ti film may be etched into a desired shape to form a wiring.

  Subsequently, an insulating film 309 is formed so as to cover the wirings 308a to 308c. As the insulating film 309, an insulating material containing oxygen or nitrogen such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) (x> y), or the like is used. A film can be used, but typically, silicon nitride oxide (SiNxOy) is preferably used.

  Next, a protective film 310 is formed over the insulating film 309. As a material for the protective film 310, a resin material such as an epoxy resin, an acrylic resin, a phenol resin, a novolac resin, a melamine resin, a urethane resin, or a silicon resin can be used. Also, organic materials such as benzocyclobutene, parylene, flare, permeable polyimide, compound materials made by polymerization of siloxane materials such as siloxane resins, composition materials containing water-soluble homopolymers and water-soluble copolymers, etc. You may form using. The protective film 310 can be formed by a screen printing method or a droplet discharge method. In this embodiment, an epoxy resin formed by a screen printing method is used as the protective film 310.

  By providing the protective film 310, the TFT layer 102 can be prevented from warping due to stress when the TFT layer 102 is separated from the substrate 300.

  Thereafter, the release film 301 is completely removed. In this embodiment, the release layer and the etching agent are chemically reacted to remove the release layer.

As shown in FIG. 14D, a gas or a liquid containing halogenated fluorine is introduced into the opening 322. At this time, the reaction rate can be increased by setting the treatment temperature to 100 ° C. to 300 ° C. by the heating means. As a result, the amount of ClF ₃ gas used can be reduced and the processing time can be shortened.

At this time, an etching agent, a gas flow rate, a temperature, and the like are set so that each layer of the TFT layer 102 is not etched. Since ClF ₃ used in this embodiment has a characteristic of selectively etching W, it selectively removes W as a peeling layer. Therefore, a layer made of a metal film containing W is used for the peeling layer, and an insulating film containing oxygen or nitrogen is used for the base film. Since the difference in reaction rate, that is, the selectivity is high, the peeling layer can be easily removed while protecting the TFT layer 102. In this embodiment, the TFT layer is not etched by ClF ₃ due to the insulating film provided above and below the TFT layer, the interlayer insulating film exposed on the side surface, the gate insulating film, and the end of the wiring.

Note that ClF ₃ can be produced through a process of Cl ₂ (g) + 3F ₂ (g) → 2ClF ₃ (g) by reacting chlorine with fluorine at 200 ° C. or higher. Further, ClF ₃ may be a liquid depending on the temperature of the reaction space (boiling point 11.75 ° C.), and in this case, wet etching can be adopted as a liquid containing halogenated fluorine.

As another gas containing halogenated fluorine, a gas in which nitrogen is mixed with ClF ₃ or the like may be used.

Further, an etchant that etches the release layer and does not etch the base film is not limited to ClF ₃ , and is not limited to halogenated fluorine. For example, a gas containing fluorine such as CF ₄ , SF ₆ , NF ₃ , F _2, etc. can be used as plasma. As another etching agent, a strong alkaline solution such as tetraethylammonium hydroxide (TMAH) may be used.

Further, in the case of chemical removal with a gas containing a halogenated fluorine such as ClF ₃ , if the condition that a material that is selectively etched is used as a peeling layer and a material that is not etched is used as a base film, the peeling layer and The combination of the base films is not limited to the above materials.

  Next, after removing the peeling layer 301, the substrate 300 is peeled off. In this embodiment, even after the peeling layer 301 is completely removed, the insulating film included in the semiconductor layer 102 is bonded to the substrate 300 in the opening 306 (FIG. 15A). Therefore, the semiconductor layer 102 and the substrate 300 are separated by using physical means. The specific method will be described below.

  As shown in FIG. 15B, an auxiliary substrate 316 is provided over the protective film 310. As the auxiliary substrate 316, a quartz substrate or a flexible substrate is used. In the case of using a flexible substrate, it can be bonded to the protective film 310 using a flexible film having an adhesive on one surface. In this case, as an adhesive used for bonding the protective film 209 and the auxiliary substrate 222, an adhesive such as a thermosetting resin, an ultraviolet curable resin, an epoxy or acrylic resin adhesive, a resin additive, a tape, or the like can be used. .

  Subsequently, the substrate 300 and the TFT layer 102 are physically separated using the auxiliary substrate 316 (FIG. 15C). Through the above process, the TFT layer 102 can be peeled from the substrate 300.

  Next, the peeling method shown in Embodiment Mode 4 will be described with reference to FIGS. 16 and 17 with respect to a more specific structure and a peeling method.

  First, as illustrated in FIG. 16A, a substrate 400 is prepared, and a separation layer 401 is formed over the substrate 400.

  Next, in FIG. 16, the peeling layer 401 is not patterned, and the TFT layer 2020 is formed over the peeling layer 401 as it is (FIG. 16B).

  Next, a protective film 410 is formed over the TFT layer 2020. In this embodiment, a portion (convex region 411) having a larger film thickness than the other portions is provided at the end of the protective film 410. The convex region 411 is formed so as to be thicker than other portions of the protective film 410. Further, the convex region 411 may be formed of the same material as the protective film 410, or only the convex region 410 may be separately formed of a different material. The convex region 411 can be easily formed by using a droplet discharge method. Note that although an example in which the protective film 410 is formed at the end portion is shown in this embodiment, any number of the protective film 410 may be formed, and it is preferable that the protective film 410 be formed at a portion where no thin film transistor is provided below. .

  Next, an etchant is introduced into the opening 422 (FIG. 16C), and the separation layer 401 is removed (FIG. 17A). At this time, by controlling the flow rate of the etching agent and the reaction time, the layers other than the release layer located below the convex region 411 are removed. The peeling layer 401 located below the convex region 411 can be left selectively because the etching progresses slowly.

  Next, as illustrated in FIG. 17B, an auxiliary substrate 416 is provided over the protective film 410. After that, the substrate 400 and the TFT layer 2020 are physically separated using the auxiliary substrate 416 (FIG. 17C). Through the above steps, the TFT layer 2020 can be peeled from the substrate 400.

  By using the method shown in this embodiment, the TFT layer 2020 after peeling can be obtained in a state of being arranged in the same manner as before peeling without being separated.

  In this embodiment, the auxiliary substrate 416 and the TFT layer 2020 are peeled off by attaching the auxiliary substrate separately, but may be peeled off using other methods.

  After that, the TFT layer 2020 separated from the substrate 400 may be mounted on an article as it is, or may be mounted in a state where it is separately transferred to a transfer substrate. As the transfer substrate, a flexible substrate is preferable. As the flexible substrate, a substrate made of plastic such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or polyethersulfone (PES), or a synthetic resin having flexibility such as acrylic is used. Can do.

  As an adhesive for adhering the flexible substrate, an adhesive such as a thermosetting resin, an ultraviolet curable resin, an epoxy resin adhesive, a resin additive, or a double-sided tape can be used.

  When transferred to a flexible substrate, the breaking strength of the thin film integrated circuit can be increased. Further, as compared with a thin film integrated circuit formed over an insulating substrate, light weight and thin film can be achieved, and flexibility can be increased.

  Further, the peeled substrate can be reused. As a result, cost reduction can be achieved even when a quartz substrate or the like is used in manufacturing a semiconductor device. In the case of reuse, it is desirable to control so as not to generate scratches on the substrate in the peeling process. However, even when scratches are generated, an organic resin or inorganic resin film may be formed by a coating method or a droplet discharge method, and planarization may be performed.

  As described above, when a thin film integrated circuit is formed over a substrate having an insulating surface, the shape of the base substrate is not limited as compared with a chip manufactured using a silicon wafer in which the chip is extracted from a circular silicon wafer. Therefore, the productivity of thin film integrated circuits can be increased and mass production can be performed. Furthermore, since the insulating substrate can be reused, the cost can be reduced.

  Note that this embodiment can be freely combined with the above embodiment modes.

  In this embodiment mode, modes different from the above embodiment mode or examples will be described with reference to FIGS.

  As shown in FIG. 22A, a substrate 200, a peeling layer 201, a TFT layer 102, and a protective film 209 are formed in this order. Note that FIG. 22A is a top view, and a cross-sectional view taken along line EF corresponds to FIG. 22B and a cross-sectional view taken along line GH corresponds to FIG.

  In this embodiment, an insulating film or a conductive film constituting the TFT layer 102 is selectively formed in each region 109 on the substrate 200 where the thin film integrated circuit is provided, and at the same time, an insulating film is formed in a part of the opening 104 at the same time. Alternatively, a conductive film is selectively formed. Note that a region where an insulating film or a conductive film is selectively formed in the opening 104 is referred to as a connection region 108.

  Note that the connection region 108 may be formed at the same time in the manufacturing process of the TFT layer 102 and may have a function of connecting the TFT layers 102 so as to be integrated. The connection region 108 may have a single-layer structure or a stacked structure, and is formed using an insulating film or a conductive film. In this embodiment, the connection region 108 is formed of a stacked structure of first and second insulating films 202 and 203, a gate insulating film 213, an interlayer insulating film 206, and an insulating film 208 (FIG. 22C). .

  Next, an etchant is introduced into the opening 104 to completely remove the peeling layer 201 (FIGS. 23A to 23C). As an etchant, as shown in the embodiment mode, a gas or a liquid containing halogen fluoride can be used.

  At this time, the reaction time and the introduction amount are adjusted so that the peeling layer located below the connection region 108 is removed. As a result, when the peeling layer is completely removed, the substrate 100 and the TFT layer 102 are separated, but each TFT layer 102 is connected by the connection region 108, so that the arrangement before peeling is maintained without being separated.

Subsequently, each TFT layer 102 is cut by dicing, scribing, or laser cutting. For example, it can be cut using a laser that is absorbed by the glass substrate, for example a CO ₂ laser. After that, as in the first embodiment, the TFT layer 102 separated from the substrate 200 may be mounted on an article as it is, or may be mounted in a state where it is separately transferred to a transfer substrate. Further, the peeled substrate 200 can be reused.

  Note that this embodiment mode can be freely combined with the above embodiment modes and examples.

  In this embodiment, a method for manufacturing a gate electrode in the TFT layer described in the above embodiment will be described with reference to FIGS.

  First, as shown in the above embodiment, a separation layer 201 is formed over a substrate 200, and semiconductor films 211 and 212 are provided over the separation layer 201 with insulating films 202 and 203 interposed therebetween. In addition, a gate insulating film 213 is formed over the semiconductor films 211 and 212. After that, a first conductive layer 901 and a second conductive layer 902 are stacked over the gate insulating film 213. In this embodiment, tantalum nitride (TaN) is used as the first conductive layer and tungsten (W) is used as the second conductive layer. Both the TaN film and the W film may be formed by sputtering, the TaN film may be formed in a nitrogen atmosphere using a Ta target, and the W film may be formed using a W target.

  In this embodiment, the first conductive layer 901 is TaN and the second conductive layer 902 is W. However, the present invention is not limited to this, and both the first conductive layer 901 and the second conductive layer 902 are Ta, You may form with the element selected from W, Ti, Mo, Al, Cu, Cr, and Nd, or the alloy material or compound material which has the said element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. Further, an AgPdCu alloy may be used. Furthermore, the combination may be selected as appropriate. The first conductive layer 901 may be formed with a thickness of 20 to 100 nm, and the second conductive layer 902 may be formed with a thickness of 100 to 400 nm. In this embodiment, a two-layer structure is used, but a single layer may be used, or a three-layer or more structure may be used.

Next, a resist 903 is selectively formed over the second conductive layer 902 by photolithography or a droplet discharge method (FIG. 19A). Thereafter, by performing a known etching process such as an O ₂ (oxygen) plasma process, the resist 903 is etched to reduce the resist 903 (FIG. 19B). In this manner, by etching the first conductive layer 901 and the second conductive layer 902 using the reduced resist 904 as a mask, a gate electrode having a smaller width can be formed. That is, a gate electrode having a smaller width can be formed than when a gate electrode is formed using a resist 903 obtained by ordinary photolithography, a droplet discharge method, or the like. Thus, by reducing the structure of the gate electrode, the width of the channel formation region is reduced, and high-speed operation is possible.

  A case where the method is different from the method for manufacturing the gate electrode illustrated in FIGS. 19A to 19C is described with reference to FIGS.

  First, as illustrated in FIG. 19A, a separation layer 201, insulating films 202 and 203, semiconductor films 211 and 212, a gate insulating film 213, a first conductive layer 901, and a second conductive layer are formed over a substrate 200. 902 are stacked, and a resist 903 is selectively formed. Subsequently, the first conductive layer 901 and the second conductive layer 902 are etched using the resist 903 as a mask (FIG. 20A). Through this step, the gate electrode 906 including the first conductive layer 901 and the second conductive layer 902 is formed. Thereafter, the gate electrode 906 is etched using a known etching method. Since the resist 903 is provided over the gate electrode 906, a side surface of the gate electrode 906 is etched, so that a gate electrode 907 having a width smaller than that of the gate electrode 906 can be formed as illustrated in FIG. .

  By using the manufacturing method shown in this embodiment, a fine gate electrode that can be formed by a photolithography method or the like can be manufactured. Further, a finer element structure can be provided by reducing the gate electrode. Therefore, since many elements can be built in the same area, a high-performance circuit can be formed. In addition, the thin film integrated circuit (IC chip or the like) can be reduced in size when formed with a structure similar to the number of conventional elements. Further, the method shown in FIG. 19 may be combined with the method shown in FIG. 20, and a finer gate electrode can be formed.

  Note that this embodiment can be freely combined with the above embodiment mode or embodiments.

    In this embodiment, a structure of a TFT layer different from that in the above embodiment will be described with reference to FIGS.

  24 shows a structure in which a lower electrode is added to the structure of the TFT layer 102 shown in FIG. 13C or FIG. 22B, for example. That is, as shown in FIG. 24, the channel region of the semiconductor layer 211 is sandwiched between the lower electrode 513 and the gate electrode 214 via the insulating film.

  The lower electrode 513 can be formed using a metal or a polycrystalline semiconductor to which an impurity of one conductivity type is added. When using a metal, W, Mo, Ti, Ta, Al, or the like can be used. Further, although the silicon nitride film 514 and the silicon oxynitride film 515 functioning as a base insulating film are provided, the material and the order of stacking are not limited.

  As described above, a TFT having a lower electrode may be used as the structure of the TFT layer 102. In general, when the size of the TFT is reduced and the clock frequency for operating the circuit is improved, the power consumption of the integrated circuit is increased. Therefore, a method of applying a bias voltage to the lower electrode is effective for suppressing an increase in power consumption. By changing this bias voltage, the threshold voltage of the TFT can be changed.

  Application of a negative bias voltage to the lower electrode of the n-channel TFT increases the threshold voltage and reduces leakage. On the other hand, when a positive bias voltage is applied, the threshold voltage is lowered and current easily flows through the channel, and the TFT operates at a higher speed or at a lower voltage. In addition, application of a positive bias voltage to the lower electrode of the p-channel TFT increases the threshold voltage and reduces leakage. On the other hand, when a negative bias voltage is applied, the threshold voltage is lowered and current easily flows through the channel, and the TFT operates at a higher speed or at a lower voltage. By controlling the bias voltage applied to the lower electrode in this way, the characteristics of the integrated circuit can be greatly improved.

  Using this bias voltage, the characteristics of the integrated circuit can be improved by balancing the threshold voltages of the n-channel TFT and the p-channel TFT. At this time, in order to reduce power consumption, both the power supply voltage and the bias voltage applied to the lower electrode may be controlled. When the circuit is in the standby mode, a large reverse bias voltage is applied, and during operation, a weak reverse bias is applied when the load is small, and a weak forward bias voltage is applied when the load is large. The application of the bias voltage may be switched by providing a control circuit depending on the operation state of the circuit or the load state. By controlling the power consumption and the TFT performance by such a method, the circuit performance can be maximized.

  Note that this embodiment can be freely combined with the above embodiment mode or embodiments.

  In this example, the semiconductor device including the thin film integrated circuit described in the above embodiment mode or the example can be used for wireless data transmission / reception such as an IC chip (wireless tag, RFID (Radio frequency identification) tag, IC tag, ID chip). A case where it is used as a possible semiconductor device will be described.

  The IC chip can be broadly divided into a non-contact type IC chip (also called a wireless tag) on which an antenna is mounted, a contact type IC chip on which a terminal for connecting to an external power source is formed without mounting an antenna, and a non-contact type. There is a hybrid IC chip in which a mold and a contact type are mixed.

  In the case where the semiconductor device including the thin film integrated circuit described in any of the above embodiments and examples is used as a contact IC chip, the peeled thin film integrated circuit can be used by directly mounting it on an article.

  On the other hand, when a thin film integrated circuit is used as a non-contact IC chip or a hybrid IC chip, it is preferable to use the integrated circuit by mounting an antenna. An example of a cross-sectional view of an IC chip when an antenna is mounted is shown in FIG. Note that the cross-sectional view shown in FIG. 25 shows a state before the IC chip is peeled from the substrate.

  FIG. 25A shows a cross-sectional view of an IC chip when the antenna 232 is directly formed over the TFT layer 102. As shown in the above embodiment, after forming the wirings 207a to 207c, the second interlayer insulating film 231 is formed to cover the wirings 207a to 207c. As the second interlayer insulating film 231, any of the materials shown as the material of the interlayer insulating film 206 in the above embodiment can be used. Here, the second interlayer insulating film 231 is formed using a siloxane material such as a siloxane resin.

  After that, contact holes are formed in the second interlayer insulating film 231 so as to reach the wirings 207a and 207c. Then, an antenna 232 that is electrically connected to the wirings 207a and 207c is formed. As a material of the antenna 232, a conductive material such as Ag, Al, Au, Cu, or Pt can be used. When using relatively high resistance Al or Au, there is a concern about the wiring resistance. However, the wiring resistance can be reduced by increasing the thickness of the antenna or the width of the antenna. Alternatively, the antennas may be stacked and covered with a material having low resistance. A conductive material such as Cu that has a concern about diffusion may be formed by forming an insulating film so as to cover the surface on which the antenna is formed or the periphery of Cu.

  Next, a protective film 233 is formed so as to cover the antenna 232. The protective film 233 can also be formed using any of the materials shown in the above embodiments.

  Subsequently, as described in the above embodiment modes or examples, the peeling layer is removed, and the IC chip can be peeled off from the substrate. Moreover, the peeling method may be performed by completely removing the peeling layer, or may be physically peeled after removing a part of the peeling layer, and may be appropriately selected by the practitioner. Thereafter, the peeled IC chip can be used by mounting it on an article or the like.

  FIG. 25B is a cross-sectional view in the case where the antenna substrate 235 provided with the antenna 234 in advance and the TFT layer 102 are bonded together with an adhesive or the like.

  As an attachment means, there is an anisotropic conductor 236 in which the conductor 237 is dispersed. The anisotropic conductor 236 can be electrically connected in the region 239 where the connection terminal 238 of the IC chip and the connection terminal of the antenna 234 are provided, because the conductor is pressed by the thickness of each connection region terminal. . In other regions, the conductors are kept at a sufficient interval and thus are not electrically connected. In addition to the anisotropic conductor, the bonding may be performed using an ultrasonic adhesive, an ultraviolet curable resin, a double-sided tape, or the like.

  FIG. 26 shows a configuration different from that in FIG.

  FIG. 26A shows a cross-sectional view of the IC chip in the case where the antenna 232 is directly formed over the TFT layer 102. As shown in the above embodiment, the wirings 207a to 207c are similarly formed, and then the second interlayer insulating film 231 is formed to cover the wirings 207a to 207c.

  As the second interlayer insulating film 231, a material similar to that shown as the material of the interlayer insulating film 206 in the above embodiment can be used, and the second interlayer insulating film 231 may be formed using the same material as the interlayer insulating film 206. Here, the second interlayer insulating film 231 is formed using a siloxane material such as a siloxane resin.

  After that, contact holes are formed in the second interlayer insulating film 231 so as to reach the wirings 207a and 207c. Then, an antenna 232 that is electrically connected to the wirings 207a and 207c is formed. As a material of the antenna 232, a conductive material such as Ag, Al, Au, Cu, or Pt can be used. When using relatively high resistance Al or Au, there is a concern about the wiring resistance. However, the wiring resistance can be reduced by increasing the thickness of the antenna or the width of the antenna. Alternatively, the antennas may be stacked and covered with a material having low resistance. A conductive material such as Cu that has a concern about diffusion may be formed by forming an insulating film so as to cover the surface on which the antenna is formed or the periphery of Cu.

  Next, a protective film 233 is formed so as to cover the antenna 232. The protective film 233 can also be formed using any of the materials shown in the above embodiments.

  Subsequently, as described in the above embodiment modes or examples, the peeling layer is removed, and the IC chip can be peeled off from the substrate. Moreover, the peeling method may be performed by completely removing the peeling layer, or may be physically peeled after removing a part of the peeling layer, and may be appropriately selected by the practitioner. Thereafter, the peeled IC chip can be used by mounting it on an article or the like.

  FIG. 26B is a cross-sectional view in the case where the antenna substrate 235 provided with the antenna 234 in advance and the TFT layer 102 are bonded together with an adhesive or the like.

  As an attachment means, there is an anisotropic conductor 236 in which the conductor 237 is dispersed. The anisotropic conductor 236 can be electrically connected in the region 239 where the connection terminal 238 of the IC chip and the connection terminal of the antenna 234 are provided, because the conductor is pressed by the thickness of each connection region terminal. . In other regions, the conductors are kept at a sufficient interval and thus are not electrically connected. In addition to the anisotropic conductor, the bonding may be performed using an ultrasonic adhesive, an ultraviolet curable resin, a double-sided tape, or the like.

  Note that a protective film is preferably formed over the antenna substrate 234 when the IC chip may be warped by stress or the like when peeled from the substrate. Thereafter, the IC chip separated from the substrate can be mounted on an article as it is, or separately mounted on a transfer substrate for mounting.

  In addition, since the IC chip shown in this embodiment uses a thin film integrated circuit formed on an insulating substrate rather than using a silicon substrate, compared with a chip formed from a circular silicon substrate, There are no restrictions on the shape of the base substrate. Therefore, the cost of the IC chip can be reduced. Unlike the chip made of a silicon substrate, the IC chip of this embodiment uses a semiconductor film having a thickness of 0.2 μm or less, typically 40 nm to 170 nm, preferably 50 nm to 150 nm as an active region. Thin. As a result, it is difficult to recognize the presence of a semiconductor device even if it is mounted on an article, leading to prevention of tampering such as forgery.

  In addition, the IC chip shown in this embodiment can receive a highly sensitive signal without worrying about radio wave absorption as compared with a chip made of a silicon substrate. Further, a thin film integrated circuit that does not have a silicon substrate has a light-transmitting property. As a result, it can be applied to various articles. For example, even if it is mounted on the printing surface of an article, the design is not impaired.

  Note that this embodiment can be freely combined with the above embodiment mode or embodiments.

  In this example, the structure of an IC chip manufactured using the peeling method of the present invention will be described.

  FIG. 27A is a perspective view illustrating one embodiment of an IC chip. Reference numeral 920 denotes an integrated circuit, and 921 denotes an antenna. The antenna 921 is electrically connected to the integrated circuit 920. Reference numeral 922 denotes a substrate, and 923 denotes a cover material. The integrated circuit 920 and the antenna 921 are sandwiched between the substrate 922 and the cover material 923.

  Next, FIG. 27B is a block diagram illustrating one functional configuration of the IC chip illustrated in FIG.

  In FIG. 27B, 900 corresponds to an antenna, and 901 corresponds to an integrated circuit. Reference numeral 903 corresponds to a capacitance formed between both terminals of the antenna 900. The integrated circuit 901 includes a demodulation circuit 909, a modulation circuit 904, a rectification circuit 905, a microprocessor 906, a memory 907, and a switch 908 for applying load modulation to the antenna 900. Note that the memory 907 is not limited to one, and a plurality of memories 907 may be used, such as SRAM, flash memory, ROM, or FeRAM.

  A signal transmitted as a radio wave from the reader / writer is converted into an AC electrical signal by electromagnetic induction in the antenna 900. The demodulation circuit 909 demodulates the alternating electrical signal and transmits it to the subsequent microprocessor 906. The rectifier circuit 905 generates a power supply voltage using an alternating electrical signal and supplies the power supply voltage to the subsequent microprocessor 906. The microprocessor 906 performs various arithmetic processes according to the input signal. The memory 907 stores programs and data used in the microprocessor 906, and can also be used as a work area during arithmetic processing.

  When data is sent from the microprocessor 906 to the modulation circuit 904, the modulation circuit 904 controls the switch 908 and can apply load modulation to the antenna 900 in accordance with the data. The reader / writer can read the data from the microprocessor 906 as a result of receiving the load modulation applied to the antenna 900 by radio waves.

  Note that the IC chip does not necessarily have the microprocessor 906. The signal transmission method is not limited to the electromagnetic induction method shown in FIG. 27B, and a microwave method or other transmission methods may be used.

  In this manner, an IC chip having an antenna can exchange data with an external device (reader / writer), and thus can be used as a wireless memory or a wireless processor.

  This embodiment can be freely combined with the above embodiment mode or embodiments.

  In this embodiment, a case where peeling and sealing are performed using an apparatus capable of peeling and sealing a thin film integrated circuit provided over a substrate (for example, a laminating apparatus) will be specifically described with reference to the drawings.

  As shown in FIG. 28, the laminating apparatus shown in the present embodiment includes a conveying means 11 that conveys a substrate 12 on which a plurality of thin film integrated circuits 13 are provided, and a first supply material in which a first sheet material 18 is wound. A first peeling means 51 having a roll 14, a roller 16 for peeling the thin film integrated circuit 13 from the substrate 12 by adhering it to the first sheet material 18, and a second sheet material 19 wound around the second sheet material 19. A supply roll 15; a second peeling means 52 including rollers 24 and 28 for peeling the thin film integrated circuit 13 from the first sheet material 18 by bonding to the second sheet material 19; and the first sheet material. The recovery roll 21 for recovering 18, the third supply roll 22 for supplying the third sheet material 23, and the thin film integrated circuit 13 are sealed by the second sheet material 19 and the third sheet material 23. Sealing mechanism 17 (Laminé It has a DOO means), and a recovery roll 20 for winding the thin film integrated circuits 13 sealed.

  In the apparatus shown in FIG. 28, first, the first sheet material 18 supplied from the first supply roll 14 is transferred onto the substrate 12 conveyed by the conveying means 11 by the first peeling means 51 provided with the rollers 16. The thin film integrated circuit 13 is peeled from the substrate 12 by bonding to the thin film integrated circuit 13. Thereafter, the peeled thin film integrated circuit 13 is bonded to the first sheet material 18 and flows toward the roller 28. Further, the second sheet material 19 supplied from the second supply roll 15 flows in the direction of the roller 24.

  Then, the second sheet material 19 is adhered to the other surface of the thin film integrated circuit 13 which has been conveyed by being adhered to the first sheet material 18 by the second peeling means 52 provided with the rollers 24, 28, The thin film integrated circuit 13 is peeled from the first sheet material 18. The second peeling means performs one or both of pressure treatment and heat treatment when the thin film integrated circuit bonded to the first sheet material 18 is bonded to the second sheet material 19. Thereafter, the peeled thin film integrated circuit 13 is bonded to the second sheet material 19 and flows toward the sealing mechanism 17. Further, the third sheet material 23 supplied from the third supply roll 22 flows in the direction of the sealing mechanism 17.

  In the sealing mechanism 17, the other surface of the thin film integrated circuit 13 that has been transferred to the third sheet material 23 while being bonded to the second sheet material (on the opposite side to the surface to which the second sheet material 19 is bonded). Surface) and one or both of pressure treatment and heat treatment. Thereafter, the sealed thin film integrated circuit 13 flows in the direction of the recovery roll 20 and winds around the recovery roll 20.

  In the laminating apparatus shown in FIG. 28, as described above, the first sheet material 18 is supplied from the first supply roll, flows in the order of the roller 16 and the roller 28 included in the first peeling means, and is collected. It is collected in the roll 21 for use. The first supply roll 14, the roller 16, and the roller 28 rotate in the same direction. The second sheet material 19 is supplied from the second supply roll 15, flows in the order of the roller 24 included in the second peeling unit, and the roller 25 included in the sealing mechanism 17, and is collected in the collection roll 20. The second supply roll 15, the roller 24, and the roller 25 rotate in the same direction. The third sheet material 23 is supplied from the third supply roll 22 and is collected by the collection roll 20 after flowing through the roller 26 included in the sealing mechanism 17. The third supply roll 22 and the roller 26 rotate in the same direction.

  The transport means 11 transports the substrate 12 on which a plurality of thin film integrated circuits 13 are provided. In FIG. 28, the transport means 11 includes a roller 27, and the substrate 12 is transported by the rotation of the roller 27. The transport unit 11 may have any configuration as long as the substrate 12 can be transported. For example, a belt conveyor, a plurality of rollers, a robot arm, or the like may be used. The robot arm transports the substrate 12 as it is, or transports the stage on which the substrate 12 is provided. Further, the transport unit 11 transports the substrate 12 at a predetermined speed in accordance with the speed at which the first sheet material 18 moves.

  A first sheet material 18, a second sheet material 19, and a third sheet material 23 are wound around the first supply roll 14, the second supply roll 15, and the third supply roll 22, respectively. ing. By rotating the first supply roll 14 at a predetermined speed, the first sheet material is caused to flow toward the roller 28 included in the second peeling means at a predetermined speed. By rotating the three supply rolls 22 at a predetermined speed, the second sheet material 19 and the third sheet material 23 are caused to flow at a predetermined speed toward the sealing mechanism 17. The first supply roll 14, the second supply roll 15, and the third supply roll 22 are cylindrical and are made of a resin material, a metal material, a rubber material, or the like.

  The 1st sheet | seat material 18 consists of a flexible film, and the surface which has an adhesive is provided in the at least one surface. Specifically, an adhesive is provided on a base film used as a base material such as polyester. As the adhesive, a material made of a resin material containing an acrylic resin or the like or a synthetic rubber material can be used. The first sheet material 18 is preferably a film having a low adhesive strength (adhesive strength is preferably 0.01 N to 0.5 N, more preferably 0.05 N to 0.35 N). This is because the thin film integrated circuit provided on the substrate is bonded to the first sheet material, and then the thin film integrated circuit is bonded to the second sheet material again. The thickness of the adhesive can be 1 μm to 100 μm, preferably 1 μm to 30 μm. Moreover, as a base film, if it forms in 10 micrometers-1 mm using films, such as polyester, it is easy to handle at the time of a process, and it is preferable.

  When the surface of the adhesive layer is protected by a separator, a separator collecting roll 30 is provided as shown in FIG. 13 when used, and the separator 29 may be removed during use. In addition, a base film used as a base material that has been subjected to antistatic treatment can also be used. The separator is made of a film such as polyester or paper, but is preferably formed of a film such as polyethylene terephthalate because paper dust or the like is not generated during processing.

  The second sheet material 19 and the third sheet material 23 are made of a flexible film, and correspond to, for example, a laminate film or paper made of a fibrous material. Laminated film refers to all films that can be used for laminating treatment, and is made of materials such as polypropylene, polystyrene, polyester, vinyl, polyvinyl fluoride, vinyl chloride, methyl methacrylate, nylon, polycarbonate, etc., and its surface is embossed, etc. The processing may be performed.

  In this embodiment mode, it is preferable to seal the thin film integrated circuit using a hot-melt adhesive. A hot-melt adhesive is a chemical substance that does not contain water or a solvent, is made of a solid and non-volatile thermoplastic material at room temperature, and adheres to an object by being applied and cooled in a molten state. In addition, the bonding time is short, pollution-free, safe and hygienic, energy saving, and low cost.

  Since the hot-melt adhesive is solid at room temperature, it can be used in the form of a film or fiber, or a film obtained by forming an adhesive layer in advance on a base film such as polyester. Here, a sheet material in which a hot melt film is formed on a base film made of polyethylene terephthalate is used. The hot melt film is made of a resin having a softening point lower than that of the base film. When heated, only the hot melt and the film are melted to form a rubber-like adhesive and are cured when cooled. As the hot melt and film, for example, a film mainly composed of ethylene / vinyl acetate copolymer (EVA), polyester, polyamide, thermoplastic elastomer, polyolefin, or the like can be used.

  One or both of the second sheet material 19 and the third sheet material 23 may have an adhesive surface on one surface. As the adhesive surface, a material to which an adhesive such as a thermosetting resin, an ultraviolet curable resin, an epoxy resin adhesive, a photocurable adhesive, a moisture curable adhesive, or a resin additive is applied can be used.

  Further, one or both of the second sheet material 19 and the third sheet material 23 may have translucency. Further, in order to protect the thin film integrated circuit 13 to be sealed on one or both of the second sheet material 19 and the third sheet material 23, the surface thereof is coated with a conductive material by charging with static electricity. Also good. In addition, one or both of the second sheet material 19 and the third sheet material 23 is a conductive film such as a thin film (diamond-like carbon film) mainly composed of carbon as a protective film or indium tin oxide (ITO). It may be coated with a material.

  The first peeling means 51 includes at least the roller 16, and peels the thin film integrated circuit 13 from the substrate 12 by bonding one surface of the thin film integrated circuit 13 to one surface of the first sheet material 18. By rotating the roller 16, the thin film integrated circuit 13 adheres to the first sheet material 18, and the thin film integrated circuit 13 is peeled from the substrate 12. Therefore, the roller 16 is provided so as to face the substrate 12 on the side where the thin film integrated circuit 13 is provided. The roller 16 has a cylindrical shape and is made of a resin material, a metal material, a rubber material, or the like, and is preferably made of a soft material.

  The second peeling means 52 includes at least rollers 24 and 28 facing each other, and adheres the thin film integrated circuit 13 adhered to the first sheet material 18 to one surface of the second sheet material 19, thereby The thin film integrated circuit 13 is peeled from the sheet material 18. At this time, when the thin film integrated circuit is adhered to the second sheet material 19 that flows from the second supply roll 15 toward the roller 24 and passes between the roller 24 and the roller 28, the roller 24 and the roller One or both of 28 are used to perform one or both of the pressure treatment and the heat treatment.

  By performing this process, the thin film integrated circuit 13 bonded to the first sheet material 18 is bonded to the second sheet material 19. The heat treatment method may be any method as long as heat energy can be applied. For example, an oven, a heating wire heater, a heating medium such as oil, a hot stamp, a thermal head, a laser beam, an infrared flash, a thermal pen, etc. Can be appropriately selected and used. The rollers 24 and 28 are cylindrical and are made of a resin material, a metal material, a rubber material, or the like, preferably a soft material.

  When the thin film integrated circuit 13 having one surface bonded to the second sheet material 19 flows, the sealing mechanism 17 adheres the third sheet material 23 to the other surface of the thin film integrated circuit 13, and The thin film integrated circuit 13 is sealed with the second sheet material 19 and the third sheet material 23. The sealing mechanism 17 includes a roller 25 and a roller 26 that are provided to face each other. When the other surface of the thin film integrated circuit 13 is adhered to the third sheet material 23 that flows from the third supply roll 22 toward the roller 26, the roller passes between the roller 25 and the roller 26. 25 and the roller 26 are used to perform one or both of pressure treatment and heat treatment. By performing this process, the thin film integrated circuit 13 is sealed with the second sheet material 19 and the third sheet material 23.

  One or both of the rollers 25 and 26 constituting the sealing mechanism 17 have heating means. As the heating means, for example, an oven, a heating wire heater, a heating medium such as oil, a hot stamp, a thermal head, a laser beam, an infrared flash, a thermal pen, or the like can be used. Further, the roller 25 and the roller 26 rotate at a predetermined speed in accordance with the rotation speed of the roller 24, the second supply roll 15, and the third supply roll 22. The rollers 25 and 26 are cylindrical and are made of a resin material, a metal material, a rubber material, or the like, preferably a soft material.

  The recovery roll 20 is a roll that recovers by winding up the thin film integrated circuit 13 sealed by the second sheet material 19 and the third sheet material 23. The collection roll 20 rotates at a predetermined speed in accordance with the rotation speed of the roller 25 and the roller 26. The collection roll 20 has a cylindrical shape, and is made of a resin material, a metal material, a rubber material, or the like, preferably a soft material.

  As described above, according to the laminating apparatus shown in FIG. 28, the first to third supply rolls 14, 15, 21, the roller 16, the rollers 24, 28, the rollers 25, 26 and the collection roll 20 are rotated. Thus, the plurality of thin film integrated circuits 13 provided on the substrate 12 can be continuously peeled, sealed, and recovered.

  As described above, the laminating apparatus shown in this embodiment can continuously peel and seal the thin film integrated circuit provided on the substrate. Therefore, for example, the thin film integrated circuit in the state shown in FIG. 12A can be efficiently peeled, sealed, and collected by using the laminating apparatus shown in FIG. , Manufacturing efficiency can be improved.

  Note that this embodiment can be freely combined with the above embodiment mode or embodiments.

  In this embodiment, an application of the thin film integrated circuit described in the above embodiment or example will be described. The thin film integrated circuit peeled off from the substrate can be used as an IC chip. For example, banknotes, coins, securities, bearer bonds, certificates (driver's license, resident's card, etc., see FIG. 29A), packaging Containers (such as wrapping paper and bottles, see FIG. 29B), recording media such as DVD software, CDs and video tapes (see FIG. 29C), vehicles such as cars, motorcycles and bicycles (FIG. 29) (See (D)), personal items such as bags and glasses (see FIG. 29E), foods, clothing, daily necessities, electronic devices, and the like. Electronic devices refer to liquid crystal display devices, EL display devices, television devices (also simply referred to as televisions or television receivers), cellular phones, and the like.

  Note that the IC chip can be fixed to the article by being attached to the surface of the article or embedded in the article. For example, a book may be embedded in paper, and a package made of an organic resin may be embedded in the organic resin. Forgery can be prevented by providing IC chips on bills, coins, securities, bearer bonds, certificates, etc. Further, by providing IC chips in packaging containers, recording media, personal items, foods, clothing, daily necessities, electronic devices, etc., it is possible to improve the efficiency of inspection systems and rental store systems. In addition, forgery and theft can be prevented by providing an IC chip in vehicles.

  Further, by applying the IC chip to an object management or distribution system, it is possible to enhance the function of the system. For example, as shown in FIG. 30, a case where a reader / writer 271 is provided on a side surface of a portable terminal including the display portion 270 and an IC chip 272 is provided on a side surface of an article 273 is considered (FIG. 30A). In this case, when the IC chip 272 is held over the reader / writer 271, the display unit 270 displays information such as the raw material and origin of the product 273 and the history of distribution process. As another example, when a reader / writer 274 is provided on the side of the belt conveyor, the product 276 can be easily inspected (FIG. 30B).

The figure which shows the peeling method of this invention. The figure which shows the peeling method of this invention. The figure which shows the peeling method of this invention. The figure which shows the peeling method of this invention. The figure which shows the peeling method of this invention. The figure which shows the peeling method of this invention. The figure which shows the peeling method of this invention. The figure which shows the peeling method of this invention. The figure which shows the peeling method of this invention. The figure which shows the peeling method of this invention. The figure which shows the peeling method of this invention. The figure which shows the peeling method of this invention. The figure which shows the peeling method of this invention. The figure which shows the peeling method of this invention. The figure which shows the peeling method of this invention. The figure which shows the peeling method of this invention. The figure which shows the peeling method of this invention. 10A and 10B illustrate a manufacturing process of a semiconductor device of the present invention. 1 is a cross-sectional view of a thin film integrated circuit of the present invention. 1 is a cross-sectional view of a thin film integrated circuit of the present invention. 4A and 4B illustrate a manufacturing device of a semiconductor device of the present invention. 1 is a cross-sectional view of a thin film integrated circuit of the present invention. 1 is a cross-sectional view of a thin film integrated circuit of the present invention. 1 is a cross-sectional view of a thin film integrated circuit of the present invention. FIG. 11 is a cross-sectional view of a semiconductor device of the present invention. FIG. 11 is a cross-sectional view of a semiconductor device of the present invention. FIG. 11 illustrates an example of a semiconductor device of the invention. 4A and 4B illustrate a manufacturing device of a semiconductor device of the present invention. FIG. 13 illustrates an example of a usage pattern of a semiconductor device of the invention. FIG. 13 illustrates an example of a usage pattern of a semiconductor device of the invention. FIG. 11 is a diagram showing a photograph of a semiconductor device of the invention.

Claims (22)

Forming a release layer containing metal on the substrate;
Forming a plurality of thin film integrated circuits on the release layer;
Covering the upper and side surfaces of the plurality of thin film integrated circuits with a resin film,
By using an etchant, the release layer is removed,
A method for peeling a thin film integrated circuit, comprising peeling off the substrate and the plurality of thin film integrated circuits. Forming a release layer containing metal on the substrate;
Forming a plurality of thin film integrated circuits on the release layer;
Covering the upper and side surfaces of the plurality of thin film integrated circuits with a resin film,
By using an etching agent, removing at least a part of the release layer located below the thin film integrated circuit,
A method for peeling a thin film integrated circuit, comprising peeling off the substrate and the plurality of thin film integrated circuits bonded by the part of the peeling layer. Forming a release layer containing metal on the substrate;
Removing a part of the release layer to form a plurality of openings in the release layer;
Forming a thin film integrated circuit on the release layer and on the substrate of the plurality of openings;
Forming a resin film on the thin film integrated circuit;
By removing the release layer using an etchant, the substrate and the thin film integrated circuit are bonded to each other in the plurality of openings,
A method for peeling a thin film integrated circuit, comprising peeling off the substrate and the thin film integrated circuit. Forming a release layer containing metal on the substrate;
Forming a thin film integrated circuit on the release layer;
On the thin film integrated circuit, to form a resin film having a convex portion on at least part of the surface,
By using an etching agent, removing at least a part of the release layer located below the convex portion of the resin film ,
A method for peeling a thin film integrated circuit, comprising peeling off the substrate and the thin film integrated circuit bonded by the part of the peeling layer. In any one of Claims 1 thru | or 4,
A method for peeling a thin film integrated circuit, wherein the peeling layer is formed of a metal film containing tungsten (W), molybdenum (Mo), niobium (Nb), or titanium (Ti). In any one of Claims 1 thru | or 4,
The peeling layer includes a metal film and a metal oxide formed on the metal film. In claim 6,
The metal film and the metal oxide include a tungsten film and a tungsten oxide film on the tungsten film, a molybdenum film and a molybdenum oxide film on the molybdenum film, a niobium film and a niobium oxide film on the niobium film, or a titanium film. A method for peeling a thin film integrated circuit, which is a titanium oxide film on the titanium film. In any one of Claims 1 thru | or 7,
A method for peeling a thin film integrated circuit, wherein a liquid or a gas containing halogen fluoride is used as the etchant. In claim 8,
A method for peeling a thin film integrated circuit, wherein chlorine trifluoride (ClF ₃ ) is used as the liquid or gas containing halogen fluoride. In any one of Claims 1 thru | or 9,
A method for peeling a thin film integrated circuit, wherein an epoxy resin is used as the resin film. In any one of Claims 1 to 10,
A method for peeling a thin film integrated circuit, wherein a glass substrate or a quartz substrate is used as the substrate. Forming a release layer containing metal on the substrate;
Forming a plurality of thin film integrated circuits on the release layer;
Covering the upper and side surfaces of the plurality of thin film integrated circuits with a resin film,
By using an etchant, the release layer is removed,
Peeling off the substrate and the plurality of thin film integrated circuits;
A method for manufacturing a semiconductor device, wherein the plurality of peeled thin film integrated circuits are fixed to a flexible substrate. Forming a release layer containing metal on the substrate;
Forming a plurality of thin film integrated circuits on the release layer;
Covering the upper and side surfaces of the plurality of thin film integrated circuits with a resin film,
By using an etching agent, removing at least a part of the release layer located below the thin film integrated circuit,
Peeling the substrate and the plurality of thin film integrated circuits bonded by the part of the peeling layer,
A method for manufacturing a semiconductor device, wherein the plurality of peeled thin film integrated circuits are fixed to a flexible substrate. Forming a release layer containing metal on the substrate;
Removing a part of the release layer to form a plurality of openings in the release layer;
Forming a thin film integrated circuit on the release layer and on the substrate of the plurality of openings;
Forming a resin film on the thin film integrated circuit;
By removing the release layer using an etchant, the substrate and the thin film integrated circuit are bonded to each other in the plurality of openings,
Peeling off the substrate and the thin film integrated circuit;
A method for manufacturing a semiconductor device, wherein the peeled thin film integrated circuit is fixed to a flexible substrate. Forming a release layer containing metal on the substrate;
Forming a thin film integrated circuit on the release layer;
On the thin film integrated circuit, to form a resin film having a convex portion on at least part of the surface,
By using an etching agent, removing at least a part of the release layer located below the convex portion of the resin film ,
The peeled off and the substrate is bonded to the previous SL thin film integrated circuit by a part of the peeling layer,
A method for manufacturing a semiconductor device, wherein the peeled thin film integrated circuit is fixed to a flexible substrate. In any one of Claims 12 to 15,
The method for manufacturing a semiconductor device, wherein the peeling layer is formed using a metal film containing tungsten (W), molybdenum (Mo), niobium (Nb), or titanium (Ti). In any one of Claims 12 to 15,
The method for manufacturing a semiconductor device, wherein the peeling layer includes a metal film and a metal oxide formed over the metal film. In claim 17,
The metal film and the metal oxide include a tungsten film and a tungsten oxide film on the tungsten film, a molybdenum film and a molybdenum oxide film on the molybdenum film, a niobium film and a niobium oxide film on the niobium film, or a titanium film. A method for manufacturing a semiconductor device, which is a titanium oxide film over the titanium film. In any one of Claims 12 to 18,
A method for manufacturing a semiconductor device, wherein a liquid or a gas containing halogen fluoride is used as the etchant. In claim 19,
A method for manufacturing a semiconductor device, wherein chlorine trifluoride (ClF ₃ ) is used as the liquid or gas containing halogen fluoride. In any one of Claims 12 to 20,
An epoxy resin is used as the resin film. A method for manufacturing a semiconductor device. In any one of Claims 12 to 21,
A method for manufacturing a semiconductor device, wherein a glass substrate or a quartz substrate is used as the substrate.