JP2011181591A - Thin film semiconductor device, apparatus for manufacturing thin film semiconductor device, and method for manufacturing thin film semiconductor device - Google Patents
Thin film semiconductor device, apparatus for manufacturing thin film semiconductor device, and method for manufacturing thin film semiconductor device Download PDFInfo
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- 239000010409 thin film Substances 0.000 title claims abstract description 85
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 48
- 238000000034 method Methods 0.000 title abstract description 32
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 106
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- 239000010408 film Substances 0.000 claims abstract description 76
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- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 53
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- 239000007789 gas Substances 0.000 claims description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 16
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 16
- 239000010703 silicon Substances 0.000 claims description 16
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 7
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 7
- 229910052771 Terbium Inorganic materials 0.000 claims description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 7
- 229910052787 antimony Inorganic materials 0.000 claims description 7
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 claims description 7
- 229910052785 arsenic Inorganic materials 0.000 claims description 7
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 7
- 229910052797 bismuth Inorganic materials 0.000 claims description 7
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 claims description 7
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- BDOSMKKIYDKNTQ-UHFFFAOYSA-N cadmium atom Chemical compound [Cd] BDOSMKKIYDKNTQ-UHFFFAOYSA-N 0.000 claims description 7
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- 229910052714 tellurium Inorganic materials 0.000 claims description 7
- PORWMNRCUJJQNO-UHFFFAOYSA-N tellurium atom Chemical compound [Te] PORWMNRCUJJQNO-UHFFFAOYSA-N 0.000 claims description 7
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- 229910052716 thallium Inorganic materials 0.000 claims description 7
- BKVIYDNLLOSFOA-UHFFFAOYSA-N thallium Chemical compound [Tl] BKVIYDNLLOSFOA-UHFFFAOYSA-N 0.000 claims description 7
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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Abstract
Description
この発明は、特にプラスチック基板を用いたフレキシブルディスプレイである薄膜半導体装置、薄膜半導体製造装置及び薄膜半導体製造方法に関するものである。 The present invention relates to a thin film semiconductor device, a thin film semiconductor manufacturing apparatus and a thin film semiconductor manufacturing method which are flexible displays using a plastic substrate.
ディスプレイの画像駆動用薄膜半導体装置（ＴＦＴ）は、その半導体層として従来からａ−Ｓｉが用いられており、現在も一般に普及している。しかし、ａ−Ｓｉ を半導体層として用いたＴＦＴは、その電界効果移動度は非常に小さいため（〜０．１ｃｍ２／Ｖｓ）、近年急速に需要が増している高精細動画対応などの高機能用途には性能限界に達しつつあった。 Thin film semiconductor devices (TFTs) for image driving of displays have conventionally used a-Si as their semiconductor layers and are still in widespread use today. However, a TFT using a-Si as a semiconductor layer has a very small field effect mobility (˜0.1 cm 2 / Vs). The application was reaching its performance limit.
このため、ａ−Ｓｉに代わる半導体層として、ａ−Ｓｉにエキシマレーザなどを照射して多結晶化することでより高い電界効果移動度（〜１０ ｃｍ２／Ｖｓ）が得られるｐｏｌｙ−Ｓｉを半導体層として用いたＴＦＴが開発された（特許文献１など）。 For this reason, as a semiconductor layer that replaces a-Si, poly-Si that can obtain higher field-effect mobility (-10 cm 2 / Vs) by irradiating a-Si with an excimer laser or the like to be polycrystallized is used. TFTs used as semiconductor layers have been developed (Patent Document 1, etc.).
この技術は、一部用途で実用化されたが、結晶粒界がランダムに分布することでＴＦＴ性能の均一化が困難なことやレーザプロセスコストが甚大なことなどが課題となり十分な普及はされていない。 Although this technology has been put to practical use for some applications, it is difficult to achieve uniform TFT performance due to random distribution of crystal grain boundaries, and the laser process cost is enormous. Not.
さらに、前記したいずれのＳｉ系ＴＦＴも半導体層の成膜温度が比較的高温であるため、フレキシブルディスプレイなどに用いるプラスチック基板やロール状フィルム基板の耐熱温度を超えてしまい、基板フレキシブル化への対応が困難であるという問題もあった。 Furthermore, since any of the Si-based TFTs described above has a relatively high semiconductor layer deposition temperature, it exceeds the heat resistance temperature of plastic substrates and roll film substrates used for flexible displays, etc. There was also a problem that it was difficult.
これらに代わる新材料として、ＩｎＧａＺｎＯｘ系酸化物半導体が検討されている。このＩｎＧａＺｎＯｘ系酸化物半導体は、スパッタなどの非真空・低温プロセスで成膜できるため、フレキシブル基板上にも形成可能であり、プロセスも低コストである。この酸化物半導体は、低温プロセス成膜後そのままの状態では未だ性能不十分で、成膜後のアニールによる焼き締めを行うことで十分な性能を引き出すことができる。焼き締めは、炉アニールの場合は３００℃程度が必要なのでフレキシブル基板の（耐熱温度こそ超えないものの）熱膨張変形などの問題を起こしてしまう。そこでレーザーアニールなどの手法（ｐｏｌｙ−Ｓｉ形成時より低エネルギーで良いためコスト上昇要因になりにくい）を併用することにより、低温のまま十分な焼き締めを行うことが考えられている。いずれの手法を用いても、この酸化物半導体はアモルファス状態が保たれるので、上述のｐｏｌｙ−Ｓｉのような粒界によるばらつき懸念がないこと、電界効果移動度（〜１０ｃｍ２／Ｖｓ）が比較的高く高精細動画対応にも可能なことなど、Ｓｉには無い多くの利点を持っている。 InGaZnOx-based oxide semiconductors have been studied as a new material that can replace them. Since this InGaZnOx-based oxide semiconductor can be formed by a non-vacuum / low-temperature process such as sputtering, the InGaZnOx-based oxide semiconductor can be formed on a flexible substrate, and the process is also low in cost. This oxide semiconductor is still insufficient in performance as it is after low-temperature process film formation, and sufficient performance can be obtained by performing baking by annealing after film formation. In the case of furnace annealing, about 300 ° C. is necessary for baking, which causes problems such as thermal expansion deformation of the flexible substrate (although the heat resistance temperature is not exceeded). In view of this, it is considered to perform sufficient baking at a low temperature by using a technique such as laser annealing (which is less likely to cause a cost increase because lower energy is required than when poly-Si is formed). Whichever method is used, the oxide semiconductor is maintained in an amorphous state, so there is no fear of variation due to grain boundaries like the above-described poly-Si, and field effect mobility (-10 cm 2 / Vs). It has many advantages over Si, such as being relatively high and capable of handling high-definition video.
しかし、酸化物半導体は熱、光に対する安定性に課題があることが明らかとなってきた。外光（特に波長５００ｎｍ以下の近紫外領域の光）が入射するとＴＦＴのオフ電流が増大（波長３７０ｎｍではオフ電流が約２桁増大）し、それに伴いＴＦＴの閾値が５Ｖも変動する。ディスプレイはバックライトや外光などがＴＦＴに入射しやすい構造のため、このような特性変動を起こすことは回路動作上非常に大きな問題となり得る。 However, it has become clear that oxide semiconductors have problems with respect to heat and light stability. When external light (particularly light in the near-ultraviolet region with a wavelength of 500 nm or less) enters, the off-current of the TFT increases (the off-current increases by about two orders of magnitude at a wavelength of 370 nm), and the TFT threshold fluctuates by 5 V accordingly. Since the display has a structure in which backlights, external light, etc. are likely to enter the TFT, such a characteristic variation can be a very serious problem in circuit operation.
このような外光への信頼性を増すためには、ＴＦＴの上下に金属（配線と共通化されている場合もある）からなる遮光層を設けることが行われるが、遮光層を避けて入射する迷光を完全に遮断することは困難なため完全な対策とはならない。 In order to increase the reliability to such external light, a light shielding layer made of metal (sometimes shared with wiring) is provided above and below the TFT. Because it is difficult to completely block the stray light, it is not a complete measure.
さらに、酸化物半導体は熱に対しても敏感で、上述したように成膜後のアニールにより焼き締めを行ったとしても、使用環境が１００℃以上の温度になるとやはりオフ電流が増大し閾値が５Ｖ程度シフトする。このシフト量は使用環境温度が高いほど顕著で、２００℃以上ではトランジスタがスイッチングできなくなるほどである。これは酸化物半導体中の酸素と他元素との結合状態が熱により変化することが原因と考えられている。この変化は可逆的で、使用環境が元に戻れば、ＴＦＴ特性も数十分程度で元に戻るものの、ディスプレイ用途としては大きな課題であることに違いはない。 In addition, an oxide semiconductor is sensitive to heat, and even if it is baked by annealing after film formation as described above, the off-state current increases and the threshold value increases when the usage environment reaches 100 ° C. or higher. Shift about 5V. This shift amount becomes more conspicuous as the use environment temperature is higher, and the transistor cannot be switched at 200 ° C. or higher. This is considered to be caused by a change in the bonding state between oxygen and another element in the oxide semiconductor due to heat. This change is reversible, and if the use environment is restored, the TFT characteristics will be restored to a few tens of minutes, but there is no doubt that this is a major problem for display applications.
ディスプレイの通常使用環境ではこれほどの高温になることはないが、例えば車中など５０〜６０℃で長時間放置されるような場合は、累積的な効果で特性変動する可能性が高い。このように酸化物半導体でも新たな課題が明らかとなりつつある。 In a normal use environment of the display, the temperature does not become so high. However, when the display is left at a temperature of 50 to 60 ° C. for a long time, for example, in a car, there is a high possibility of characteristic fluctuation due to a cumulative effect. Thus, new problems are becoming apparent in oxide semiconductors.
この発明は、以上の点を考慮してなされたもので、低温プロセスで形成可能であり、低プロセスコストを実現し、また比較的高い電界効果移動度を実現でき、かつ光、熱に対して安定な特性を有し、曲げ環境にも適用できる薄膜半導体装置、薄膜半導体製造装置及び薄膜半導体製造方法を提案することを目的とする。 The present invention has been made in consideration of the above points, can be formed by a low-temperature process, can realize a low process cost, can realize a relatively high field-effect mobility, and is resistant to light and heat. An object of the present invention is to propose a thin film semiconductor device, a thin film semiconductor manufacturing apparatus, and a thin film semiconductor manufacturing method that have stable characteristics and can be applied to a bending environment.
前記課題を解決し、かつ目的を達成するために、この発明は、以下のように構成した。 In order to solve the above-described problems and achieve the object, the present invention is configured as follows.
請求項１に記載の発明は、プラスチック基板と、
前記プラスチック基板上に形成されたバリア層と、
前記バリア層上に形成された半導体層と、
前記半導体層の上下いずれかの面に接して形成された絶縁層と、
前記絶縁層に接して形成された金属層と、
を有し、
前記半導体層をチャネル、前記金属層をソース電極、ドレイン電極、およびゲート電極、前記絶縁層をゲート絶縁膜として用い、
前記半導体層は、非金属元素の窒素（Ｎ）、酸素（Ｏ）のうち少なくともひとつ、半金属元素のホウ素（Ｂ）、シリコン（Ｓｉ）、ゲルマニウム（Ｇｅ）、ヒ素（Ａｓ）、アンチモン（Ｓｂ）、テルル（Ｔｅ）、ポロニウム（Ｐｏ）のうち少なくともひとつ、および金属元素のアルミニウム（Ａｌ）、亜鉛（Ｚｎ）、ガリウム（Ｇａ）、カドニウム（Ｃｄ）、インジウム（Ｉｎ）、錫（Ｓｎ）、水銀（Ｈｇ）、タリウム（Ｔｌ）、テルビウム（Ｐｂ）、ビスマス（Ｂｉ）のうち少なくともひとつを含み、
前記非金属元素が、少なくとも酸素（Ｏ）と窒素（Ｎ）の混合物で、酸素（Ｏ）に対する窒素（Ｎ）の比（Ｎ数密度／Ｏ数密度）が０乃至２であることを特徴とする薄膜半導体装置である。
The invention according to claim 1 is a plastic substrate;
A barrier layer formed on the plastic substrate;
A semiconductor layer formed on the barrier layer;
An insulating layer formed in contact with either upper or lower surface of the semiconductor layer;
A metal layer formed in contact with the insulating layer;
Have
Using the semiconductor layer as a channel, the metal layer as a source electrode, a drain electrode, and a gate electrode, and the insulating layer as a gate insulating film,
The semiconductor layer includes at least one of nonmetallic elements nitrogen (N) and oxygen (O), semimetallic elements boron (B), silicon (Si), germanium (Ge), arsenic (As), and antimony (Sb). ), Tellurium (Te), at least one of polonium (Po), and the metal elements aluminum (Al), zinc (Zn), gallium (Ga), cadmium (Cd), indium (In), tin (Sn), Including at least one of mercury (Hg), thallium (Tl), terbium (Pb), bismuth (Bi),
The nonmetallic element is at least a mixture of oxygen (O) and nitrogen (N), and the ratio of nitrogen (N) to oxygen (O) (N number density / O number density) is 0 to 2. It is a thin film semiconductor device.
請求項２に記載の発明は、前記半金属元素が、少なくともシリコン（Ｓｉ）とゲルマニウム（Ｇｅ）の混合物Ｓｉ１−ｘＧｅｘ（ｘはＳｉとＧｅの混合比でｘ＝０乃至１が成り立つ）で、前記混合物（Ｓｉ１−ｘＧｅｘ）に対する窒素（Ｎ）の比（Ｎ数密度／Ｓｉ１−ｘＧｅｘ数密度）が１乃至２であることを特徴とする請求項１に記載の薄膜半導体装置である。 In the invention according to claim 2, the metalloid element is at least a mixture Si1-xGex of silicon (Si) and germanium (Ge) (x is a mixture ratio of Si and Ge, and x = 0 to 1 is established), 2. The thin film semiconductor device according to claim 1, wherein a ratio (N number density / Si 1-x Gex number density) of nitrogen (N) to the mixture (Si 1-x Gex) is 1 to 2. 3.
請求項３に記載の発明は、前記プラスチック基板が、少なくともロール状フィルム基板であることを特徴とする請求項１または請求項２に記載の薄膜半導体装置である。 A third aspect of the present invention is the thin film semiconductor device according to the first or second aspect, wherein the plastic substrate is at least a roll-shaped film substrate.
請求項４に記載の発明は、前記半導体層は、アモルファスであることを特徴とする請求項１乃至請求項３のいずれか１項に記載の薄膜半導体装置である。 A fourth aspect of the present invention is the thin film semiconductor device according to any one of the first to third aspects, wherein the semiconductor layer is amorphous.
請求項５に記載の発明は、前記半導体層のバンドギャップは、１ｅＶ乃至５ｅＶであることを特徴とする請求項１乃至請求項４のいずれか１項に記載の薄膜半導体装置である。 A fifth aspect of the present invention is the thin film semiconductor device according to any one of the first to fourth aspects, wherein a band gap of the semiconductor layer is 1 eV to 5 eV.
請求項６に記載の発明は、前記半導体層の主キャリアは、電子で、キャリア濃度は３００Ｋの熱平衡状態において１×１０Ｅ１６乃至１×１０Ｅ２１（ｍ−３）、電界効果移動度は０．１乃至５０（ｃｍ２／Ｖｓ）であることを特徴とする請求項１乃至請求項４のいずれか１項に記載の薄膜半導体装置である。 According to a sixth aspect of the present invention, the main carrier of the semiconductor layer is an electron, the carrier concentration is 1 × 10E 16 to 1 × 10E 21 (m −3 ) in a thermal equilibrium state of 300K, and the field effect mobility is 0.1. It is 1 thru | or 50 (cm < 2 > / Vs), It is a thin film semiconductor device of any one of Claim 1 thru | or 4 characterized by the above-mentioned.
請求項７に記載の発明は、前記半導体層が、液晶表示装置を駆動する回路を構成することを特徴とする請求項１乃至請求項６のいずれか１項に記載の薄膜半導体装置である。 The invention described in claim 7 is the thin film semiconductor device according to any one of claims 1 to 6, wherein the semiconductor layer constitutes a circuit for driving a liquid crystal display device.
請求項８に記載の発明は、前記ロール状フィルム基板と、
前記ロール状フィルム基板上に形成されたバリア層と、
前記バリア層上に形成された半導体層と、
前記半導体層の上下いずれかの面に接して形成された絶縁層と、
前記絶縁層に接して形成された金属層と、
を有し、
前記半導体層をチャネル、前記金属層をソース電極、ドレイン電極、およびゲート電極、前記絶縁層をゲート絶縁膜として用い、
前記半導体層は、非金属元素の窒素（Ｎ）、酸素（Ｏ）のうち少なくともひとつ、半金属元素のホウ素（Ｂ）、シリコン（Ｓｉ）、ゲルマニウム（Ｇｅ）、ヒ素（Ａｓ）、アンチモン（Ｓｂ）、テルル（Ｔｅ）、ポロニウム（Ｐｏ）のうち少なくともひとつ、および金属元素のアルミニウム（Ａｌ）、亜鉛（Ｚｎ）、ガリウム（Ｇａ）、カドニウム（Ｃｄ）、インジウム（Ｉｎ）、錫（Ｓｎ）、水銀（Ｈｇ）、タリウム（Ｔｌ）、テルビウム（Ｐｂ）、ビスマス（Ｂｉ）のうち少なくともひとつを含み、
前記非金属元素が、少なくとも酸素（Ｏ）と窒素（Ｎ）の混合物で酸素（Ｏ）に対する窒素（Ｎ）の比（Ｎ数密度／Ｏ数密度）が０乃至２である前記半導体層をスパッタ装置により形成する薄膜半導体製造装置である。
The invention according to claim 8 is the roll film substrate,
A barrier layer formed on the roll film substrate;
A semiconductor layer formed on the barrier layer;
An insulating layer formed in contact with either upper or lower surface of the semiconductor layer;
A metal layer formed in contact with the insulating layer;
Have
Using the semiconductor layer as a channel, the metal layer as a source electrode, a drain electrode, and a gate electrode, and the insulating layer as a gate insulating film,
The semiconductor layer includes at least one of nonmetallic elements nitrogen (N) and oxygen (O), semimetallic elements boron (B), silicon (Si), germanium (Ge), arsenic (As), and antimony (Sb). ), Tellurium (Te), at least one of polonium (Po), and the metal elements aluminum (Al), zinc (Zn), gallium (Ga), cadmium (Cd), indium (In), tin (Sn), Including at least one of mercury (Hg), thallium (Tl), terbium (Pb), bismuth (Bi),
The non-metallic element is a mixture of at least oxygen (O) and nitrogen (N), and the ratio of nitrogen (N) to oxygen (O) (N number density / O number density) is 0 to 2 is sputtered. A thin film semiconductor manufacturing apparatus formed by the apparatus.
請求項９に記載の発明は、前記半金属元素が、少なくともシリコン（Ｓｉ）とゲルマニウム（Ｇｅ）の混合物Ｓｉ１−ｘＧｅｘ（ｘはＳｉとＧｅの混合比でｘ＝０乃至１が成り立つ）で、前記混合物（Ｓｉ１−ｘＧｅｘ）に対する窒素（Ｎ）の比（Ｎ数密度／Ｓｉ１−ｘＧｅｘ数密度）が１乃至２であることを特徴とする請求項８に記載の薄膜半導体製造装置である。 In the invention according to claim 9, the metalloid element is at least a mixture Si1-xGex of silicon (Si) and germanium (Ge) (x is a mixture ratio of Si and Ge, and x = 0 to 1 is established), 9. The thin film semiconductor manufacturing apparatus according to claim 8, wherein a ratio of nitrogen (N) to the mixture (Si 1-x Gex) (N number density / Si 1-x Gex number density) is 1 to 2. 9.
請求項１０に記載の発明は、前記スパッタ装置は、
前記ロール状フィルム基板を装着するロール巻機構と、
前記ロール状フィルム基板を長尺方向に沿って一方の端部から送り出す送出機構と、
送り出された前記ロール状フィルム基板を巻き取る巻取機構と、
位置合わせパターンを有する前記ロール状フィルム基板に対し、前記ロール状フィルム基板の平面位置合わせを行う位置合わせ機構と、
前記ロール状フィルム基板の半導体形成面に対面する金属ターゲットと、
を有し、
前記全ての機構を内部に保持する真空チャンバを備えたことを特徴とする請求項８また請求項９に記載の薄膜半導体製造装置である。
The invention according to claim 10 is characterized in that the sputtering apparatus comprises:
A roll winding mechanism for mounting the roll film substrate;
A delivery mechanism for delivering the roll-shaped film substrate from one end along the longitudinal direction;
A winding mechanism for winding up the rolled film substrate that has been sent out;
An alignment mechanism that performs planar alignment of the roll-shaped film substrate with respect to the roll-shaped film substrate having the alignment pattern,
A metal target facing the semiconductor forming surface of the roll film substrate;
Have
10. The thin film semiconductor manufacturing apparatus according to claim 8, further comprising a vacuum chamber for holding all the mechanisms therein.
請求項１１に記載の発明は、前記スパッタ装置は、
前記非金属元素を含む雰囲気ガスを真空チャンバ内に導入するガス導入機構と、
前記金属元素または前記半金属元素またはこれらの混合物を含む金属ターゲットと、を複数有し、
前記金属ターゲットが、前記ロール状フィルム基板の長尺に沿った直線状の位置に配列されていることを特徴とする請求項８または請求項９に記載の薄膜半導体製造装置である。
The invention according to claim 11 is characterized in that the sputtering apparatus comprises:
A gas introduction mechanism for introducing an atmospheric gas containing the nonmetallic element into a vacuum chamber;
A plurality of metal targets including the metal element or the metalloid element or a mixture thereof,
The thin film semiconductor manufacturing apparatus according to claim 8 or 9, wherein the metal targets are arranged at linear positions along the length of the roll film substrate.
請求項１２に記載の発明は、前記スパッタ装置は、
前記非金属元素、前記金属元素、前記半金属元素それぞれ少なくともひとつを含む複数の元素を混ぜ合わせた混合物を、単一のターゲットとして用いたことを特徴とする請求項８乃至請求項１１のいずれか１項に記載の薄膜半導体製造装置である。
The invention according to claim 12 is characterized in that the sputtering apparatus comprises:
The mixture of a plurality of elements each including at least one of the non-metallic element, the metallic element, and the metalloid element is used as a single target. 2. A thin-film semiconductor manufacturing apparatus according to item 1.
請求項１３に記載の発明は、請求項８乃至請求項１２のいずれか１項に記載の薄膜半導体製造装置を用い、
薄膜半導体装置を製造することを特徴とする薄膜半導体製造方法である。
Invention of Claim 13 uses the thin film semiconductor manufacturing apparatus of any one of Claim 8 thru | or 12,
A thin film semiconductor device manufacturing method characterized by manufacturing a thin film semiconductor device.
前記構成により、この発明は、以下のような効果を有する。 With the above configuration, the present invention has the following effects.
請求項１に記載の発明では、薄膜半導体装置の半導体層をチャネル、金属層をソース、ドレイン、およびゲート、絶縁層をゲート絶縁膜として用い、半導体層は、非金属元素の窒素（Ｎ）、酸素（Ｏ）のうち少なくともひとつ、半金属元素のホウ素（Ｂ）、シリコン（Ｓｉ）、ゲルマニウム（Ｇｅ）、ヒ素（Ａｓ）、アンチモン（Ｓｂ）、テルル（Ｔｅ）、ポロニウム（Ｐｏ）のうち少なくともひとつ、および金属元素のアルミニウム（Ａｌ）、亜鉛（Ｚｎ）、ガリウム（Ｇａ）、カドニウム（Ｃｄ）、インジウム（Ｉｎ）、錫（Ｓｎ）、水銀（Ｈｇ）、タリウム（Ｔｌ）、テルビウム（Ｐｂ）、ビスマス（Ｂｉ）のうち少なくともひとつを含み、非金属元素が、少なくとも酸素（Ｏ）と窒素（Ｎ）の混合物で、酸素（Ｏ）に対する窒素（Ｎ）の比（Ｎ数密度／Ｏ数密度）が０乃至２であることで、半導体層への窒素（Ｎ）の導入により比較的高い電界効果移動度を実現できる。また、半導体層への窒素（Ｎ）の導入によりバンドギャップを広げることで、光、熱による特性変動を抑制することができる。また、半導体層への窒素（Ｎ）の導入により弾性定数（ヤング率）を増加させ、プラスチック基板やロール状フィルム基板上での構造的強度を向上させ、曲げ環境にも適用できる。また、半導体層は、スパッタリングの低温プロセスで形成可能であり、低プロセスコストを実現できる。 In the first aspect of the present invention, the semiconductor layer of the thin film semiconductor device is used as a channel, the metal layer is used as a source, drain, and gate, the insulating layer is used as a gate insulating film, and the semiconductor layer includes nitrogen (N) of a nonmetallic element, At least one of oxygen (O), boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te), polonium (Po) at least one of the metalloid elements One and the metal elements aluminum (Al), zinc (Zn), gallium (Ga), cadmium (Cd), indium (In), tin (Sn), mercury (Hg), thallium (Tl), terbium (Pb) , Including at least one of bismuth (Bi), and the nonmetallic element is a mixture of at least oxygen (O) and nitrogen (N), and nitrogen (N By the ratio (N number density / O number density) of from 0 to 2, it can be realized relatively high field-effect mobility by the introduction of nitrogen (N) into the semiconductor layer. Further, by widening the band gap by introducing nitrogen (N) into the semiconductor layer, characteristic fluctuation due to light and heat can be suppressed. Further, by introducing nitrogen (N) into the semiconductor layer, the elastic constant (Young's modulus) is increased, the structural strength on the plastic substrate or the roll-shaped film substrate is improved, and it can be applied to a bending environment. Further, the semiconductor layer can be formed by a low-temperature process of sputtering, and a low process cost can be realized.
請求項２に記載の発明では、半金属元素が、少なくともシリコン（Ｓｉ）とゲルマニウム（Ｇｅ）の混合物Ｓｉ１−ｘＧｅｘ（ｘはＳｉとＧｅの混合比でｘ＝０乃至１が成り立つ）で、前記混合物（Ｓｉ１−ｘＧｅｘ）に対する窒素（Ｎ）の比（Ｎ数密度／Ｓｉ１−ｘＧｅｘ数密度）が１乃至２であり、半金属元素のシリコン（Ｓｉ）にゲルマニウム（Ｇｅ）を導入することによりバンドギャップを小さくすることができ、これと請求項１の窒素（Ｎ）の導入によるバンドギャップ増大とを組み合わせて、自在にバンドギャップを制御でき、また電界効果移動度を増大させることができる。 In the invention according to claim 2, the metalloid element is at least a mixture Si1-xGex of silicon (Si) and germanium (Ge) (where x is a mixture ratio of Si and Ge, x = 0 to 1), and The ratio of nitrogen (N) to the mixture (Si1-xGex) (N number density / Si1-xGex number density) is 1 to 2, and a band is formed by introducing germanium (Ge) into the metalloid silicon (Si). The gap can be reduced, and this can be combined with the band gap increase by introducing nitrogen (N) in claim 1 to freely control the band gap and to increase the field effect mobility.
請求項３に記載の発明では、プラスチック基板が、少なくともロール状フィルム基板であり、製造時にロール状態から送り出しロール状態に巻き取り、低プロセスコストを実現し、低価格のディスプレイを提供することができる。 In the invention according to claim 3, the plastic substrate is at least a roll-shaped film substrate, and is wound from the roll state to the feed roll state at the time of manufacture, realizing a low process cost and providing a low-cost display. .
請求項４に記載の発明では、半導体層は、アモルファスであり、粒界がないことで、特性の均一性を増加させ、かつプラスチック基板やロール状フィルム基板上に形成された場合の曲げ強度を向上させることができる。 In the invention of claim 4, the semiconductor layer is amorphous and has no grain boundary, thereby increasing the uniformity of characteristics and the bending strength when formed on a plastic substrate or a roll film substrate. Can be improved.
請求項５に記載の発明では、半導体層のバンドギャップは、半導体層への窒素（Ｎ）の導入により広げることができるが、１ｅＶ乃至５ｅＶであることで、可視から近紫外領域の外光入射による特性変動を抑制することができる。 In the invention described in claim 5, the band gap of the semiconductor layer can be widened by introducing nitrogen (N) into the semiconductor layer. However, by being 1 eV to 5 eV, external light incidence in the visible to near-ultraviolet region is achieved. Variations in characteristics due to
請求項６に記載の発明では、半導体層の主キャリアは、電子で、キャリア濃度は３００Ｋの熱平衡状態において１×１０Ｅ１６乃至１×１０Ｅ２１（ｍ−３）、電界効果移動度は０．１乃至５０（ｃｍ２／Ｖｓ）であり、より高い電界効果移動度が得られることで、高精細の動画まで対応できる。 In the invention according to claim 6, the main carrier of the semiconductor layer is an electron, the carrier concentration is 1 × 10E16 to 1 × 10E21 (m −3 ) in a thermal equilibrium state of 300 K, and the field effect mobility is 0.1 to 50. (Cm 2 / Vs), and higher field-effect mobility can be obtained, so that even high-definition movies can be handled.
請求項７に記載の発明では、半導体層が、液晶表示装置を駆動する回路を構成し、
アクティブマトリクス型液晶表示装置に対応できる。
In the invention according to claim 7, the semiconductor layer constitutes a circuit for driving the liquid crystal display device,
Compatible with active matrix liquid crystal display devices.
請求項８に記載の発明では、半導体層をスパッタ方式により形成することで、低温プロセスで形成可能であり、低プロセスコストを実現し、また比較的高い移動度を実現でき、かつ光、熱に対して安定な特性を有する薄膜半導体装置を製造することができる。 In the invention according to claim 8, by forming the semiconductor layer by a sputtering method, it can be formed by a low temperature process, a low process cost can be realized, a relatively high mobility can be realized, and light and heat can be realized. In contrast, a thin film semiconductor device having stable characteristics can be manufactured.
請求項９に記載の発明では、自在にバンドギャップを制御でき、また電界効果移動度を増大させることができる薄膜半導体製造装置を製造することができる。 According to the ninth aspect of the present invention, it is possible to manufacture a thin film semiconductor manufacturing apparatus capable of freely controlling the band gap and increasing the field effect mobility.
請求項１０に記載の発明では、スパッタ装置は、全ての機構を内部に保持する真空チャンバを備え、製造時にロール状態から送り出しロール状態に巻き取るロールツーロール法を用いて低プロセスコストを実現することができる。 In a tenth aspect of the present invention, the sputtering apparatus includes a vacuum chamber that holds all the mechanisms therein, and realizes a low process cost by using a roll-to-roll method of winding from a roll state to a feed roll state during manufacturing. be able to.
請求項１１に記載の発明では、スパッタ装置は、非金属元素を含む雰囲気ガスを真空チャンバ内に導入し、金属元素または半金属元素またはこれらの混合物を含む金属ターゲットを複数有し、金属ターゲットが、ロール状フィルム基板の長尺に沿った直線状の位置に配列され、ロール状フィルム基板内に均一な性質の半導体層を形成できる。 In the invention according to claim 11, the sputtering apparatus introduces an atmospheric gas containing a nonmetallic element into the vacuum chamber, and has a plurality of metal targets containing a metal element, a metalloid element, or a mixture thereof. A semiconductor layer having a uniform property can be formed in the roll film substrate by being arranged at linear positions along the length of the roll film substrate.
請求項１２に記載の発明では、スパッタ装置は、非金属元素、金属元素、半金属元素それぞれ少なくともひとつを含む複数の元素を混ぜ合わせた混合物を、単一のターゲットとして用い、半導体層の性質をさらに均一にするとともにスパッタプロセスコストを低減できる。 In the invention described in claim 12, the sputtering apparatus uses a mixture obtained by mixing a plurality of elements including at least one of a nonmetallic element, a metallic element, and a semimetallic element as a single target, and the properties of the semiconductor layer are adjusted. Furthermore, the sputtering process cost can be reduced while making it uniform.
請求項１３に記載の発明では、請求項８乃至請求項１２のいずれか１項に記載の薄膜半導体製造装置を用い、薄膜半導体装置を製造する。 In a thirteenth aspect of the present invention, a thin film semiconductor device is manufactured using the thin film semiconductor manufacturing apparatus according to any one of the eighth to twelfth aspects.
以下、この発明の薄膜半導体装置、薄膜半導体製造装置及び薄膜半導体製造方法の実施の形態について説明する。この実施の形態は好ましい形態を示すものであるが、この発明はこれに限定されない。 Hereinafter, embodiments of the thin film semiconductor device, the thin film semiconductor manufacturing apparatus, and the thin film semiconductor manufacturing method of the present invention will be described. Although this embodiment shows a preferred embodiment, the present invention is not limited to this.
［薄膜半導体装置］
まず、この発明の薄膜半導体装置について説明する。図１は薄膜半導体装置の構成を説明する断面図である。
[Thin film semiconductor device]
First, the thin film semiconductor device of the present invention will be described. FIG. 1 is a cross-sectional view illustrating the structure of a thin film semiconductor device.
この実施の形態の薄膜半導体装置１は、プラスチック基板２を有し、このプラスチック基板２の両面にバリア層３，４が形成されている。プラスチック基板２上に形成されたバリア層３の上面には、接着層５を介してガラス基板６が設けられ、このガラス基板６の上面に半導体層７が形成されている。ガラス基板６は、半導体層７を形成するための土台として、ある程度の厚さ（０．５ｍｍ程度）を持っていた元状態から、半導体層７形成後にエッチングなどの処理で削って薄型化（０．１ｍｍ以下）したものであり、接着層５を介してプラスチック基板２と半導体層７が接合された後は不要となる。このため、場合によりガラス基板６を完全にエッチング除去しても良い。 The thin film semiconductor device 1 of this embodiment has a plastic substrate 2, and barrier layers 3 and 4 are formed on both surfaces of the plastic substrate 2. A glass substrate 6 is provided on the upper surface of the barrier layer 3 formed on the plastic substrate 2 via an adhesive layer 5, and a semiconductor layer 7 is formed on the upper surface of the glass substrate 6. The glass substrate 6 is thinned from the original state having a certain thickness (about 0.5 mm) as a base for forming the semiconductor layer 7 by a process such as etching after the formation of the semiconductor layer 7 (0 .1 mm or less) and becomes unnecessary after the plastic substrate 2 and the semiconductor layer 7 are bonded via the adhesive layer 5. Therefore, in some cases, the glass substrate 6 may be completely removed by etching.
このようにして半導体層７がバリア層３上に形成され、この半導体層７の下面がガラス基板６の上面に形成した絶縁層８ａと接して形成され、上面が層間絶縁膜８ｂと接して形成されている。絶縁層８ａ下面に接して金属層９ｃが形成されている。また、半導体層７上面に接して金属層９ａ、９ｂが形成されている。半導体層７をチャネル、金属層９ａをソース電極、金属層９ｂをドレイン電極、および金属層９ｃをゲート電極、絶縁層８ａをゲート絶縁膜として用いている。図１では上から、金属層９ａおよび９ｂ、半導体層７、絶縁層８ａ、金属層９ｃの順となっている（ボトムゲート構造）が、場合により上下を逆にして、上から金属層９ｃ、絶縁層８ａ、半導体層７、金属層９ａおよび９ｂ（トップゲート構造）としても良いことは言うまでもない。 In this way, the semiconductor layer 7 is formed on the barrier layer 3, the lower surface of the semiconductor layer 7 is formed in contact with the insulating layer 8a formed on the upper surface of the glass substrate 6, and the upper surface is formed in contact with the interlayer insulating film 8b. Has been. A metal layer 9c is formed in contact with the lower surface of the insulating layer 8a. Metal layers 9 a and 9 b are formed in contact with the upper surface of the semiconductor layer 7. The semiconductor layer 7 is used as a channel, the metal layer 9a as a source electrode, the metal layer 9b as a drain electrode, the metal layer 9c as a gate electrode, and the insulating layer 8a as a gate insulating film. In FIG. 1, the metal layers 9a and 9b, the semiconductor layer 7, the insulating layer 8a, and the metal layer 9c are arranged in this order from the top (bottom gate structure). Needless to say, the insulating layer 8a, the semiconductor layer 7, and the metal layers 9a and 9b (top gate structure) may be used.
半導体層７は、非金属元素の窒素（Ｎ）、酸素（Ｏ）のうち少なくともひとつ、半金属元素のホウ素（Ｂ）、シリコン（Ｓｉ）、ゲルマニウム（Ｇｅ）、ヒ素（Ａｓ）、アンチモン（Ｓｂ）、テルル（Ｔｅ）、ポロニウム（Ｐｏ）のうち少なくともひとつ、および金属元素のアルミニウム（Ａｌ）、亜鉛（Ｚｎ）、ガリウム（Ｇａ）、カドニウム（Ｃｄ）、インジウム（Ｉｎ）、錫（Ｓｎ）、水銀（Ｈｇ）、タリウム（Ｔｌ）、テルビウム（Ｐｂ）、ビスマス（Ｂｉ）のうち少なくともひとつを含み、非金属元素が、少なくとも酸素（Ｏ）と窒素（Ｎ）の混合物で酸素（Ｏ）に対する窒素（Ｎ）の比（Ｎ数密度／Ｏ数密度）が０乃至２である。 The semiconductor layer 7 includes at least one of non-metallic elements nitrogen (N) and oxygen (O), semi-metallic elements boron (B), silicon (Si), germanium (Ge), arsenic (As), and antimony (Sb). ), Tellurium (Te), at least one of polonium (Po), and the metal elements aluminum (Al), zinc (Zn), gallium (Ga), cadmium (Cd), indium (In), tin (Sn), It contains at least one of mercury (Hg), thallium (Tl), terbium (Pb), and bismuth (Bi), and the nonmetallic element is a mixture of at least oxygen (O) and nitrogen (N) and nitrogen relative to oxygen (O) The ratio of (N) (N number density / O number density) is 0 to 2.
半導体層７は、金属原料（Ｉｎ２Ｏ３， ＳｎＯ２）と絶縁体原料（Ｓｉ３Ｎ４）の組み合わせから作製する。金属原料は窒化物を用いようとしてもそれ自体が初めから絶縁体なので、他の絶縁体原料といくら混ぜても半導体は形成できない。このため、金属原料はそれ自体が金属である酸化物を用いる。これに対し、絶縁体原料に窒化物を用いると、両者を混ぜて作製される半導体は酸素（Ｏ）と窒素（Ｎ）の両方を含む酸窒化物の混合物となる。混合の様子を次の式で表す。正負の価数が釣り合う条件で混合比ｘ、ｙを決めることができる。
The semiconductor layer 7 is produced from a combination of a metal raw material (In 2 O 3 , SnO 2 ) and an insulator raw material (Si 3 N 4 ). Even if nitride is used as the metal raw material, it is an insulator itself from the beginning, so that no semiconductor can be formed no matter how much it mixes with other insulator raw materials. For this reason, the metal raw material uses the oxide which is a metal itself. On the other hand, when nitride is used as the insulator raw material, a semiconductor produced by mixing both becomes an oxynitride mixture containing both oxygen (O) and nitrogen (N). The state of mixing is expressed by the following formula. The mixing ratios x and y can be determined under conditions where the positive and negative valences are balanced.
主たる金属原料Ｉｎ２Ｏ３の混合比ｘ、絶縁体材料Ｓｉ３Ｎ４の混合比ｙとすると、価数釣り合いから、従たる金属原料ＳｎＯ２の混合比は６−ｘとなる。金属原料と絶縁体原料の比ｘ：ｙは、原料それぞれのバンドギャップと、混合後に形成される半導体のバンドギャップによって決まり、例えばｘの範囲としてはｘ＝０〜６（典型値５）、ｙの範囲としてはｙ＝０〜６（典型値３）が望ましい。
従って、Ｏ：Ｎの数量比は、
Ｏ＝１２〜１８ （典型値１７）
Ｎ＝０〜２４（典型値１２）となる。
従って、Ｏ：Ｎ＝１：０〜２
酸素１に対する窒素の数密度比、すなわち酸素（Ｏ）に対する窒素（Ｎ）の比（Ｎ数密度／Ｏ数密度）は０乃至２である。
If the mixing ratio x of the main metal raw material In 2 O 3 and the mixing ratio y of the insulator material Si 3 N 4 are set, the mixing ratio of the subordinate metal raw material SnO 2 is 6-x from the valence balance. The ratio x: y of the metal raw material to the insulator raw material is determined by the band gap of each raw material and the band gap of the semiconductor formed after mixing. For example, the range of x is x = 0-6 (typical value 5), y Is preferably y = 0 to 6 (typical value 3).
Therefore, the quantity ratio of O: N is
O = 12-18 (typical value 17)
N = 0 to 24 (typical value 12).
Therefore, O: N = 1: 0 to 2
The number density ratio of nitrogen to oxygen 1, that is, the ratio of nitrogen (N) to oxygen (O) (N number density / O number density) is 0 to 2.
また、半金属元素が、少なくともシリコン（Ｓｉ）とゲルマニウム（Ｇｅ）の混合物Ｓｉ１−ｘＧｅｘ（ｘはＳｉとＧｅの混合比でｘ＝０乃至１が成り立つ）で、混合物（Ｓｉ１−ｘＧｅｘ）に対する窒素（Ｎ）の比（Ｎ数密度／Ｓｉ１−ｘＧｅｘ数密度）が１乃至２である。
Ｓｉ：Ｇｅの組成比は、
Ｓｉ、Ｇｅ間の組成変化は前記バランスに影響しないので、
Ｓｉに対するＧｅの組成比は、Ｓｉ１−ｘＧｅｘにおいてｘ＝０〜１である。
Further, the metalloid element is at least a mixture Si1-xGex of silicon (Si) and germanium (Ge) (x is a mixture ratio of Si and Ge, where x = 0 to 1), and nitrogen with respect to the mixture (Si1-xGex) The ratio (N) (N number density / Si1-xGex number density) is 1 to 2.
The composition ratio of Si: Ge is
Since the composition change between Si and Ge does not affect the balance,
The composition ratio of Ge to Si is x = 0 to 1 in Si1-xGex.
ＳｉＧｅに対する窒素の数量比は、
（Ｓｉ１−ｘＧｅｘ）３ｙに対しＮ４ｙより常に１：１．３３である。
The quantity ratio of nitrogen to SiGe is
(Si1-xGex) 3y is always 1: 1.33 than N4y.
この実施の形態では、半導体層７は、非金属元素の窒素（Ｎ）、酸素（Ｏ）のうち少なくともひとつ、半金属元素のホウ素（Ｂ）、シリコン（Ｓｉ）、ゲルマニウム（Ｇｅ）、ヒ素（Ａｓ）、アンチモン（Ｓｂ）、テルル（Ｔｅ）、ポロニウム（Ｐｏ）のうち少なくともひとつ、および金属元素のアルミニウム（Ａｌ）、亜鉛（Ｚｎ）、ガリウム（Ｇａ）、カドニウム（Ｃｄ）、インジウム（Ｉｎ）、錫（Ｓｎ）、水銀（Ｈｇ）、タリウム（Ｔｌ）、テルビウム（Ｐｂ）、ビスマス（Ｂｉ）のうち少なくともひとつを含むことで、安価で容易に得ることができる半金属元素、金属元素を用いている。 In this embodiment, the semiconductor layer 7 includes at least one of non-metallic elements nitrogen (N) and oxygen (O), semi-metallic elements boron (B), silicon (Si), germanium (Ge), arsenic ( As), antimony (Sb), tellurium (Te), polonium (Po), and the metal elements aluminum (Al), zinc (Zn), gallium (Ga), cadmium (Cd), indium (In) Including at least one of tin (Sn), mercury (Hg), thallium (Tl), terbium (Pb), and bismuth (Bi), a metalloid element that can be easily obtained at low cost is used. ing.
上述の半金属元素、金属元素は、いずれもそれぞれの単体で半金属、金属として振る舞うものである。元素にはこの他にもアルカリ金属、遷移元素などがあり、それらの混合物まで考えると候補は無数に考えられるが、単体でわかりやすい性質を持つこと、入手しやすさ、原料費、プロセス取り扱いなどに優れている点を考慮すると、候補原料は事実上これらに限定される。 Each of the above-mentioned metalloid elements and metal elements behaves as a metalloid and a metal by themselves. In addition to these elements, there are alkali metals, transition elements, etc., and even a mixture of them can be considered innumerable candidates, but they have easy-to-understand properties, availability, raw material costs, process handling, etc. Considering the superiority, the candidate raw materials are practically limited to these.
また、室温でのスパッタプロセスで形成できる酸化物半導体をベースし、これに酸素（Ｏ）のみでなく窒素（Ｎ）を組み合わせた酸窒化物半導体とする。 In addition, an oxide semiconductor that can be formed by a sputtering process at room temperature is used as an oxynitride semiconductor in which not only oxygen (O) but also nitrogen (N) is combined.
非金属元素が、少なくとも酸素（Ｏ）と窒素（Ｎ）の混合物で、酸素（Ｏ）に対する窒素（Ｎ）の比（Ｎ数密度／Ｏ数密度）が０乃至２であることで、半導体層７への窒素（Ｎ）の導入により比較的高い電界効果移動度を実現できる。また、半導体層７への窒素（Ｎ）の導入によりバンドギャップを広げることで、光、熱による特性変動を抑制することができる。また、半導体層７への窒素（Ｎ）の導入により弾性定数（ヤング率）を増加させ、プラスチック基板やロール状フィルム基板上での構造的強度を向上させ、低温プロセスで形成可能であり、低プロセスコストを実現できる。 The non-metallic element is a mixture of at least oxygen (O) and nitrogen (N), and the ratio of nitrogen (N) to oxygen (O) (N number density / O number density) is 0 to 2, whereby the semiconductor layer By introducing nitrogen (N) into 7, a relatively high field effect mobility can be realized. Further, by widening the band gap by introducing nitrogen (N) into the semiconductor layer 7, it is possible to suppress fluctuations in characteristics due to light and heat. In addition, the introduction of nitrogen (N) into the semiconductor layer 7 increases the elastic constant (Young's modulus), improves the structural strength on the plastic substrate and the roll film substrate, and can be formed by a low-temperature process. Process costs can be realized.
酸素（Ｏ）に対する窒素（Ｎ）の比（Ｎ数密度／Ｏ数密度）が０乃至２の範囲となるのは、上記「酸素（Ｏ）に対する窒素（Ｎ）の比（Ｎ数密度／Ｏ数密度）は０乃至２」について述べたように、バンドギャップと価数釣り合いから決まる。仮にこの値が０（窒素が全く存在しない）となった場合、酸素の量によっては、半導体のバンドギャップが小さすぎて金属的となり、薄膜半導体装置１が常時オン状態となってしまう。逆にこの値が２を超える（酸素不足、窒素過剰）場合、半導体のバンドギャップが大きすぎて絶縁体的となり、薄膜半導体装置１が常時オフ状態となってしまう。いずれの場合もＴＦＴ特性として問題が起きる。 The ratio of nitrogen (N) to oxygen (O) (N number density / O number density) is in the range of 0 to 2 because the ratio of nitrogen (N) to oxygen (O) (N number density / O The number density is determined from the band gap and the valence balance, as described for “0 to 2”. If this value is 0 (no nitrogen is present), depending on the amount of oxygen, the band gap of the semiconductor is too small and metallic, and the thin film semiconductor device 1 is always on. Conversely, when this value exceeds 2 (oxygen deficiency, nitrogen excess), the band gap of the semiconductor becomes too large and becomes insulating, and the thin film semiconductor device 1 is always turned off. In either case, problems occur as TFT characteristics.
また、半金属元素が、少なくともシリコン（Ｓｉ）とゲルマニウム（Ｇｅ）の混合物Ｓｉ１−ｘＧｅｘ（ｘはＳｉとＧｅの混合比でｘ＝０乃至１が成り立つ）で、混合物（Ｓｉ１−ｘＧｅｘ）に対する窒素（Ｎ）の比（Ｎ数密度／Ｓｉ１−ｘＧｅｘ数密度）が１乃至２であり、半金属元素のシリコン（Ｓｉ）にゲルマニウム（Ｇｅ）を導入することによりバンドギャップを小さくすることができ、これと窒素（Ｎ）の導入によるバンドギャップ増大とを組み合わせて、自在にバンドギャップを制御でき、また電界効果移動度を増大させることができる。 Further, the metalloid element is at least a mixture Si1-xGex of silicon (Si) and germanium (Ge) (x is a mixture ratio of Si and Ge, where x = 0 to 1), and nitrogen with respect to the mixture (Si1-xGex) The ratio of (N) (N number density / Si1-xGex number density) is 1 to 2, and the band gap can be reduced by introducing germanium (Ge) into the metalloid silicon (Si), By combining this with the band gap increase by introducing nitrogen (N), the band gap can be freely controlled and the field effect mobility can be increased.
混合物（Ｓｉ１−ｘＧｅｘ）に対する窒素（Ｎ）の比（Ｎ数密度／Ｓｉ１−ｘＧｅｘ数密度）が１乃至２であることは、上記「混合の様子を表す式」から導かれる。すなわちＳｉの混合比が３ｙの時、Ｎの混合比は４ｙであるため、その比は１．３３となり１乃至２の範囲に収まる。ところが半導体形成過程ではスパッタ工程中のガス流量、密度などにより窒素の過不足が発生し、１．３３を中心としたある範囲のばらつきが起こる。多少のばらつきの範囲であれば薄膜半導体装置として動作に問題が起こらないが、この値が１未満の極端な窒素不足あるいは２以上の極端な窒素過剰の場合には半導体が形成されず、それぞれ金属、絶縁体となってしまうため相応しくない。 The fact that the ratio of nitrogen (N) to the mixture (Si1-xGex) (N number density / Si1-xGex number density) is 1 to 2 is derived from the above-described “expression representing the state of mixing”. That is, when the mixing ratio of Si is 3y, the mixing ratio of N is 4y, so that the ratio is 1.33 and falls within the range of 1 to 2. However, in the semiconductor formation process, nitrogen deficiency occurs due to gas flow rate, density, etc. during the sputtering process, resulting in a certain range of variation centered on 1.33. If it is in the range of some variation, there will be no problem in operation as a thin film semiconductor device. However, if this value is extremely short of nitrogen less than 1 or excessively more than 2 nitrogen, a semiconductor is not formed and each metal Because it becomes an insulator, it is not suitable.
半導体層７のバンドギャップは、半導体層７への窒素（Ｎ）の導入により広げることができるが、バンドギャップが、１ｅＶ乃至５ｅＶであることで、可視から近紫外領域の外光入射による特性変動を抑制することができる。 The band gap of the semiconductor layer 7 can be widened by introducing nitrogen (N) into the semiconductor layer 7. However, when the band gap is 1 eV to 5 eV, characteristic variation due to external light incidence in the visible to near-ultraviolet region. Can be suppressed.
バンドギャップが１ｅＶ以下の場合、価電子帯のキャリアが小さなエネルギーで容易に伝導帯に励起されるため、ＴＦＴのオフ電流が増加して消費電力が増し、極端な場合は常時オン状態となりスイッチングすらできなくなってしまう。この小さなエネルギー源には光のみでなく熱もなり得るため、温度に対してもＴＦＴ動作が不安定になる。一方、バンドギャップが５ｅＶ以上になると、価電子帯のキャリアが大きなエネルギーによっても伝導帯に励起されなくなるため、ＴＦＴのオン電流が減少して移動度を確保できなくなり、極端な場合は常時オフ状態となりスイッチングできなくなってしまう。このような場合は、元々特性の良い酸窒化物半導体を使うメリットがなくなる。 When the band gap is 1 eV or less, the carriers in the valence band are easily excited to the conduction band with a small energy, so that the off-current of the TFT increases and the power consumption increases. It becomes impossible. Since this small energy source can be not only light but also heat, the TFT operation becomes unstable with respect to temperature. On the other hand, when the band gap is 5 eV or more, carriers in the valence band are not excited to the conduction band even by large energy, so that the on-current of the TFT is reduced and the mobility cannot be secured. It becomes impossible to switch. In such a case, the merit of using an oxynitride semiconductor with originally good characteristics is lost.
また、半導体層７の主キャリアは、電子で、キャリア濃度は３００Ｋの熱平衡状態において１×１０Ｅ１６乃至１×１０Ｅ２１（ｍ−３）、電界効果移動度は０．１乃至５０（ｃｍ２／Ｖｓ）であり、高精細の動画まで対応できる。 The main carrier of the semiconductor layer 7 is an electron, the carrier concentration is 1 × 10E 16 to 1 × 10E 21 (m −3 ) in a thermal equilibrium state of 300 K, and the field effect mobility is 0.1 to 50 (cm 2 / Vs), and can handle high-definition movies.
電界効果移動度が０．１未満の場合、アモルファスシリコン程度以下となってしまうので、この実施の形態の酸窒化物半導体を用いる利点がなくなってしまう。また、電界効果移動度上限５０は、この実施の形態の酸窒化物半導体が最適な条件で形成された場合の性能限界に相当する。 When the field effect mobility is less than 0.1, it becomes less than or equal to amorphous silicon, so the advantage of using the oxynitride semiconductor of this embodiment is lost. The field-effect mobility upper limit 50 corresponds to a performance limit when the oxynitride semiconductor of this embodiment is formed under optimum conditions.
この実施の形態の薄膜半導体装置１は、ディスプレイを駆動する回路に用いられ、薄膜半導体装置１の半導体層７が、液晶表示装置を駆動する回路を構成し、アクティブマトリクス型液晶表示装置に対応でき、さらにアクティブマトリックス型有機ＥＬ表示装置などに対応できる。 The thin film semiconductor device 1 of this embodiment is used in a circuit for driving a display, and the semiconductor layer 7 of the thin film semiconductor device 1 constitutes a circuit for driving a liquid crystal display device, and can be applied to an active matrix liquid crystal display device. Furthermore, it can correspond to an active matrix type organic EL display device.
図２はロール状フィルム基板上に形成された薄膜半導体装置を示す図である。 FIG. 2 is a view showing a thin film semiconductor device formed on a roll film substrate.
ロール状フィルム基板Ｐ上には、所定位置にディスプレイパネルＤが複数個形成され、この実施の形態ではディスプレイパネルＤが４個ずつ所定間隔で長尺方向に沿って形成されている。このディスプレイパネルＤは、拡大して示すように、画素Ｇと、ゲート線Ｌ１と、データ線Ｌ２と、薄膜半導体装置１を有している。 A plurality of display panels D are formed at predetermined positions on the roll-shaped film substrate P. In this embodiment, four display panels D are formed at predetermined intervals along the longitudinal direction. The display panel D includes a pixel G, a gate line L1, a data line L2, and a thin film semiconductor device 1 as shown in an enlarged manner.
図１のプラスチック基板２は、少なくともロール状フィルム基板Ｐとし、ガラス基板６もフィルム基板とすることで、製造時にロール状態から送り出しロール状態に巻き取るロールツーロール法を用いて低プロセスコストを実現し、曲げ環境にも適用できるフレキシブルディスプレイを製造することができる。 The plastic substrate 2 in FIG. 1 is at least a roll-shaped film substrate P, and the glass substrate 6 is also a film substrate, so that a low process cost is realized by using a roll-to-roll method of winding from a roll state to a roll state at the time of manufacture. In addition, a flexible display that can be applied to a bending environment can be manufactured.
また、半導体層７は、アモルファスであり、粒界がないことで、特性の均一性を増加させ、かつプラスチック基板やロール状フィルム基板上に形成された場合の曲げ強度を向上させることができる。 Moreover, since the semiconductor layer 7 is amorphous and has no grain boundary, the uniformity of characteristics can be increased, and the bending strength when formed on a plastic substrate or a roll film substrate can be improved.
［薄膜半導体製造装置及び薄膜半導体製造方法］
次に、薄膜半導体製造装置及び薄膜半導体製造方法について説明する。図３は薄膜半導体製造装置の概略構成図、図４はロール状フィルム基板の平面図、図５はスパッタ装置の概略構成図である。
[Thin Film Semiconductor Manufacturing Apparatus and Thin Film Semiconductor Manufacturing Method]
Next, a thin film semiconductor manufacturing apparatus and a thin film semiconductor manufacturing method will be described. 3 is a schematic configuration diagram of a thin film semiconductor manufacturing apparatus, FIG. 4 is a plan view of a roll-shaped film substrate, and FIG. 5 is a schematic configuration diagram of a sputtering apparatus.
図３において、薄膜半導体製造装置１００は、図１の薄膜半導体装置１を製造するから薄膜半導体装置１の説明は同じ符号を付して省略する。ロール状フィルム基板Ｐは、図１のプラスチック基板２の両面にバリア層３，４が形成されている。 In FIG. 3, since the thin film semiconductor manufacturing apparatus 100 manufactures the thin film semiconductor device 1 in FIG. In the roll film substrate P, barrier layers 3 and 4 are formed on both surfaces of the plastic substrate 2 of FIG.
この薄膜半導体製造装置１００は、ロール巻機構１１０ａ，１１０ｂと、送出機構１１１と、巻取機構１１２と、位置合わせ機構１１３とを有し、ロール巻機構１１０ａからロール状フィルム基板Ｐを送出機構１１１によって送り出し、位置合わせ機構１１３によって位置決めして送り出されたロール状フィルム基板Ｐ上に薄膜半導体装置１を製造して巻取機構１１２に巻き取り、ロール巻機構１１０ｂに装着する。 The thin film semiconductor manufacturing apparatus 100 includes roll winding mechanisms 110a and 110b, a sending mechanism 111, a winding mechanism 112, and an alignment mechanism 113, and the roll-shaped film substrate P is sent from the roll winding mechanism 110a. The thin film semiconductor device 1 is manufactured on the roll-shaped film substrate P sent out by the positioning mechanism 113 and sent out by the positioning mechanism 113, wound up by the winding mechanism 112, and mounted on the roll winding mechanism 110b.
このロール状フィルム基板Ｐの送り出しは、位置合わせ機構１１３によって、図４に示すように、ロール状フィルム基板Ｐに形成された位置合わせパターンＡを検出し、送出機構１１１を制御して所定位置で停止するように位置合わせを行う。 As shown in FIG. 4, the roll-shaped film substrate P is sent out by detecting the alignment pattern A formed on the roll-shaped film substrate P and controlling the feed mechanism 111 at a predetermined position as shown in FIG. Align so that it stops.
このロール状フィルム基板Ｐが搬送される直線状の位置に沿って、シート状基板貼合装置１２０と、ゲート電極形成装置１３０と、絶縁層形成装置１４０と、半導体層形成装置１５０と、ソース・ドレイン電極形成装置１６０と、層間接縁膜形成装置１７０が順に配置されている。 Along the linear position where the roll-shaped film substrate P is conveyed, the sheet-like substrate bonding apparatus 120, the gate electrode forming apparatus 130, the insulating layer forming apparatus 140, the semiconductor layer forming apparatus 150, A drain electrode forming device 160 and a layer indirect edge film forming device 170 are arranged in this order.
シート状基板貼合装置１２０では、プラスチック基板２上に形成されたバリア層３の上面には、接着層５を介してガラス基板に代えてシート状プラスチック基板６０を貼り付ける。 In the sheet-like substrate bonding apparatus 120, a sheet-like plastic substrate 60 is attached to the upper surface of the barrier layer 3 formed on the plastic substrate 2 in place of the glass substrate via the adhesive layer 5.
ゲート電極形成装置１３０では、プラスチック基板６０の上に金属層９ｃのゲート電極をメッキやスパッタリングなどで形成し、絶縁層形成装置１４０では、絶縁層８ａを転写などで形成し、半導体層形成装置１５０では、スパッタ装置により絶縁層８ａの上に半導体層７を形成し、ソース・ドレイン電極形成装置１６０では、金属層９ａのソース電極と、金属層９ｂのドレイン電極をメッキやスパッタリングなどによって形成し、さらに層間接縁膜形成装置１７０では、層間接縁膜８ｂを転写などによって形成し、図１の薄膜半導体装置１を製造する。 In the gate electrode forming apparatus 130, the gate electrode of the metal layer 9c is formed on the plastic substrate 60 by plating or sputtering, and in the insulating layer forming apparatus 140, the insulating layer 8a is formed by transfer or the like, and the semiconductor layer forming apparatus 150 is formed. Then, the semiconductor layer 7 is formed on the insulating layer 8a by a sputtering apparatus, and the source / drain electrode forming apparatus 160 forms the source electrode of the metal layer 9a and the drain electrode of the metal layer 9b by plating or sputtering, Furthermore, in the layer indirect edge film forming apparatus 170, the layer indirect edge film 8b is formed by transfer or the like, and the thin film semiconductor device 1 in FIG. 1 is manufactured.
この薄膜半導体製造装置１００によって薄膜半導体製造方法が実施され、半導体層形成装置１５０では、スパッタ装置１５０ａが真空チャンバ１５０ａ１の内部に金属ターゲット１５０ａ２を保持し、非金属元素を含む雰囲気ガスを真空チャンバ１５０ａ１内に導入する用に構成され、金属ターゲット１５０ａ２に高電圧をかけるとその表面の原子がはじき飛ばされ、真空チャンバ１５０ａ１内に導入された非金属元素を含む雰囲気ガスと、はじき飛ばされた金属と反応させることによって、ロール状フィルム基板Ｐに半導体層７を製膜する。 A thin film semiconductor manufacturing method is implemented by the thin film semiconductor manufacturing apparatus 100. In the semiconductor layer forming apparatus 150, the sputtering apparatus 150a holds the metal target 150a2 inside the vacuum chamber 150a1, and the atmosphere gas containing a nonmetallic element is supplied to the vacuum chamber 150a1. When a high voltage is applied to the metal target 150a2, atoms on its surface are repelled, and an atmosphere gas containing a nonmetallic element introduced into the vacuum chamber 150a1 is reacted with the repelled metal. Thus, the semiconductor layer 7 is formed on the roll film substrate P.
この実施の形態のスパッタ装置は、図５に示すように構成することができ、このスパッタ装置２１は、ロール巻機構２２ａ，２２ｂと、送出機構２３と、巻取機構２４と、位置合わせ機構２５と、金属ターゲット２６ａ，２６ｂと、を有し、これらの全ての機構を内部に保持する真空チャンバ２７を備えている。この真空チャンバ２７は、ロール巻機構２２ａ，２２ｂ側に開閉扉２７ａ，２７ｂを有し、開閉扉２７ａを開閉してロール状フィルム基板Ｐをセットし、開閉扉２７ｂを開閉して半導体層７が設けられたロール状フィルム基板Ｐを取り出す。 The sputtering apparatus of this embodiment can be configured as shown in FIG. 5, and this sputtering apparatus 21 includes roll winding mechanisms 22 a and 22 b, a feeding mechanism 23, a winding mechanism 24, and an alignment mechanism 25. And a metal target 26a, 26b, and a vacuum chamber 27 that holds all these mechanisms inside. This vacuum chamber 27 has opening / closing doors 27a, 27b on the roll winding mechanisms 22a, 22b side, opens / closes the opening / closing door 27a, sets the roll-shaped film substrate P, opens / closes the opening / closing door 27b, and the semiconductor layer 7 is opened. The provided roll-shaped film substrate P is taken out.
ロール状フィルム基板Ｐは、図１のプラスチック基板２の両面にバリア層３，４が形成され、プラスチック基板２上に形成されたバリア層３の上面には、接着層５を介してガラス基板に代えてシート状プラスチック基板６０を設けてロール状にした構成であり、図４に示すように、位置合わせパターンＡを有する。 The roll-shaped film substrate P has barrier layers 3 and 4 formed on both surfaces of the plastic substrate 2 in FIG. 1, and the upper surface of the barrier layer 3 formed on the plastic substrate 2 is attached to the glass substrate via the adhesive layer 5. Instead, a sheet-like plastic substrate 60 is provided to form a roll, and has an alignment pattern A as shown in FIG.
ロール巻機構２２ａは、回転軸２２ａ１にロール状フィルム基板Ｐを装着し、回転軸２２ａ１はロール状フィルム基板Ｐの送り出しによって回転し、ロール巻機構２２ｂは、回転軸２２ｂ１にロール状フィルム基板Ｐを装着し、回転軸２２ｂ１はロール状フィルム基板Ｐの巻き取りによって回転する。 The roll winding mechanism 22a mounts the roll-shaped film substrate P on the rotation shaft 22a1, the rotation shaft 22a1 rotates by feeding the roll-shaped film substrate P, and the roll winding mechanism 22b causes the roll-shaped film substrate P to rotate on the rotation shaft 22b1. The rotating shaft 22b1 is rotated by winding the roll-shaped film substrate P.
送出機構２３は、一対の送出ローラ２３ａを有し、この一対の送出ローラ２３ａの回転によってロール状フィルム基板Ｐを長尺方向に沿って一方の端部から送り出す。 The delivery mechanism 23 has a pair of delivery rollers 23a, and feeds the roll-shaped film substrate P from one end along the longitudinal direction by the rotation of the pair of delivery rollers 23a.
巻取機構２４は、一対の巻取ローラ２４ｂを有し、この一対の巻取ローラ２４ｂの回転によってロール状フィルム基板Ｐを長尺方向に沿って一方の端部から巻き取る。 The winding mechanism 24 has a pair of winding rollers 24b, and winds the roll-shaped film substrate P from one end along the longitudinal direction by the rotation of the pair of winding rollers 24b.
位置合わせ機構２５は、検出センサ２５ａ、制御装置２５ｂ、ローラ駆動装置２５ｃを有し、検出センサ２５ａによってロール状フィルム基板Ｐの位置合わせパターンＡを検出し、この検出情報を制御装置２５ｂに送り、制御装置２５ｂはローラ駆動装置２５ｃを介して送出機構２３及び巻取機構２４を制御し、ロール状フィルム基板Ｐの平面位置合わせを行う。 The alignment mechanism 25 includes a detection sensor 25a, a control device 25b, and a roller drive device 25c. The detection sensor 25a detects the alignment pattern A of the roll film substrate P, and sends this detection information to the control device 25b. The control device 25b controls the feeding mechanism 23 and the winding mechanism 24 through the roller driving device 25c, and performs planar alignment of the roll-shaped film substrate P.
真空チャンバ２７内は、真空ポンプ２８に駆動によって真空状態であり、この真空チャンバ２７には、ガス導入機構２９が設けられ、このガス導入機構２９は非金属元素を含む雰囲気ガスを真空チャンバ２７内に導入する。 The inside of the vacuum chamber 27 is in a vacuum state by being driven by a vacuum pump 28, and a gas introduction mechanism 29 is provided in the vacuum chamber 27, and the gas introduction mechanism 29 supplies an atmospheric gas containing a non-metallic element in the vacuum chamber 27. To introduce.
金属ターゲット２６ａ，２６ｂは、ロール状フィルム基板Ｐの半導体形成面に対面し、ロール状フィルム基板Ｐの長尺に沿った直線状の位置に配列されている。 The metal targets 26 a and 26 b face the semiconductor formation surface of the roll film substrate P and are arranged at linear positions along the length of the roll film substrate P.
金属ターゲット２６ａは、金属元素のターゲットであり、金属ターゲット２６ｂａは、半金属元素のターゲットである。 The metal target 26a is a metal element target, and the metal target 26ba is a metalloid element target.
スパッタ装置２１は、金属ターゲット２６ａ，２６ｂとし、非金属元素、金属元素、半金属元素それぞれ少なくともひとつを含む複数の元素を混ぜ合わせた混合物を、単一のターゲットとして用いているが、金属ターゲット２６ａ，２６ｂを一体のターゲットとてもよい。 The sputtering apparatus 21 uses metal mixtures 26a and 26b as a single target, which is a mixture of a plurality of elements including at least one of a nonmetallic element, a metallic element, and a semimetallic element, but the metallic target 26a. , 26b is a very good target.
このように、スパッタ装置２１は、ガス導入機構２９により、真空チャンバ２７内に非金属元素を含む雰囲気ガスを導入し、真空チャンバ２７内に金属ターゲット２６ａ，２６ｂの金属元素または半金属元素またはこれらの混合物を含む金属ターゲットを複数配置し、電極を介して金属ターゲット２６ａ，２６ｂに高電圧をかけると金属ターゲット表面の原子がはじき飛ばされ、真空チャンバ２７内に導入された非金属元素を含む雰囲気ガスと、はじき飛ばされた金属と反応させることによって、ロール状フィルム基板Ｐに半導体層７を製膜することができる。 As described above, the sputtering apparatus 21 introduces the atmospheric gas containing the nonmetallic element into the vacuum chamber 27 by the gas introduction mechanism 29, and the metal element or metalloid element of the metal targets 26 a and 26 b or these elements into the vacuum chamber 27. When a high voltage is applied to the metal targets 26 a and 26 b through the electrodes by arranging a plurality of metal targets containing a mixture of the above, atoms on the surface of the metal target are repelled and an atmospheric gas containing a nonmetallic element introduced into the vacuum chamber 27 Then, the semiconductor layer 7 can be formed on the roll-shaped film substrate P by reacting with the repelled metal.
半導体層７を成膜する場合、ロール状フィルム基板Ｐは特に加熱や冷却されることはなく室温に置かれる（ただし、金属ターゲット２６ａ、２６ｂへの高電圧印加やはじき飛んでくる原子との反応により、数十℃程度の自然昇温はあると考えられる）。また、成膜時の真空チャンバ２７内の圧力は約０．５Ｐａ、ガス導入機構２９から供給される雰囲気ガスの分圧は約０．００５Ｐａである。金属ターゲットへの高電圧印加の成膜パワーは約２Ｗ／ｃｍ２である。 When the semiconductor layer 7 is formed, the roll-shaped film substrate P is not heated or cooled, and is placed at room temperature (however, a high voltage is applied to the metal targets 26a and 26b and reaction with flying atoms is performed. Therefore, it is considered that there is a natural temperature rise of several tens of degrees Celsius). The pressure in the vacuum chamber 27 during film formation is about 0.5 Pa, and the partial pressure of the atmospheric gas supplied from the gas introduction mechanism 29 is about 0.005 Pa. The film forming power when a high voltage is applied to the metal target is about 2 W / cm 2 .
この薄膜半導体製造装置１００では、スパッタ装置１５０ａまたは図５のスパッタ装置２１を用い、低温プロセスで半導体層７を形成可能であり、低プロセスコストを実現することができる。また、半導体層７は、比較的高い電界効果移動度を実現でき、かつ光、熱に対して安定な特性を有する薄膜半導体装置１を製造することができる。 In this thin film semiconductor manufacturing apparatus 100, the semiconductor layer 7 can be formed by a low temperature process using the sputtering apparatus 150a or the sputtering apparatus 21 of FIG. 5, and a low process cost can be realized. Moreover, the semiconductor layer 7 can manufacture the thin film semiconductor device 1 that can realize a relatively high field effect mobility and has stable characteristics with respect to light and heat.
また、半導体層７は自在にバンドギャップを制御でき、また電界効果移動度を増大させることができる薄膜半導体製造装置１を製造することができる。 Moreover, the semiconductor layer 7 can manufacture the thin film semiconductor manufacturing apparatus 1 which can control a band gap freely and can increase a field effect mobility.
また、図５のスパッタ装置２１は、全ての機構を内部に保持する真空チャンバ２７を備え、製造時にロール状態から送り出しロール状態に巻き取り、低プロセスコストを実現することができる。 Further, the sputtering apparatus 21 of FIG. 5 includes a vacuum chamber 27 that holds all the mechanisms therein, and can be wound from a roll state to a feed roll state at the time of manufacturing, thereby realizing a low process cost.
また、スパッタ装置２１は、非金属元素を含む雰囲気ガスを真空チャンバ２７内に導入し、金属元素または半金属元素またはこれらの混合物を含む金属ターゲット２６ａ，２６ｂを複数有し、金属ターゲット２６ａ，２６ｂが、ロール状フィルム基板Ｐの長尺に沿った直線状の位置に配列され、ロール状フィルム基板Ｐ内に均一な性質の半導体層７を形成できる。 Further, the sputtering apparatus 21 introduces an atmospheric gas containing a non-metallic element into the vacuum chamber 27, has a plurality of metal targets 26a and 26b containing a metal element, a semi-metal element, or a mixture thereof, and the metal targets 26a and 26b. However, the semiconductor layer 7 having a uniform property can be formed in the roll-shaped film substrate P by being arranged at linear positions along the length of the roll-shaped film substrate P.
また、スパッタ装置２１は、非金属元素、金属元素、半金属元素それぞれ少なくともひとつを含む複数の元素を混ぜ合わせた混合物を、単一のターゲットとして用い、半導体層７の性質をさらに均一にするとともにスパッタプロセスコストを低減できる。 Further, the sputtering apparatus 21 uses a mixture obtained by mixing a plurality of elements including at least one of a non-metallic element, a metallic element, and a semi-metallic element as a single target, and makes the properties of the semiconductor layer 7 more uniform. Sputtering process costs can be reduced.
この発明は、特にプラスチック基板を用いたフレキシブルディスプレイである薄膜半導体装置、薄膜半導体製造装置及び薄膜半導体製造方法に適用可能で、低温プロセスで形成可能であり、低プロセスコストを実現し、また比較的高い電界効果移動度を実現でき、かつ光、熱に対して安定な特性を有し、曲げ環境にも適用できる。 The present invention is particularly applicable to a thin film semiconductor device, a thin film semiconductor manufacturing apparatus and a thin film semiconductor manufacturing method, which are flexible displays using a plastic substrate, can be formed by a low temperature process, realizes a low process cost, and is relatively High field effect mobility can be realized, and it has stable characteristics against light and heat, and can be applied to a bending environment.
１ 薄膜半導体装置
２ プラスチック基板
３，４ バリア層
５ 接着層
６ ガラス基板
７ 半導体層
８ａ 絶縁層
９ａ，９ｂ，９ｃ 金属層
２１，１５０ａ スパッタ装置
２２ａ，２２ｂ ロール巻機構
２３ 送出機構
２４ 巻取機構
２５ 位置合わせ機構
２６ａ，２６ｂ 金属ターゲット
２７ 真空チャンバ
２９ ガス導入機構
Ｐ ロール状フィルム基板
DESCRIPTION OF SYMBOLS 1 Thin film semiconductor device 2 Plastic substrate 3, 4 Barrier layer 5 Adhesion layer 6 Glass substrate 7 Semiconductor layer 8a Insulating layers 9a, 9b, 9c Metal layers 21, 150a Sputtering devices 22a, 22b Roll winding mechanism 23 Sending mechanism 24 Winding mechanism 25 Positioning mechanism 26a, 26b Metal target 27 Vacuum chamber 29 Gas introduction mechanism P Rolled film substrate
Claims (13)
前記プラスチック基板上に形成されたバリア層と、
前記バリア層上に形成された半導体層と、
前記半導体層の上下いずれかの面に接して形成された絶縁層と、
前記絶縁層に接して形成された金属層と、
を有し、
前記半導体層をチャネル、前記金属層をソース電極、ドレイン電極、およびゲート電極、前記絶縁層をゲート絶縁膜として用い、
前記半導体層は、非金属元素の窒素（Ｎ）、酸素（Ｏ）のうち少なくともひとつ、半金属元素のホウ素（Ｂ）、シリコン（Ｓｉ）、ゲルマニウム（Ｇｅ）、ヒ素（Ａｓ）、アンチモン（Ｓｂ）、テルル（Ｔｅ）、ポロニウム（Ｐｏ）のうち少なくともひとつ、および金属元素のアルミニウム（Ａｌ）、亜鉛（Ｚｎ）、ガリウム（Ｇａ）、カドニウム（Ｃｄ）、インジウム（Ｉｎ）、錫（Ｓｎ）、水銀（Ｈｇ）、タリウム（Ｔｌ）、テルビウム（Ｐｂ）、ビスマス（Ｂｉ）のうち少なくともひとつを含み、
前記非金属元素が、少なくとも酸素（Ｏ）と窒素（Ｎ）の混合物で、酸素（Ｏ）に対する窒素（Ｎ）の比（Ｎ数密度／Ｏ数密度）が０乃至２であることを特徴とする薄膜半導体装置。 A plastic substrate,
A barrier layer formed on the plastic substrate;
A semiconductor layer formed on the barrier layer;
An insulating layer formed in contact with either upper or lower surface of the semiconductor layer;
A metal layer formed in contact with the insulating layer;
Have
Using the semiconductor layer as a channel, the metal layer as a source electrode, a drain electrode, and a gate electrode, and the insulating layer as a gate insulating film,
The semiconductor layer includes at least one of nonmetallic elements nitrogen (N) and oxygen (O), semimetallic elements boron (B), silicon (Si), germanium (Ge), arsenic (As), and antimony (Sb). ), Tellurium (Te), at least one of polonium (Po), and the metal elements aluminum (Al), zinc (Zn), gallium (Ga), cadmium (Cd), indium (In), tin (Sn), Including at least one of mercury (Hg), thallium (Tl), terbium (Pb), bismuth (Bi),
The nonmetallic element is at least a mixture of oxygen (O) and nitrogen (N), and the ratio of nitrogen (N) to oxygen (O) (N number density / O number density) is 0 to 2. Thin film semiconductor device.
前記ロール状フィルム基板上に形成されたバリア層と、
前記バリア層上に形成された半導体層と、
前記半導体層の上下いずれかの面に接して形成された絶縁層と、
前記絶縁層に接して形成された金属層と、
を有し、
前記半導体層をチャネル、前記金属層をソース電極、ドレイン電極、およびゲート電極、前記絶縁層をゲート絶縁膜として用い、前記半導体層は、非金属元素の窒素（Ｎ）、酸素（Ｏ）のうち少なくともひとつ、半金属元素のホウ素（Ｂ）、シリコン（Ｓｉ）、ゲルマニウム（Ｇｅ）、ヒ素（Ａｓ）、アンチモン（Ｓｂ）、テルル（Ｔｅ）、ポロニウム（Ｐｏ）のうち少なくともひとつ、および金属元素のアルミニウム（Ａｌ）、亜鉛（Ｚｎ）、ガリウム（Ｇａ）、カドニウム（Ｃｄ）、インジウム（Ｉｎ）、錫（Ｓｎ）、水銀（Ｈｇ）、タリウム（Ｔｌ）、テルビウム（Ｐｂ）、ビスマス（Ｂｉ）のうち少なくともひとつを含み、
前記非金属元素が、少なくとも酸素（Ｏ）と窒素（Ｎ）の混合物で酸素（Ｏ）に対する窒素（Ｎ）の比（Ｎ数密度／Ｏ数密度）が０乃至２である前記半導体層をスパッタ装置により形成する薄膜半導体製造装置。 The roll film substrate;
A barrier layer formed on the roll film substrate;
A semiconductor layer formed on the barrier layer;
An insulating layer formed in contact with either upper or lower surface of the semiconductor layer;
A metal layer formed in contact with the insulating layer;
Have
The semiconductor layer is used as a channel, the metal layer is used as a source electrode, a drain electrode, and a gate electrode, the insulating layer is used as a gate insulating film, and the semiconductor layer is made of nitrogen (N) or oxygen (O) of a nonmetallic element At least one of the metalloid elements boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te), polonium (Po), and metal elements Aluminum (Al), zinc (Zn), gallium (Ga), cadmium (Cd), indium (In), tin (Sn), mercury (Hg), thallium (Tl), terbium (Pb), bismuth (Bi) Including at least one of them,
The non-metallic element is a mixture of at least oxygen (O) and nitrogen (N), and the ratio of nitrogen (N) to oxygen (O) (N number density / O number density) is 0 to 2 is sputtered. Thin film semiconductor manufacturing equipment formed by equipment.
前記ロール状フィルム基板を装着するロール巻機構と、
前記ロール状フィルム基板を長尺方向に沿って一方の端部から送り出す送出機構と、
送り出された前記ロール状フィルム基板を巻き取る巻取機構と、
位置合わせパターンを有する前記ロール状フィルム基板に対し、前記ロール状フィルム基板の平面位置合わせを行う位置合わせ機構と、
前記ロール状フィルム基板の半導体形成面に対面する金属ターゲットと、
を有し、
前記全ての機構を内部に保持する真空チャンバを備えたことを特徴とする請求項８また請求項９に記載の薄膜半導体製造装置。 The sputtering apparatus is
A roll winding mechanism for mounting the roll film substrate;
A delivery mechanism for delivering the roll-shaped film substrate from one end along the longitudinal direction;
A winding mechanism for winding up the rolled film substrate that has been sent out;
An alignment mechanism that performs planar alignment of the roll-shaped film substrate with respect to the roll-shaped film substrate having the alignment pattern,
A metal target facing the semiconductor forming surface of the roll film substrate;
Have
10. The thin film semiconductor manufacturing apparatus according to claim 8, further comprising a vacuum chamber for holding all the mechanisms therein.
前記非金属元素を含む雰囲気ガスを真空チャンバ内に導入するガス導入機構と、
前記金属元素または前記半金属元素またはこれらの混合物を含む金属ターゲットと、を複数有し、
前記金属ターゲットが、前記ロール状フィルム基板の長尺に沿った直線状の位置に配列されていることを特徴とする請求項８または請求項９に記載の薄膜半導体製造装置。 The sputtering apparatus is
A gas introduction mechanism for introducing an atmospheric gas containing the nonmetallic element into a vacuum chamber;
A plurality of metal targets including the metal element or the metalloid element or a mixture thereof,
The thin film semiconductor manufacturing apparatus according to claim 8, wherein the metal target is arranged at a linear position along the length of the roll-shaped film substrate.
前記非金属元素、前記金属元素、前記半金属元素それぞれ少なくともひとつを含む複数の元素を混ぜ合わせた混合物を、単一のターゲットとして用いたことを特徴とする請求項８乃至請求項１１のいずれか１項に記載の薄膜半導体製造装置。 The sputtering apparatus is
The mixture of a plurality of elements each including at least one of the non-metallic element, the metallic element, and the metalloid element is used as a single target. 2. The thin film semiconductor manufacturing apparatus according to item 1.
薄膜半導体装置を製造することを特徴とする薄膜半導体製造方法。 A thin film semiconductor manufacturing apparatus according to any one of claims 8 to 12,
A method of manufacturing a thin film semiconductor device, comprising manufacturing a thin film semiconductor device.
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| WO2011104894A1 (en) | 2011-09-01 |
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