JP5039698B2 - 複製されたロジックを使用するデバッグ及びテスト方法並びにシステム - Google Patents

複製されたロジックを使用するデバッグ及びテスト方法並びにシステム Download PDF

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Publication number
JP5039698B2
JP5039698B2 JP2008525222A JP2008525222A JP5039698B2 JP 5039698 B2 JP5039698 B2 JP 5039698B2 JP 2008525222 A JP2008525222 A JP 2008525222A JP 2008525222 A JP2008525222 A JP 2008525222A JP 5039698 B2 JP5039698 B2 JP 5039698B2
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Prior art keywords
circuit
logic
trigger condition
recorded data
replicated
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Japanese (ja)
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JP2009503749A (ja
JP2009503749A5 (https=
Inventor
チュン キット ング
マリオ ラルーシュ
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Synopsys Inc
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Synopsys Inc
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30—Marginal testing, e.g. by varying supply voltage
    • G01R31/3016—Delay or race condition test, e.g. race hazard test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31705—Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequences by preliminary fault modelling, e.g. analysis, simulation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318364—Generation of test inputs, e.g. test vectors, patterns or sequences as a result of hardware simulation, e.g. in an HDL environment
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Hardware Redundancy (AREA)
JP2008525222A 2005-08-02 2006-08-02 複製されたロジックを使用するデバッグ及びテスト方法並びにシステム Active JP5039698B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/195,180 2005-08-02
US11/195,180 US7398445B2 (en) 2002-08-09 2005-08-02 Method and system for debug and test using replicated logic
PCT/US2006/030417 WO2007016699A2 (en) 2005-08-02 2006-08-02 Method and system for debug and test using replicated logic

Publications (3)

Publication Number Publication Date
JP2009503749A JP2009503749A (ja) 2009-01-29
JP2009503749A5 JP2009503749A5 (https=) 2009-08-27
JP5039698B2 true JP5039698B2 (ja) 2012-10-03

Family

ID=37488031

Family Applications (1)

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JP2008525222A Active JP5039698B2 (ja) 2005-08-02 2006-08-02 複製されたロジックを使用するデバッグ及びテスト方法並びにシステム

Country Status (6)

Country Link
US (1) US7398445B2 (https=)
EP (1) EP1913410B1 (https=)
JP (1) JP5039698B2 (https=)
AT (1) ATE469359T1 (https=)
DE (1) DE602006014549D1 (https=)
WO (1) WO2007016699A2 (https=)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7222315B2 (en) * 2000-11-28 2007-05-22 Synplicity, Inc. Hardware-based HDL code coverage and design analysis
US7213216B2 (en) * 2002-08-09 2007-05-01 Synplicity, Inc. Method and system for debugging using replicated logic and trigger logic
US6904576B2 (en) * 2002-08-09 2005-06-07 Synplicity, Inc. Method and system for debugging using replicated logic
US8756557B2 (en) * 2007-05-09 2014-06-17 Synopsys, Inc. Techniques for use with automated circuit design and simulations
US7904859B2 (en) * 2007-05-09 2011-03-08 Synopsys, Inc. Method and apparatus for determining a phase relationship between asynchronous clock signals
US7984400B2 (en) * 2007-05-09 2011-07-19 Synopsys, Inc. Techniques for use with automated circuit design and simulations
US7908574B2 (en) * 2007-05-09 2011-03-15 Synopsys, Inc. Techniques for use with automated circuit design and simulations
US8397195B2 (en) * 2010-01-22 2013-03-12 Synopsys, Inc. Method and system for packet switch based logic replication
US8638792B2 (en) * 2010-01-22 2014-01-28 Synopsys, Inc. Packet switch based logic replication
EP2586128B1 (en) * 2010-06-23 2019-03-06 Altera Corporation Rescaling
US9495492B1 (en) * 2015-01-05 2016-11-15 Cadence Design Systems, Inc. Implementing synchronous triggers for waveform capture in an FPGA prototyping system

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DE68928837T2 (de) * 1988-09-07 1999-05-12 Texas Instruments Inc., Dallas, Tex. Prüf-Puffer/Register
US5056094A (en) * 1989-06-09 1991-10-08 Texas Instruments Incorporated Delay fault testing method and apparatus
US5272390A (en) * 1991-09-23 1993-12-21 Digital Equipment Corporation Method and apparatus for clock skew reduction through absolute delay regulation
US5452239A (en) * 1993-01-29 1995-09-19 Quickturn Design Systems, Inc. Method of removing gated clocks from the clock nets of a netlist for timing sensitive implementation of the netlist in a hardware emulation system
US5706473A (en) * 1995-03-31 1998-01-06 Synopsys, Inc. Computer model of a finite state machine having inputs, outputs, delayed inputs and delayed outputs
US5761488A (en) * 1996-06-13 1998-06-02 International Business Machines Corporation Logic translation method for increasing simulation emulation efficiency
JPH10177590A (ja) * 1996-12-18 1998-06-30 Toshiba Corp 論理回路モデルのデバッグ装置およびデバッグ方法
US5923676A (en) * 1996-12-20 1999-07-13 Logic Vision, Inc. Bist architecture for measurement of integrated circuit delays
US6286114B1 (en) * 1997-10-27 2001-09-04 Altera Corporation Enhanced embedded logic analyzer
US6286128B1 (en) * 1998-02-11 2001-09-04 Monterey Design Systems, Inc. Method for design optimization using logical and physical information
KR100846089B1 (ko) * 1998-09-30 2008-07-14 카덴스 디자인 시스템즈 인크 설계 블록들 사이에 다수의 글루 로직 엘리먼트들을 분배하는 방법 및 글루 로직 분배 효율을 증가시키는 방법
US6438735B1 (en) * 1999-05-17 2002-08-20 Synplicity, Inc. Methods and apparatuses for designing integrated circuits
US6519754B1 (en) * 1999-05-17 2003-02-11 Synplicity, Inc. Methods and apparatuses for designing integrated circuits
US7065481B2 (en) * 1999-11-30 2006-06-20 Synplicity, Inc. Method and system for debugging an electronic system using instrumentation circuitry and a logic analyzer
US6551227B1 (en) * 1999-12-08 2003-04-22 Heidelberger Druckmaschinen Ag Device for seizing of flat material on a transporting surface
DE10030349A1 (de) 2000-06-20 2002-01-10 Kuratorium Offis E V Verfahren zum Analysieren der Verlustleistung bzw. der Energieaufnahme einer elektrischen Schaltung bzw. eines elektrischen Bauelementes
US6516449B2 (en) * 2001-04-02 2003-02-04 Sun Microsystems, Inc. Methodology to create integrated circuit designs by replication maintaining isomorphic input output and fault behavior
US6580299B2 (en) * 2001-04-05 2003-06-17 Parthus Ireland Limited Digital circuit for, and a method of, synthesizing an input signal
JP2003099495A (ja) * 2001-09-25 2003-04-04 Fujitsu Ltd 集積回路の設計システム、集積回路の設計方法およびプログラム
US6687882B1 (en) * 2002-01-31 2004-02-03 Synplicity, Inc. Methods and apparatuses for non-equivalence checking of circuits with subspace
US6904576B2 (en) * 2002-08-09 2005-06-07 Synplicity, Inc. Method and system for debugging using replicated logic
US7266489B2 (en) * 2003-04-28 2007-09-04 International Business Machines Corporation Method, system and program product for determining a configuration of a digital design by reference to an invertible configuration database
US7055117B2 (en) * 2003-12-29 2006-05-30 Agere Systems, Inc. System and method for debugging system-on-chips using single or n-cycle stepping

Also Published As

Publication number Publication date
US7398445B2 (en) 2008-07-08
EP1913410B1 (en) 2010-05-26
US20060259834A1 (en) 2006-11-16
JP2009503749A (ja) 2009-01-29
EP1913410A2 (en) 2008-04-23
WO2007016699A2 (en) 2007-02-08
WO2007016699A3 (en) 2007-03-29
ATE469359T1 (de) 2010-06-15
DE602006014549D1 (de) 2010-07-08

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