JP5034372B2 - Level shift circuit, driving device, imaging device - Google Patents

Description

  The present invention relates to a level shift circuit, and a driving apparatus and an imaging apparatus that drive an element having an impedance component (particularly capacitive) using a system circuit including the level shift circuit.

  Level shift circuits are used in various electronic devices for signal level conversion. The level shift circuit includes a step-up type and a step-down type. In a general step-up type level shift circuit, in a semiconductor device using two types of voltage sources, a low voltage source and a high voltage source, a circuit on the low voltage source side is provided. Is converted to the logic level of the circuit on the high voltage source side.

  Here, there are various configurations of the step-up type level shift circuit. For example, a configuration using a so-called positive feedback type circuit configuration in which positive feedback is performed by differential input is known. For example, FIG. 10 of Patent Document 1 and FIG. 14 of Patent Document 2 show the basic circuit as a conventional technique, and these documents also propose a further improved circuit configuration.

JP 2003-309463 A JP 2004-153524 A

  Here, the improved circuits described in Patent Documents 1 and 2 are exclusively focused on prevention of through current, high speed drive, and low power consumption.

  On the other hand, with respect to a semiconductor integrated circuit (IC), it is necessary to consider hot carrier resistance, and this also applies to a level shift circuit.

  Here, during low-speed driving (for example, 10 MHz or less), the period during which hot carrier resistance becomes a problem is relatively narrow, and the problem of hot carrier resistance is small compared to the problems of through current and power consumption. It can be considered that the carrier tolerance problem has been virtually ignored. This is because, for example, at the time of low-speed driving, the lifetime (reliability guarantee period) from the viewpoint of hot carrier resistance is about 100 years or more. This lifetime is obtained by estimating from the substrate current Isub by simulation.

  However, during high-speed driving (for example, 100 MHz or more), the period in which hot carrier resistance is a problem cannot be relatively ignored. For example, the lifetime from the viewpoint of hot carrier resistance is about 10 years. That is, the problem of hot carrier resistance becomes apparent during high-speed driving.

For example, when the level shift circuit is applied to a drive circuit (a so-called horizontal driver) for driving a horizontal transfer electrode for a horizontal CCD of a CCD solid-state imaging device , high-speed driving is required as the pixel density increases. In addition to preventing through current and reducing power consumption, it has become necessary to study a circuit that takes into consideration hot carrier resistance, which has not been considered in the past.

  Actual damage at the circuit system level due to deterioration of hot carrier tolerance appears in circuit characteristics that are easily affected by fluctuations in mutual conductance gm, such as slew rate, delay characteristics, and drive capability. If the state of power drop or slow response due to aging due to the use of the actual product is observed, the driving force due to the deterioration of hot carrier tolerance at the interface of the semiconductor integrated circuit (IC) This is thought to be partly due to the fall.

  The detailed mechanism of the hot carrier resistance deterioration phenomenon is described in Non-Patent Document 1, for example. This Non-Patent Document 1 details the mechanism and confirmation method of hot carrier resistance deterioration.

Shin-ichi Takagi and Akira Toriumi, “New Experimental Findings on Hot Carrier Transport under Velocity Saturation Regime in Si MOSFETs”, IEDM92 paper, IEEE1992, P28.6.1 to P28.6.4.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a level shift circuit capable of improving hot carrier resistance, a driving device (driving circuit) and an imaging device using the level shift circuit. And

  In the present invention, as a result of the search for the cause of deterioration of hot carrier resistance in the level shift circuit, in order to prevent the deterioration of hot carrier resistance and improve the hot carrier resistance, 1) the drain of the MOS transistor when passing through the pinch-off region It has been found that reducing the source-to-source voltage or 2) operating in such a way as to quickly pass through the pinch-off region is effective in enhancing hot carrier resistance and extending the circuit life.

  For example, the first mechanism according to the present invention realizes 1). First, the level shift circuit is configured as follows. That is, a pair of differential transistors based on a pulse signal output from a signal generation circuit using a first voltage source as a power supply is supplied to each control signal input terminal, and one input Located on the inverting output terminal side of the stage transistor, located on the inverting output terminal side of one output stage transistor arranged on the second voltage source side and the other input stage transistor, on the second voltage source side And the other output stage transistor. Then, a pair of output signals corresponding to the pair of differential signals is acquired based on the signals obtained at the inverting output terminals of the input stage transistors.

  Further, in order to form a positive feedback circuit to the output stage transistor, a feedback signal based on the output pulse signal obtained at the inverting output terminal of one input stage transistor is supplied to the control signal input terminal of the other output stage transistor, A reverse connection is provided for supplying a feedback signal based on the output pulse signal obtained at the inverting output terminal of the input stage transistor to the control signal input terminal of one of the output stage transistors.

  Here, each transistor pair on the input stage side and the output stage side is the same as that provided in the conventional level shift circuit. In the present application, however, the inverting output terminal of one of the input stage transistors An impedance element is provided between the inverted output terminal of the other output stage transistor and an impedance element provided between the inverted output terminal of the other output stage transistor and the inverted output terminal of the other output stage transistor. Is provided.

  In the first mechanism, the potential difference generated at both ends of the impedance element is caused by the operating current flowing when the input stage transistor is turned on to the impedance element interposed between the inverting output terminals of the transistors of the input stage and the output stage. Utilizing this, the potential difference between the inverting output terminal (typically the drain) and the reference side terminal (typically the source) of the input stage transistor when passing through the pinch-off region is reduced.

  In the second mechanism according to the present invention, first, the level shift circuit is configured as follows. That is, a pair of first conductivity type input stage transistors in which a pair of differential signals based on a pulse signal output from a signal generation circuit using a first voltage source as a power supply is supplied to each control signal input terminal Located on the inverting output terminal side of one input stage transistor, positioned on the inverting output terminal side of one output stage transistor disposed on the second voltage source side, and on the inverting output terminal side of the other input stage transistor, 2 and the other output stage transistor arranged on the voltage source side.

  The output pulse signal obtained at the inverting output terminal of one input stage transistor is used as a feedback signal supplied to the control signal input terminal of the other output stage transistor, and the output pulse signal obtained at the inverting output terminal of the other input stage transistor. Are connected as a feedback signal to be supplied to the control signal input terminal of one of the output stage transistors.

Here, the transistor pairs on the input stage side and the output stage side, and the connection between the transistors are the same as those provided in the conventional level shift circuit . In accordance with the degree, the mutual conductance of the one and the other input stage transistors is made larger than the mutual conductance of the one and the other output stage transistors .

  The inventions described in the dependent claims define further advantageous specific examples of the mechanism according to the present invention.

For example, in the first mechanism, an inductive element is provided between the inverting output terminal of each input stage transistor and each signal output terminal for outputting an output signal corresponding to a pair of differential signals. be able to.

  In the first mechanism, the impedance element interposed between the inverting output terminals of the input stage transistor and the output stage transistor is also used for obtaining a feedback signal to the other output stage transistor. 2) should also be realized.

  That is, a signal based on the operating current flowing in the impedance element interposed between the inverting output terminal of one input stage transistor and the inverting output terminal of the other output stage transistor is supplied to the control signal input terminal of the other output stage transistor. One feedback signal acquisition unit to acquire as a feedback signal, and a signal based on an operating current flowing in an impedance element interposed between the inverting output terminal of the other input stage transistor and the inverting output terminal of the other output stage transistor The other feedback signal acquisition unit that acquires the feedback signal supplied to the control signal input terminal of the output stage transistor is provided.

  In other words, when acquiring a feedback signal for positive feedback operation of the transistor pair on the output stage side, an impedance element provided between the inverting output terminals of each transistor in the input stage and the output stage is used. A signal based on a potential difference generated at both ends of the impedance element by the flowing operating current is used as a feedback signal to the other (the other party).

  If such a configuration is adopted, the potential difference generated at both ends of the impedance element when the operating current flows when the input stage transistor is turned on to the impedance element interposed between the inverting output terminals of the transistors of the input stage and the output stage. Can be used to obtain a feedback signal that keeps the ON state of the counterpart output stage transistor in a shallow state.

  Further, for example, in the first mechanism, the feedback signal acquisition unit uses a signal obtained at a terminal opposite to the inverting output terminal of the input stage transistor among the terminals on both sides of the impedance element as a feedback signal. It can be. This configuration is particularly effective when the feedback signal acquisition unit is configured by one impedance element, and a signal obtained at the inverting output terminal of the output stage transistor is actually used as the feedback signal.

  Alternatively, the feedback signal acquisition unit may be configured by a series circuit of a plurality of impedance elements, and a signal appearing at a connection point of the plurality of impedance elements may be used as a feedback signal. Even in this case, the signal obtained at the terminal opposite to the inverted output terminal of the input stage transistor among the terminals on both sides of the impedance element connected to the input stage transistor side is used as a feedback signal. Absent. By using the potential at the connection point as a feedback signal, the ON state of the counterpart output stage transistor can be more reliably brought into a shallow state.

  Further, it is easy to use a resistance element as the impedance element.

  In addition, the level shift circuit of the first and second mechanisms as described above includes, for example, a driving device for driving various electronic loads, and a charge transfer path (charge transfer element) having a capacitive impedance. The present invention can also be applied to an imaging apparatus including an imaging unit provided as a load.

  According to the first mechanism of the present invention, the operating current when the input stage transistor is on flows through the impedance element interposed between the inverting output terminals of the transistors of the input stage and the output stage, so that both ends of the impedance element Can be used to reduce the potential difference between the inverting output terminal (drain) of the input stage transistor and the reference terminal (source) when passing through the pinch-off region during the switching operation. Carrier tolerance can be improved.

  In addition, the impedance element interposed between the inverting output terminals of each transistor in the input stage and the output stage uses the potential difference generated at both ends of the impedance element when the operating current flows when the input stage transistor is on. By acquiring a feedback signal that keeps the ON state of the output stage transistor shallow, positive feedback when the logic level of the output signal is about to transition during the transition of the logic level of the input differential signal In operation, the output stage transistor shifts from a shallow on-state to an off-state, so that its response becomes faster. As a result, it is possible to perform an operation of quickly passing through the pinch-off region, so that the hot carrier resistance can be further improved.

  Further, according to the second mechanism of the present invention, when the logic level of the output signal is about to transition at the time of transition of the logic level of the input differential signal, the inductive element is switched to at the transition of the inverting output terminal of the input stage transistor. By using the back electromotive force that occurs, the potential difference between the inverting output terminal (drain) of the input stage transistor and the reference side terminal (source) is reduced suddenly at the start of the transition. Since the potential difference between the inverting output terminal (drain) and the reference side terminal (source) of the input stage transistor when passing through the pinch-off region can be reduced, hot carrier resistance can be improved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

<Level Shift Circuit; First Embodiment>
FIG. 1 is a diagram illustrating a basic configuration example of the first embodiment of the level shift circuit. 2 and 3 are diagrams showing modifications thereof. FIG. 4 is a diagram showing a configuration example of a conventional level shift circuit as a comparative example.

  The level shift circuit 100 according to the first embodiment has a boost type configuration, and is configured by a combination of a first circuit block 100_1 and a second circuit block 100_1 having a differential configuration. In the following description, when describing each circuit block, each component member, node, signal, etc. is shown with reference symbols “_1” and “_2” for each circuit block. The reference is shown without a reference for each circuit block.

  Each of the circuit blocks 100_1 and 100_2 has a voltage higher than a voltage supplied from a power source VDDH to a logic circuit operating with a power source of a low voltage VDDL (not shown) (eg, a general logic level of about 1.0 to 5V). A voltage (also called a power supply voltage) VDDH is supplied. For example, a power supply voltage of 10 V or more is supplied with respect to the reference potential Vss (in this example, the ground potential GND).

  The first circuit block 100_1 includes a differential input node IN_1 and a differential output node OUT_1, and the second circuit block 100_2 includes a differential input node IN_2 and a differential output node OUT_2.

  One differential input signal (also referred to as a complementary input signal) Vin_1 is input to the differential input node IN_1, and the other differential input signal (also referred to as a complementary input signal) is input to the differential input node IN_2. Vin_2 is input. The details of the differential input signals Vin_1 and Vin_2 will be described later.

  An output pulse signal corresponding to the pulse-like differential input signal Vin_1 is obtained at the output terminal (drain) of the transistor Q101_1, and this output pulse signal is directly supplied to the differential output node OUT_1 as the output signal Vout_1. Further, an output pulse signal corresponding to the pulsed differential input signal Vin_2 is obtained at the output terminal (drain) of the transistor Q101_2, and this output pulse signal is directly supplied to the differential output node OUT_2 as the output signal Vout_2. The

  A first external load Load_1 is connected to the differential output node OUT_1, and a second external load Load_2 is connected to the differential output node OUT_2.

  Each external load Load corresponds to, for example, a predetermined impedance circuit provided with an impedance element (including one represented by an equivalent circuit). For example, each of the circuit blocks 100_1 and 100_2 is used for a driver circuit for a CCD, for example, for driving an element having a capacitive impedance such as a charge transfer device (CCD; Charge Coupled Device) (details will be described later). To do).

  In the first circuit block 100_1, first, one differential input signal Vin_1 output from a logic circuit of a low voltage source (not shown) is input to a gate (control input terminal) via one differential input node IN_1. And a first conductivity type input stage transistor Q101_1 (hereinafter simply referred to as transistor Q101_1) having a source grounded and a drain (transistor output terminal) connected to one differential output node OUT_1. Here, the first conductivity type is an N-type, and an N-channel MOS-FET (Metal Oxide Semiconductor Field Effect Transistor: NMOS) is used as the transistor Q101_1.

  Also, the first circuit block 100_1 has the gate of the feedback signal SFB_2 from the second circuit block 100_2 through the feedback input node FBI_1 and the source connected to the power source VDDH. Q103_1 (hereinafter simply referred to as transistor Q103_1). Here, the second conductivity type is a P-type, and a P-channel MOS-FET (PMOS) is used as the transistor Q103_1.

  Further, as a configuration unique to the present embodiment, the first circuit block 100_1 is interposed between the drain of the transistor Q101_1 (that is, the differential output node OUT_1) and the drain of the transistor Q103_1, and the second circuit block 100_2. Is provided with a feedback signal acquisition unit 105_1 for acquiring a feedback signal SFB_1 supplied to. The feedback signal SFB_1 acquired by the feedback signal acquisition unit 105_1 is supplied to the feedback input node FBI_2 of the second circuit block 100_2 via the feedback output node FBO_1.

  Here, the feedback signal acquisition unit 105_1 of the present embodiment is configured by a combination of a plurality of impedance elements 106, and a signal corresponding to a potential difference between both ends of the impedance element 106 based on an operating current flowing through the impedance element 106, in particular, A division signal between both drains corresponding to a division ratio determined by the ratio of impedance components of the impedance element 106 is obtained as a feedback signal SFB_1.

  As the impedance element 106, it is necessary to pass an operating current (DC current), so that a passive element such as a resistance element, an inductive element, a rectifier element (diode), or an active element such as a transistor (including an FET) is used. It is also possible to set an operating point and practically use it as an impedance component. Among these, the use of a resistance element is considered to be the simplest in terms of circuit configuration.

  For this reason, in this embodiment, a resistance dividing circuit composed of a series circuit of the resistance elements R106_1a and R106_1b is employed, and the connection node N106_1 is connected to the feedback output node FBO_1.

  For example, in the illustrated example, one terminal of the resistor element R106_1a is connected to the drain of the transistor Q101_1 (ie, the differential output node OUT_1), one terminal of the resistor element R106_1b is connected to the drain of the transistor Q103_1, and the resistor element R106_1a , R106_1b is connected to the other output terminal (middle point; connection node N106_1) is connected to the feedback output node FBO_1.

  The second circuit block 100_2 is basically configured such that a signal whose input signal is complementary to the signal input to the first circuit block 100_1 is input. The circuit block 100_1 is configured in the same manner.

  For example, in the second circuit block 100_2, first, the other differential input signal (complementary input signal) Vin_2 output from the logic circuit of the low voltage source not shown is gated via the other differential input node IN_2. , A source is grounded, and a drain is connected to the other differential output node OUT_2. The first conductivity type input stage transistor Q101_2 (hereinafter simply referred to as transistor Q101_2) is provided. The first conductivity type is an N type, and an N channel type MOS-FET (NMOS) is used as the transistor Q101_2.

  The second circuit block 100_2 has a second conductive type output stage transistor in which the feedback signal SFB_1 from the first circuit block 100_1 is input to the gate via the feedback input node FBI_2 and the source is connected to the power source VDDH. Q103_2 (hereinafter simply referred to as transistor Q103_2). The second conductivity type is P-type, and a P-channel type MOS-FET (PMOS) is used as the transistor Q103_2.

  The second circuit block 100_2 obtains a feedback signal SFB_2 to be supplied to the first circuit block 100_1 by being interposed between the drain of the transistor Q101_2 (that is, the differential output node OUT_2) and the drain of the transistor Q103_2. The feedback signal acquisition unit 105_2 is provided. The feedback signal SFB_2 acquired by the feedback signal acquisition unit 105_2 is supplied to the feedback input node FBI_1 of the first circuit block 100_1 via the feedback output node FBO_2.

  Like the feedback signal acquisition unit 105_1, the feedback signal acquisition unit 105_2 includes a combination of a plurality of impedance elements 106, and a signal corresponding to the potential difference between both ends of the impedance element 106 based on the operating current flowing through the impedance element 106, In particular, a division signal between both drains corresponding to a division ratio determined by the ratio of impedance components of the impedance element 106 is obtained as a feedback signal SFB_2.

  Specifically, the feedback signal acquisition unit 105_2 employs a resistance dividing circuit formed of a series circuit of resistance elements R106_2a and R106_2b, and the connection node N106_2 is connected to the feedback output node FBO_2. .

  For example, in the illustrated example, one terminal of the resistor element R106_2a is connected to the drain of the transistor Q101_2 (ie, the differential output node OUT_2), one terminal of the resistor element R106_2b is connected to the drain of the transistor Q103_2, and the resistor element R106_2a , R106_2b is connected to the other output terminal (middle point; connection node N106_2) is connected to the feedback output node FBO_2.

  As can be seen, in the level shift circuit 100 of the present embodiment, in the output stage, the feedback output node FBO_1 is connected to the gate of the transistor Q103_2 via the feedback input node FBI_2, and the feedback output node FBO_2 is connected to the feedback input node FBI_1. And is connected to the gate of the transistor Q103_1 through a hanging connection structure.

  Further, the level shift circuit 100 has a differential input interface in its input stage. By receiving a differential input signal supplied to the gates of the transistors Q101_1 and Q101_2, a level positive feedback loop is formed in the output stage. Have to have.

  Here, the mutual conductance gm of the transistors Q101_1 and Q101_2 in the input stage is set larger than the gm of the transistors Q103_1 and Q103_2 in the output stage in accordance with the degree of boosting according to the input / output conditions. The boost type level shift circuit 100 having such a configuration can flexibly design the degree of boosting, and is suitable for use as an interface between multiple power supplies in various multiple power supply circuits.

  If the feedback signal acquisition units 105_1 and 105_2 are omitted, the drains of the transistors Q101_1 and Q103_1 are directly connected, and the drains of the transistors Q101_2 and Q103_2 are directly connected, as shown in FIG. Further, this is the same as the positive feedback type level shift circuit 900 shown in FIG. 10 of Patent Document 1 and FIG. 14 of Patent Document 2.

  Here, in the level shift circuit 100 of the first embodiment, the feedback signal SFB_1 acquired by the feedback signal acquisition unit 105_1 is expressed by the following equation (1−1) where the drain voltage of the transistor Q101_1 is V101_1 and the drain voltage of the transistor Q103_1 is V103_1. 1).

  Further, the feedback signal SFB_2 acquired by the feedback signal acquisition unit 105_2 is expressed by Expression (1-2), where the drain voltage of the transistor Q101_2 is V101_2 and the drain voltage of the transistor Q103_2 is V103_2.

  In the present embodiment, each feedback signal acquisition unit 105 is interposed at least between the output terminal (drain) of the transistor Q101 as the input stage transistor and the output terminal (drain) of the transistor Q103 as the output stage transistor. It is only necessary to have an element that effectively functions as an impedance element, and it is not necessary to be a series circuit of a plurality of impedance elements 106.

  For example, when the feedback signal acquisition unit 105 is configured by including one impedance element 106, the side opposite to the drain of the transistor Q101 of the impedance element 106 as in the first modification (modification 1) shown in FIG. The signal obtained at the terminal (that is, the drain of the transistor Q103) can be a feedback signal SFB. Alternatively, as in the second modification (modification 2) shown in FIG. 3, the signal obtained at the connection point between the impedance element 106 and the drain of the transistor Q101 (that is, the drain of the transistor Q101) is used as the feedback signal SFB. Can also be adopted.

  Here, when the first modification example shown in FIG. 2 is compared with the second modification example (modification 2) shown in FIG. 3, there is a difference in the function of “making the operation to quickly pass through the pinch-off region”. . That is, in the first modification, the ON state of the counterpart transistor Q103 is set to a shallow state using the potential difference generated at both ends of the impedance element 106_a due to the operating current flowing through the impedance element 106_a when the transistor Q101 is ON. The feedback signal SFB to be stored can be acquired.

  As a result, at the time of transition of the logic level of the input differential signal, the transistor Q103 shifts from the shallow ON state to the OFF state during the positive feedback operation when the logic level of the output signal is about to transition. As a result, it is possible to operate so as to quickly pass through the pinch-off region, so that the hot carrier resistance can be further improved.

  On the other hand, in the second modified example, the feedback signal is the same as that of the conventional level shift circuit 900 shown in FIG. 4, and therefore, the ON state of the counterpart transistor Q103 cannot be kept shallow.

  Of course, in order to make the hot carrier resistance more complete, the feedback signal acquisition unit 105 is configured by a series circuit of a plurality of impedance elements 106, and a signal appearing at a connection point of the plurality of impedance elements 106 is defined as a feedback signal SFB. It is preferable (details will be described later).

<Operation; First Embodiment>
FIG. 5 is a diagram for explaining the operation of the level shift circuit 100 of the first embodiment (particularly the basic configuration shown in FIG. 1). FIG. 6 is a diagram for explaining the operation of the conventional level shift circuit 900 shown in FIG. 4 as a comparative example.

  5A and 6A show one differential input signal (complementary input signal) Vin_1 supplied to the transistors Q101_1 and Q901_1 in one input stage, and FIG. FIG. 6B shows the other differential input signal (complementary input signal) Vin_2 supplied to the transistors Q101_2 and Q901_2 of the other input stage. 5C and 6C show the output pulse signal Vout_1 obtained at one differential output node OUT_1, and FIGS. 5D and 6D show the other differential output. An output pulse signal Vout_2 obtained at the node OUT_2 is shown. When the voltage level is low, “L” is displayed, and when the voltage level is high, “H” is displayed.

  First, the operation of the conventional level shift circuit 900 shown in FIG. 4 as a comparative example will be described. As shown in FIGS. 6A and 6B, differential signals Vin_1 and Vin_2 having substantially opposite phases are input to the input stage of the level shift circuit 900.

  Here, “substantially opposite-phase differential signals Vin_1 and Vin_2” are referred to as “input signals, although they are so small that there is no period during which the transistors Q901_1 and Q901_2 of the input stage are simultaneously turned on in the transition process”. The signal is provided with a non-overlap period, that is, a period in which both input signals are both at the L level (the level at which the transistor Q101 is turned on), and an operation for creating a state where the transistors Q901_1 and Q901_2 in the input stage are simultaneously turned off for a moment. It is because it was made to let it.

  This is because when the input is completely in reverse phase, the transistors Q901 and Q903 in the input stage and the output stage of each circuit block 100_1 and 100_2 are both turned on (simultaneously) in the transition process at the time of logic inversion of the input signal Vin. This is in order to prevent a through current that flows when a period is generated and at the same time the power is turned on and the power consumption increases.

  First, when the voltage of the input signal Vin_1 to the transistor Q901_1 (NMOS) is “H” (before t90), the transistor Q901_1 is turned on, so that the output voltage of the differential output node OUT_1 is the reference potential. The voltage is the same as Vss (= ground potential GND), the voltage of the input signal Vin_2 to the transistor Q901_2 (NMOS) is “L”, and the transistor Q901_2 is off.

  At this time, since the gate of the transistor Q903_2 (PMOS) is on because the voltage at the differential output node OUT_1 is equal to the reference potential Vss, the transistor Q903_2 (PMOS) has the differential output node OUT_2 that is the output of the transistor Q901_2 in the off state. The voltage is the same as the power supply potential VDDH. Further, the transistor Q903_1 (PMOS) is turned off because its gate is at the voltage of the differential output node OUT_2 = the power supply potential VDDH.

  In this state, the drain current Ids_1 of the transistor Q901_1 is in a saturated state, and the drain current Ids_2 of the transistor Q901_2 is in a non-saturated state.

  Next, for non-overlapping operation, the input signal Vin_1 is set to “L” to turn off the transistor Q901_1 (NMOS) (t90 to t91), and then the input signal Vin_2 is set to “H” to set the transistor Q901_2 (NMOS). Is turned on (t91 to t92).

  In the process of turning on the transistor Q901_2 (NMOS), the transistor Q901_1 is in the off state. When the transistor Q901_2 (NMOS) is turned on, the transistor Q903_2 (PMOS) remains in the on state, or the transistor Q901_1 (NMOS) is in the process of shifting to the off state slightly due to the off state. The potential of the differential output node OUT_2 slowly decreases from the previous power supply voltage VDDH to a value obtained by dividing the power supply voltage VDDH by the operating resistance of the transistor Q903_2 (PMOS) and the on-resistance of the transistor Q901_2 (NMOS) (t90). ~ T92).

  The voltage of the differential output node OUT_2, which is the output of the transistor Q901_2 (NMOS), becomes the gate voltage of the transistor Q903_1, the gate voltage drops from the power supply potential VDDH (t91), becomes lower than the threshold voltage of the transistor Q903_1, and the transistor Q903_1 Is turned on (t92), the transistor Q903_1 transits from the non-saturated state to the saturated state.

  In this state, since the transistor Q901_1 (NMOS) is in the off state, the voltage of the differential output node OUT_1 as its output rises above the reference potential Vss. Then, as the voltage of the differential output node OUT_1 increases, the transistor Q903_2 shifts to an off state.

  By continuing such an operation, the voltage of the differential output node OUT_2 rapidly changes from the power supply potential VDDH to the reference potential Vss, and the voltage of the differential output node OUT_1 rapidly changes from the reference potential Vss. The power supply potential VDDH is reached, and the level shift operation ends (t93).

  Even when the voltage of the input signal Vin_1 changes from “L” to “H”, the same operation as described above is performed in the transistors Q901 (NMOS) and Q903 (PMOS) (t95 to t98).

  In the conventional level shift circuit 900 shown in FIG. 4, a positive feedback loop in which the differential output node OUT, which is the output of the transistor Q901 (NMOS), is used as the feedback signal SFB supplied to the other circuit blocks 900_1 and 900_2. Is configured. The voltage of the differential output node OUT is at the reference potential Vss or the power supply potential VDDH.

  For this reason, since the voltage (= differential output node OUT) supplied to the gate of the transistor Q103 is at the drain voltage (= reference voltage Vss) when the transistor Q101 is in the ON state, the voltage of the transistor Q903 (PMOS) The on state is at a very deep level.

  Accordingly, when the logic is inverted during the switching operation, a positive feedback loop from a very deep level is formed. Therefore, when the transistor Q903_2 (_1) (PMOS) is turned off and the transistor Q901_2 (_1) (NMOS) is turned on, a positive feedback operation from a very deep level is performed. Therefore, the input signal Vin to the transistor Q901 (NMOS) Even if the transistor Q903_2 (_1) (PMOS) is turned off, the voltage change of the differential output node OUT_2 due to the turning on of the transistor Q901_2 (_1) (NMOS) is also delayed. Response during switching operation becomes heavy.

  For example, in the process of turning on the transistor Q901_2 (NMOS), even if the input signal Vin_2 to the transistor Q901_2 (NMOS) becomes “H”, the output becomes the on level (reference voltage Vss). There is a delay, indicating a slow response.

  By the way, when a voltage is applied to the miniaturized NMOS drain, a high electric field region is formed in the vicinity of the drain. When carriers (electrons) flow into this region, the carriers obtain high energy by an electric field and become hot carriers. Some of these phonon scatter and some lose energy due to impact ionization. Among the hot carriers, those having energy sufficient to exceed the potential barrier of Si—SiO 2 are injected into the gate oxide film, causing fluctuations in the threshold voltage (Vth) and mutual conductance gm of the MOS transistor. Causes an accelerated phenomenon.

  For example, when the non-overlap operation is performed as described above, as shown in FIGS. 6C and 6D, the low transconductance gm of each transistor Q903 (PMOS) in the output stage and the slow feedback loop caused by the positive feedback loop. A response indicating a bad transition is observed.

  At this time, the drain potential (ie, differential output node OUT) of each transistor Q901 (NMOS) transitions from the power source VDDH to the reference potential Vss (= ground potential GND), that is, the transistor Q901 (NMOS) is turned on from the off state. In the process of transition to the state, the pinch-off region is passed with the drain-source voltage Vds being large.

  However, when passing through the pinch-off region with a large drain-source voltage Vds, an electric field stronger than that of other logic circuits is applied in the vertical direction (gate-drain direction), and a sharp channel near the drain Is applied with a strong electric field in the horizontal direction (between the drain and the source), and carriers (electrons) in the channel are accelerated by the strong electric field in the horizontal direction. It is easy to cause a phenomenon of generating an electron-hole pair by collision, so-called impact ionization phenomenon.

  In the case of the transistor Q901 (NMOS), the impact-ionized electron-hole pair is likely to cause a hole to enter the gate insulating film to form a trap level in the gate insulating film and to deteriorate hot carrier resistance. Therefore, an element having low hot carrier resistance causes deterioration of mutual conductance gm and reduction of drain current saturation characteristic Idsat.

  In any case, slow passage through the pinch-off region while a large drain-source voltage Vds is applied promotes deterioration of hot carrier resistance. In other words, in the conventional boost type level shift circuit 900, boosting is performed by the configuration using the positive feedback loop, but the input / output response that deteriorates the hot carrier tolerance in the input / output response due to the positive feedback loop. There is concern about hot carrier resistance.

In view of this, in order to prevent deterioration of hot carrier resistance and improve hot carrier resistance,
1) Reduce the drain-source voltage Vds of the MOS transistor when passing through the pinch-off region.
2) Make it move quickly through the pinch-off area,
It is considered effective to devise this in order to enhance the hot carrier resistance and extend the life of the circuit.

  The circuit configuration of the first embodiment shown in FIG. 1 and the operation shown in FIG. 5 satisfy both of these conditions simultaneously. That is, in the circuit configuration and operation of the first embodiment shown in FIG. 1, as shown in FIG. 5, the input / output characteristics substantially similar to the input / output characteristics of the logic inverter can be adopted. Therefore, as in the input / output characteristics shown in FIG. 6, it is possible to alleviate a situation in which deterioration of hot carrier resistance such as slow passage through the pinch-off region of the MOS transistor with a large drain-source voltage Vds is promoted. .

  Here, the background of the input / output characteristics shown in FIG. 6 is that the feedback signal acquisition unit 105 that employs a resistance dividing circuit composed of a series circuit of resistance elements R106_a and R106_b is connected to a transistor Q101 (NMOS) and a transistor Q103 (PMOS). ) Between the drains of the transistor Q103, and a signal obtained from the middle point thereof is supplied as a feedback signal SFB to each gate of the transistor Q103 (PMOS).

  This is because the current Ids generated during the switching operation flows through the impedance element 106 (resistive elements R106_a and R106_b in this example), thereby generating a potential difference between the terminals of the impedance element 106 and the drain of the transistor Q101 (NMOS) during the switching operation. -It works to reduce the source-to-source voltage Vds (the function 1 described above).

  Furthermore, a divided signal obtained from the connection node N106, which is a connection point of a plurality of impedance elements 106 (two resistance elements R106_a and R106_b in this example) connected in series, is fed back to the other circuit blocks 100_1 and 100_2. A positive feedback loop is formed as SFB. This makes it possible to form a positive feedback loop from a shallow level compared to the positive feedback from a deep level in the conventional level shift circuit 900 shown in FIG. 4, so that the response can be lightened and a fast response can be realized ( Function 2) described above).

  That is, first, when the voltage of the input signal Vin_1 to the transistor Q101_1 (NMOS) is “H” (before t10), the transistor Q101_1 is turned on, so that the voltage of the differential output node OUT_1 as its output is It becomes the same potential as the reference potential Vss (= ground potential GND), the voltage of the input signal Vin_2 to the transistor Q101_2 (NMOS) is “L”, and the transistor Q101_2 is in an off state.

  At this time, the transistor Q103_2 (PMOS) is turned on because its gate is at the voltage of the connection node N106_1 (see later), so that the drain voltage is the same as the power supply potential VDDH and the transistor Q101_2 in the off state. Since the voltage at the differential output node OUT_2, which is the output of, becomes the same potential as the power supply potential VDDH, the voltage at the connection node N106_2 also becomes the same potential as the power supply potential VDDH.

  Further, the transistor Q103_1 (PMOS) is in an OFF state because its gate is at the voltage of the connection node N106_2 = the power supply potential VDD. Therefore, the voltage of the drain is substantially the same as the voltage of the connection node N106_1 obtained by adding the product of the drain current Ids_1 and the resistance element R106_1a at the time of ON to the voltage of the differential output node OUT_1 that is the output of the transistor Q101_1 in the on state. Become potential.

  Note that the voltage at the connection node N106_1 obtained by adding the product of the drain current Ids_1 at the ON time and the resistance element R106_1a to the voltage at the differential output node OUT_1 becomes a voltage that turns on the transistor Q103_2 (PMOS). A constant of the element R106_1a is set.

  In this state, the drain current Ids_1 of the transistor Q101_1 is in a saturated state, and the drain current Ids_2 of the transistor Q101_2 is in a non-saturated state.

  Next, in order to achieve a non-overlapping operation, the input signal Vin_1 is set to “L” to turn off the transistor Q101_1 (NMOS) (t10 to t11), and then the input signal Vin_2 is set to “H” to set the transistor Q101_2 (NMOS). Is turned on (t11 to t12).

  In the process of turning on the transistor Q101_2 (NMOS), the transistor Q101_1 is in an off state. Further, the differential output node OUT_2 which is the output of the transistor Q101_2 (NMOS) becomes the gate voltage of the transistor Q103_1 via the impedance element 106 (here, the resistance element R106_1a), and the gate voltage drops from the power supply potential VDDH (t11). ) When the transistor Q103_1 becomes lower than the threshold voltage of the transistor Q103_1 and can be turned on, the transistor Q103_1 transitions from the non-saturated state to the saturated state.

  In this state, since the transistor Q101_1 (NMOS) is in the off state, the voltage of the differential output node OUT_1 that is the output rises above the reference potential Vss. Then, when the voltage of the differential output node OUT_1 increases, the transistor Q103_2 shifts to an off state.

  By continuing such an operation, the voltage of the differential output node OUT_2 changes from the power supply potential VDDH to the reference potential Vss, and the voltage of the differential output node OUT_1 changes from the reference potential Vss to the power supply potential VDDH. Thus, the level shift operation ends (t12).

  Even when the voltage of the input signal Vin_1 changes from “L” to “H”, the same operation as described above is performed in the transistors Q101 (NMOS) and Q103 (PMOS) (t15 to t18).

  Here, when the transistor Q101 (NMOS) is going to be turned on (during switching operation), the operating current flows at least through the impedance element 106_a on the transistor Q101 side, so that the switching is performed by the potential difference generated at both ends of the impedance element 106_a. The potential between the drain and source of the transistor Q101 (NMOS) during operation can be reduced.

  The voltage of the connection node N106 supplied to the gate of the transistor Q103 is the drain voltage (= differential output node OUT) when the transistor Q101 is on, and the drain current Ids and resistance element R106_a of the on-resistance Since the voltage is obtained by adding the products, the on-state of the transistor Q903 (PMOS) is at a shallower level than the conventional configuration shown in FIG.

  Therefore, when the logic is inverted during the switching operation, a positive feedback loop from a shallow level can be formed, so that the response can be reduced and a fast transition response can be realized. If a fast transition response can be realized, the pinch-off region can be quickly overcome.

  In the present embodiment, the resistor element R106_b is also interposed between the connection node N106 and the transistor Q103 (PMOS). Even when the transistor Q103 (PMOS) is turned off, there is a delay during the switching operation. The function of reducing the drain-source voltage Vds of the transistor Q101 (NMOS) (the function 1 described above) and the fast transition response (the function 2 described above) are made to function more effectively.

  That is, when the resistor element R106_b is not interposed, if there is a delay in turning off one transistor Q103 (PMOS), the function of reducing the drain-source voltage Vds is naturally only the potential difference of the resistor element R106_a, and the delay. Accordingly, the decrease in the potential of the connection node N106 due to the turning on of the transistor Q101 (NMOS) is delayed, and as a result, the turning on of the other (counterpart) transistor Q103 (PMOS) is delayed, and the entire switching operation is delayed.

  On the other hand, when the resistor element R106_b is interposed, even if there is a delay in turning off the transistor Q103 (PMOS) and the H level remains, by utilizing the potential difference between the resistor elements R106_a and R106_b, the drain-source The effect of reducing the inter-voltage Vds is enhanced.

  In addition, when the transistor Q101 (NMOS) is turned on, the voltage of its drain (= differential output node OUT) becomes the same voltage as the reference potential Vss, and the region between the H level and the reference potential Vss is divided by the resistance elements R106_a and R106_b. As a result, the potential of the connection node N106 is obtained, and this is supplied to the gate of the other (counterpart) transistor Q103 (PMOS).

  Therefore, regardless of the delay in turning off of the transistor Q103 (PMOS), the potential drop of the connection node N106 due to the turning on of the transistor Q101 (NMOS) contributes immediately to turn on the other (counter) transistor Q103 (PMOS). To do.

  Note that the potential of the connection point (= the voltage of the connection node N106_1 obtained by adding the product of the drain current Ids_1 and the resistance element R106_1a to the drain voltage of the transistor Q101) obtained by the drain current Ids_1 flowing through the resistance elements R106_1a and R106_1b is the transistor The constants of the resistance elements R106_1a and R106_1b are set so as to be a voltage for turning on the Q103_2 (PMOS). As long as that is the case, the constants of the resistance elements R106_1a and R106_1b may be the same or different. By adjusting the constant ratio of the resistance elements R106_1a and R106_1b, the optimum feedback signal SFB can be obtained.

  Even if there is a delay in turning off the transistor Q103 (PMOS), a positive feedback loop from a shallow voltage level of the connection node N106_2 can be formed immediately, so that the response can be lightened and a fast response can be realized. If a quick response can be realized, the pinch-off region can be quickly overcome.

  During the switching operation, the operating points of the transistors Q101_1 and Q101_2 (NMOS) can be alleviated from passing through a pinch-off region where the drain-source voltage Vds is large, and hot carrier resistance deterioration can be improved. The time during which the differential output node OUT of the level shift circuit 100 remains at the intermediate potential between the power supply voltage VDDH and the reference voltage Vss can be significantly reduced, and the reduction of the mutual conductance gm due to impact ionization can be reduced. .

  As an additional effect, there is an advantage that the through current flowing at that time can be limited even if the NMOS and the PMOS are turned on at the same time by interposing the resistance elements R106_a and R106_b. As a result, the non-overlap period can be shortened as much as possible. The delay time can be shortened, and it becomes more suitable for high-speed operation.

  As described above, in the structure of the first embodiment, it is more preferable that 1) the device is adapted to reduce the drain-source voltage Vds of the MOS transistor when passing through the pinch-off region. By taking measures to cope with such an operation, it is possible to realize a level shift circuit that can contribute to prevention and reduction of hot carrier resistance deterioration, and as an additional effect, it can also contribute to high-speed operation.

<Simulation results>
7 and 8 are diagrams showing the results of analyzing the operation of the level shift circuit 100 of the first embodiment shown in FIG. 1 by simulation. Here, FIG. 7 shows a state in which the constant of the resistance element used as the impedance element 106 is set to “0Ω”, which is practically the same as the conventional level shift circuit 900. FIG. 8 shows a state where the constants of the resistance elements R106_a and R106_b used as the impedance element 106 are “2 kΩ”.

  As can be seen from FIG. 7, when the constant of the resistance element R106 is set to “0Ω”, that is, in the conventional level shift circuit 900, when the pinch-off region is gradually changed, the hot carrier resistance may be easily deteriorated. I understand that there is.

  On the other hand, as can be seen from FIG. 8, when the constant of the resistance element R106 is “2 kΩ”, the pinch-off region changes more quickly than when the constant of the resistance element R106 is “0Ω”. It can be seen that carrier resistance is improved.

  Further, there is no harmful effect caused by interposing the feedback signal acquisition unit 105_1 for acquiring the feedback signal SFB_1 supplied to the other circuit block 100 between the drain of the transistor Q101 (differential output node OUT_1) and the drain of the transistor Q103_1. You may think.

  Rather, when the constant of the resistive element R106 is “0Ω”, the logic can be switched when the differential input is 2.5 Vpp or more, whereas when the constant of the resistive element R106 is “2 kΩ”, the differential input is The logic can be switched when the voltage is 1.5 Vpp or higher. In other words, when there is no resistor, an input range of 2.5 Vpp or more is required, but when a resistor of 2 kΩ is inserted, an input range of 1.5 Vpp or more is required. It means that the function has been improved in the direction where mistakes are unlikely to occur. Therefore, it can be seen that there is an advantage that the dynamic range in which the logic is switched can be expanded.

<Level Shift Circuit; Second Embodiment>
FIG. 9 is a diagram illustrating a configuration example of the second embodiment of the level shift circuit. The level shift circuit 100 of the second embodiment is based on the conventional level shift circuit 900 shown in FIG. 4 and is different from the drains of the transistors Q101_1 and Q101_2 (NMOS) of the input stage (transistor output nodes 107_1 and 107_2). It is characterized in that inductive elements (inductors) 108_1 and 108_2, which are examples of impedance elements, are interposed between the dynamic output nodes OUT_1 and OUT_2.

  The external loads Load_1 and Load_2 are not directly connected to the output nodes 107_1 and 107_2 of the transistors Q101_1 and Q101_2 (NMOS), but are connected to the differential output nodes OUT_1 and OUT_2 via the inductive elements 108_1 and 108_2. The inductive element 108 is used for advance compensation.

<Operation; Second Embodiment>
FIG. 10 is a diagram for explaining the operation of the level shift circuit 100 of the second embodiment. The mechanism of the second embodiment uses a momentary change (back electromotive voltage) of the current flowing through the inductive element 108 at the time of the switching operation, so that the drain-source voltage Vds is large in the pinch-off region of the MOS transistor. It is intended to alleviate the situation that promotes the deterioration of the hot carrier resistance of passing slowly.

  That is, the output nodes 107_1 and 107_2 transition from the power supply voltage VDDH to the reference voltage Vss (= ground potential GND) by utilizing the fact that the potential difference generated at both ends of the inductive element 108 during the switching operation is proportional to the time differentiation of the current. In this case, the potential is suddenly lowered for a moment at the start of the transition so that the transistor Q101_1, Q101_2 (NMOS) transitions in a state where the drain-source voltage Vds is reduced when passing through the pinch-off region at the moment when the transistor Q101_1 and Q101_2 (NMOS) start to turn on. Can be made. The inductive element 108 serves to reduce the drain-source voltage Vds of the transistor Q101 (NMOS) during the switching operation.

  During the switching operation, the drain voltages of the transistors Q101_1 and Q101_2 (NMOS) are instantaneously lowered, so that the operating point of the transistors Q101_1 and Q101_2 (NMOS) can be prevented from passing through the pinch-off region where the drain-source voltage Vds is large. , Hot carrier resistance deterioration can be improved.

  When the logic level of the output signal is about to transition at the time of transition of the logic level of the input differential signal, transition is performed using the back electromotive voltage generated in the inductive element 108 at the transition of the output terminal (output node 107) of the transistor Q101. This is because the drain-source voltage of the transistor Q101 is decreased suddenly at the start, and in the subsequent transition process, the drain-source voltage of the transistor Q101 when passing through the pinch-off region is decreased. .

<Level Shift Circuit; Third Embodiment>
FIG. 11 is a diagram illustrating a configuration example of the third embodiment of the level shift circuit. The level shift circuit 100 according to the third embodiment is based on the level shift circuit 100 according to the first embodiment shown in FIG. 1, and the drains of the transistors Q101_1 and Q101_2 (NMOS) in the input stage (transistor output nodes 107_1 and 107_2). ) And differential output nodes OUT_1 and OUT_2, the inductive elements 108_1 and 108_2 are interposed.

  The external loads Load_1 and Load_2 are not directly connected to the output nodes 107_1 and 107_2 of the transistors Q101_1 and Q101_2 (NMOS), but are connected to the differential output nodes OUT_1 and OUT_2 via the inductive elements 108_1 and 108_2.

<Operation; Third Embodiment>
FIG. 12 is a diagram for explaining the operation of the level shift circuit 100 of the third embodiment. The mechanism of the third embodiment is a combination of the mechanism of the second embodiment and the mechanism of the first embodiment, and both operations are realized.

  Similar to the second embodiment, by using the instantaneous change of the current flowing through the inductive element 108 during the switching operation, the MOS transistor slowly passes through the pinch-off region with a large drain-source voltage Vds. It is intended to further alleviate the situation that promotes the deterioration of hot carrier resistance.

  When the output nodes 107_1 and 107_2 transit from the power supply voltage VDDH to the reference voltage Vss (= ground potential GND) during the switching operation, the potential difference generated at both ends of the inductive element 108 is proportional to the time differentiation of the current. The drain voltage of the transistors Q101_1 and Q101_2 (NMOS) is instantaneously reduced when passing through the pinch-off region at the moment when the transistors Q101_1 and Q101_2 (NMOS) start to turn on by suddenly lowering the potential at the start of the transition. By lowering, the transition is made with the drain-source voltage Vds being reduced.

  As a result, it is possible to alleviate the operating point of the transistors Q101_1 and Q101_2 (NMOS) from passing through the pinch-off region where the drain-source voltage Vds is large during the switching operation, and to improve hot carrier resistance deterioration.

  Here, in the second embodiment or the third embodiment, how to form the inductor component of the inductive element 108 can be a problem. For example, in recent process technologies for radio frequency (RF) circuits, it has become possible to produce thick film metal for inductors. Therefore, it is conceivable to adopt a method of making and using a winding inductor.

  On the other hand, it is also conceivable to employ a method of using an inductor component attached to a wire using a bonding wire in the IC chip. However, when a bonding wire is used, a mutual inductor is formed by the outgoing line and the return line, so it is necessary to consider reduction of the total inductance due to the mutual inductor component. In addition, it is necessary to consider the presence of parasitic capacitance given to the pad (Pad).

  Also, from the viewpoint of inductor component accuracy, it is considered better to use a thick film metal process.

<Outline of CCD solid-state imaging device and peripheral part>
FIG. 13 is a schematic diagram of a solid-state imaging device 202 including a CCD solid-state imaging device 210 and a drive control unit 240 that is an embodiment of a driving device (hereinafter also referred to as a driver circuit) that drives the CCD solid-state imaging device 210. It is. In the present embodiment, the interline transfer (IT) type CCD solid-state imaging device 210 is vertically driven and transferred in 6 or 8 phases and horizontally transferred in N (N is a positive integer of 2 or more) phase. Will be described as an example. Here, an example of horizontal transfer driving in two phases is shown.

  In FIG. 13, the drive control unit 240 that is an embodiment of the driver circuit includes a timing signal generation unit 241 and a drive unit 242. The timing signal generator 241 is an example of a logic circuit that operates with a power supply of a low voltage VDDL (for example, a general logic level of about 1.0 to 5 V).

  The driving unit 242 includes the level shift circuit 100 according to the first to third embodiments described above, and in the final stage, for each electrode to be driven, a P-channel MOS transistor and an N-channel MOS transistor are connected in series. A circuit is provided (details will be described later).

  A drain voltage VDD and a reset drain voltage VRD are applied to the CCD solid-state imaging device 210 as an example of a power supply voltage VDDH that is higher than the low voltage VDDL supplied to the timing signal generator 241 from the drive power supply 246 and driven. A predetermined voltage as an example of the power supply voltage VDDH is also supplied to the drive unit 242 corresponding to the output stage of the control unit 240.

  A CCD solid-state imaging device 210 constituting the solid-state imaging device 202 is provided on a semiconductor substrate 221 with a sensor unit (photosensitive unit; photocell) 211 including a photodiode as an example of a light receiving element corresponding to a pixel (unit cell). Are arranged in a two-dimensional matrix in the vertical (column) direction and the horizontal (row) direction. These sensor units 211 convert incident light incident from the light receiving surface into signal charges having a charge amount corresponding to the amount of light, and store the signal charges.

  The CCD solid-state imaging device 210 has a plurality of vertical transfer electrodes 224 (224-1 in this example) corresponding to 6-phase or 8-phase drive for each vertical row of the sensor unit 211 (6 or 8 per unit cell). ˜224-6 or 224-1 to 224-8) are arranged, a vertical CCD (V register unit, vertical transfer unit) 213 is arranged.

  The transfer direction of the vertical CCD 213 is the vertical direction in the figure, the vertical CCD 213 is provided in this direction, and a plurality of vertical transfer electrodes 224 are arranged in a direction (horizontal direction) orthogonal to this direction. Further, a read gate (ROG) 212 is interposed between the vertical CCD 213 and each sensor unit 211. A channel stop CS is provided at the boundary between the unit cells. An imaging area 214 is configured by a plurality of vertical CCDs 213 that are provided for each vertical column of the sensor units 211 and vertically transfer signal charges read from the sensor units 211 by the read gate unit 212.

  The signal charges accumulated in the sensor unit 211 are read out to the vertical CCD 213 when a drive pulse corresponding to the readout pulse XSG is applied to the readout gate unit 212. The vertical CCD 213 is driven to be driven by drive pulses φV1 to φV6 (φV8) based on 6-phase (8-phase) vertical transfer clocks V1 to V6 (V8), and the read signal charges are included in a part of the horizontal blanking period. Then, the portions corresponding to one scanning line (one line) are sequentially transferred in the vertical direction. This vertical transfer for each line is called a line shift.

  Further, the CCD solid-state imaging device 210 includes horizontal CCDs (H register units, H) extending in the horizontal direction in the figure adjacent to the respective transfer destination side ends of the plurality of vertical CCDs 213, that is, the vertical CCDs 213 in the last row. Horizontal transfer unit) 215 is provided for one line. In the present embodiment, the horizontal CCD 215 is transfer-driven by drive pulses φH1 and φH2 based on two horizontal transfer clocks H1 and H2 (specifically, there are P-channel and N-channel clocks, respectively), and a plurality of vertical CCDs 215 are driven. The signal charges for one line transferred from the CCD 213 are sequentially transferred in the horizontal direction in the horizontal scanning period after the horizontal blanking period. Therefore, a plurality (two) of horizontal transfer electrodes 229 (229-1, 229-2) corresponding to the two-phase driving are provided.

  At the end of the transfer destination of the horizontal CCD 215, for example, a charge-voltage converter 216 having a floating diffusion amplifier (FDA) configuration is provided. The charge / voltage converter 216 sequentially converts the signal charges horizontally transferred by the horizontal CCD 215 into voltage signals and outputs them. This voltage signal is derived as a CCD output (VOUT) corresponding to the amount of incident light from the subject. Thus, the interline transfer type CCD solid-state imaging device 210 is configured.

  Further, the solid-state imaging device 202 generates various pulse signals (binary of “L” level and “H” level) for driving the CCD solid-state imaging device 210 as a characteristic part of the solid-state imaging device 202 of the present embodiment. And a drive unit 242 that supplies various pulses supplied from the timing signal generation unit 241 to drive pulses of a predetermined level and supplies them to the CCD solid-state imaging device 210.

  For example, the timing signal generation unit 241 reads out the readout pulse XSG for reading out the signal charge accumulated in the sensor unit 211 of the CCD solid-state imaging device 210 based on the horizontal synchronization signal (HD) and the vertical synchronization signal (VD). Vertical transfer clocks V1 to Vn (n indicates the number of phases at the time of driving; for example, V6 at the time of six-phase driving, V8 at the time of eight-phase driving), Horizontal transfer clocks H1 and H2, a reset pulse RG and the like for transferring and driving the transferred signal charges in the horizontal direction and passing them to the charge voltage conversion unit 216 are generated and supplied to the drive unit 242.

  The drive unit 242 converts various clock pulses supplied from the timing signal generation unit 241 into voltage signals (drive pulses) of a predetermined level, or converts them into other signals and supplies them to the CCD solid-state image sensor 210. For example, the n-phase vertical transfer clocks V 1 to V 6 (V 8) generated from the timing signal generation unit 241 are converted into vertical drive pulses φV 1 to φV 6 (φV 8) via the drive unit 242, and are stored in the CCD solid-state imaging device 210. The voltage is applied to a corresponding predetermined vertical transfer electrode (224-1 to 224-6 or 224-1 to 224-8). Similarly, the two-phase horizontal transfer clocks H1 and H2 are converted into horizontal drive pulses φH1 and φH2 via the drive unit 242, and corresponding predetermined horizontal transfer electrodes (229-1, 229− in the CCD solid-state imaging device 210). 2) to be applied.

  The drive unit 242 superimposes the readout pulse XSG on V1, V3, V5 (, V7) of the six-phase or eight-phase vertical transfer clocks V1 to V6 (V8), thereby setting the ternary level. The obtained vertical drive pulses φV1, φV3, φV5 (, φV7) are supplied to the CCD solid-state imaging device 210. That is, the vertical drive pulses φV1, φV3, φV5 (, φV7) are used not only for the original vertical transfer operation but also for reading the signal charges.

  An outline of a series of operations of the CCD solid-state imaging device 210 having such a configuration is as follows. First, the timing signal generator 241 generates various pulse signals such as transfer clocks V1 to V6 (V8) for vertical transfer and a read pulse XSG. These pulse signals are converted into drive pulses of a predetermined voltage level by the drive unit 242 and then input to predetermined terminals of the CCD solid-state image sensor 210.

  For the signal charges accumulated in each of the sensor units 211, the readout pulse XSG generated from the timing signal generation unit 241 is applied to the transfer channel terminal electrode of the readout gate unit 212, and the potential below the transfer channel terminal electrode is deepened. As a result, data is read out to the vertical CCD 213 through the readout gate unit 212. Then, the vertical CCD 213 is driven based on the six-phase (eight-phase) vertical drive pulses φV1 to φV6 (φV8), and sequentially transferred to the horizontal CCD 215.

  The horizontal CCD 215 is one line vertically transferred from each of the plurality of vertical CCDs 213 based on the two-phase horizontal drive pulses φH1 and φH2 emitted from the timing signal generator 241 and converted to a predetermined voltage level by the driver 242. Are sequentially transferred horizontally to the charge-voltage converter 216 side.

  The charge-voltage conversion unit 216 accumulates signal charges sequentially injected from the horizontal CCD 215 in a floating diffusion (not shown), converts the accumulated signal charges into a signal voltage, and outputs the signal charge via, for example, an output circuit having a source follower configuration (not shown). The image signal (CCD output signal) VOUT is output under the control of the reset pulse RG generated from the timing signal generator 241.

<Configuration example of drive unit>
FIG. 14 is a block diagram illustrating a configuration example of the drive unit 242. The driving unit 242 makes a pair of differences between various pulse signals (transfer clocks V1 to Vn, H1, H2 in this example) of the single-ended output generated by the timing signal generating unit 241 operating at a relatively low power supply voltage VDDL. A preamplifier circuit 310 that is an example of a differential signal generation unit that converts and outputs a dynamic signal and a pair of differential signals output from the preamplifier circuit 310 as a differential input signal Vin_1 and Vin_2 as a pair of output pulse signals A level shift circuit 320 that generates Vout_1 and Vout_2, and a drive pulse signal to be supplied to the vertical transfer electrode 224 and the horizontal transfer electrode 229 (not shown) are generated based on the output pulse signals Vout_1 and Vout_2 of the level shift circuit 320. The output buffer circuit 330 is an example of an output signal generation unit.

  The preamplifier circuit 310 employs a configuration using a differential amplifier 311. First, various transfer clocks V1 to Vn, H1, and H2 are supplied to one input terminal 312 from a timing signal generator 241 that operates at a low voltage VDDL that is not shown. On the other input terminal 313 side, a resistor series circuit 314 including resistor elements 315 and 316 for dividing the power supply voltage VDDL and the reference voltage Vss is provided, and a connection point between the resistor elements 315 and 316 is connected to the input terminal 313. Connected.

  Here, the preamplifier circuit 310 of the present embodiment functioning as a differential signal generation unit is arranged as a pair of differential signals at the input stage of the subsequent level shift circuit 320 at the time of transition of each differential signal. A signal capable of forming a state in which the pair of transistors Q101 (NMOS) are simultaneously turned off is generated.

  For example, in a preamplifier circuit, a single-ended input signal is converted into a differential signal having a uniform amplitude, and the DC (Direct Current) level of each differential signal is changed to a reference level (reference potential Vss: ground potential in this example). Operate to shift to GND). By setting the DC level to the reference level, the signal component below the reference level is cut in the differential signal after the shift, and the reference level is pasted on the signal component of the cut portion, and only the signal component above the reference level Can be taken out. As a result, a non-overlapping differential output signal can be obtained by the preamplifier circuit.

  Further, as the level shift circuit 320 of this configuration example, the level shift circuit 900 similar to the conventional one is adopted for the vertical transfer clocks V1 to Vn, and the horizontal transfer clocks H1 and H2 are fast. In consideration of hot carrier resistance during driving, the level shift circuit 100 shown in the first to third embodiments of the present application is adopted. Of course, the level shift circuit 100 shown in the first to third embodiments may be adopted for the transfer clocks V1 to Vn of the vertical transfer system.

  As the output buffer circuit 330, an exponential horn (Exp-Horn) type inverter circuit is employed. Here, the exponential horn type inverter circuit is characterized in that the driving capability is exponentially increased as the number of cascade (cascade connection) stages is increased. The load interface is used in a system circuit that requires high-speed driving.

  When the horizontal CCD 215 of the CCD solid-state imaging device 210 shown in FIG. 13 is driven by the drive unit 242 of the drive control unit 240, the drive frequency becomes higher than the drive frequency of the vertical CCD 213, and when the number of pixels increases, this further increases. The problem of hot carrier resistance accompanying charging / discharging when driving the horizontal CCD 215 becomes more prominent as the driving speed becomes higher.

  However, by employing the level shift circuit 100 of the first to third embodiments described above, high-speed driving can be performed while improving the problem.

It is a figure which shows the basic structural example of 1st Embodiment of a level shift circuit. It is a figure which shows the 1st modification of 1st Embodiment. It is a figure which shows the 2nd modification of 1st Embodiment. It is a figure which shows the structural example of the conventional level shift circuit as a comparative example. It is a figure explaining operation | movement of the level shift circuit of 1st Embodiment. It is a figure explaining operation | movement of the conventional level shift circuit shown in FIG. 4 as a comparative example. It is a figure which shows the result (when resistance value = 0ohm) which analyzed the operation | movement of the level shift circuit of 1st Embodiment shown in FIG. 1 by simulation. It is a figure which shows the result (when resistance value = 2k (ohm)) which analyzed the operation | movement of the level shift circuit of 1st Embodiment shown in FIG. 1 by simulation. It is a figure which shows the structural example of 2nd Embodiment of a level shift circuit. It is a figure explaining operation | movement of the level shift circuit of 2nd Embodiment. It is a figure which shows the structural example of 3rd Embodiment of a level shift circuit. It is a figure explaining operation | movement of the level shift circuit of 3rd Embodiment. It is the schematic of the solid-state imaging device provided with the drive device using the level shift circuit which drives a CCD solid-state imaging device. It is a block diagram which shows one structural example of a drive part.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 100 ... Level shift circuit, Q101 ... Input stage transistor, Q103 ... Output stage transistor, 105 ... Feedback signal acquisition part, 106 ... Impedance element, R106 ... Resistance element, 107 ... Output node, 108 ... Induction element, 202 ... Solid-state imaging device , 210... CCD solid-state imaging device, 215... Horizontal CCD, 240... Drive control unit (drive device), 241... Timing signal generation unit, 242 ... drive unit, 310 ... preamplifier circuit, 320 ... level shift circuit, 330. circuit

Claims (6)

A pair of input stage transistors in which a pair of differential signals based on a pulse signal output from a signal generation circuit having a first voltage source as a power source is supplied to each control signal input terminal;
One output stage transistor located on the inverting output terminal side of the one input stage transistor and disposed on the second voltage source side;
The other output stage transistor located on the inverting output terminal side of the other input stage transistor and disposed on the second voltage source side;
An impedance element provided between the inverting output terminal of one of the input stage transistors and the inverting output terminal of one of the output stage transistors, the inverting output terminal of the other input stage transistor, and the inversion of the other output stage transistor An impedance element interposed between the output terminal and
A feedback signal based on an output pulse signal obtained at one inverting output terminal of the input stage transistor is supplied to the control signal input terminal of the other output stage transistor, and obtained at the other inverting output terminal of the input stage transistor. A strut connection for supplying a feedback signal based on the output pulse signal to the control signal input terminal of the one output stage transistor;
With
Along with the degree of boosting according to the input / output conditions, the mutual conductance of the one and the other input stage transistors is made larger than the mutual conductance of the one and the other output stage transistors ,
The striking connection is
A signal based on an operating current flowing in the impedance element interposed between the inverting output terminal of the one input stage transistor and the inverting output terminal of the one output stage transistor is a control signal input terminal of the other output stage transistor. One feedback signal acquisition unit to acquire as the feedback signal to be supplied to,
A signal based on an operating current flowing in the impedance element interposed between the inverting output terminal of the other input stage transistor and the inverting output terminal of the other output stage transistor is a control signal input terminal of the one output stage transistor. The other feedback signal acquisition unit to acquire as the feedback signal supplied to
Comprising
The feedback signal acquisition unit
It consists of a series circuit of a plurality of impedance elements,
A level shift circuit that reduces a drain-source voltage of the input stage transistor during a switching operation and constitutes a positive feedback loop by using a signal appearing at a connection point of the plurality of impedance elements as the feedback signal . The level shift circuit according to claim 1, wherein the impedance element is a resistance element. The level according to claim 1, further comprising an inductive element between an inverting output terminal of each input stage transistor and each signal output terminal for outputting an output signal corresponding to the pair of input signals. Shift circuit. A signal generation unit that generates a pulse signal using the first voltage source as a power source;
A differential signal generation unit that converts the pulse signal output from the signal generation unit into a pair of differential signals;
A pair of input stage transistors to which a pair of differential signals output from the differential signal generator are supplied to respective control signal input terminals;
One output stage transistor located on the inverting output terminal side of the one input stage transistor and disposed on the second voltage source side;
The other output stage transistor located on the inverting output terminal side of the other input stage transistor and disposed on the second voltage source side;
An impedance element interposed between the inverting output terminal of one of the input stage transistors and the inverting output terminal of one of the output stage transistors;
An impedance element interposed between the inverting output terminal of the other input stage transistor and the inverting output terminal of the other output stage transistor;
The output pulse signal obtained at the inverting output terminal of one of the input stage transistors is used as a feedback signal supplied to the control signal input terminal of the other output stage transistor, and the output pulse obtained at the inverting output terminal of the other input stage transistor. A striking connection that provides a signal as a feedback signal to be supplied to the control signal input terminal of one of the output stage transistors;
An output for generating a drive pulse signal for driving a load based on a pair of output pulse signals corresponding to the pair of differential signals output from the inverting output terminals of the pair of input stage transistors. A signal generator and
Along with the degree of boosting according to the input / output conditions, the mutual conductance of the one and the other input stage transistors is made larger than the mutual conductance of the one and the other output stage transistors ,
The striking connection is
A signal based on an operating current flowing in the impedance element interposed between the inverting output terminal of the one input stage transistor and the inverting output terminal of the one output stage transistor is a control signal input terminal of the other output stage transistor. One feedback signal acquisition unit to acquire as the feedback signal to be supplied to,
A signal based on an operating current flowing in the impedance element interposed between the inverting output terminal of the other input stage transistor and the inverting output terminal of the other output stage transistor is a control signal input terminal of the one output stage transistor. The other feedback signal acquisition unit to acquire as the feedback signal supplied to
Comprising
The feedback signal acquisition unit
It consists of a series circuit of a plurality of impedance elements,
A drive device that forms a positive feedback loop while reducing a drain-source voltage of the input stage transistor during a switching operation by using a signal appearing at a connection point of the plurality of impedance elements as the feedback signal . The differential signal generation section, as a differential signal of the pair, the at the time of transition differential signal to claim 4 input stage transistor of said pair is for generating a formable signal state turned off simultaneously The drive device described. A plurality of signal charge generation units that respectively acquire signal charges, and a charge transfer path that sequentially transfers the signal charges generated by each of the signal charge generation units to a subsequent stage based on a drive pulse signal supplied to a transfer electrode An imaging unit comprising:
A signal generation unit that generates a pulse signal that is a source of the drive pulse signal using a first voltage source as a power source;
A differential signal generation unit that converts the pulse signal output from the signal generation unit into a pair of differential signals;
A pair of input stage transistors to which a pair of differential signals output from the differential signal generator are supplied to respective control signal input terminals;
One output stage transistor located on the inverting output terminal side of the one input stage transistor and disposed on the second voltage source side;
The other output stage transistor located on the inverting output terminal side of the other input stage transistor and disposed on the second voltage source side;
An impedance element interposed between the inverting output terminal of one of the input stage transistors and the inverting output terminal of one of the output stage transistors;
An impedance element interposed between the inverting output terminal of the other input stage transistor and the inverting output terminal of the other output stage transistor;
The output pulse signal obtained at the inverting output terminal of one of the input stage transistors is used as a feedback signal supplied to the control signal input terminal of the other output stage transistor, and the output pulse obtained at the inverting output terminal of the other input stage transistor. A striking connection that provides a signal as a feedback signal to be supplied to the control signal input terminal of one of the output stage transistors;
A drive pulse signal to be supplied to the transfer electrode is generated based on a pair of output pulse signals corresponding to the pair of differential signals output from the inverting output terminals of the pair of input stage transistors. And an output signal generator that
Along with the degree of boosting according to the input / output conditions, the mutual conductance of the one and the other input stage transistors is made larger than the mutual conductance of the one and the other output stage transistors ,
The striking connection is
A signal based on an operating current flowing in the impedance element interposed between the inverting output terminal of the one input stage transistor and the inverting output terminal of the one output stage transistor is a control signal input terminal of the other output stage transistor. One feedback signal acquisition unit to acquire as the feedback signal to be supplied to,
A signal based on an operating current flowing in the impedance element interposed between the inverting output terminal of the other input stage transistor and the inverting output terminal of the other output stage transistor is a control signal input terminal of the one output stage transistor. The other feedback signal acquisition unit to acquire as the feedback signal supplied to
Comprising
The feedback signal acquisition unit
It consists of a series circuit of a plurality of impedance elements,
An image pickup apparatus that reduces a drain-source voltage of the input stage transistor during a switching operation and constitutes a positive feedback loop by using a signal appearing at a connection point of the plurality of impedance elements as the feedback signal .

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