JP5031256B2 - スーパースカラ処理装置内の指示送出制御 - Google Patents

スーパースカラ処理装置内の指示送出制御 Download PDF

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JP5031256B2
JP5031256B2 JP2006103563A JP2006103563A JP5031256B2 JP 5031256 B2 JP5031256 B2 JP 5031256B2 JP 2006103563 A JP2006103563 A JP 2006103563A JP 2006103563 A JP2006103563 A JP 2006103563A JP 5031256 B2 JP5031256 B2 JP 5031256B2
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execution
program instruction
data
hazard
instruction
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JP2006331399A (ja
JP2006331399A5 (enExample
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デイヴィッド・ジェイムス・ウィリアムソン
グレン・アンドリュー・ハリス
スティーブン・ジョン・ヒル
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アーム・リミテッド
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3826—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
    • G06F9/3828—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage with global bypass, e.g. between pipelines, between clusters
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
JP2006103563A 2005-05-26 2006-04-04 スーパースカラ処理装置内の指示送出制御 Active JP5031256B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/137,792 US7774582B2 (en) 2005-05-26 2005-05-26 Result bypassing to override a data hazard within a superscalar processor
US11/137,792 2005-05-26

Publications (3)

Publication Number Publication Date
JP2006331399A JP2006331399A (ja) 2006-12-07
JP2006331399A5 JP2006331399A5 (enExample) 2011-04-14
JP5031256B2 true JP5031256B2 (ja) 2012-09-19

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JP2006103563A Active JP5031256B2 (ja) 2005-05-26 2006-04-04 スーパースカラ処理装置内の指示送出制御

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US (1) US7774582B2 (enExample)
JP (1) JP5031256B2 (enExample)
CN (1) CN100538627C (enExample)
GB (1) GB2426605B (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8485902B2 (en) 2010-02-26 2013-07-16 Nintendo Co., Ltd. Storage medium storing object controlling program, object controlling apparatus and object controlling method

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US20090055636A1 (en) * 2007-08-22 2009-02-26 Heisig Stephen J Method for generating and applying a model to predict hardware performance hazards in a machine instruction sequence
US8990543B2 (en) * 2008-03-11 2015-03-24 Qualcomm Incorporated System and method for generating and using predicates within a single instruction packet
US7921279B2 (en) * 2008-03-19 2011-04-05 International Business Machines Corporation Operand and result forwarding between differently sized operands in a superscalar processor
US9858077B2 (en) 2012-06-05 2018-01-02 Qualcomm Incorporated Issuing instructions to execution pipelines based on register-associated preferences, and related instruction processing circuits, processor systems, methods, and computer-readable media
JP2014164659A (ja) * 2013-02-27 2014-09-08 Renesas Electronics Corp プロセッサ
US10417152B2 (en) * 2016-06-03 2019-09-17 International Business Machines Corporation Operation of a multi-slice processor implementing datapath steering
CN111736900B (zh) * 2020-08-17 2020-11-27 广东省新一代通信与网络创新研究院 一种并行双通道的cache设计方法和装置
CN114691206A (zh) * 2020-12-29 2022-07-01 上海兆芯集成电路有限公司 执行新增指令的方法及系统
US12379932B2 (en) * 2023-12-22 2025-08-05 Arm Limited Execution of instructions requiring access to an array register

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US5471593A (en) * 1989-12-11 1995-11-28 Branigin; Michael H. Computer processor with an efficient means of executing many instructions simultaneously
US5488729A (en) * 1991-05-15 1996-01-30 Ross Technology, Inc. Central processing unit architecture with symmetric instruction scheduling to achieve multiple instruction launch and execution
KR100309566B1 (ko) * 1992-04-29 2001-12-15 리패치 파이프라인프로세서에서다중명령어를무리짓고,그룹화된명령어를동시에발행하고,그룹화된명령어를실행시키는방법및장치
US6073231A (en) * 1993-10-18 2000-06-06 Via-Cyrix, Inc. Pipelined processor with microcontrol of register translation hardware
US6101597A (en) * 1993-12-30 2000-08-08 Intel Corporation Method and apparatus for maximum throughput scheduling of dependent operations in a pipelined processor
JP3745450B2 (ja) * 1996-05-13 2006-02-15 株式会社ルネサステクノロジ 並列処理プロセッサ
JP3578883B2 (ja) * 1997-01-31 2004-10-20 三菱電機株式会社 データ処理装置
US5958041A (en) * 1997-06-26 1999-09-28 Sun Microsystems, Inc. Latency prediction in a pipelined microarchitecture
JP4006887B2 (ja) 1999-06-03 2007-11-14 松下電器産業株式会社 コンパイラ、プロセッサおよび記録媒体
US6408381B1 (en) * 1999-10-01 2002-06-18 Hitachi, Ltd. Mechanism for fast access to control space in a pipeline processor
US6587940B1 (en) * 2000-01-18 2003-07-01 Hewlett-Packard Development Company Local stall/hazard detect in superscalar, pipelined microprocessor to avoid re-read of register file
ATE529802T1 (de) * 2000-02-09 2011-11-15 Texas Instruments Inc Datenverarbeitungsvorrichtung
EP1199629A1 (en) * 2000-10-17 2002-04-24 STMicroelectronics S.r.l. Processor architecture with variable-stage pipeline
JP2002333978A (ja) * 2001-05-08 2002-11-22 Nec Corp Ｖｌｉｗ型プロセッサ
US7051191B2 (en) * 2001-12-26 2006-05-23 Intel Corporation Resource management using multiply pendent registers
US6944751B2 (en) * 2002-02-11 2005-09-13 Hewlett-Packard Development Company, L.P. Register renaming to reduce bypass and increase apparent physical register size
US7200738B2 (en) * 2002-04-18 2007-04-03 Micron Technology, Inc. Reducing data hazards in pipelined processors to provide high processor utilization
JP3769249B2 (ja) * 2002-06-27 2006-04-19 富士通株式会社 命令処理装置および命令処理方法
US6922760B2 (en) * 2002-12-05 2005-07-26 Lsi Logic Corporation Distributed result system for high-performance wide-issue superscalar processor
WO2004084065A2 (en) * 2003-03-19 2004-09-30 Koninklijke Philips Electronics N.V. Pipelined instruction processor with data bypassing
US7290121B2 (en) * 2003-06-12 2007-10-30 Advanced Micro Devices, Inc. Method and data processor with reduced stalling due to operand dependencies
US20060095732A1 (en) * 2004-08-30 2006-05-04 Tran Thang M Processes, circuits, devices, and systems for scoreboard and other processor improvements
US7409520B2 (en) * 2005-01-25 2008-08-05 International Business Machines Corporation Systems and methods for time division multiplex multithreading
US7454598B2 (en) * 2005-05-16 2008-11-18 Infineon Technologies Ag Controlling out of order execution pipelines issue tagging

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8485902B2 (en) 2010-02-26 2013-07-16 Nintendo Co., Ltd. Storage medium storing object controlling program, object controlling apparatus and object controlling method

Also Published As

Publication number Publication date
CN100538627C (zh) 2009-09-09
GB0606086D0 (en) 2006-05-03
JP2006331399A (ja) 2006-12-07
US7774582B2 (en) 2010-08-10
US20060271768A1 (en) 2006-11-30
GB2426605B (en) 2010-06-30
CN1869920A (zh) 2006-11-29
GB2426605A (en) 2006-11-29

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