JP5008612B2 - Semiconductor integrated circuit and control method thereof - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit and a control method therefor, and more specifically, a full-time core and a part-time core as circuit areas that are independently supplied with power, and a part-time during power supply to the full-time core. The present invention relates to a semiconductor integrated circuit having a standby mode in which power supply to a core is temporarily interrupted to reduce power consumption, for example, a semiconductor integrated circuit used in a microcomputer system.

  In recent years, semiconductor miniaturization processes have evolved to reduce the size of transistors, improving their operating speed, and reducing the power consumption of transistors due to the lower voltage inside semiconductor integrated circuits. However, as the voltage decreases, the power supply voltage approaches the threshold voltage of the transistor, and the leakage current tends to increase when the circuit is stopped. In addition, as the speed of the transistor increases, the clock frequency of the synchronous circuit increases, making it difficult to adjust timing during circuit design. For this reason, a large number of delay buffers for timing adjustment are arranged in the synchronous circuit, and the increase in the leakage current is accelerated by increasing the number of transistors.

  Such a leakage current cannot be ignored in a device that is strongly required to reduce power consumption, such as a mobile phone. Accordingly, there is an increasing need to dynamically turn on / off the power supply to the stopped circuit area in the semiconductor integrated circuit in accordance with the operation state of the device.

  A conventional method for dynamically turning on / off power supply to a semiconductor integrated circuit will be described with reference to FIGS. FIG. 12 is a diagram showing an example of power source separation inside the semiconductor integrated circuit. In this semiconductor integrated circuit, a large number of I / O cells are divided into five I / O cell blocks 101 to 105, and different power supply voltages VDD_B1, VDD_B2, VDD_B3, VDD_B4, and VDD_B5 are supplied thereto. A power supply voltage VDD_C is supplied to the core 120, which is a main circuit area, and is separated from the power supplies of the I / O cell blocks 101 to 105.

  Each of the I / O cell blocks 101 to 105 includes I / O gate circuits 111 to 115 as power source separation elements for the core 120. The I / O gate circuits 111 to 115 are controlled by externally input I / O gate signals G1 to G5, and can fix input / output signals for the core 120 at a predetermined level.

  FIG. 13 shows a detailed configuration of the I / O cell block 101 of FIG. The I / O cell block 101 and the core 120 are supplied with different power supply voltages and are connected via a level shifter LS for converting the voltage level. The I / O cell block 101 is composed of a large number of I / O cells 130. Each I / O cell 130 includes a tri-state buffer 131 for data output, a pull-up transistor 132, a pull-down transistor 133, and an I / O gate circuit 111. The I / O gate circuit 111 can fix the input / output signal to the core 120 at a low level by setting the gate signal G1 to a low level.

  From the core 120 to each I / O cell 130, a pull-up control signal PU for controlling on / off of the pull-up transistor 132, an input / output switching signal EN for controlling on / off of the output buffer 131, and an output from the external terminal T are output. An output data signal DO to be turned on and a pull-down control signal PD for turning on / off the pull-down transistor 133 are output. The input data signal DI input from the external terminal T1 is input from the I / O cell 130 to the core 120.

  When this semiconductor integrated circuit is in an operating state, the signal from the core 120 to the I / O cell block 101 and the signal from the I / O cell block 101 to the core 120 are both propagated by setting the gate signal G1 to the high level. be able to. On the other hand, when the operation inside the semiconductor integrated circuit is temporarily unnecessary and it is desired to cut off the power supply of the core 120, the I / O gate signal G1 is set to a low level, so that the core 120 transmits the I / O cell block 101. Each signal is fixed to a level for setting the I / O cell 130 to an initial state. All signals from the I / O cell block 101 to the core 120 are fixed at a low level. Although the I / O cell block 101 has been described here, the other I / O blocks 102 to 105 are configured in exactly the same manner.

  In this way, the I / O gate signals G1 to G5 are set to the low level, all the input signals from the I / O cell blocks 101 to 105 are fixed to the low level, and the power supply to the core 120 is cut off. Thus, there is no current path flowing from the signal toward the power source in the core 120, and the power source of the core 120 can be safely shut off. Therefore, it is possible to dynamically turn on / off power supply to unnecessary circuit portions in the semiconductor integrated circuit.

  However, when the power supply to the core 120 is cut off, all the external terminals T of the semiconductor integrated circuit are in an initial state, and there is a problem that a terminal state different from the initial state cannot be maintained. That is, there is a problem that the power supply to the core 120 cannot be cut off while the external terminal T is maintained in an arbitrary output state. For example, when a low-active reset signal is supplied from the external terminal T that outputs a low level in the initial state to another semiconductor integrated circuit, the I / O is used to cut off the power supply to the core 120. If the gate circuits 111 to 115 are cut off, a low level signal is output from the external terminal T, and the other semiconductor integrated circuit is reset.

  Therefore, a technique has been proposed in which the level of the output terminal is latched in advance and an arbitrary terminal state is maintained even after the power supply to the core 120 is cut off (for example, Patent Document 1 and Patent Document 2). . If such a semiconductor integrated circuit is used, the output state of the external terminal T while the power supply to the core 120 is shut off can be held in an arbitrary state, and the above problem can be solved.

However, in such a semiconductor integrated circuit, the level of the output terminal can only be fixed while the power supply to the core 120 is shut off, and the terminal setting information of the external terminal T used as the input terminal is held. In addition, there is a problem that the output level of the output terminal cannot be changed. That is, the input / output switching signal EN, the pull-up control signal PU, the pull-down control signal PD, etc. cannot be held so as to function as input terminals while the power to the core 120 is shut off. Further, there is a problem in that the logic circuit cannot be operated based on the input level to the input terminal and the output level of the output terminal cannot be changed while the power to the core 120 is shut off. For example, when an interrupt signal INT1 is input from another peripheral circuit to the external terminal T for interrupt reception, an interrupt signal INT is generated in consideration of mask setting and polarity setting for the interrupt signal INT1, and an interrupt output is generated. The operation of outputting from the external terminal T to the microcomputer cannot be performed.
JP 2003-215214 A JP 2005-197478 A

  The present invention has been made in view of the above circumstances, and is a semiconductor capable of performing input / output operations even in a standby mode in which power supply to a part of a circuit area is cut off to reduce power consumption. An object is to provide an integrated circuit. In particular, it is an object to provide a semiconductor integrated circuit capable of generating an output signal corresponding to an input signal during a standby mode.

  It is another object of the present invention to provide a semiconductor integrated circuit in which an input / output operation in the standby mode is determined when shifting to the standby mode.

  It is another object of the present invention to provide a semiconductor integrated circuit capable of safely performing transition and return to standby mode, that is, power shutdown and power on to a part of a circuit area.

  It is another object of the present invention to provide a semiconductor integrated circuit capable of restoring the contents of a register included in a part of a circuit area to a state before shifting to the standby mode when returning from the standby mode.

  Another object of the present invention is to reduce the number of terminals of the semiconductor integrated circuit.

  A semiconductor integrated circuit according to a first aspect of the present invention includes a full-time core and a part-time core as circuit regions that are independently supplied with power, and a large number of external terminals for performing external input and external output. A semiconductor integrated circuit capable of temporarily interrupting power supply to the part-time core during power supply to the time core, wherein the part-time core includes a synchronization circuit including a plurality of registers. In addition, the full-time core fixes and shuts off the input / output signal to the part-time core at a predetermined level based on a core gate signal input from the outside, and from the synchronization circuit via the core gate circuit A combination circuit of a latch circuit for selectively passing and holding an input signal based on a latch signal to which an output signal is input and externally input, and a logic element, the first signal being externally input and the latch And an asynchronous circuit that generates a second signal output externally based on the output signal of the circuit.

  With such a configuration, by controlling the core gate circuit from the outside using the core gate signal, the input / output signals for the part-time core of the full-time core can be fixed at a predetermined level. Therefore, it is possible to safely turn on and off the power to the part-time core while supplying power to the full-time core.

  In addition, by controlling the latch circuit from the outside using the latch signal, the signal input from the synchronous circuit to the asynchronous circuit is retained even in the standby mode where the power supply to the part-time core is shut off. I can keep it. Moreover, the asynchronous circuit generates the second signal based on the first signal input from the outside and the output signal of the latch circuit. For this reason, even in the standby mode, the operation of generating the second signal according to the first signal can be performed, and this operation is determined according to the output signal of the synchronization circuit immediately before the transition to the standby mode. be able to. Therefore, a desired operation for generating the second signal from the first signal can be performed during the standby mode. That is, even in the standby mode, it is possible to maintain a minimum function as viewed from the outside.

  A semiconductor integrated circuit according to a second aspect of the present invention includes, in addition to the above configuration, an I / O cell block as a circuit region that is independently supplied with power, and the I / O cell block includes the full time core and the full time core. An I / O cell for connecting an external terminal is provided, and the I / O cell fixes an input / output signal between the full-time core and the external terminal at a predetermined level based on an I / O gate signal input from the outside. And a first I / O gate circuit that shuts off.

  With such a configuration, the input / output signals for the full-time core of the I / O cell block can be fixed at a predetermined level by controlling the core gate circuit from the outside using the core gate signal. Accordingly, it is possible to safely turn on and shut off the power to the full-time core while supplying power to the I / O cell block.

  In a semiconductor integrated circuit according to a third aspect of the present invention, in addition to the above configuration, the I / O cell block includes an I / O cell that connects the part-time core and the external terminal. And a second I / O gate circuit for blocking an input / output signal between the part-time core and the external terminal at a predetermined level based on the core gate signal.

  With such a configuration, the core gate circuit and the second I / O gate circuit can be controlled using the same core gate signal. Therefore, there is no need to prepare matching signal external terminals for each of the core gate circuit and the second I / O gate circuit, and the number of external terminals of the semiconductor integrated circuit can be reduced.

  In a semiconductor integrated circuit according to a fourth aspect of the present invention, in addition to the above configuration, the first signal and the second signal are input / output from the external terminal via the I / O cell, and the first signal is input. The input / output direction of the I / O cell is controlled based on the output control signal generated by the synchronization circuit, and the output control signal is input to the I / O cell via the core gate circuit and the latch circuit. The

  With such a configuration, even in a bidirectional I / O cell whose input / output direction is controlled by the output control signal from the synchronization circuit, the latch circuit holds this output control signal so that it is in the standby mode. Even so, the input / output direction can be controlled. Therefore, the first signal can be input via the I / O.

  In the semiconductor integrated circuit according to the fifth aspect of the present invention, in addition to the above configuration, a reset signal for resetting the register is sent to the part-time core via the core gate circuit or the second I / O gate circuit. A write signal and a read signal for the register are input from the external terminal to the part-time core via the core gate circuit or the second I / O gate circuit. The data read from the register is output to the external terminal via the core gate circuit or the second I / O gate circuit without interposing the latch circuit.

  With such a configuration, when returning from the standby mode, before switching the latch circuit from the holding state to the passing state, the register in the synchronization circuit can be reset, and desired data can be written and read. For this reason, for example, since the state before the transition to the standby mode is restored and the latch circuit can be switched to the passing state, the return from the standby mode can be performed safely and easily.

  In the semiconductor integrated circuit according to a sixth aspect of the present invention, in addition to the above configuration, the part-time core has a power supply voltage lower than that of the I / O cell block, and the core gate signal is passed through a level shifter that performs voltage conversion. The I / O cell block is configured to be output to the part time core.

  With such a configuration, the core gate circuit and the second I / O gate circuit can be controlled using the same core gate signal even when the power supply voltages of the part-time core and the I / O cell block are different. .

  A control method for a semiconductor integrated circuit according to a seventh aspect of the present invention is a control method for initializing the semiconductor integrated circuit, the core gate circuit, the first I / O gate circuit, and the second I / O gate. Maintaining the circuit in a cut-off state, passing through the latch circuit, and maintaining the register in a reset state, starting power supply to the full-time core and I / O cell block, and the full-time core and I / O After stabilization of the power supply voltage of the O cell block, the step of switching the first I / O gate circuit from the cut-off state to the passing state, and the power supply to the part-time core is started after the conduction of the I / O gate circuit And after the power supply voltage of the part-time core is stabilized, whether the core gate circuit and the second I / O gate circuit are in a cut-off state. A step of switching each to pass state, after conducting the Koageto circuit and the second I / O gate circuit, and a step for releasing the reset state. With such a configuration, it is possible to safely power on the semiconductor integrated circuit.

  A semiconductor integrated circuit control method according to an eighth aspect of the present invention is a control method for shifting a semiconductor integrated circuit to a standby mode in which power supply to the part-time core is cut off. A step of switching the latch circuit from a passing state to a holding state during power supply to the core and the I / O cell block; and after the switching of the latch circuit to the holding state, the core gate circuit and the second I / O gate Switching from a passing state to a cut-off state, and a step of cutting off power supply to the part-time core after the core gate circuit and the second I / O gate circuit are cut off. With such a configuration, it is possible to safely shift to the standby state and to perform a desired operation after shifting to the standby state.

  A control method for a semiconductor integrated circuit according to a ninth aspect of the present invention is a control method for returning the semiconductor integrated circuit from the standby mode in addition to the above-described configuration, and includes a step of starting power supply to the part-time core; Switching the core gate circuit and the second I / O gate circuit from a cut-off state to a passing state after stabilizing the power supply voltage of the part-time core and maintaining the register in a reset state; and After the circuit and the second I / O gate circuit are turned on, writing to and reading from the register to return the register to a state immediately before the transition to the standby mode; And switching the latch circuit from the holding state to the passing state. With such a configuration, it is possible to return from the standby state safely and easily.

  According to the present invention, it is possible to provide a semiconductor integrated circuit capable of performing an input / output operation even in a standby mode in which power supply to a part of a circuit region is interrupted to reduce power consumption. In particular, a semiconductor integrated circuit capable of generating an output signal corresponding to an input signal during the standby mode can be provided.

  Further, it is possible to provide a semiconductor integrated circuit in which an input / output operation in the standby mode is determined at the time of transition to the standby mode.

  Further, it is possible to provide a semiconductor integrated circuit that can safely perform the transition and return of the standby mode, that is, the power cutoff and power on to a part of the circuit area.

  In addition, it is possible to provide a semiconductor integrated circuit that can restore the contents of the registers included in a part of the circuit area to the state before the transition to the standby mode when returning from the standby mode.

  In addition, the number of terminals of the semiconductor integrated circuit can be reduced.

Embodiment 1 FIG.
FIG. 1 is a diagram showing a schematic configuration example of a semiconductor integrated circuit according to Embodiment 1 of the present invention, and shows a layout on a semiconductor chip. This semiconductor integrated circuit is formed on a semiconductor chip made of a thin silicon single crystal, and is used in a state of being enclosed in a package in which external terminals are exposed.

[I / O cell blocks 101 to 105]
A large number of I / O cells are arranged on the periphery of the rectangular semiconductor chip. These I / O cells are divided into five I / O cell blocks 101 to 105, and the power source is separated. . Each of the I / O cell blocks 101 to 105 is supplied with power supply voltages VDD_B1, VDD_B2, VDD_B3, VDD_B4, and VDD_B5, and can be individually turned on / off. The power supply voltage is selected according to the devices constituting the I / O cell blocks 101-105. For example, VDD_B1 = 1.8V, VDD_B2 = 3.0V, VDD_B3 = VDD_B4 = VDD_B5 = 2.6V. In this embodiment, although divided into five I / O cell blocks 101 to 105, if the power supply voltage is the same, it can be divided into one I / O cell block without being divided, and further divided. You can also increase the number.

[Core 121, 122]
The core, which is a main circuit area other than the I / O cell, is divided into a full-time core 121 and a part-time core 122, and the power source is separated. The power supply voltages VDD_C1 and VDD_C2 are supplied to the cores 121 and 122, respectively, and can be turned on / off individually. In recent years, with the miniaturization of semiconductor processes, the power supply voltage of the core has been reduced, and is generally lower than the supply voltage to the I / O cell. For example, VDD_C1 = VDD_C2 = 1.2V can be set. In this embodiment, the core is separated into two cores. However, the number of divisions may be further increased so that the power supply can be independently turned on / off by further dividing functionally.

[I / O gate circuits 111 to 116]
Each I / O cell block 101-105 is provided with I / O gate circuits 111-116 as power source separation elements, and input / output signals to / from the full-time core 121 and the part-time core 122 are input to the I / O gate circuit 111. Are input / output via .about.116. The I / O gate circuits 111 to 115 are controlled by I / O gate signals G1 to G5 inputted from the outside, respectively. The I / O gate circuit 116 is controlled by a core gate signal G6 input from the outside. These I / O gate circuits 111 to 116 pass signals if the I / O gate signals G1 to G5 or the core gate signal Gc are at a high level, and input / output signals to the core 122 if they are at a low level. Can be fixed to level.

  In this embodiment, if the I / O gate signals G1 to G5 and the core gate signal Gc are at a low level, the output signals to the I / O cell side and the core side are both fixed at a low level, and the I / O cell Even if the power is supplied to the blocks 101 to 105 and the power supply to the full-time core 121 or the part-time core 122 is cut off, the current is prevented from flowing from the signal line to the circuit area where the power is cut off. Latch-up and the like are prevented from occurring by preventing a voltage higher than the power supply voltage in the circuit area inside from being applied.

  The I / O gate circuits 111 to 116 are arranged in the I / O cell blocks 101 to 105 and are operated by the power supply of the I / O cell blocks 101 to 105. Therefore, the I / O gate signals G1 to G5 and the core gate signal Gc are signals corresponding to the power supply voltages VDD_B1, VDD_B2, VDD_B3, VDD_B4, and VDD_B5 of the I / O cell blocks 101 to 105 to which the respective I / O gate signals G1 to G5 are input. Yes. When the power supply to each I / O cell block 101-105 is turned on / off independently, it is necessary to externally input the I / O gate signals G1-G5 as individual control signals. In the embodiment, on / off control of different power supply voltages VDD_B1, VDD_B3, and VDD_B4 is performed collectively.

  The I / O gate signal G1 input at the level of VDD_B1 is converted to the level of VDD_B4 in the level shifter LS between the I / O cell blocks 101 and 104, and becomes the I / O gate signal G4. Further, the I / O gate signal G4 is converted to the level of VDD_B3 in the level shifter LS between the I / O cell blocks 103 and 104, and becomes the I / O gate signal G3. Therefore, it is possible to control the three I / O gate circuits 111, 113, and 114 using one gate signal G1 input from the outside. On the other hand, the power supply voltages VDD_B2 and VDD_B5 are controlled on / off independently and are externally input as independent I / O gate signals G2 and G5, respectively.

  In the present embodiment, the I / O gate signal for the I / O cell block that is collectively turned on / off is created using the level shifter LS inside the chip, thereby inputting the I / O gate signal. However, it goes without saying that each may be configured to input from the external terminal. Also, even if the I / O gate signal for the I / O cell block that is independently controlled on / off can be generated inside the chip based on another I / O gate signal, The other I / O gate signal can be used after level conversion. For example, the VDD_B1 level gate signal G1 may be level-converted to generate the VDD_B2 level gate signal B2 or the VDD_B5 level gate signal B5 inside the chip. This is desirable because all the I / O gate signals can be controlled from the outside by controlling only one power level signal.

[Core gate circuit 151]
The full-time core 121 is provided with a core gate circuit 151 as a power source separation element, and input / output signals for the part-time core 122 are input / output through the core gate circuit 151. The core gate signal Gcc for controlling the core gate circuit 151 is input from the external terminal to the I / O cell block 101 as the core gate signal Gc, and is input to the full-time core 121 via the level shifter LS. The control signals of the core gate circuit 151 and the I / O gate circuit 116 may be externally input as individual signals, but the number of external terminals is reduced by using the same core gate signal Gc as in this embodiment. can do.

  The core gate circuit 151 passes the signal if the core gate signal Gcc is at a high level, and fixes the input / output signal for the part time core 122 at a predetermined signal level if the core gate signal Gcc is at a low level. As a result, even if the power of the part-time core 122 is cut off while the power is supplied to the full-time core 121, the current is prevented from flowing into the part-time core 122 being cut off via the signal line. A voltage higher than the power supply voltage VDD_C2 of the part-time core 122 being cut off is not applied to prevent the occurrence of latch-up or the like.

  Note that the part-time core 122 may be further separated into a plurality of core portions. In that case, the separated part-time cores 122 may be connected via a core gate circuit. Further, as control signals for these core gate circuits, signals from registers arranged in the full-time core 121 or other part-time cores 122 can be used.

[Write-back terminal]
The input / output signals between the part-time core 122 and the I / O cell blocks 101 to 105 are not all input / output via the full-time core 121. That is, some of the input / output signals between the part time core 122 and the I / O cell blocks 101 to 105 are transferred between the part time core 122 and the I / O cell blocks 101 to 105 without interposing the full time core 121. Direct input / output.

  The I / O cell block 101 includes an I / O cell connected to the full time core 121 and an I / O cell connected to the part time core 122. On the other hand, in the I / O cell blocks 103 and 104, all I / O cells are connected to the full-time core 121, and in the I / O cell blocks 102 and 105, all I / O cells are connected to the part-time core 122. Has been.

  As described above, the I / O cell block 101 includes the two I / O gate circuits 111 and 116, and the I / O gate circuit 111 is based on the I / O gate signal G1. The I / O gate circuit 116 blocks the input / output signal for the part-time core 122 based on the core gate signal Gc.

[Detailed Configuration of I / O Cell 130]
FIG. 2 is a circuit diagram showing a configuration example of the I / O cell block 101 and the full-time core 121 of FIG. A large number of I / O cells 130 are arranged in the I / O cell block 101, but for convenience of explanation, only two I / O cells 130 connected to the full-time core 121 and the part-time core 122, respectively. Is illustrated.

  The I / O cell 130 is connected to the external terminal T by wire bonding or flip chip connection by bumps, and is electrically connected to the outside of the package. Each I / O cell 130 includes a tri-state buffer 131 that drives an external output, a pull-up Pch transistor 132, and a pull-down Nch transistor 133, and a terminal control signal PU, for controlling the I / O cell 130, DO, EN, and PD are input from the cores 121 and 122, and the input data signal DI is output to the cores 121 and 122.

  When the input / output switching signal EN is at a low level, the output terminal of the tri-state buffer 131 becomes high impedance and enters an input state. On the other hand, when the input / output switching signal EN is at a high level, the output data signal DO is output from the output terminal of the tri-state buffer 131. Is output. When the pull-up control signal PU is at a low level, the Pch transistor 132 is turned on and a pull-up resistor is added to the external terminal T. On the other hand, when the pull-up control signal PU is at a high level, the Pch transistor 132 is turned on and pulled from the external terminal T. The up resistor is disconnected. When the pull-down control signal PD is at a high level, the Nch transistor 133 is turned on and a pull-down resistor is added to the external terminal T. On the other hand, when the pull-down control signal PD is at a low level, the Nch transistor 133 is turned on and a pull-down resistor is connected from the external terminal T. Disconnected. An input signal from the external terminal is output to the cores 121 and 122 as an input data signal DI.

[Detailed Configuration of I / O Gate Circuits 111 and 116]
The I / O cell 130 connected to the full-time core 121 includes an I / O gate circuit 111, and the I / O cell 130 connected to the part-time core 122 includes an I / O gate circuit 116. Yes.

  The I / O gate circuits 111 and 116 are constituted by a plurality of AND elements 134. Input and output signals for the full-time core 121 are input to one input terminal of these AND elements 134, and the other input terminal is connected in common. In the case of the I / O gate circuit 111, the I / O gate signal G1 is input to the other input terminal, and the logical product of each input / output signal and the I / O gate signal G1 is obtained. In the case of the I / O gate circuit 116, the core gate signal Gc is input to the other input terminal, and the logical product of each input / output signal and the I / O gate signal Gc is obtained.

  That is, when the I / O gate signal G1 is at a low level, all the input / output signals for the full-time core 121 are fixed at a predetermined level, in this example, at a low level. On the other hand, when the I / O gate signal G1 is set to the high level, the input / output signal for the full-time core 121 can be passed as it is. Similarly, when the core gate signal Gc is at a low level, all the input / output signals for the part-time core 122 are fixed to a predetermined level, in this example, the low level, while when the core gate signal Gc is set to a high level, the part time Input / output signals for the core 122 can be passed as they are.

  Thus, by setting the gate signals G1 and Gc to the low level, the output signals of the I / O gate circuits 111 and 116 are fixed to the initial values, and the external terminal T is set to the initial state (Gate state). it can. In the example shown in FIG. 2, since the initial values of the terminal control signals PU, EN and PD are all at a low level, the initial state of the external terminal T is an input pull-up state.

  In order to change the initial state of the external terminal T, the logic of the AND element 134 to which the terminal control signals PU, EN, PD, and DO are input may be changed to change the initial value of each signal. For example, if each initial value is PU = High and EN = PD = Low, the initial state of the external terminal T is an input high impedance state. If each initial value is PU = High, EN = Low, PD = High, the initial state of the external terminal T is an input pull-down state, and if PU = EN = High, PD = Low, DO = Low, The initial state of the external terminal T is a low level output state. If PU = EN = High, PD = Low, and DO = High, the initial state of the external terminal T is a high level output state.

  If the gate signals G1 and Gc are set to a low level, the input data signal DI output to the cores 121 and 122 can be fixed to a low level. For this reason, all of the input signals from the I / O cell block 101 can be set to a low level while the power supply to the cores 121 and 122 is shut off, and the I / O cell block 101 passes through the signal line to the cores 121 and 122. Current can be prevented from flowing, and power supply to the cores 121 and 122 can be safely shut off. In addition, the AND element 134 in the gate circuits 111 and 116 has a structure in which no through current flows even when the input level is in a floating state, and the power supply to the cores 121 and 122 is cut off. Even if the input signals to the gate circuits 111 and 116 are in a floating state, no abnormal current flows through the AND element 134.

[Level Shifter LS]
A level shifter LS is disposed between the I / O cell block 101 and the cores 121 and 122, and performs voltage conversion of signals across both. The I / O cells 130 having the I / O gate circuit 111 are arranged adjacent to each other in the I / O cell block 101, and the I / O gate signal G1 is sequentially connected to these I / O cells 130. Yes. The I / O cells 130 having the I / O gate circuit 116 are also arranged adjacent to each other, and the core gate signal Gc is sequentially connected to these I / O cells 130. The core gate signal Gc is voltage-converted by the level shifter LS and input to the full-time core 121 as the core gate signal Gcc. The latch signal L is also voltage-converted by the level shifter LS and input to the full time core 121.

[Core gate circuit 151]
An I / O cell 130 having an I / O gate circuit 111 is connected to a part-time core 122 through a full-time core 121. An output signal from the part time core is output to the I / O cell block 101 as a terminal control signal PU, EN, PD via the core gate circuit 151 and the latch circuit 152 in the full time core 121. On the other hand, the input data signal DI from the I / O cell block 101 is output to the part time core 122 via the core gate circuit 151 in the full time core 121.

  The core gate circuit 151 includes a plurality of AND elements 153 in the same manner as the I / O gate circuit. Input and output signals for the part-time core 122 are input to one input terminal of these AND elements 153, and the other input terminal is commonly connected. The other terminal is connected to a signal Gcc obtained by voltage-converting the core gate signal Gc, and the logical product of each input / output signal and the core gate signal Gc is obtained.

  That is, when the core gate signal Gc is at a low level, all input / output signals for the part-time core 122 are fixed at a predetermined level, in this example, at a low level. On the other hand, when the core gate signal Gc is set to the high level, the input / output signal for the part-time core 122 can be passed as it is. As in the case of the I / O gate circuit 111, the initial value (STBY value) of the output signal from the part-time core 122 can be changed by changing the logic of the AND element 153. Therefore, the initial state of the external terminal T when the I / O gate circuit 111 is in the passing state can be determined.

[Latch circuit 152]
The terminal control signals PU, EN, PD, and DO are generated by the part time core 122 and output to the full time core 121 and the I / O cell blocks 101 to 105. The part-time core 122 has a large number of registers therein, and performs a predetermined operation based on these registers to generate a terminal control signal. The terminal control signal output from the part time core 122 to the full time core 121 is input to the latch circuit 152 via the core gate circuit 151.

  The latch circuit 152 includes a plurality of latch elements 154. Each latch element 154 can select the passage and holding of the input signal to the input terminal D based on the gate signal input to the gate terminal G. That is, if the gate signal is high level, the input signal of the input terminal D is output as it is from the output terminal Q (passing state), and if the gate signal is low level, the input signal at the fall of the gate signal is held. Then, this input signal is output from the output terminal Q (latch state).

  These latch elements 154 have gate terminals G connected in common and receive a latch control signal Lc. The latch control signal Lc is a latch signal L that is voltage-converted by the level shifter LS and further inverted in logic. Therefore, if the latch signal L is at a low level, the latch control signal Lc is at a high level, and the output signal from the part-time core 122 that has passed through the core gate circuit 151 passes through the latch circuit 152 as it is. On the other hand, if the latch signal L is at a high level, the latch control signal Lc is at a low level, and a past output signal held by the latch circuit 152 is output.

  By using the latch signal L, the terminal control signals PU, EN, PD, and DO generated by the part-time core 122 are held in the latch circuit 152, so that the input / output direction of the external terminal T, the output level, and the pull-up resistor are turned on. Terminal states such as ON / OFF and pull-down resistor ON / OFF can be maintained. In such a holding state, if the core gate circuit 151 is cut off using the core gate signal Gc, the power supply to the part-time core 122 can be cut off while the terminal state of the external terminal T is held.

Embodiment 2. FIG.
In the first embodiment, the example in which the full-time core 121 includes the core gate circuit 151 and the latch circuit 152 has been described. In contrast, in the present embodiment, a case will be described in which full-time core 121 further includes a logic circuit that generates a terminal control signal for I / O cell 130.

  FIG. 3 is an explanatory diagram showing a configuration example of the main part of the semiconductor integrated circuit according to the second embodiment of the present invention. The layout on the semiconductor chip is the same as that in FIG. 1, and the main parts of the I / O cell blocks 101 and 105, the full-time core 121 and the part-time core 122 are shown. This diagram is a conceptual diagram for explaining the basic configuration and operation, and components not directly related to the explanation are omitted.

  The I / O cell block 101 has a large number of I / O cells 130. Among these I / O cells 130, the I / O cell 130 to which the I / O gate signal G 1 is input is connected to the full-time core 121. On the other hand, the I / O cell 130 to which the core gate signal Gc is input is connected to the part time core 122. The I / O cell block 105 also has a large number of I / O cells 130. The I / O gate signal G5 is input to these I / O cells 130 and is connected to the part-time core 122. Has been.

[Synchronization circuit 161]
The part time core 122 includes a synchronization circuit 161 that operates in synchronization with a clock signal. The clock signal is input from the external terminal T. Further, the synchronization circuit 161 has a large number of registers 163 and operates based on data held by these registers 163 to generate an output signal. This output signal is output to full-time core 121 and I / O cell blocks 101-105.

  The synchronization circuit 161 can be reset from the outside of the semiconductor integrated circuit by externally inputting a reset signal RST. Further, data can be written to the register 163 in the synchronization circuit 161 by externally inputting a write signal and write data. Furthermore, data can be read from the register 163 in the synchronization circuit 161 by externally inputting a read signal. Each of these signals may be input via any of the I / O cell blocks 101-105. Further, when input is made via the I / O cell block 101, it may be inputted to the part-time core 122 via the full-time core 121.

  On the other hand, read data read from the register 163 is output to an external terminal without the latch circuit 152 interposed. In other words, the data is output to the external terminal via any of the I / O cell blocks 101 to 105, and may further be output via the full-time core 121, but is output without passing through the latch circuit 152 in the full-time core 121. For this reason, if the I / O gate circuits 111 to 116 and the core gate circuit 151 through which each signal passes are set to the passing state, the synchronization circuit 161 is reset even if the latch circuit 152 is in the holding state. Data writing and data reading can be performed. In particular, by enabling register reading while maintaining the latch circuit 152 in the holding state, the internal state of the synchronization circuit 161 can be confirmed in the procedure for returning from the standby mode, and the return from the standby mode can be performed quickly. Can be done.

[Asynchronous circuit 162]
The full time core 121 includes a core gate circuit 151, a latch circuit 152, and an asynchronous circuit 162. The asynchronous circuit 162 is an example of a logic circuit, and is a combinational circuit including two or more logic elements. The asynchronous circuit 162 receives the signal s1 from the synchronization circuit 161 and the signal s2 from the external terminal T1, and outputs the signal s3. ing. The input signal s1 is generated by the synchronous circuit 161, input to the full-time core 121, and then input to the asynchronous circuit 162 via the core gate circuit 151 and the latch circuit 152. On the other hand, the input signal s <b> 2 is input from the external terminal T <b> 1 to the I / O cell block 101 and then input to the asynchronous circuit 162 in the full-time core 121. On the other hand, the signal s3 generated by the asynchronous circuit 162 is output to the external terminal T2 via the I / O cell block 101.

  That is, the asynchronous circuit 162 generates an externally output signal s3 based on the signal s1 generated by the synchronous circuit 161 and the externally input signal s2. For this reason, when power is supplied to the part-time core 122, various operations for performing an external output in accordance with the external input can be realized under the control of the synchronization circuit 161.

  In addition to this, even in the standby mode in which no power is supplied to the part-time core 122, external output can be performed according to the external input. Since the signal s2 of the asynchronous circuit 162 is input to the asynchronous circuit via the latch circuit 152 in the full-time core 121, the data held in the latch circuit 152 becomes the signal s2 even during the standby mode. Is input to the asynchronous circuit 162. For this reason, a complicated operation cannot be performed as in the case of supplying power to the part-time core 122, but an external output can be performed according to an external input.

  Further, the operation is not determined only by the configuration of the asynchronous circuit 162, but can be designated or selected by the asynchronous circuit 162 when the standby mode is shifted. Therefore, even during the standby mode, a minimum function can be maintained from the outside.

  Further, the asynchronous circuit 162 can be realized with a smaller number of gates and has less leakage current than the synchronous circuit. For this reason, the circuit scale is not significantly increased. Further, it can be realized without significantly increasing the power consumption.

  Note that, in this embodiment, a case has been described in which each of the signals s1 and s2 input to the asynchronous circuit 162 is one and the signal s3 output from the asynchronous circuit 162 is one, but both are two or more. It goes without saying that it can be done. Further, although it is desirable that the full-time core 121 does not include a synchronization circuit, a part of the synchronization circuit may be included.

Embodiment 3 FIG.
In this embodiment, a case where a through interrupt function, a selector function, and a level shifter function are realized by using the asynchronous circuit 162 in the full-time core 121 will be described.

  FIG. 4 is a diagram showing a configuration example of a main part of the semiconductor integrated circuit according to the third embodiment of the present invention. This semiconductor integrated circuit realizes a through interrupt function, a selector function, and a level shifter function that can be operated even when the power to the part-time core 122 is shut off. The through interrupt is a function of outputting an interrupt signal input from an external terminal from another external terminal based on the mask setting and polarity inversion setting held therein. For example, it is used when one interrupt signal is generated based on two or more interrupt signals.

[Through interrupt]
The external terminal T2a is an output terminal for the interrupt signal INT, and an initial value (I / O gate state) during the interruption of the I / O gate circuit 111 is a low level output state. The part time core 122 generates a high active interrupt signal INT0. The interrupt signal INT0 is inverted in polarity based on the value POL of the output polarity setting register and output from the external terminal T2a. Here, if the output polarity setting POL is at a low level, the high active interrupt signal INT0 is output as it is from the external terminal T2a as the interrupt signal INT. On the other hand, if the output polarity setting is at a high level, the signal INT0 is inverted by the EXOR gate and is output from the external terminal T2a as a low active interrupt signal INT.

  An interrupt signal INT1 is input to the external terminal T1a. Therefore, if the low-level input / output switching signal EN is input to the I / O cell 130 of the external terminal T1a, the external terminal T1a can be used as an input terminal. In this case, the input signal of the external terminal T 1 a is input to the full time core 121 as the input data signal DI of the I / O cell 130. The input data signal DI is further input to the part time core 122 and is also transmitted to the external terminal T2a via the asynchronous circuit 162 in the full time core 121.

  Whether the interrupt signal INT1 is high active or low active is specified by the polarity setting POL1 from the part time core 122. If the polarity setting POL1 is at a low level, the interrupt signal INT1 is high active, and therefore passes through the EXOR gate as it is. On the other hand, if the polarity setting POL1 is at a high level, the interrupt signal INT1 is low active and is inverted at the EXOR gate.

  Whether to mask the interrupt signal INT1 is specified by the mask setting MSK1 from the part-time core 122. If the mask setting MSK1 is at a low level, the interrupt signal INT1 is masked, and is interrupted by an AND gate that calculates a logical product with the mask setting MSK1. On the other hand, if the mask setting MSK1 is at a high level, the interrupt signal INT1 is permitted and can pass through the element AND gate. The interrupt signal INT1 passing through the AND gate is bundled with other interrupt signals in the OR gate and transmitted to the external terminal T2a.

  Similarly, the interrupt signal INT2 is input to the external terminal T1b. For this reason, a low-level input / output switching signal EN is input to the I / O cell 130 so that the external terminal T1b becomes an input terminal. Therefore, the input signal of the external terminal T 1 b is input to the full time core 121 as the input data signal DI of the I / O cell 130. The input data signal DI is further input to the part time core 122 and is also transmitted to the external terminal T2a via the asynchronous circuit 162 in the full time core 121.

  Whether the interrupt signal INT2 is high active or low active is specified by the polarity setting POL2 from the part time core 122. If the polarity setting POL2 is at a low level, the interrupt signal INT2 is high active, and therefore passes through the EXOR gate as it is. On the other hand, if the polarity setting POL2 is at a high level, the interrupt signal INT2 is inactive at the low level, and is inverted in the EXOR gate.

  Whether to mask the interrupt signal INT2 is specified by the mask setting MSK2 from the part-time core 122. If the mask setting MSK2 is at a low level, the interrupt signal INT2 is masked and interrupted by an AND gate that calculates a logical product with the mask setting MSK2. On the other hand, if the mask setting MSK2 is at a high level, the interrupt signal INT2 is permitted and can pass through the element AND gate. The interrupt signal INT2 that has passed through the AND gate is bundled with other interrupt signals in the OR gate and transmitted to the external terminal T2a.

  With such a configuration, even when the part-time core 122 is in an operating state or in a state where only the full-time core 121 is operating with the power supply to the part-time core 122 cut off, the polarity setting POL1, POL2 and mask Considering the settings MSK1 and MSK2, the interrupt signals INT1 and INT2 input to the external terminals T1a and T1b can be transmitted to the external terminal T2a and output as the interrupt signal INT.

[Selector level shifter]
Further, the output signal of the selector is input to the I / O cell 130 of the external terminal T1a as the output data signal DO. Therefore, when a high-level input / output switching signal EN is input to the I / O cell 130, the external terminal T1a can be used as an output terminal, and the output signal of the selector can be output to the external terminal T1a.

  Which of the four input signals the selector selects as an output signal is designated by 2-bit select signals SEL1 and SEL2 output from the part-time core 122. If the select signals SEL1, SEL2 are “00”, the output signal from the part time core 122 is selected. If “01”, the input data signal DI of the I / O cell 130 of the external terminal T1b is selected, and if “10” and “11”, input signals from other external terminals not shown are respectively selected. The

  With such a configuration, even when the part-time core 122 is in an operating state, or when only the full-time core 121 is operating with the power supply to the part-time core 122 being cut off, the I / O cell 130 is turned on. By latching the output switching signal EN and the select signals SEL1 and SEL2, an input signal from another input terminal can be selected and transmitted as an output signal, and can function as a selector.

  Further, the signal input to the selector is an input signal from an external terminal of another I / O cell block, and is transmitted across the I / O cell blocks having different power supply voltages connected via the level shifter. If it is a signal, the voltage of an input signal and an output signal can be varied, and it can function as a level shifter from the outside.

Embodiment 4 FIG.
In the present embodiment, a case where an address decoder is realized using the asynchronous circuit 162 in the full-time core 121 will be described.

  FIG. 5 is a diagram showing a configuration example of the main part of the semiconductor integrated circuit according to the fourth embodiment of the present invention. This semiconductor integrated circuit realizes an address decoder that can be operated even when the power to the part-time core 122 is shut off.

[Address decoder]
The external terminal T1c is an input terminal to which the chip select signal CS is input, and is in an input state when the I / O gate circuit 111 of the corresponding I / O cell 130 is cut off. The chip select input signal CS is a low active signal for activating the semiconductor integrated circuit from the outside.

  If both CS setting 1 and CS setting 2 output from the part time core 122 are at a low level, the chip select input signal CS input to the external terminal T1c is directly transmitted to the part time core 122 as an internal CS signal. The On the other hand, if both CS setting 1 and CS setting 2 are at a high level, the two selectors in full-time core 121 both select the “1” side. As a result, according to the chip select input signal CS and the address signal input to the external terminals T1c and T1d, the internal CS input to the part time core 122 and the chip select output signal CS output from the external terminal T2b are generated.

  FIG. 6 is a display showing an example of the operation when both CS setting 1 and CS setting 2 are at a high level. If the address input signal is “0” and the chip select input signal CS is active (= 0), the internal CS signal is active (= 0) and the chip select output signal CS is inactive (= 1). When the address input signal is “1” and the chip select input signal CS becomes active (= 0), the internal CS signal is made inactive (= 1), and the chip select output signal CS is made active (= 0).

  That is, if an upper address signal is input to the external terminal T1d for address input, one CS address space is divided into two, and the internal CS space of this semiconductor integrated circuit and the chip select output signal CS are input. It can be divided into CS spaces of other semiconductor integrated circuits. In addition, the address decoder function allows the latch circuit 152 to latch CS setting 1 and CS setting 2 regardless of whether the part time core of the semiconductor integrated circuit is in an operating state or the part time core is in a power-off state. By doing so, it can be operated.

Embodiment 5 FIG.
FIG. 7 is a block diagram showing an example of a microcomputer system including a semiconductor integrated circuit according to the fifth embodiment of the present invention.

  The microcomputer system includes a microcomputer chip 200, a plurality of power supply circuits 201, a semiconductor integrated circuit 202 according to this embodiment, a memory 203, an LCD 204, a camera 205, and a memory card 206. The microcomputer chip 200 includes a CPU (Central Processing Unit) 210, a general-purpose port 211, an interrupt controller 212, and a memory I / F 213, which are connected to each other via an internal bus.

  The general-purpose port 211 performs on / off control of seven power supply circuits. These power supply circuits supply power independently of each other, and supply power supply voltages VDD_B1 to VDD_B5, VDD_C1, and VDD_C2 corresponding to the I / O cell blocks 101 to 105, the full-time core 121, and the part-time core 122, respectively. Supply. Note that power supplies that are simultaneously turned on / off can be controlled by the same general-purpose port. The general-purpose port 211 outputs I / O gate signals G1, G2, and G5, a core gate signal Gc, a latch signal L, and a reset signal RST that are input to the semiconductor integrated circuit 202.

  The interrupt controller 212 receives and processes the interrupt signal INT output to the semiconductor integrated circuit 202. When the interrupt signal INT becomes active, the CPU 210 executes an interrupt process. In addition, a memory bus is connected to the memory I / F 213, and a memory 203 is connected to the memory bus, and a bus I / F of the semiconductor integrated circuit 202 is also connected to the memory I / F 213. Writing to and reading from the register 163 and the like are performed via this memory bus.

  Further, an LCD 204, a camera 205, and a memory card 206 as peripheral devices are connected to the semiconductor integrated circuit 202. These peripheral devices are examples, and various peripheral devices can be connected to the semiconductor integrated circuit 202.

  In this embodiment, the memory bus and the reset signal are connected to the external terminal T corresponding to the I / O cell block 101 in the semiconductor integrated circuit 202, and the I / O cell is not passed through the full-time core 121. It is assumed that input / output is performed between the block 101 and the part time core 122.

  8 to 10 are timing charts showing respective signals of the semiconductor integrated circuit 202 according to the fifth embodiment of the present invention, for explaining the procedure for controlling the semiconductor integrated circuit 202 on the microcomputer system of FIG. FIG. VDD_B1, VDD_B2, VDD_B5, VDD_C1, and VDD_C2 in the figure are power supplies to the I / O cell blocks 101, 102, and 105, the full-time core 121, and the part-time core 122, respectively. RST is a reset signal, G1, G2, and G5 are I / O gate signals of the I / O gate circuits 111, 112, and 115, Gc is a core gate signal, and L is a latch signal. “B1 → C1” is an input signal from the I / O cell block 101 to the full time core 121, “C1 → B1” is an output signal from the full time core 121 to the I / O cell block 101, and “C1 → C2”. "Is an input signal from the full-time core 121 to the part-time core 122.

[Initialization procedure]
The I / O cell blocks 102 and 105 to which VDD_B2 and VDD_B5 are supplied are not connected to the full-time core 121. Further, VDD_B5 is controlled to be turned on / off simultaneously with VDD_B1, VDD_B3, and VDD_B4, and VDD_B2 is controlled independently and is turned on only when the part-time core 122 is in an operating state.

  First, all external terminals are at a low level before the power supply to the semiconductor integrated circuit is turned on. From this state, the I / O power supplies VDD_B1, VDD_B3, VDD_B4 and VDD_B5 and the full-time core power supply VDD_CORE1 are turned on, and after the power supply voltage is stabilized, the I / O gate signal G1 is changed from the low level to the high level.

  At this time, the I / O cell 130 side of the I / O gate circuit 111 changes the initial state of the terminal determined by the cutoff state of the core gate circuit 151 from the initial state of the terminal determined by the cutoff state of the I / O gate circuit 111 (Gate state). Transition to (STBY state). The full time core 121 side of the I / O gate circuit 111 changes from a low fixed state to a state in which the input data signal DI is input to the full time core 121. The full time core 121 side of the core gate circuit 151 of the full time core 121 remains in the STBY state, and the part time core 122 side of the core gate circuit 151 remains in the low fixed state.

  Thereafter, the part-time core 122 is powered on, and after the power supply voltage is stabilized, the I / O gate signal G5 and the core gate signal Gc are changed from the low level to the high level. At this time, since both the I / O gate circuit 111 and the core gate circuit 151 are in the passing state, and the part-time core 122 is in the reset state, all the external terminals T are in the initial state (Reset state) determined by the reset state of the part-time core 122 ) During this time, the power can be safely turned on without going through an abnormal current or an abnormal state of the terminal. Thereafter, the reset signal RST is changed from the low level to the high level, and the operation of the part time core 122 is started.

  When using the external terminal T of the I / O cell block 102, after the operation of the part-time core 122 is started, the VDD_B2 is turned on, and after the power supply voltage is stabilized, the gate signal G2 is changed from the low level to the high level. The I / O gate circuit 112 is set in the passing state, and the operation of the external terminal T of the I / O cell block 102 is started. Thereafter, when the operation of these external terminals T becomes unnecessary, the gate signal G2 is lowered to a low level to turn off the I / O gate circuit 112, and then the VDD_B2 power supply is cut off.

[Standby procedure]
When the operation of the part time core 122 which is a main circuit part is temporarily unnecessary, the power source of the part time core 122 can be cut off in order to reduce the leakage current. After the operation of the circuit of the part time core 122 is stopped and the state of the external terminal T is set to a desired state, the latch signal L is changed from the low level to the high level. Thereby, the terminal control signal is held in the latch circuit 152 in the full-time core 121, and the current terminal state can be held thereafter. The latch circuit 152 not only fixes the output level of the external terminal T but also holds terminal setting information of the external terminal T, that is, the pull-up control signal PU, the input / output switching signal EN, and the pull-down control signal PD. Furthermore, setting information associated with the terminal control information of the external terminal T input to the logic circuit in the full-time core 121, for example, a mask setting for a through interrupt is held.

  Thereafter, the reset signal RST is changed from the high level to the low level. At this time, the part-time core 122 is in a reset state, but since the terminal control signal is held by the latch circuit 152, the terminal state is held immediately before the latch signal L is raised.

  Thereafter, the core gate signal Gc and the I / O gate signal G5 are changed from the high level to the low level, the entire outside of the part time core 122 is fixed by the gate circuit, and the part time core power supply VDD_CORE2 is shut off. At this time, the power of the part-time core 122 is lost, but the terminal state is held immediately before the latch signal is raised based on the state held by the latch circuit 152 in the full-time core 121. It remains. During this time, it is possible to safely enter the standby state without passing through an abnormal current or an abnormal state of the terminal.

[Standby recovery procedure]
In order to operate the part-time core 122 from the standby state, the part-time core power supply VDD_CORE2 is first turned on, and after the power supply voltage is stabilized, the I / O gate signal G5 and the core gate signal Gc are changed from the low level to the high level. . The reset signal RST is directly transmitted from the I / O cell block 101 to the part time core 122 without interposing the full time core 121. Here, the reset signal RST is raised to release the reset of the part time core 122. Further, the signal group of the memory bus is also directly transmitted from the I / O cell block 101 to the part-time core 122 by raising the core gate signal Gc without interposing the full-time core 121. Writing to and reading from the registers of the part-time core 122 can be performed from the memory bus.

  Before the latch signal L is lowered, the terminal related information is written back to the state immediately before the standby state is input via the memory bus. These register set values to be written back are not stored in the semiconductor integrated circuit 202. For this reason, it is stored in advance in the memory 203 or the like in the microcomputer system. When all the terminal control information is written back to the state immediately before it was put into standby last time, the latch signal L is lowered and the latch circuit 152 is made to pass. At this time, the terminal state depends on the circuit state of the part-time core 122, but is the same state as immediately before the standby state is last entered, and the terminal state is continuously returned from the standby state.

  Here, the external terminal necessary for writing back the terminal control signal into the part-time core 122 in the latched state is configured not to interpose the full-time core, and the reset signal and the memory bus signal are used. The signal group is not limited to such a case, and any signal group necessary for writing back the setting information may be used. For example, when register setting is performed by serial communication, the serial communication related terminal does not interpose the full-time core 121. , It may be transmitted to the part-time core 122.

[Power-off procedure]
When the power supply of the entire semiconductor integrated circuit 202 is cut off in the operation state of the part time core 122, the reset signal RST is first lowered to reset the operation of the part time core 122, and the I / O gate signal G5 and the core gate signal Gc are reset. And the entire outside of the part-time core 122 is fixed by the gate circuit, and the part-time core power supply VDD_CORE2 is shut off. Next, the I / O gate signal G1 is lowered, the I / O gate circuit 111 of the I / O cell block 101 is fixed, the full-time core power supply VDD_CORE1 is shut off, and the I / O power supplies VDD_B1, VDD_B3, VDD_B4 , Shut off VDD_B5 and shut off all power. During this time, the power supply can be safely shut off without going through an abnormal current or an abnormal state of the terminal.

[Through interrupt handling procedure]
FIG. 11 is a flowchart showing the control procedure of the through interrupt. It is assumed that the functions of the general-purpose port are multiplexed at all the input terminals of the through interrupt signal INT1. To enable the through interrupt, first, the input terminal of the interrupt signal INT1 is set to the input state, that is, the input / output switching signal EN is set to the low level, the through interrupt polarity setting POL1 is appropriately set, and the mask is set. Set the setting MSK1 to the permitted side. At this time, when an active level is input from a desired interrupt input terminal, an interrupt is transmitted to the interrupt output terminal regardless of whether the part-time core 122 is in an operating state or in a standby state.

  When shifting to the standby mode, the contents of all the registers 163 and the like in the part-time core 122 are erased by turning off the power. For this reason, it is stored in advance in the memory 203 on the microcomputer system. In particular, the polarity setting POL1 and POL2 of the through interrupt, the mask settings MSK1 and MSK2, the register setting of the multiplexed general-purpose port, and the switching setting are stored if the terminal has a terminal function switching function.

  When an interrupt from the semiconductor integrated circuit 202 of the present embodiment is generated in the CPU 210 of the microcomputer system, first, whether or not it is in a standby state is managed by software control. The register indicating the interrupt factor in the part-time core 122 is read, and interrupt processing is performed according to the contents. If any of the interrupt factors is not flagged, it is determined as a through interrupt and through interrupt processing is performed. Alternatively, if it is currently in a standby state, through interrupt processing is performed after the part-time core 122 is started in the standby return procedure.

  In the through interrupt process, first, the external terminal to which the through interrupt signal INT1 is input is switched to the general-purpose port input, the level of the through interrupt signal INT1 is held in the register, and then the register of the general-purpose port is read, thereby enabling the through interrupt. Get the input status to the external terminal. Depending on the polarity setting POL1 and mask setting MSK1 of the through interrupt stored in advance and the terminal input state read now, the mask setting MSK1 is enabled, the polarity setting POL1 is high active, and the terminal input state is high. If there is, it is determined that a high active interrupt at the corresponding terminal has occurred, and the interrupt processing is performed. If the mask setting MSK1 is enabled, the polarity setting POL1 is low active, and the terminal input state is low level, it is determined that a low active interrupt has occurred for the corresponding terminal, and the interrupt processing is performed.

  If no interrupt factor is detected, it is determined that chattering has occurred at the through interrupt input terminal. In other words, an active level interrupt input occurred, but the interrupt input terminal state changed to the reverse level during the standby recovery procedure, etc., and it was determined from the general-purpose port input register that the terminal input state was not at the active level. Judge that In this case, if chattering, the interrupt process is terminated without expecting that an interrupt will occur again.

  In the semiconductor integrated circuit according to the above embodiment, the I / O gate signals 111 to 115 are externally controlled using the I / O gate signals G1 to G5 and the core gate signal Gc, thereby turning on the power to the semiconductor integrated circuit. And can be safely shut off. In addition, by controlling the I / O gate circuit 116 and the core gate circuit 151 from the outside using the core gate signal Gc, the power supply to the part-time core 122 is interrupted and restarted during the power supply to the full-time core 121. Can be done safely.

  Further, by controlling the latch circuit 152 from the outside using the latch signal L, the terminal control signals EN, PU, DO, and PD of the external terminal T can be held and maintained in the control state even during the standby mode. it can. In particular, the control state of the external terminal T used as the input terminal can be maintained. Further, an asynchronous circuit 162 is provided in the full-time core 121, and a signal input to the asynchronous circuit 162, for example, setting information of the input / output terminal peripheral circuit can be held. For this reason, even in the standby mode, the minimum operating state seen from the outside can be maintained. Further, by using the reset signal RST, the write signal to the register 163, the write data, and the read signal, the internal state of the part-time core 122 can be changed to a desired state before returning from the standby mode. Therefore, the return from the standby mode can be performed safely and easily.

  In addition, the terminal control signal output from the part-time core 122 initialized by the reset signal RST at the time of initial activation is simultaneously set in the latch circuit 152 and is initialized in the procedure for setting the operation state, so that the terminal can be safely and The power can be turned on as a continuous state.

  Further, the power to the part-time core can be shut off while maintaining the minimum operating state seen from the outside by the procedure for shifting to the standby state.

  Further, by the procedure for returning from the standby state, it is possible to return from the standby state safely and with the terminal state being continued.

  In addition, by converting a plurality of I / O gate signals G1, G3, and G4 into common and inputting them from the outside, I / O cell blocks that operate with a plurality of power supply voltages are individually connected to I / O cell blocks. It is not necessary to prepare the / O gate signal, and an increase in the number of terminals can be prevented.

  Further, the core gate signal Gc for controlling the I / O gate circuit 116 in the I / O cell block 101 is voltage-converted in the level shifter LS and used as the gate signal for the core gate circuit 151 in the full-time core 121. Therefore, the I / O gate circuit 116 that separates the I / O cell block 101 and the part-time core 122 and the core gate circuit 151 that separates the full-time core 121 and the part-time core 122 are controlled by a single external input. And increase in the number of terminals can be prevented.

  Further, the asynchronous circuit 162 is provided in the full-time core 121. The asynchronous circuit 162 can operate even when power is supplied to the part-time core 122 or when the power is cut off. The output signal of the latch circuit 152 and the external terminal T It operates based on the input signal from. For this reason, the logic circuit that realizes the function of linking the input terminal and the output terminal can be operated even when the power of the part-time core is shut off, and the terminal control information of these external terminals and the setting information of the logic circuit Can also be held together.

  Further, a selector that selects and outputs either an input signal from the external terminal T or an output signal from the part time core 122, a latch circuit 152 that latches signal selection information instructing signal selection by the selector, and an output By providing the full-time core 121 with a latch circuit 152 that latches signal inversion information indicating whether to invert the signal level, the part-time core 122 may be in an operating state or in a power-off state. The input state of the external terminal T can be selectively transmitted to the output state of another external terminal T. Further, when these external terminals T are connected to different I / O cell blocks 101 to 105 connected through the level shifter LS, the semiconductor integrated circuit can be used as a level shifter.

  Further, based on the address signal and chip select signal input from the external terminal T, the address decoder for generating a new chip select signal, and the part time core 122 and the output signal of the address decoder are selected and output. And a latch circuit 152 for latching signal selection information for instructing signal selection by the selector are provided in the full-time core, so that a new one can be obtained regardless of whether the part-time core 122 is in an operating state or a power-off state. A chip select signal can be output to the external terminal T, and can always be used as a chip select for another semiconductor integrated circuit.

  Even when the part-time core 122 is in an operating state or a power-off state, a plurality of interrupt signals generated by other semiconductor integrated circuits can be bundled and transmitted to the microcomputer unit as an interrupt.

  Further, it is possible to provide a microcomputer system that can normally process an interrupt that is transmitted regardless of whether the part-time core is in an operating state or a power-off state.

  In this embodiment, the part-time core is a single core block. However, the power consumption can be further optimized by further dividing the part-time core into a plurality of part-time cores and shutting off the power for each operation function. .

  In the above embodiment, an example in which the terminal control signal of the external terminal T is the pull-up control signal PU, the input / output switching signal EN, the pull-down control signal PD, and the output data DO has been described. A drive capability switching signal, a Schmitt trigger input function on / off control signal, a pull-up resistance or pull-down resistance value switching signal, and the like can also be included.

  In the above embodiment, an example in which the I / O cell is a digital CMOS input / output terminal has been described. However, the present invention is also applicable to a semiconductor integrated circuit including an analog buffer. For example, if an oscillation buffer for crystal oscillation or CR oscillation is included, the oscillation on / off setting or the like can be used as the terminal control signal. If a differential output buffer is included, a signal for controlling setting of differential amplitude and differential offset voltage, ON / OFF of the differential buffer, and the like can be used as a terminal control signal. If a differential input buffer is included, a signal for controlling setting of a differential input threshold voltage, ON / OFF of the differential buffer, and the like can be used as a terminal control signal. If an analog voltage input / output buffer is included, the path may be cut by a pass transistor instead of the I / O gate circuit.

  In the above embodiment, only the combinational circuit is taken as an example of the logic circuit built in the full-time core 121. However, a sequential circuit that requires a clock may be built in. However, in order to reduce the leakage current of the full-time core 121, it is effective to reduce the circuit scale of the full-time core 121, that is, the number of transistors as much as possible. In recent years, a sequential circuit designed synchronously is built in the full-time core 121. Then, since the clock tree, the gate for adjusting the timing of the path, and the like are included in the full-time core 121, it is necessary to pay attention to the scale of the full-time core 121.

  In the above embodiment, the full-time core 121 and the part-time core 122 are cores that operate at the same voltage level, but may operate at different power supply voltages. Increasing the core voltage increases the operating current, but the leakage current tends to decrease. Therefore, the full-time core 121 supplies a higher voltage, and the leakage current can be further reduced as compared with the part-time core 122. Further, if the full-time core 121 is designed to operate with the power supply voltage of the I / O cell blocks 101 to 105, it can be designed with a circuit using a higher voltage transistor, and the leakage current can be further reduced. .

  In the above embodiment, the I / O gate signals G1 to G5, the core gate signal Gc, and the latch signal L are all input terminal signals from the outside. However, these are used as the full-time core 121 and the I / O cell block 101. If the serial communication or the like is used for the control from the microcomputer chip, the number of terminals can be further reduced.

  In the above embodiment, an example in which the power supply circuit is placed outside and the output on / off control is performed by the general-purpose port of the microcomputer is described. However, the power supply circuit itself is the semiconductor of this embodiment. You may arrange | position inside an integrated circuit. In addition, a pass transistor that can control whether or not to supply power from the power supply circuit may be incorporated in the semiconductor integrated circuit according to the above embodiment. In these cases, on / off control of power supply can be controlled not by a general-purpose port but by serial communication.

1 is a diagram illustrating a schematic configuration example of a semiconductor integrated circuit according to a first embodiment of the present invention. FIG. 2 is a circuit diagram illustrating a configuration example of an I / O cell block 101 and a full-time core 121 in FIG. 1. It is explanatory drawing which showed one structural example about the principal part of the semiconductor integrated circuit by Embodiment 2 of this invention. It is the figure which showed one structural example about the principal part of the semiconductor integrated circuit by Embodiment 3 of this invention. It is the figure which showed one structural example about the principal part of the semiconductor integrated circuit by Embodiment 4 of this invention. It is the display which showed an example of the operation | movement when both CS setting 1 and CS setting 2 are high level. It is the block diagram which showed an example of the microcomputer system containing the semiconductor integrated circuit by Embodiment 5 of this invention. 10 is a timing chart showing signals of a semiconductor integrated circuit 202 according to a fifth embodiment of the present invention. 10 is a timing chart showing signals of a semiconductor integrated circuit 202 according to a fifth embodiment of the present invention. 10 is a timing chart showing signals of a semiconductor integrated circuit 202 according to a fifth embodiment of the present invention. It is the flowchart which showed the control procedure of through interruption. It is the figure which showed an example of the power supply isolation | separation in the conventional semiconductor integrated circuit. A detailed configuration of the I / O cell block 101 of FIG. 12 is shown.

Explanation of symbols

101-106 I / O cell block 111-116 I / O gate circuit 101-105 I / O cell block 111-115 Gate circuit 121 Full time core 122 Part time core 130 I / O cell 131 Output buffer 132 Pull-up transistor 133 Pull-down transistor 134 AND element LS Level shifter 151 Core gate circuit 152 Latch circuit 153 AND element 154 Latch element 161 Synchronous circuit 162 Asynchronous circuit 163 Register 200 Microcomputer chip 201 Power supply circuit 202 Semiconductor integrated circuit 203 Memory 211 General-purpose port 212 Interrupt controllers B1 to B5 Gate signal CS Chip select signal DI Input data signal DO Output data signal EN Input / output switching signal PD Pull-down control signal PU Pull-up control signal G1-G5 I / O gate signal Gc, Gcc Core gate signal L Latch signal Lc Latch control signal LS Level shifter POL1, POL2 Polarity setting MSK1, MSK2 Mask setting RST Reset signal SEL1, SEL2 Select signal RST Reset signal T, T1, T1a to T1d , T2, T2a, T2b External terminals
VDD_B1 to VDD_B5 I / O cell block power supply voltage
VDD_C1 Full-time core power supply voltage
VDD_C2 Part time core power supply voltage

Claims (9)

A full-time core and a part-time core as circuit areas to be independently supplied with power, and a plurality of external terminals for external input and output, and the part-time during the power supply to the full-time core In a semiconductor integrated circuit capable of temporarily interrupting power supply to the core,
The part-time core has a synchronization circuit including a large number of registers,
The full-time core is based on a core gate signal input from the outside, and a core gate circuit that fixes and shuts off an input / output signal for the part-time core at a predetermined level;
A latch circuit that receives an output signal from the synchronization circuit via the core gate circuit and selectively passes and holds the input signal based on an externally input latch signal;
A semiconductor integrated circuit comprising a combination circuit of logic elements and an asynchronous circuit that generates a second signal output externally based on a first signal input externally and an output signal from the latch circuit circuit. An I / O cell block as a circuit area that is independently supplied with power,
The I / O cell block has an I / O cell that connects the full-time core and the external terminal,
The I / O cell includes a first I / O gate circuit that blocks an input / output signal between the full-time core and an external terminal at a predetermined level based on an input I / O gate signal. The semiconductor integrated circuit according to claim 1, comprising: The I / O cell block has an I / O cell that connects the part-time core and the external terminal,
The I / O cell includes a second I / O gate circuit that blocks an input / output signal between the part-time core and the external terminal at a predetermined level based on the core gate signal. The semiconductor integrated circuit according to claim 2. The first signal and the second signal are input / output from the external terminal via the I / O cell,
The input / output direction of the I / O cell to which the first signal is input is controlled based on the output control signal generated by the synchronization circuit,
3. The semiconductor integrated circuit according to claim 2, wherein the output control signal is input to the I / O cell via the core gate circuit and the latch circuit. A reset signal for resetting the register is input from the external terminal to the part-time core via the core gate circuit or the second I / O gate circuit.
A write signal and a read signal for the register are input from the external terminal to the part-time core via the core gate circuit or the second I / O gate circuit,
The data read from the register is output to the external terminal via the core gate circuit or the second I / O gate circuit without interposing the latch circuit. 2. The semiconductor integrated circuit according to 2 or 3. The part-time core has a lower power supply voltage than the I / O cell block,
4. The semiconductor integrated circuit according to claim 3, wherein the core gate signal is output from the I / O cell block to the part-time core through a level shifter that performs voltage conversion. A control method for initializing a semiconductor integrated circuit according to claim 5, comprising:
Maintaining the core gate circuit, the first I / O gate circuit and the second I / O gate circuit in a cut-off state, passing through the latch circuit, and maintaining the register in a reset state;
Starting power supply to the full-time core and I / O cell block;
After the power supply voltage of the full-time core and the I / O cell block is stabilized, switching the first I / O gate circuit from a cut-off state to a pass state;
Starting power supply to the part-time core after conduction of the I / O gate circuit;
Switching the core gate circuit and the second I / O gate circuit from a cut-off state to a passing state after stabilization of the power supply voltage of the part-time core, and
A method for controlling a semiconductor integrated circuit, comprising: releasing the reset state after the core gate circuit and the second I / O gate circuit are turned on. A control method for shifting the semiconductor integrated circuit according to claim 5 to a standby mode in which power supply to the part-time core is interrupted,
Switching the latch circuit from a passing state to a holding state during power supply to the full-time core, part-time core, and I / O cell block;
Switching the core gate circuit and the second I / O gate from a passing state to a blocking state after switching to the holding state of the latch circuit;
And a step of shutting off power supply to the part-time core after the core gate circuit and the second I / O gate circuit are shut off. A control method for returning a semiconductor integrated circuit from the standby mode,
Starting power supply to the part-time core;
Switching the core gate circuit and the second I / O gate circuit from a cut-off state to a passing state after stabilizing the power supply voltage of the part-time core and maintaining the register in a reset state;
After the core gate circuit and the second I / O gate circuit are turned on, writing to and reading from the register to return the register to the state immediately before the transition to the standby mode;
9. The method of controlling a semiconductor integrated circuit according to claim 8, further comprising a step of switching the latch circuit from a holding state to a passing state after the register is restored.

Images