JP4883621B2 - Semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly, to a configuration of a scan path for saving stored information and facilitating a test when an information holding element such as a sequential circuit arranged in a data path together with a combinational circuit is turned off. For example, the present invention relates to a technique useful when applied to a system LSI or a microprocessor for portable devices.

  In recent years, as a result of the advancement of high integration by miniaturization of semiconductor manufacturing processes, it is possible to provide a system-on-a-chip (SoC) in which most of the system is integrated on one LSI (semiconductor integrated circuit). Became. On the other hand, due to the miniaturization of this process, the leakage current of a single transistor has been increasing as represented by the subthreshold leakage current, and the leakage current of the entire SoC chip has become very large. In order to reduce this leakage current, an on-chip power cutoff technique (Patent Document 1) is known. When such a power shut-off mechanism is mounted inside the SoC, in order to use the power shut-off mechanism efficiently, it is important to quickly return from the power shut-off state. It is desirable to prevent the state of the internal logic circuit from being lost when the power is shut off. As a fast recovery technology from power shutdown, there are known technologies (Patent Document 2 and Patent Document 3) that hold a stored data in a state holding element (flip-flop or latch) inside a logic circuit even when the power is shut off. Patent Document 2 discloses a flip-flop in which an operation power supply of a master latch unit is cut off in a low power consumption mode, and only a slave latch unit increases the voltage level of the operation power supply to hold an information signal while reducing a leakage current. There is a description. Patent Document 3 describes a nonvolatile master-slave flip-flop that includes a master-slave latch unit that can be powered off and a save latch that retains stored information of the slave latch unit and is not shut off when the power is turned off. Patent Document 4 includes an observation flip-flop that holds an input to the power shut-off block and an output from the power shut-off block at the time of power shut-off. There is a description about making it possible to confirm whether or not the control is normal.

Japanese Patent Laid-Open No. 2003-92359 JP 2000-244287 A JP 2005-167184 A JP 2003-98223 A

  As described in the background art, in the future SoC, on-chip power cut-off is indispensable, and high-speed recovery from the power cut-off state is desired. However, it is indispensable to provide a scan latch that constitutes a scan path for inputting / outputting necessary data to / from a sequential circuit constituting a logic circuit for the purpose of facilitating device testing. If a state-holding element (such as a flip-flop or a latch) that can hold data even when the power is shut down is also provided, the chip-occupying area by the state-holding element will be significantly increased, so that it can be virtually on-chip. The problem is that the logical scale is limited.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit having a small circuit scale required for holding data for a scan latch and holding data when the power is turned off.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  [1] A semiconductor integrated circuit according to the present invention has a circuit block (CKB) in which supply of power can be selectively cut off. The circuit block includes a plurality of data holding elements (DRPL) arranged in the middle of the signal path (RPASS) and the test path (TPASS). The data holding element is a first latch circuit (ML) that receives and latches data in synchronization with a clock, which is targeted for power supply cutoff, and a second latch circuit (non-target for power supply cutoff) that latches data statically. SL) and a transfer circuit (DT) for selectively connecting the storage nodes (nd1, nd2) of the first latch circuit and the storage nodes (nd3, nd4) of the second latch circuit so as to be able to transfer data. The semiconductor integrated circuit receives data input from the test path through the first latch circuit, the transfer circuit, and the second latch circuit, and is input from the signal path. A second operation mode for propagating data to the signal path through the first latch circuit; and a second operation mode for saving data stored in the first latch circuit to the second latch circuit through the transfer circuit when power supply is cut off. A third operation mode and a fourth operation mode in which stored data of the second latch circuit is returned to the first latch circuit through the transfer circuit when the supply of power is resumed.

  According to the semiconductor integrated circuit, the test data is sequentially sent to the plurality of data holding elements arranged in the test path in the first operation mode via the first latch circuit and the second latch circuit, or held by the first latch circuit. Data can be retrieved. In short, a plurality of first latch circuits and second latch circuits connected in series can be used as scan paths for ease of testing. Compared to the second operation mode used for actual operation, in the first operation mode, data propagation can be controlled in master / slave operation using the first latch circuit and second latch circuit for one data holding element. Therefore, the transfer clock used in the first operation mode does not need to be highly accurate with respect to the synchronous clock used in the second operation mode. The second latch circuit is used as a latch circuit for configuring a scan path, and also serves as a latch circuit for saving the stored information of the first latch circuit when the power is cut off. At the same time, it is possible to reduce the circuit scale required for data retention when the power is shut off. In order to check whether the logic of the manufactured semiconductor integrated circuit operates as designed, the test ease configuration by the scan path is evaluated by inputting operation data into the actual semiconductor integrated circuit and actually operating the program. For this reason, it is an indispensable function at present, and in the present situation that there is a high demand for adding a storage mechanism for saving and restoring the state at the time of power-off in a short time, the data holding element by the above means should be adopted. Is effective in reducing area overhead.

  As one specific form of the present invention, the first latch circuit includes a data input terminal (D) connected upstream of the signal path, a test data input terminal (SI) connected upstream of the test path, and a clock. A clock input terminal (CK) for inputting a signal, and an input gate (TG1) for inputting data from the data input terminal or the test data input terminal in response to a first state of the clock signal input from the clock input terminal The first static latch (INV1, CINV1) that latches data input from the input gate in response to the second state of the clock signal input from the clock input terminal, and stored data of the first static latch A data output terminal (Q) for outputting downstream of the signal path is provided. The second latch circuit includes a second static latch and a test output terminal (SO) for outputting stored information of the second static latch downstream of the test path.

  [2] As one form of power shutoff of the circuit block, for example, the circuit block has a ground switch (PSW1) used to shut off the supply of operating power between the ground terminal of the semiconductor integrated circuit. When the power supply is shut off with the ground switch turned off, the virtual ground inside the circuit block connected to the ground switch becomes floating, and the internal node of the circuit block tends to converge to the power supply voltage due to the leakage current.

  At this time, it is preferable that the first state of the clock signal is at a low level, and the period of the first state is shorter than the period of the second state of the clock signal. When the power is turned on again, when the retained data of the second latch circuit is returned to the first latch circuit in the fourth operation mode, an undesired signal is first input to the first latch circuit via the input gate. It is necessary that the saved data is not destroyed by being input to the latch circuit. Since the internal node of the circuit block in the power shut-off state has converged to the power supply voltage, that is, the high level, this state is at the time of turning on the power and acts to cut off or put the input gate into the high impedance state and return. It works to suppress unwanted corruption of data. Further, by making the period of the first state shorter than the period of the second state of the clock signal, input data in the latch operation by the first latch circuit using the one-phase clock signal input from the clock input terminal. Can be made difficult to occur.

  The transfer circuit includes, for example, a pair of n-channel transfer MOS transistors (MN1, MN2) disposed between a complementary storage node of the first latch circuit and a complementary storage node of the second latch circuit, A pair of p-channel charge MOS transistors (MP4, MP4) whose drains are coupled to the complementary storage nodes of the first latch circuit and whose gates are respectively cross-coupled to the complementary storage nodes of the second latch circuit across the transfer MOS transistor. MP5) and a first switch MOS transistor (MP3) for selectively connecting the sources of the pair of charge MOS transistors to a power supply terminal. In the third operation mode, the transfer MOS transistor is controlled to be on and the first switch MOS transistor is controlled to be off. In the fourth operation mode, the transfer MOS transistor is controlled to be in an off state and the first switch MOS transistor is controlled to be in an on state. A characteristic configuration of the transfer circuit is a drive mechanism for the complementary storage node of the first latch circuit for restoring the saved data in the fourth operation mode. If a transfer MOS transistor is used in the same way as for saving in recovery, it is easy to drive the complementary storage node of the first latch circuit charged to the power supply voltage to the complementary level in the second latch circuit in the power-off state. On the contrary, the inverted data may be restored. On the other hand, in the case of using the above drive mechanism, the transfer MOS transistor is cut off in the return operation in the fourth operation mode, so the saved data held by the second latch circuit is not destroyed, and One charge MOS transistor is driven in accordance with the value of the saved data to maintain the high level for the storage node on the high level side of the first latch circuit. Since the internal node has converged to the high level of the power supply voltage in the power cutoff state, it does not require a large driving capability to maintain it at the high level. As the power is turned on again and the ground potential is supplied to the floating virtual ground, the storage node to be set to the low level is discharged toward the ground potential. Since the high level is maintained for the storage node on the high level side of the first latch circuit, the potential difference from the storage node to be set to the low level gradually increases, and the first latch circuit is the second latch circuit. The stored data can be received accurately.

  In the first operation mode, the gate input signal of the transfer MOS transistor is a non-overlapping clock with respect to the clock signal supplied to the clock input terminal. In short, in the first operation mode, the first latch circuit and the second latch circuit perform a master / slave latch operation.

  The second static latch includes, for example, a pair of CMOS inverters (INV3 and INV4) connected in reverse parallel and a second switch MOS transistor that can selectively cut off the power supply to the p-channel MOS transistor of the CMOS inverter. (MP1, MP2). The second switch MOS transistor is switch-controlled in the opposite phase to the transfer MOS transistor. Thus, in the save operation in the third operation mode, the second latch circuit performs only the discharge on the low level side when the data held in the first latch circuit is supplied during the ON period of the transfer MOS transistor. Since the complementary level of the storage node of the static latch is realized, a through current due to the transient response of the CMOS inverter is not generated, which contributes to low power consumption. Since the power is supplied from the second switch MOS transistor to the second static latch together with the transfer MOS transistor being turned off, the saved data can be held as it is.

  [3] As another form of the power cut-off form of the circuit block, the circuit block has a power switch (PSW2) used to cut off the supply of operating power between the power terminal of the semiconductor integrated circuit. When the power switch is turned off and the power is shut off, the virtual power supply wiring inside the circuit block connected to the power switch becomes floating, and the internal node of the circuit block tends to converge to the ground potential due to the leak current. At this time, it is preferable that the first state of the clock signal is at a high level and the period of the first state is shorter than the period of the second state of the clock signal. If the polarity is reversed with respect to the above means for blocking the ground side, the same effect can be obtained for the same reason.

  The transfer circuit includes a pair of n-channel transfer MOS transistors (MN3 and MN4) disposed between a complementary storage node of the first latch circuit and a complementary storage node of the second latch circuit, and the first A pair of n-channel discharge MOS transistors (MN6, MN7) whose drains are coupled to the complementary storage nodes of the latch circuit and whose gates are cross-coupled to the complementary storage nodes of the second latch circuit, respectively, across the transfer MOS transistor. And a third switch MOS transistor (MN5) for selectively connecting the sources of the pair of discharge MOS transistors to a ground terminal. In the third operation mode, the transfer MOS transistor is controlled to be on and the third switch MOS transistor is controlled to be off. In the fourth operation mode, the transfer MOS transistor is controlled to an off state and the third switch MOS transistor is controlled to an on state. A characteristic configuration of the transfer circuit is a drive mechanism for the complementary storage node of the first latch circuit for restoring the saved data in the fourth operation mode. If the polarity is reversed with respect to the above means for blocking the ground side, the same effect can be obtained for the same reason.

  In the first operation mode, the gate input signal of the transfer MOS transistor is a non-overlapping clock with respect to the clock signal supplied to the clock input terminal. In short, in the first operation mode, the first latch circuit and the second latch circuit perform a master / slave latch operation.

  The second static latch includes, for example, a pair of CMOS inverters connected in reverse parallel and a fourth switch MOS transistor capable of selectively cutting off power supply to the p-channel MOS transistor of the CMOS inverter. The fourth switch MOS transistor is switch-controlled in the opposite phase to the transfer MOS transistor. Similarly to the above, no through current is generated due to the transient response of the CMOS inverter, which contributes to low power consumption.

  [4] As another specific form of the present invention, the data holding element has an initialization circuit that selectively initializes the output terminal of the first latch circuit. Further, the data holding element has terminals (RS, PRS) for selecting an initialization level of the output terminal by the initialization circuit as a high level or a low level. It can be used for initialization by power-on reset, initialization after sequentially taking out data from the data holding element through the test path in the first operation mode, and the like.

  A plurality of data holding elements serially connected via the test path in the first operation mode constitute a scan register for facilitating the test. For example, in the first operation mode, there is provided a JTAG circuit that performs control to input data transferred via the scan register from the outside of the semiconductor integrated circuit and output to the outside.

  [5] A semiconductor integrated circuit according to another aspect of the present invention has a circuit block in which supply of power can be selectively cut off. The circuit block includes a plurality of data holding elements arranged in the middle of the signal path and the test path. The data holding element is an object of power supply interruption, and latches data latched by inputting data in synchronization with a clock from a data input terminal connected to the signal path or a test data input terminal connected to a test path. A first latch circuit that outputs from a data output terminal connected to the signal path, a first latch circuit that is not subject to power supply interruption, statically latches data, and outputs latched data from a test data output terminal that connects to the test path The data of the storage node of the second latch circuit and the first latch circuit is transferred to the storage node of the second latch circuit, or the data of the storage node of the second latch circuit is transferred to the storage node of the first latch circuit A transfer circuit. In the semiconductor integrated circuit, when the supply of power is cut off, the transfer circuit saves data stored in the first latch circuit to the second latch circuit, and when the supply of power is resumed, the transfer circuit The data stored in the two latch circuits is restored to the first latch circuit.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, in the semiconductor integrated circuit, the circuit scale required for holding the data for the scan latch and holding the data when the power is shut off can be reduced.

<Semiconductor integrated circuit>
FIG. 2 shows an example of a semiconductor integrated circuit according to the embodiment of the present invention. The semiconductor integrated circuit LSI shown in the figure is formed on a single semiconductor substrate such as single crystal silicon by a complementary MOS (CMOS) integrated circuit manufacturing technology, and is a system-on-chip semiconductor integrated circuit such as a microcomputer. Composed.

  The figure typically illustrates one circuit block CKB. The circuit block CKB includes a pulse latch circuit DRPL typically shown as a sequential circuit, and an inverter circuit INV and a NAND gate circuit NAND typically shown as a combinational circuit are shown. The pulse latch circuit DRPL includes a data input terminal D and a data output terminal Q, as well as a scan input terminal SI and a scan output terminal SO for connection to the scan path. The data input terminal D and the data output terminal Q are connected to a signal path RPASS for realizing the original data processing function of the semiconductor integrated circuit LSI. Usually, combinational circuits INV and NAND are arranged between the pulse latch circuits DRPL. ing. The scan input terminal SI and the scan output terminal SO are connected to the test path TPASS constituting the scan path. Due to the nature of the scan path, the scan output terminal SO of the pulse latch circuit DRPL arranged upstream of the test path TPASS is connected to the scan input terminal SI of the pulse latch circuit DRPL arranged downstream, and the entire semiconductor integrated circuit LSI is tested. The pulse latch circuits DRPL are sequentially arranged in series on the path TPASS. As a result, the pulse latch circuit DRPL is enabled to perform a shift register operation along the test path TPASS.

  The circuit block CKB is a circuit that can selectively cut off the supply of operating power. The circuit block CKB is supplied with an operation power supply voltage VDD as a high potential side power supply, and with a ground voltage VSS and a virtual ground voltage VSSM as a low potential side power supply. The virtual ground voltage VSSM is connected to the ground voltage VSS via the n-channel power switch MOS transistor PSW1. The power switch MOS transistor PSW1 is turned off in response to the instruction to the low power consumption state, and is turned on in response to the release instruction. The power switch MOS transistor PSW1 is formed of, for example, an N-channel MOS transistor having a thick gate insulating film thickness. The power switch controller PSWC is a switch control circuit for the power switch MOS transistor PSW1. When the power switch MOS transistor PSW1 is turned off, the circuit node of the virtual ground voltage VSSM is brought into a floating state.

  The pulse latch circuit DRPL is a first latch circuit (master latch circuit) ML that inputs and latches data from the data input terminal D or the scan input terminal SI in synchronization with the clock from the clock input terminal CK. A second latch circuit (slave latch circuit) SL for statically latching data, and a transfer circuit (data transfer circuit) for selectively connecting the storage node of the master latch circuit ML and the storage node of the slave latch circuit SL so as to be able to transfer data ) It is composed of DT. For convenience, the clock signal input from the clock input terminal CK is referred to as a clock signal CK. For example, the data output terminal Q is connected to the storage node of the master latch circuit ML, and the scan output terminal SO is connected to the storage node of the slave latch circuit SL. The pulse latch circuit DRPL has its input system switched to the data input terminal D or the scan input terminal SI according to the scan enable signal SE.

  In the pulse latch circuit DRPL, the master latch circuit ML is connected to the virtual ground voltage VSSM, and the supply of power is cut off in response to the low power consumption state. The slave latch circuit SL is connected to the ground voltage VSS and does not shut off the power supply even in the low power consumption state, and functions as a so-called balloon latch that holds the stored information of the master latch circuit ML in the low power consumption state. STR is a control terminal for transferring the stored data of the master latch circuit ML to the slave latch circuit SL, and RSTR is a control terminal for returning the stored data of the slave latch circuit SL to the master latch circuit ML. For convenience, the signal input from the control terminal RSTR is referred to as a restore signal RSTR.

  Although the details will be described later, the operation mode of the pulse latch circuit DRPL is roughly divided into first to fourth operation modes. In the first operation mode, data input to the scan input terminal SI from the test path TPASS (also referred to as scan data or test data) is propagated downstream of the test path TPASS through the master latch circuit ML, the data transfer circuit DL, and the slave latch circuit SL. (Hereinafter, referred to as a scan operation mode). At this time, the master latch circuit ML and the slave latch circuit SL perform a master / slave latch operation. In the first operation mode, the master latch circuit ML is synchronized with the clock from the clock input terminal CK, and the slave latch circuit SL is synchronized with the clock from the control terminal STR. The second operation mode is an operation mode in which data input from the signal path RPASS to the data input terminal D is propagated downstream of the signal path RPASS from the data output terminal Q through the master latch circuit ML (hereinafter referred to as a normal operation mode). ). The third operation mode is an operation mode in which the stored data of the master latch circuit ML is saved to the slave latch circuit SL through the transfer circuit DT when the power switch MOS transistor PSW1 is turned off to cut off the supply of operation power (hereinafter referred to as the slave latch circuit SL). , Referred to as power off mode). The fourth operation mode is an operation mode in which the stored data of the slave latch circuit SL is returned to the master latch circuit ML through the data transfer circuit DT when the supply of the operation power is resumed by turning on the power switch MOS transistor PSW1 ( Hereinafter, it is referred to as a power resumption mode).

<< Pulse latch circuit DRPL >>
FIG. 1 illustrates details of the circuit configuration of the pulse latch circuit DRPL. The master latch circuit ML includes a first static latch including a CMOS inverter circuit INV1 and a clocked CMOS inverter circuit CINV1 connected in reverse parallel, a transmission gate TG1, and the like. The transmission gate TG1 inputs data from the data input terminal D or scan data from the scan input terminal SI in response to the clock signal CK. The clock signal CK is a negative active type clock and is standby at a high level. That is, when the clock signal CK is at a high level, the transmission gate TG1 is cut off and is turned on at a low level. The first static latch latches data input from the transmission gate TG1 in response to the high level of the clock signal CK. The data stored in the first static latch is output from the data output terminal Q to the signal path RPASS in the normal operation mode.

  The data transfer circuit DT includes, for example, a pair of n-channel transfer MOS transistors MN1 and MN2, a pair of p-channel charge MOS transistors MP4 and MP5, a p-channel switch MOS transistor MP3, the control terminal STR, and a control terminal. RSTR etc. are provided. Transfer MOS transistors MN1 and MN2 are arranged between complementary storage nodes nd1 and nd2 of master latch circuit ML and complementary storage nodes nd3 and nd4 of slave latch circuit SL, respectively. The gate input signals of the transfer MOS transistors MN1 and MN2 are a data save signal STR0 or a scan data transfer signal SCANCK (see FIG. 3) input from the control terminal STR. Charge MOS transistors MP4 and MP5 have drains coupled to complementary storage nodes nd1 and nd2 of master latch circuit ML, respectively, and gates intersect with complementary storage nodes nd3 and nd4 of slave latch circuit SL across transfer MOS transistors MN1 and MN2, respectively. Are combined. The switch MOS transistor MP3 selectively connects the sources of the charge MOS transistors MP4 and MP5 to the power supply terminal. The gate input signal of the switch MOS transistor MP3 is a restore signal RSTR. In the power cut-off mode, the transfer MOS transistors MN1 and MN2 receive a high level data save signal STR0 from the control terminal STR at their gates and are controlled to be in an on state, and the switch MOS transistor MP3 has a high level at its gate. The restore signal RSTR is received and controlled to the off state. As a result, the complementary storage nodes nd1 and nd2 of the master latch circuit ML are connected to the complementary storage nodes nd3 and nd4 of the slave latch circuit SL, and the data stored in the master latch circuit ML is saved in the slave latch circuit SL.

  The slave latch circuit SL includes a second static latch disposed in a circuit block CKVSS that operates with the ground voltage VSS, and a scan output terminal SO. The second static latch includes, for example, a pair of anti-parallel connected CMOS inverter circuits INV3 and INV4, and switch MOS transistors MP1 and MP2 that can selectively cut off power supply to the p-channel MOS transistors of the CMOS inverter circuit, Is provided. The switch MOS transistors MP1 and MP2 are switch-controlled in the opposite phase to the transfer MOS transistors MN1 and MN2. As a result, in the power shut-off mode, the slave latch circuit SL performs only the low-level discharge when the stored data of the master latch circuit ML is supplied during the ON period of the transfer MOS transistors MN1 and MN2. The complementary levels of the storage nodes nd3 and nd4 are realized. For this reason, a through current due to a transient response of the CMOS inverter circuit is not generated, and accordingly, it contributes to low power consumption. For example, a save operation can be performed at a low voltage of about 0.5V. Further, since the power is supplied from the switch MOS transistors MP1 and MP2 to the second static latch as the transfer MOS transistors MN1 and MN2 are turned off, the stored data can be held as it is.

  Next, the power supply restart mode will be described. In the data transfer circuit DT, the transfer MOS transistors MN1 and MN2 receive a low level data save signal STR0 at their gates and are controlled to be turned off, and the switch MOS transistor MP3 has a low level restore signal RSTR at its gate. And is controlled to be on. Since the transfer MOS transistors MN1 and MN2 are cut off, the stored data held by the slave latch circuit SL is not destroyed, and one of the charge MOS transistors MP4 and MP5 is driven according to the value of the stored data. The high level for the storage node on the high level side of the master latch circuit ML is maintained.

  In the power cutoff state in which the power switch MOS transistor PSW1 is turned off, the virtual ground voltage VSSM inside the circuit block CKB is in a floating state, and the internal node of the circuit block CKB tends to converge to the power supply voltage due to the leakage current. A large driving capability is not required to maintain the internal node that has converged to the high level of the power supply voltage at the high level. Then, as the power is turned on again and the ground potential VSS is supplied to the floating virtual ground voltage VSSM, the storage node to be set to the low level is discharged toward the ground potential VSS. Therefore, since the high level is maintained for the storage node on the high level side of the master latch circuit ML, the potential difference from the storage node that should be set to the low level gradually increases, and the master latch circuit ML becomes the slave latch circuit SL. The stored data can be received accurately.

  On the other hand, if the transfer MOS transistors MN1 and MN2 are used in the power supply restart mode, the complementary storage nodes nd1 and nd2 of the master latch circuit ML are charged to the power supply voltage in the power cutoff state. It is not easy to drive nd1 and nd2 to complementary levels by the slave latch circuit SL, the return operation cannot be performed at high speed, and the inverted data may be recovered.

  In the power supply restart mode, when the stored data saved in the slave latch circuit SL is returned to the master latch circuit ML, an undesired signal is input to the master latch circuit ML via the transmission gate TG1 and returned from the slave latch circuit SL. It is necessary to avoid the stored data being destroyed. Since the internal node of the circuit block CKB in the power shut-off state has converged to a high level, when the power is turned on, the transmission gate TG1 acts to be in a cut-off state or a high impedance state, and the stored data is undesirably destroyed. Works to suppress. Further, in the power supply restart mode, the clock signal CK is set to have a low level period shorter than a high level period. Thereby, it is possible to make it difficult for the input data to penetrate through the latch operation by the master latch circuit ML using the one-phase clock signal CK input from the clock input terminal.

<< Clock supply system >>
FIG. 3 illustrates a clock supply system of the semiconductor integrated circuit LSI. The semiconductor integrated circuit LSI includes a phase-locked loop circuit PLL, a store circuit STRC, a scan control circuit SCANCNT, and the like. The phase-locked loop circuit PLL generates a global clock CLK having a duty ratio of 50 in which the high level period and the low level period are equal. Store circuit STRC outputs data save signal STR0 for saving the data stored in master latch circuit ML in the power-off mode. The scan control circuit SCANCNT outputs a scan enable signal SE for executing the scan operation mode. The clock supply system of the semiconductor integrated circuit LSI has a clock tree structure that distributes the global clock CLK over the entire area of the semiconductor integrated circuit LSI. The global clock CLK is propagated to a plurality of clock trees CKTR via a plurality of branches and a plurality of stages of clock buffers CKBUF. In the clock tree CKTR, a plurality of local clock trees LCKTR, a plurality of clock buffers CKBUF, and the like are arranged. The clock wiring of the clock supply system is, for example, an equal width and an equal length wiring. The local clock tree LCKTR is divided as a unit for supplying the global clock CLK, the data save signal STR0, and the scan enable signal SE in common, and the circuit block CKB shares the cut-off and restart of the power supply in common. Are separated as units that can be done with.

  The local clock tree LCKTR has a tree structure, and includes a clock buffer CKBUF for equalizing driving capability for each same hierarchy by branching, a plurality of pulse generation circuits PG, an inverter circuit INV, a selector SEL, and the like. Has been. The global clock CLK, the data save signal STR0, and the scan enable signal SE are input to the local clock tree LCKTR. In the figure, a plurality of pulse generation circuits PG and an inverter circuit INV are arranged on the clock wiring included in the upper region surrounded by a dotted line, the global clock CLK is input, and the clock signal CK is output. The The pulse generation circuit PG via the inverter circuit INV outputs a scan data transfer signal SCANCK having a phase opposite to that of the clock signal CK, that is, a non-overlap clock with respect to the clock signal CK. In addition, a selector SEL is arranged in the clock wiring included in the lower region surrounded by the dotted line, the data save signal STR0 and the scan data transfer signal SCANCK are input, and the scan enable signal SE is used as a selection signal. Entered. The selector SEL selects the scan data transfer signal SCANCK when the scan enable signal SE is at a high level (scan operation mode), and selects the data save signal STR0 when the scan enable signal SE is at a low level. Is output to the control terminal STR.

  In the scan operation mode, since the scan data transfer signal SCANCK is input from the control terminal STR, the master latch circuit ML and the slave latch circuit SL perform a master / slave latch operation. That is, in the scan operation mode as compared with the normal operation mode, data propagation can be controlled by master / slave operation using the master latch circuit ML and the slave latch circuit SL for one pulse latch circuit DRPL. For this reason, the transfer clock used in the scan operation mode does not need to be highly accurate with respect to the synchronous clock used in the normal operation mode. In the upper region, since the clock signal CK is output, the delay amount of each clock signal CK with respect to the global clock CLK needs to be small. In the lower region, the scan data transfer signal SCANCK used for the scan operation mode is output, and this is not necessary.

<< Pulse generation circuit PG >>
FIG. 4 illustrates a circuit configuration of the pulse generation circuit PG. As shown in FIG. 4A, the pulse generation circuit PG has an odd-numbered stage, for example, three-stage inverter circuit, and a final-stage NAND gate circuit. Both the global clock CLK and the delay signal from the inverter circuit are high. When the signal is at the level, the output clock signal CK is set to the low level, and otherwise, the output is fixed to the high level. The period during which the clock signal CK is at a low level is determined by the delay time of the clock signal by the inverter circuit. Thereby, the pulse generation circuit PG generates a pulsed clock signal CK having a short low level period and a long high level period. The pulse width may be adjusted by the number of inverter circuit stages.

  By the way, in the power supply restart mode, the virtual ground voltage VSSM is generally non-uniform in the semiconductor integrated circuit LSI, and if the distance between the pulse generation circuit PG and the pulse latch circuit DRPL is large, the clock signal supplied to the pulse latch circuit DRPL. There is a possibility that fixing CK to a high level cannot be guaranteed in the middle of signal transmission. For this reason, the pulse generation circuit PG is arranged in the lower layer of the above-described local clock tree LCKTR, that is, close to the pulse latch circuit DRPL. As a result, the clock signal CK is reliably fixed at the high level, and the pulse latch circuit DRPL malfunctions when the data transfer circuit DT restores the stored data from the slave latch circuit SL to the master latch circuit ML in the power supply restart mode. Can be avoided.

  In the power shut-off mode, both the global clock CLK and the clock signal CK are floating on the ground side. In addition, the storage node whose logical value is at a low level before the power supply is cut rises to the power supply voltage VDD side by the power supply cut-off. When power supply is resumed, the storage node that should be at the low level falls from a level close to the power supply voltage VDD. At this time, since the return of the power source is not uniform, for example, a signal from a long distance has no correlation with the local power source, so there is a possibility that the time for returning to the high level is delayed. In this case, when the power supply is temporarily restored, the logical value appears as a low level, and switching may occur in a subsequent circuit, which may cause a malfunction.

  On the other hand, if the circuits are arranged in the local clock tree LCKTR, their power supplies respond almost simultaneously, so that the above malfunction does not occur. In short, according to the pulse generation circuit PG, the clock signal CK can be fixed at a high level even in the power supply restart mode. Further, even when the distance between the pulse generation circuit PG and the pulse latch circuit DRPL is large, the malfunction can be avoided by providing the pull-up P-channel MOS transistor as illustrated in FIG. 4B. . The pull-up P-channel MOS transistor is controlled by a control signal CTL that is linked to a power cut-off signal (not shown), for example. The pull-up P-channel MOS transistor is disposed inside the pulse generation circuit PG. However, the present invention is not limited to this, and the pull-up P-channel MOS transistor may be disposed near the pulse latch circuit DRPL or inside the pulse latch circuit DRPL. Good.

<Operation of pulse latch circuit in actual operation mode>
FIG. 5 illustrates a timing chart showing the operation timing in the actual operation mode of the pulse latch circuit DRPL. The actual operation mode is a generic term for the normal operation mode, the power cut-off mode, and the power resume mode. At times T1 and T2, the pulse latch circuit DRPL takes in data from the data input terminal D and outputs it from the data output terminal Q. This period of time T1 to T2 corresponds to the normal operation mode and is indicated as “NORM” in the figure. Next, the pulse latch circuit DRPL shifts to the power cutoff mode. First, at time T3, the clock signal CK is fixed to a high level by the pulse generation circuit PG. Then, the data save signal STR0 is set to the high level by the store circuit STRC, and the data transfer circuit DT saves the data stored in the master latch circuit ML in the slave latch circuit SL. At time T4, the data save signal STR0 is set to the low level, and the stored data is held by the slave latch circuit SL. In synchronization with this, at time T5, the request signal PSW_REQ for requesting power-off is set to the low level, and in response to this, the response signal PSW_ACK is set to the low level at time T5. The request signal PSW_REQ and the response signal PSW_ACK are signals exchanged between the standby control circuit STBYC (see FIG. 17) and the power switch controller PSWC. The period from the time T3 to T5 is indicated as “RESERVE” in the figure.

  At time T6, the power is shut off by the power switch MOS transistor PSW1. As a result, the virtual ground voltage VSSM gradually rises due to the leakage current of the internal logic circuit, and rises to a level near the power supply voltage VDD at time T7. At time T8, in preparation for turning on the power switch MOS transistor PSW1, the restore signal RSTR is set to low level, and preparation is made to restore the data stored in the slave latch circuit SL to the master latch circuit ML. In synchronization with this, at time T9, the request signal PSW_REQ for requesting power-on is set to the high level. During the period from time T6 to time T9, the semiconductor integrated circuit LSI is turned off and a preparatory operation for turning on the power is performed, which is indicated as “POWERDN” in the drawing.

  At time T10, the power switch MOS transistor PSW1 is turned on in synchronization with the request signal PSW_REQ at time T9, and power supply is resumed. As a result, the virtual ground voltage VSSM gradually decreases and is discharged to near the ground level at time T11. At times T10 to T11, when the values of the storage nodes nd1 and nd2 of the master latch circuit ML are gradually fixed according to the storage data of the slave latch circuit SL, and the virtual ground voltage VSSM becomes completely 0V at the time T11 The stored data restoration operation is completed. This period from time T10 to T11 corresponds to the power supply resumption mode and is indicated as “POWERON” in the drawing.

  Thereafter, when the response signal PSW_ACK becomes high level at time T12, the restore signal RSTR is returned to high level at time T13, the supply of the clock signal CK is started at time T14, and the normal operation mode is resumed. These times T12 to T14 are indicated as “NORM” in the figure.

<< Operation of pulse latch circuit DRPL in scan operation mode >>
FIG. 6 illustrates a timing chart showing the operation timing of the pulse latch circuit DRPL in the scan operation mode. Here, the correspondence between global clock CLK, clock signal CK, and scan data transfer signal SCANCK will be mainly described. The clock signal CK is set to a low level in synchronization with the rising edge of the global clock CLK. Here, the period during which the clock signal CK is at a low level is P1. The scan enable signal SE is at a high level in the scan operation mode. Since the scan enable signal SE is at a high level, the selector SEL selects the scan data transfer signal SCANCK and outputs it to the control terminal STR of the pulse latch circuit DRPL. The scan data transfer signal SCANCK is set to the high level in synchronization with the falling edge of the global clock CLK. Here, the period during which the scan data transfer signal SCANCK is at a high level is P1. In addition, although P1 was set as the period between synchronization by the clock signal CK and the scan data transfer signal SCANCK, it is not restricted to this and may change suitably.

  In the pulse latch circuit DRPL, the scan input terminal SI holds scan data (for example, D1) during the P1 period of the clock signal CK. This scan data D1 is held in the master latch circuit ML in the period P1. After that, during the P1 period of the scan data transfer signal SCANCK, the value of the node nd1 (for example, / D1) of the master latch circuit ML is transferred to the node nd3 of the slave latch circuit SL via the data transfer circuit DT, which is not shown. The value of the node nd2 of the master latch circuit ML is transferred to the node nd4 of the slave latch circuit SL. At this time, the value of the scan output terminal SO is also set as the scan data D1, and the scan data D1 is transferred to the scan input terminal SI of the pulse latch circuit DRPL at the next stage.

  In the pulse latch circuit DRPL at the next stage, the scan enable signal SE is set to the high level and the input system is the scan input terminal SI, so that the scan data of the scan input terminal SI is determined. Thereafter, when the clock signal CK becomes low level, the scan data is held in the pulse latch circuit DRPL at the next stage. In short, in the plurality of pulse latch circuits DRPL that share the scan enable signal SE, scan data is sequentially sent through the master latch circuit ML and the slave latch circuit SL, or data held by the master latch circuit ML is stored in the semiconductor integrated circuit LSI. It can also be taken out. Therefore, the plurality of master latch circuits ML and slave latch circuits SL connected in series perform a shift register operation. The extracted data is compared with an expected value outside the semiconductor integrated circuit LSI, for example, and used for failure detection or the like. In other words, the plurality of master latch circuits ML and slave latch circuits SL connected in series constitute a scan path for ease of testing.

  As described above, according to the semiconductor integrated circuit LSI, the slave latch circuit SL is used as a latch circuit for configuring a scan path in the scan operation mode, and is a latch circuit that saves data stored in the master latch circuit ML in the power cut-off mode. Therefore, it is possible to reduce the circuit scale required for holding the data for the scan latch and holding the data when the power is shut off. Therefore, the arrangement of the pulse latch circuit DRPL in the circuit block CKB is effective in reducing the area overhead.

<< Pulse latch circuit with reset function >>
7 to 11 illustrate circuit configurations of a pulse latch circuit having a reset function. In each pulse latch circuit exemplified below, the same reference numerals are given to the overlapping parts with the pulse latch circuit DRPL exemplified in FIG. 1, and the description thereof is omitted as appropriate. Here, the reset function is realized by an initialization circuit that selectively initializes the data output terminal Q of the master latch circuit ML. In the following, the initialization level is a low level. This initialization circuit is used for initialization by power-on reset, initialization after sequentially taking out scan data from the pulse latch circuit through the test path in the scan operation mode to the outside of the semiconductor integrated circuit LSI, and the like.

  Compared to the master latch circuit ML, the master latch circuit MLa of the pulse latch circuit DRPLa illustrated in FIG. 7 is provided with a reset terminal RS to which a reset signal RSB is input, and instead of the clocked inverter circuit CINV1, the clock donand gate circuit CNAND1. Are arranged, and a part of the inverter circuit of the clock buffer is changed to a NOR gate circuit NOR1. The reset control is performed after the clock signal CK is in the gating state. When the reset signal RSB becomes low level, the clock output ckb from the NOR gate circuit NOR1 is fixed at low level, so that the transmission gate TG1 is cut off and stored by the output from the clock donand gate circuit CNAND1. The node nd1 becomes high level. As a result, the data output terminal Q is fixed at a low level. According to such a master latch circuit MLa, the level of the storage node nd2 can be fixed in a short time in the normal operation mode, and the latch operation can be stabilized in a short time. Further, the NOR gate circuit NOR1 can fix the clock signal CK with the reset signal RSB, so that clock control is unnecessary.

  As compared with the master latch circuit ML, the master latch circuit MLb of the pulse latch circuit DRPLb illustrated in FIG. 8 is provided with the reset terminal RS, the data output terminal Q is connected to the storage node nd2, and the output value is the master latch circuit ML. The data output terminal Q is an inverted signal, and a NAND gate circuit NAND1 circuit is arranged instead of the inverter circuit INV1. When the reset signal RSB becomes low level, the storage node nd2 becomes high level, so that the data output terminal Q is fixed at low level. In master latch circuit MLb, the number of constituent elements can be reduced, and it is not necessary to gate clock signal CK during the reset period. For this reason, reset control can be performed independently of clock gating control. In the master latch circuit MLb, the input and output polarities are different. However, by adding one stage of inverter circuit to the output or by logical design so that the input becomes an inverting input, the input and output polarities You may make it match.

  Compared with the master latch circuit ML, the master latch circuit MLc of the pulse latch circuit DRPLc illustrated in FIG. 9 includes the reset terminal RS, the NAND gate circuit NAND1 instead of the inverter circuit INV1, and the data input terminal D. The inverter circuits connected to the data input terminal SI are respectively changed to NOR gate circuits NOR, and the inverter circuit INV2 is arranged between these NOR gate circuits NOR and the reset terminal RS. In the master latch circuit ML, the number of constituent elements increases, but reset control is possible regardless of the value of the clock signal CK. That is, if the clock signal CK is at a high level, the data output terminal Q is determined by the output of the NAND gate circuit NAND1. If the clock signal CK is at a low level, the output from the NOR gate circuit NOR receiving the input data from the data input terminal D and the scan data input terminal SI becomes the output of the data output terminal Q. In short, according to the master latch circuit MLc, reset control can be performed without fixing the clock signal at a high level, in other words, without performing clock control.

  Compared with the master latch circuit ML, the master latch circuit MLd of the pulse latch circuit DRPLd illustrated in FIG. 10 includes the reset terminal RS, the NAND gate circuit NAND1 instead of the inverter circuit INV1, and a part of the clock buffer. The inverter circuit is changed to the NOR gate circuit NOR1, and the inverter circuit INV2 is arranged between the NOR gate circuit NOR1 and the reset terminal RS. In the master latch circuit MLd, the reset function is realized by fixing the clock signal CK to a high level during the reset period.

  Compared to the master latch circuit ML, the master latch circuit MLe of the pulse latch circuit DRPLe illustrated in FIG. 11 includes a NOR gate circuit NOR2 instead of the inverter circuit INV1, and the reset terminal RS. In the master latch circuit ML, clock gating can be interlocked during reset control. That is, when the reset signal RS becomes high level, the storage node nd2 first becomes low level and the storage node nd1 becomes high level, so that the data output terminal Q is fixed at low level. In the master latch circuit MLe, it is necessary to gate the clock signal CK, but the number of constituent elements can be reduced.

<< Pulse latch circuit with reset and preset functions >>
In the pulse latch circuits DRPLa-D illustrated in FIG. 7 to FIG. 11, only the reset function for setting the initialization level of the data output terminal Q of the master latch circuits MLa-e to the low level has been described. A pulse latch circuit having a preset function for fixing the initialization level to a high level will be described. Compared to the master latch circuit ML, the master latch circuit MLf of the pulse latch circuit DRPLf illustrated in FIG. 12 is provided with a preset terminal PRS to which a preset signal PRSB is input and the reset terminal RS, and an inverter circuit INV1 and a clocked inverter circuit CINV1. Instead, a NAND gate circuit NAND3 and a clock NAND gate circuit CNAND1 are arranged, respectively, and a part of the inverter circuit of the clock buffer is changed to a NOR gate circuit NOR1. In the master latch circuit MLf, after the clock gating is performed, for example, if both the reset signal RS and the preset signal PRSB are set to the low level, the data output terminal Q can be fixed to the high level. That is, according to the master latch circuit ML, the data output terminal Q can be fixed at a low level or a high level by using the reset signal RSB and the preset signal PRSB. It is possible to add a preset function to the pulse latch circuits DRPLa to e illustrated in FIGS. 7 to 11, and when only the preset function is required, for example, the master latch circuit MLa illustrated in FIG. In contrast, the clocked NAND gate circuit CNAND1 may be changed to a clocked NOR gate circuit to reverse the high level and low level of the reset signal RSB. Such a change can also be made to the master latch circuits MLb to e illustrated in FIGS.

  Compared to the master latch circuit ML, the master latch circuit MLg of the pulse latch circuit DRPLg illustrated in FIG. 13 includes the preset terminal PRS and the reset terminal RS, and a composite gate ORNAND instead of the inverter circuit INV1. The pulse latch circuit DRPLg can have a reset function and a preset function by using a composite gate ORNAND. In the master latch circuit MLg, the reset signal RSB and the negative preset signal PRSB are input to the composite gate ORNAND. At the time of reset, if both the reset signal RSB and the negative preset signal PRSB are set to the high level, the data output terminal Q is set to the low level. Fixed. At the time of presetting, the data output terminal Q is fixed at a high level by setting the preset signal PRSB to a low level and the reset signal RES to a high level or a low level. In the normal operation mode, the preset signal PRSB may be at a high level and the reset signal RES may be at a low level.

<Power supply structure>
FIG. 14 illustrates a power supply structure together with an inverter circuit. In the inverter circuit that is turned off when the power is turned off, the source power and substrate voltage of the P-channel MOS transistor are VDD, the source power of the N-channel MOS transistor is the virtual ground line VSSM, as shown in FIG. The substrate power supply is set to VSS. In the inverter circuit in which the power is not shut down when the power is shut off, the source power and substrate power of the P-channel MOS transistor are set to VDD, and the source power and substrate power of the N-channel MOS transistor are set to VSS as shown in FIG. The The occurrence of leakage current to the substrate can be suppressed when the power is shut off by (a) in the figure.

  FIG. 15 illustrates the layout of the power supply structure illustrated in FIG. Here, the structure of the standard cell is shown by taking an inverter circuit as an example, and the VSS power source and the VDD power source are arranged at the upper and lower ends of the standard cell. The area (a) in the figure corresponds to the inverter circuit where the power is cut off, and the area (b) corresponds to the inverter circuit where the power is not cut off. Since the same VSS is applied to the substrate of the N-channel MOS transistor of the standard cell, it is applied to the substrate of the N-channel MOS transistor through the contact from the VSS wiring of the first metal M1 at the lower end of the standard cell. In the N channel type MOS transistor power source for the standard cell, the VSSM power source line is wired with the first metal M1. It is desirable that this is wired by a wiring channel immediately above the VSS wiring. On the other hand, the source power supply of the N-channel MOS transistor on the power cutoff side has VSSM wiring, so it cannot be wired with the first metal M1 from the VSS power supply, but is wired using diffusion wiring instead.

<< Power supply for various signals wired in the semiconductor integrated circuit LSI >>
FIG. 16 illustrates the power supply of various signals wired in the semiconductor integrated circuit LSI together with the power supply structure of the logic circuit. The circuit block CKB has a power switch PSW connected to both ends thereof. A VDD power source, a VSS power source, and a virtual ground power source VSSM via a power switch PSW are applied to the circuit block CKB. The power switch PSW corresponds to the power switch MOS transistor PSW1 described above, and is formed of, for example, a high-breakdown-voltage and low-leakage N-channel MOS transistor with a thick gate insulating film used in an I / O circuit. The power switch controller PSWC that controls the gate input signal of the power switch PSW operates with the I / O power supplies VCC and VSS. Therefore, the gate input signal is a control signal at the VCC potential level. The control circuit DRSEC controls the pulse latch circuit DRPL, and includes not only the above-described store circuit STRC and scan control circuit SCANCNT (see FIG. 3) but also a predetermined circuit that generates the restore signal RSTR.

  The control circuit DRSEC operates with VDD and VSS power supplies. The data saving signal STR0 input to the control terminal STR is transmitted by a circuit to which VDD and VSS are applied inside the circuit block CKB so that control is possible even when the circuit block CKB is shut off. Since the restore signal RSTR does not need to be controlled when the circuit block CKB is powered off, the restore signal RSTR is transmitted by a circuit to which VDD and VSSM are applied inside the circuit block CKB. The global clock CLK is transmitted by a circuit to which VDD and VSSM are applied in the circuit block CKB, similarly to the restore signal RSTR.

<Standby control>
FIG. 17 illustrates a schematic configuration of a standby control circuit STBYC that controls transition to and return from various standby modes. Here, the standby control circuit STBYC is shown as an example of a system control circuit of the semiconductor integrated circuit LSI. The standby control circuit STBYC is a circuit that controls the power switch controller PSWC, the pulse latch circuit DRPL, and the circuit block CKB. For example, the standby control circuit STBYC performs a power shutdown or a return operation from the power shutdown in response to an interrupt signal from the outside. Control. When the power is shut down by the interrupt signal, the request signal PSW_REQ signal and the response PSW_ACK are exchanged with the power switch controller PSWC, the state of the power switch controller PSWC is grasped, and then the system control is performed. The pulse latch circuit DRPL is controlled by a signal (the data save signal STR0) input to the control terminal STR and a restore signal RSTR.

  In the following, the fast return standby mode executed by the standby control circuit STBYC will be mainly described. First, the case where the pulse latch circuit DRPL is applied to the minimum necessary latches and registers will be described. The standby control circuit STBYC is connected to a system bus SYSBUS for reading / writing internal registers, and receives an interrupt request signal IRQ, a reset signal RST, a clock signal RCLK, and a response signal PSW_ACK from the power switch controller PSWC. Is done. The output of the standby control circuit STBYC includes a data save signal STR0 input to the control terminal STR, a restore signal RSTR, an interrupt signal (not shown) for notifying the CPU after returning from standby mode, and a CPU execution start address RST after reset. -VEC, logic circuit reset signal RST1, and power switch PSW_REQ.

  The standby control circuit STBYC includes a standby mode control register STBCR and a boot address register BAR as registers that can be read and written from the system bus SYSBUS, and read / write operations from the system bus SYSBUS are controlled by a decoder. The standby mode control register STBCR holds a value corresponding to the current standby mode. Also, writing to the standby mode control register STBCR from the system bus SYSBUS becomes a request for transition to various corresponding low current modes. The boot address register BAR holds the address of the instruction executed first by the CPU when returning from the fast return standby mode and releasing the reset. In this example, the transition request to the standby mode is given by writing to the standby mode control register STBCR. However, the transition is made by using a dedicated instruction such as a sleep instruction or a standby instruction or a combination of the standby mode control register STBCR and the dedicated instruction. Can also be requested. In that case, the CPU can be realized by transmitting a transition request to the standby control circuit STBYC via a sleep request response line (not shown).

  The synchronization circuit SYNC included in the standby control circuit STBYC synchronizes the interrupt request IRQ from the outside of the semiconductor integrated circuit LSI with the external clock signal RCLK. The current mode control sequential circuit STBYC-FSM determines the necessity for transition / return to the standby mode, and outputs a transition / return sequence if necessary. The input of the current mode control sequential circuit STBYC-FSM is a value of the standby mode register STBCR, an interrupt request IRQ, and a state holding register STATE indicating which step is executed in the sequence at transition / return. The output of the current mode control sequential circuit STBYC-FSM is an output of the standby control circuit STBYC and a standby mode signal STBYMODE indicating whether or not the current standby mode is set.

  When a transition is made to the fast return standby mode in response to an external interrupt request signal IRQ, control for gating the clock is first performed. Thereafter, the data save signal STR0 is issued and output to the control terminal STR, and the data stored in the main latch SL in the pulse latch circuit DRPL is saved in the slave latch circuit SL to prepare for power shutdown. After the stored data saving operation is completed, control to turn off the power switch MOS transistor PSW1 is performed by the request signal PSW_REQ. Whether or not the power is shut off is detected by a response signal PSW_ACK. When the power is cut off, the circuit block CKB transitions to the fast return standby mode.

  Next, the case where the interrupt request signal IRQ from the outside is received to return from the fast return standby mode will be described. Here, a case where only the minimum necessary data is held in the pulse latch circuit DRPL will be described. In response to the external interrupt signal, the standby control circuit STBYC performs control to turn on the power switch MOS transistor PSW1 of the circuit block CKB. At that time, first, a restore signal RSTR is issued, and then a request signal PSW_REQ is issued to the power switch controller PSWC in order to control to turn on the power switch MOS transistor PSW1. As a result, as the power switch MOS transistor PSW1 is turned on, the stored data saved in the slave latch circuit SL of the pulse latch circuit DRPL returns to the master latch circuit ML, and the minimum necessary setting data is restored. When entering the fast recovery standby mode after the power is supplied, it is necessary to perform interrupt processing corresponding to the interrupt request signal IRQ after returning the information saved in the internal memory or external memory to each circuit module such as a CPU. is there. This interrupt process is performed by executing a predetermined instruction.

  Therefore, when returning from the fast return standby mode, it is necessary to hold the address of the memory storing the instruction to be executed first after the return. Therefore, a boot address register BAR is provided to hold the address of the memory storing the instruction to be executed first when returning from the standby mode, and execution is started in the boot address register BAR when transitioning to the fast return standby mode. The address is set. It is also possible to always make the execution start address the same when returning from the fast return standby mode. In this case, it is possible to omit the setting of the execution address at the time of transition to the fast return standby mode by configuring with hard wired. According to the standby control circuit STBYC here, since the boot address register BAR is provided, it is possible for the software creator to freely set the execution start address after the return, and a program necessary for returning to the fast return standby mode. Can be arranged at an arbitrary position in the memory space. Here, the standby control circuit STBYC in the case where the pulse latch circuit DRPL is partially adopted has been described. However, the present invention is not limited to this, and all the latches and registers included in the logic circuit in the circuit block CKB are transferred to the pulse control circuit STBYC. It may be replaced with a latch circuit DRPL. In such a system, since all information in the CPU (circuit module) is held at the time of return by interruption, it is not necessary to write a value with the CPU execution start address RST-VEC. Therefore, in such a system, the boot address register BAR and the selector SEL1 are unnecessary.

<Test circuit>
FIG. 18 illustrates a schematic configuration of a test circuit arranged in the semiconductor integrated circuit LSI. The test circuit sequentially sends test data to a plurality of serially connected master latch circuits ML and slave latch circuits SL in the plurality of pulse latch circuits DRPL in the scan operation mode described above, or extracts data held by the master latch circuit ML. It is a circuit for. In many cases, the test circuit generally satisfies a common specification called JTAG. During the test, for example, a test clock signal TCK, a test data signal TDI, a test module switching signal TMS, a reset signal TRST, and the like are input from the JTAG terminal into the semiconductor integrated circuit LSI. Input to DBGIO. A test output signal TDO is output from the debug interface circuit DBGIO to the outside of the semiconductor integrated circuit LSI. A debug clock, input data, a module selection signal, a reset signal, and the like are input to the debug control circuit DBGCNT, and the test input signal is sequentially latched in the logic unit inside the semiconductor integrated circuit LSI by the test clock signal TCK. Transmit to circuit DRPL.

  In the scan operation mode, the pulse latch circuit DRPL needs to receive the clock signal CK at the clock input terminal and the scan data transfer signal SCANCK at the control terminal STR. Here, the clock signal CK2 output from the debug control circuit DBGCNT is input to the pulse generation circuit PG1, and the pulsed clock signal CK3 that becomes low level at the rising edge of the clock signal CK2 is generated. This clock signal CK3 is input to the clock input terminal of the pulse latch circuit DRPL as the clock signal CK. Further, the clock signal CK2 is input to the pulse generation circuit PG2, and a pulsed clock signal CK4 that becomes high level at the falling edge of the clock signal CK2 is generated. This clock signal CK4 is input to the selector SEL. Since the scan enable signal SE is at the high level, the selector SEL selects the clock signal CK4 instead of the data save signal STR0, and outputs it to the control terminal STR as the scan data transfer signal SCANCK.

  Furthermore, the test data sent using the clock signal CK3 and the clock signal CK4 are sequentially set in the pulse latch circuit DRPL, and after the setting is completed for all the pulse latch circuits DRPL, the operation verification is performed. A predetermined operation is executed from the set state, and internal data after a prescribed cycle is taken out from the scan data output terminal SO of the pulse latch circuit DRPL at the final stage to the debug control circuit DBGCNT. For example, as shown in the figure, test data SD0 is set in the first-stage pulse latch circuit DRPL, and test data SD1 is extracted from the last-stage pulse latch circuit DRPL. Data transfer at this time also uses the clock signal CK3 and the clock signal CK4. Then, it is taken out of the semiconductor integrated circuit LSI via the debug interface circuit DBGIO. That is, in the scan operation mode, the plurality of pulse latch circuits DRPL serially connected via the test path constitute a scan register for facilitating the test. As a result, a predetermined operation verification can be performed by comparing a predetermined expected value with the extracted data outside the semiconductor integrated circuit LSI. Note that since a clock is input from the outside to the JTAG terminal, the phase-locked loop circuit PLL may be unnecessary, but is illustrated in consideration of the necessity of an internal clock during debugging.

  As mentioned above, although the invention made by this inventor was concretely demonstrated based on embodiment, it cannot be overemphasized that this invention is not limited to it and can be variously changed in the range which does not deviate from the summary.

  For example, in the above-described pulse latch circuit DRPL, the power supply is cut off on the ground voltage VSS side. However, the present invention is not limited to this, and the power supply may be cut off on the power supply voltage VDD side. FIG. 19 illustrates a circuit configuration of a pulse latch that is different from the pulse latch circuit DRPL illustrated in FIG. Compared with the pulse latch circuit DRPL, the pulse latch circuit DRPLh is arranged between the power supply terminals of the semiconductor integrated circuit LSI and includes a power switch MOS transistor PSW2 used for shutting off the supply of operating power. In order to shut off, the circuit configuration of the data transfer circuit DT is changed.

  The data transfer circuit DTa includes, for example, a pair of n-channel transfer MOS transistors MN3 and MN4, a pair of n-channel discharge MOS transistors MN6 and MN7, an n-channel switch MOS transistor MN5, and the like. Transfer MOS transistors MN3 and MN4 are arranged between complementary storage nodes nd1 and nd2 of master latch circuit ML and complementary storage nodes nd3 and nd4 of slave latch circuit SL, respectively. The discharge MOS transistors MN6 and MN7 have drains coupled to the complementary storage nodes nd1 and nd2 of the master latch circuit ML, respectively, and gates intersect with the complementary storage nodes nd3 and nd4 of the slave latch circuit SL across the transfer MOS transistors MN3 and MN4, respectively. Are combined. The switch MOS transistor MN5 selectively connects the sources of the discharge MOS transistors MN6 and MN7 to the ground terminal.

  Next, the operation of the data transfer circuit DTa will be described. In the power cut-off mode, the transfer MOS transistors MN3 and MN4 are controlled to be on, and the switch MOS transistor MN5 is controlled to be off. In the power supply restart mode, the transfer MOS transistors MN3 and MN4 are controlled to the off state, and the switch MOS transistor MN5 is controlled to the on state. The data transfer circuit DT is characterized by a driving mechanism for the complementary storage nodes nd1 and nd2 of the master latch circuit ML in the return operation in the power supply restart mode. That is, in the data transfer circuit DTa, the transfer MOS transistors MN3 and MN4 receive the low level data save signal STR0 at their gates and are controlled to be turned off, and the switch MOS transistor MN5 has a high level restore at its gate. In response to the signal RSTR, the signal is controlled to be turned on. Since the transfer MOS transistors MN3 and MN4 are cut off, the stored data held by the slave latch circuit SL is not destroyed, and one of the discharge MOS transistors MN6 and MN7 is driven according to the value of the stored data. The low level for the storage node on the low level side of the master latch circuit ML is maintained.

  In the power cutoff state in which the power switch MOS transistor PSW2 is turned off, the virtual power supply voltage VDDM inside the circuit block CKB becomes floating, and the internal node of the circuit block CKB tends to converge to the ground voltage due to the leak current. A large driving capability is not required to maintain the internal node that has converged to the low level of the ground voltage at the low level. Then, as the power is turned on again and the power supply potential VDD is supplied to the floating virtual ground voltage VDDM, the storage node to be set to the high level is charged toward the power supply potential VDD. Therefore, since the low level is maintained for the storage node on the low level side of the master latch circuit ML, the potential difference from the storage node to be set to the high level gradually increases, and the master latch circuit ML is connected to the slave latch circuit SL. The stored data can be received accurately. In the pulse latch circuit DRPLh, the high level period of the clock signal CK is preferably shorter than the low level period. This is because the internal node of the circuit block CKB tends to converge to the ground voltage when the power supply is cut off with respect to the pulse latch circuit DRPL illustrated in FIG. By shortening the high level period of CK, it is possible to avoid the transmission gate TG1 from being turned on undesirably. In short, the clock signal CK here is a positive active type clock, and is standby at a low level.

  FIG. 20 illustrates a timing chart showing the operation timing of the pulse latch circuit DRPLh in the actual operation mode. Times T1 to T2 correspond to the normal operation mode, and data moves from the data input terminal D to the data output terminal Q. At time T3, the clock signal CK is stopped and fixed at a low level. Thereafter, the data save signal STR0 is set to the high level, and the data stored in the master latch circuit ML is saved in the slave latch circuit SL. At time T4, the data save signal STR0 is set to the low level, and the stored data is held by the slave latch circuit SL. At time T5, the request signal PSW_REQ is set to low level, and the response signal PSW_ACK is set to low level.

  At time T6, power supply is cut off by the power switch MOS transistor PSW2. As a result, the virtual power supply line VDDM gradually approaches the VSS level due to the leakage current of the internal logic circuit. In preparation for turning on the power switch MOS transistor PSW2 (or regulator) at time T8, the restore signal RSTR is set to the high level. Thereby, preparations are made to restore the stored data of the slave latch circuit SL to the master latch circuit ML. In synchronization with this, at time T9, the request signal PSW_REQ is set to the high level. When the power switch MOS transistor PSW2 is ON-controlled at time T10, the VDDM level is gradually charged toward the ground level. At times T10 to T11, when the values of the storage nodes nd1 and nd2 are gradually fixed according to the storage data of the slave latch circuit SL, the master latch circuit ML completes the recovery operation of the storage data when VSSM is completely 0V. To do. Thereafter, when the response signal PSW_ACK from the power switch MOS transistor PSW2 becomes high level at time T12, the restore signal RSTR is returned to low level at time T13 in synchronization with this. Then, the supply of the clock signal CK is started at time T14, and the normal operation mode is entered again.

  FIG. 2 illustrates the power supply structure of the pulse latch circuit DRPL and a predetermined logic circuit, but is not limited to this. FIG. 21 illustrates another power supply structure of the pulse latch circuit DRPL and the logic circuit. Here, an example is shown in which the second virtual ground power supply VSSM2 different from the substrate is applied to the circuit block including the second static latch of the slave latch circuit SL when the power supply of the pulse latch circuit DRPL is shut off. The circuit block CKB is controlled by the power switch controller PSWC1 and connected to the virtual ground power supply VSSM. The circuit block CKB is controlled by the power switch controller PSWC2 and connected to the second virtual ground power supply VSSM2. The power switch PSW3 is connected to the ground. The power supply is cut off on the ground side by the power switch PSW4 connected to the power supply VSS.

  FIG. 22 illustrates the power supply structure illustrated in FIG. 21 using an inverter circuit. Note that the inverter circuit shown in FIG. 14A is the same as the inverter circuit shown in FIG. In the inverter circuit in which the power is not shut down when the power is shut off, as shown in FIG. 5B, the source power and substrate power of the P-channel MOS transistor are VDD, and the source power of the N-channel MOS transistor is the second virtual ground line VSSM2. The substrate power supply is set to VSS.

  FIG. 23 illustrates the layout of the power supply structure illustrated in FIG. Here, the structure of the standard cell shows an inverter circuit as an example, and the VSS power source and the VDD power source are arranged at the upper and lower ends of the standard cell. The area (a) in the figure corresponds to the area (a) in the figure of FIG. 15 described above, and a description thereof will be omitted as appropriate. Further, the region (b) in the figure corresponds to the inverter circuit which is not shut off from the power source illustrated in FIG. Since the same VSS is applied to the substrate of the N-channel MOS transistor of the standard cell, it is applied to the substrate of the N-channel MOS transistor through the contact from the VSS wiring of the first metal M1 at the lower end of the standard cell. In the N channel type MOS transistor power source for the standard cell, the VSSM power source line is wired with the first metal M1. It is desirable that this is wired by a wiring channel immediately above the VSS wiring. On the other hand, the second virtual ground VSSM2 is necessary for the source power supply of the N-channel MOS transistor on the power cutoff side. However, since this VSSM2 power supply is not necessary in a normal standard cell such as an inverter circuit different from the pulse latch circuit DRPL when the power is shut off, wiring in all the cells is not preferable in terms of area efficiency. . Therefore, VSSM2 is defined as a terminal and wired as a signal wiring. Even if it does in this way, since the circuit which requires VSSM2 does not require high-speed operation, even if a power supply impedance becomes a little high, a problem will not arise.

  FIG. 24 illustrates a circuit configuration of a pulse latch excluding the scan function with respect to the pulse latch circuit DRPL. Since the scan path is not formed in the pulse latch circuit DRPLi, the circuit configuration can be simplified as compared with the pulse latch circuit DRPL. If the pulse latch circuit DRPLi is applied to a portion where the scan function is not necessarily required, the circuit scale can be further reduced. FIG. 25 illustrates a circuit configuration of a pulse latch excluding the scan function with respect to the pulse latch circuit DRPLh. Since the scan path is not formed in the pulse latch circuit DRPLj, the circuit configuration can be simplified as compared with the pulse latch circuit DRPLh. If the pulse latch circuit DRPLj is applied to a portion where the scan function is not necessarily required, the circuit scale can be further reduced.

It is explanatory drawing which illustrates the detail of the circuit structure of the pulse latch circuit DRPL. It is explanatory drawing which illustrates schematic structure of the semiconductor integrated circuit which concerns on embodiment of this invention. FIG. 3 is an explanatory diagram illustrating a schematic configuration of a clock supply system in a semiconductor integrated circuit LSI. It is explanatory drawing which illustrates the circuit structure of the pulse generation circuit PG. 6 is a timing chart showing operation timings in the actual operation mode of the pulse latch circuit DRPL. 4 is a timing chart showing operation timings in a scan operation mode of a pulse latch circuit DRPL. It is explanatory drawing which illustrates the circuit structure of the pulse latch circuit DRPLa. It is explanatory drawing which illustrates the circuit structure of the pulse latch circuit DRPLb. It is explanatory drawing which illustrates the circuit structure of the pulse latch circuit DRPLc. It is explanatory drawing which illustrates the circuit structure of pulse latch circuit DRPLd. It is explanatory drawing which illustrates the circuit structure of the pulse latch circuit DRPLe. It is explanatory drawing which illustrates the circuit structure of the pulse latch circuit DRPLf. It is explanatory drawing which illustrates the circuit structure of the pulse latch circuit DRPLg. It is explanatory drawing which illustrates a power supply structure with an inverter circuit. It is explanatory drawing which illustrates the layout of a power supply structure. It is explanatory drawing which illustrates the power supply of the various signals wired in the semiconductor integrated circuit LSI with the power supply structure of a logic circuit. It is explanatory drawing which illustrates schematic structure of the standby control circuit STBYC which controls the transition to various standby modes, and return. FIG. 3 is an explanatory diagram illustrating a schematic configuration of a test circuit disposed in a semiconductor integrated circuit LSI. It is explanatory drawing which illustrates the circuit structure of the pulse latch circuit from which the pulse latch circuit DRPL differs from a power supply interruption | blocking form. 6 is a timing chart showing the operation timing in the actual operation mode of the pulse latch circuit DRPLh. It is explanatory drawing which illustrates the other power supply structure of the pulse latch circuit DRPL and a logic circuit. It is explanatory drawing which illustrates the power supply structure illustrated in FIG. 21 using an inverter circuit. It is explanatory drawing which illustrates the layout of the power supply structure illustrated in FIG. It is explanatory drawing which illustrates the circuit structure of the pulse latch circuit without a scan function with respect to the pulse latch circuit DRPL. It is explanatory drawing which illustrates the circuit structure of the pulse latch circuit without a scan function with respect to the pulse latch circuit DRPLh.

Explanation of symbols

LSI Semiconductor integrated circuit DRPL Pulse latch circuit D Data input terminal Q Data output terminal SI Scan input terminal SO Scan output terminal SE Scan enable signal CLK Global clock CK Clock signal SCANCK Scan data transfer signal STR0 Data save signal RSTR Restore signal ML Master latch SL Slave Latch DT Data transfer circuit CKB Circuit block PSWC Power switch controller PSW1 Power switch VSSM Virtual ground line PG Pulse generation circuit TG Transmission gate INV Inverter circuit CINV Clocked inverter circuit MP P channel type MOS transistor MN N channel type MOS transistor

Claims (1)

It has a circuit block that can selectively cut off the power supply,
The circuit block includes a plurality of data holding elements disposed in the middle of the signal path and the test path,
The data holding element includes a first latch circuit that receives and latches data in synchronization with a clock that is targeted for power supply cutoff, a second latch circuit that statically latches data that is not targeted for power supply cutoff, and the first latch circuit A transfer circuit that selectively connects the storage node of one latch circuit and the storage node of the second latch circuit so that data can be transferred;
A first operation mode for propagating data input from the test path to the test path through the first latch circuit, the transfer circuit, and the second latch circuit;
A second operation mode in which data input from the signal path is propagated to the signal path through the first latch circuit;
A third operation mode for saving data stored in the first latch circuit to the second latch circuit through the transfer circuit when power supply is interrupted;
Have a, a fourth operation mode to return to the first latch circuit stores data through the transfer circuit of the second latch circuit when resuming the supply of the power supply,
The first latch circuit includes a data input terminal connected upstream of the signal path, a test data input terminal connected upstream of the test path, a clock input terminal for inputting a clock signal, and a clock input from the clock input terminal An input gate for inputting data from the data input terminal or the test data input terminal in response to a first state of the signal, and a second clock signal input from the clock input terminal to the data input from the input gate. A first static latch that latches in response to a state; and a data output terminal that outputs data stored in the first static latch downstream of the signal path;
The second latch circuit has a test output terminal for outputting storage information of the second static latch and the second static latch downstream of the test path,
The circuit block includes a ground switch used to cut off supply of operating power between the ground terminal of the semiconductor integrated circuit,
The first state of the clock signal is at a low level, and the period of the first state is shorter than the period of the second state of the clock signal .

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