JP4416682B2 - Semiconductor integrated circuit device - Google Patents

Description

The present invention relates to a semiconductor integrated circuit that performs a predetermined operation by applying a main power supply (for example, a core power supply), an input / output (hereinafter referred to as “I / O”) terminal, the semiconductor integrated circuit and I The present invention relates to a semiconductor integrated circuit device including an input / output circuit for signal transmission / reception (interface) connected between the / O terminals.

  Conventionally, as a technique related to a semiconductor integrated circuit device having an input / output circuit for performing an interface between the semiconductor integrated circuit and an I / O terminal, for example, there are those described in the following documents.

JP-A-5-259879 (FIG. 1) Japanese Patent Laying-Open No. 2003-332901 (FIG. 1)

  FIG. 5 is a schematic configuration diagram showing a conventional semiconductor integrated circuit device having an input / output circuit described in Patent Documents 1 and 2 and the like.

  The semiconductor integrated circuit device includes a semiconductor integrated circuit 10 that performs a predetermined logical operation or the like by a main power supply (for example, a core power supply) V1, and an input / output interface for signals to the semiconductor integrated circuit 10 that operates by an I / O power supply V2. And an I / O terminal (for example, I / O pad) 25 for transmitting / receiving signals to / from the input / output circuit 20 to the outside.

  The semiconductor integrated circuit 10 is operated by the core power supply V1, outputs the output enable signal OE and the output data signal OD to the input / output circuit 20, and inputs the input data signal ID given from the input / output circuit 20 from the input unit 11. Thus, the circuit performs a predetermined logical operation or the like. The input unit 11 in the semiconductor integrated circuit 10 includes, for example, a P-channel MOS transistor (hereinafter referred to as “PMOS”) 11a to which an input data signal ID is applied to the gate and an N to which the input data signal ID is applied to the gate. A channel type MOS transistor (hereinafter referred to as “NMOS”) 11b, and these PMOS 11a and NMOS 11b are connected in series between the power supply Vdd and the ground. The power source Vdd is a power source having the same potential as the core power source V1 or a predetermined potential generated from the core power source V1.

  The input / output circuit 20 has an I / O buffer circuit 21 that operates with an I / O power supply V2. The I / O buffer circuit 21 includes an output buffer 21 a connected between the semiconductor integrated circuit 10 and the I / O terminal 25, and between the I / O terminal 25 and the input unit 11 in the semiconductor integrated circuit 10. And an input buffer 21b connected thereto. The output buffer 21 a is configured by, for example, a tristate buffer, and is turned on by the “H” level (high level) of the output enable signal OE output from the semiconductor integrated circuit 10 and output from the semiconductor integrated circuit 10. The output data signal OD is driven and output to the I / O pad 25. The output enable signal OE is set to a high impedance state by the “L” level (low level) of the output enable signal OE, and the semiconductor integrated circuit 10 and the I / O terminal 25 are connected. It is a circuit that releases the gap. The input buffer 21 b is a circuit that drives the input data signal ID input from the I / O pad 25 and applies the input data signal ID to the input unit 11 in the semiconductor integrated circuit 10.

This type of semiconductor integrated circuit device is activated when the core power supply V1 and the I / O power supply V2 are applied, and in the input mode, the output enable signal OE of “L” level is output from the semiconductor integrated circuit 10 and output. The buffer 21a enters a high impedance state. Then, the input data signal ID input from the outside to the I / O pad 25 is driven by the input buffer 21 b and input to the input unit 11 in the integrated circuit 10. As a result, a predetermined logical operation or the like is performed in the semiconductor integrated circuit 10.

In the output mode, the semiconductor integrated circuit 10 outputs an “H” level output enable signal OE and an output data signal OD. Then, the output buffer 21 a is turned on by the “H” level output enable signal OE, and the output data signal OD is driven by the output buffer 21 a and output to the I / O pad 25.

  When the semiconductor integrated circuit device is set to the standby mode, for example, a core power supply that occupies most of the quiescent current while applying the I / O power supply V2 to keep the input / output circuit 20 in an operating state in order to speed up the rise. Only V1 is turned off to stop the operation of the semiconductor integrated circuit 10 to reduce power consumption.

  However, the conventional semiconductor integrated circuit device has the following problems (a) and (b).

(A) In order to reduce power consumption, in the standby mode, for example, with the I / O power supply V2 applied, the core power supply V1 that occupies most of the quiescent current is turned off and the semiconductor integrated circuit 10 The operation is stopped. At this time, since the output enable signal OE and the output data signal OD from the stopped semiconductor integrated circuit 10 become indeterminate outputs, the signal appearing on the I / O pad 25 becomes unstable by the output buffer 21a in the operating state. Or noise may occur. Therefore, damaged external devices connected to the I / O pads 25, there is a possibility that data in the external memory connected to the I / O pads 25 may be destroyed.

(B) In the standby mode, for example, when an “H” level signal is input from the I / O pad 25, the signal is driven by the input buffer 21b in an operating state, and an “H” level input data signal is input. The ID is given to the input unit 11 in the semiconductor integrated circuit 10. Therefore, the NMOS 11b of the input unit 11 is turned on, a circuit element (not shown) in the semiconductor integrated circuit 10 is latched up, and a large current flows from the power source to the ground side via the circuit element and the NMOS 11b. The circuit 10 may be damaged.

  In order to prevent the generation of a large current due to the latch-up, for example, an output enable signal is output between the output side of the input buffer 21b and the input unit 11 using the technique described in FIG. A configuration is possible in which a pull-down circuit such as an AND gate that opens and closes by OE is provided and the output side of the input buffer 21b is fixed to the ground potential by a pull-down circuit such as an AND gate in the standby mode. However, since the output enable signal OE from the stopped semiconductor integrated circuit 10 is an indefinite output, the output side of the input buffer 21b cannot be reliably fixed to the ground potential by a pull-down circuit such as an AND gate. Can not be adopted.

  The present invention solves such a conventional problem, and can prevent generation of a large current due to damage to an external device, an external memory or the like in a standby mode, or latch-up in the semiconductor integrated circuit. It is an object of the present invention to provide a device and a standby mode setting method thereof.

  In order to solve the above-described problems, a semiconductor integrated circuit device according to the present invention includes a semiconductor integrated circuit, an I / O terminal for inputting an external signal and outputting an external signal, the semiconductor integrated circuit, and the I And an input / output circuit connected to the / O terminal.

  The semiconductor integrated circuit operates by applying a main power supply that is turned on by the first potential of the first power supply switching signal having the first potential and the second potential or turned off by the second potential, and an output enable signal In addition, the output data signal is output and the selected data signal is input to perform a predetermined operation. The input / output circuit switches to the third potential when the first power supply switching signal is the first potential, and switches the second potential when the first power supply switching signal is switched from the first potential to the second potential. A second power source switching signal having a fourth potential is applied before, an I / O power source is applied, and the I / O power source is applied to operate the semiconductor integrated circuit and the I / O terminal. It is a circuit that exchanges signals between them.

  In the input / output circuit, the output enable signal output from the semiconductor integrated circuit is selected when the second power supply switching signal is the third potential, and a predetermined level is selected when the second power supply switching signal is the fourth potential. First selection means for selecting the first fixed signal, and when the second power supply switching signal is at the third potential, the output data signal output from the semiconductor integrated circuit is selected, and the second power supply switching signal is Second selection means for selecting a second fixed signal at a predetermined level when the fourth potential is selected, and an input data signal inputted when the second power source switching signal is the third potential, and the second power source switching before A third selection means for selecting a third fixed signal of "L" level when the signal is at the fourth potential, and supplying the selected data signal to be selected to the semiconductor integrated circuit; and the second selection Is connected between the stage and the I / O terminal, and is turned on or in a high impedance state by the signal selected by the first selection means, and when in the on state, drives the signal selected by the second selection means And output to the I / O terminal, and in the high impedance state, an output buffer for releasing the space between the second selection means and the I / O terminal, the I / O terminal and the third selection And an input buffer which is connected between the input and output means and drives the input data signal input from the I / O terminal and supplies the input data signal to the third selection means.

According to the semiconductor integrated circuit device of the present invention, when the standby mode is set, the second power supply switching signal is changed from the third potential to the fourth potential, and then the first power supply switching signal is changed from the first potential to the second potential. Since the main power supply (first power supply potential) is turned off, the signal state appearing at the I / O terminal before the main power supply is turned off is changed to the input state, “H” level signal output state, “ Among the L ″ level signal output states, it can be fixed to one specific state. In addition, since the input side of the semiconductor integrated circuit is fixed to the “L” level before the main power supply (first power supply potential) is turned off, the main power supply (first power supply potential) is turned off. If the I / O pin or al "H" level signal is applied, it is possible to prevent a large current due to latch-up or the like flowing through the semiconductor integrated circuit.

  In the semiconductor integrated circuit device of the best mode of the present invention, a semiconductor integrated circuit, an I / O pad for inputting and outputting an external signal, the semiconductor integrated circuit and the I / O pad, And an input / output circuit connected between them. The semiconductor integrated circuit is turned on by the first potential of the first power supply switching signal having the first potential (for example, “L” level) and the second potential (for example, “H” level) or turned off by the second potential. The circuit operates by applying a core power supply that enters a state, outputs an output enable signal and an output data signal, and inputs a selected data signal from an input unit to perform a predetermined operation. The input / output circuit has a third potential (eg, “L” level) when the first power supply switching signal is the first potential, and the second potential when the first power supply switching signal is switched from the first potential to the second potential. Before switching, a second power source switching signal that becomes a fourth potential (for example, “H” level) is applied, an I / O power source is applied, and the semiconductor integrated circuit operates by applying the I / O power source. And a circuit for transferring signals between the I / O terminals.

  When the standby mode is set, the second power supply switching signal applied to the input / output circuit is changed from the third potential to the fourth potential, and the output enable signal and output output from the semiconductor integrated circuit are output by the input / output circuit. A fixed signal of a predetermined level is output to the I / O terminal instead of the data signal, and an “L” level fixed signal is input to the input portion of the semiconductor integrated circuit instead of the input data signal input from the I / O terminal. give. Thereafter, the first power supply switching signal is changed from the first potential to the second potential, the main power applied to the semiconductor integrated circuit is turned off, and the semiconductor integrated circuit is set to the standby mode.

(Configuration of Example 1)
1A, 1B, and 1C are schematic configuration diagrams of a semiconductor integrated circuit device showing Embodiment 1 of the present invention. FIG. 1A is an overall configuration diagram, and FIG. ) Is a circuit diagram of the output enable signal fixing circuit and the output data signal fixing circuit in FIG. 4A, and FIG. 4C is a circuit diagram of the input data signal fixing circuit in FIG.

  As shown in FIG. 1A, the semiconductor integrated circuit device has a third circuit block (for example, a switching signal generation circuit) that generates a first power switching signal ST and a second power switching signal STB for switching to a standby mode. 30, a first circuit block (for example, a semiconductor integrated circuit) 40 that performs a predetermined logical operation or the like by a main power source (for example, a core power source) V 1 that is a first power source potential, and an I that is a second power source potential. A second circuit block (for example, an input / output circuit) 50 that operates by the / O power supply V2 and performs an input / output interface of signals to / from the semiconductor integrated circuit 40, and a signal between the input / output circuit 50 and the outside And an I / O terminal (for example, an I / O pad) 95.

  The switching signal generation circuit 30 is, for example, a circuit that is operated by the I / O power source V2, and a signal generation unit 31 that generates the second power source switching signal STB and the second power source switching signal STB are latched and delayed for a predetermined time. A latch circuit 32 for outputting the first power supply switching signal ST. The signal generation unit 31 outputs an “L” level power supply switching signal STB in the input mode and the output mode in accordance with a control signal output from the semiconductor integrated circuit 40, and “H” level power supply when the standby mode is set. It has a function of outputting the switching signal STB.

  The semiconductor integrated circuit 40 is operated by the core power supply V1, outputs the output enable signal OE and the output data signal OD to the input / output circuit 50, and inputs the non-selected data signal SID selected by the input / output circuit 50. It is a circuit that performs a predetermined logical operation or the like. The semiconductor integrated circuit 40 includes a core unit 41 that performs a predetermined logical operation, a switch element (for example, PMOS) 42 that controls on / off of the core power supply V1 supplied to the core unit 41, and a selected data signal. An input unit 43 and the like for inputting the SID to the core unit 41 are provided.

  The PMOS 42 is a transistor whose source and drain are connected to the core power supply V1 and the core section 41 and which is turned on / off by a power supply switching signal ST applied to the gate. The input unit 43 includes, for example, a PMOS 43a to which the selected data signal SID is applied to the gate and an NMOS 43b to which the selected data signal SID is applied to the gate. The source / drain of the PMOS 43a and the source / drain of the NMOS 43b The drain is connected in series between the power supply Vdd and the ground. The power source Vdd is a power source having the same potential as the core power source V1 or a predetermined potential generated from the core power source V1. The drain of the PMOS 43 a and the source of the NMOS 43 b are connected in common and connected to the core unit 41. A first signal line 44 for outputting an output enable signal OE and a second signal line 45 for outputting an output data signal OD are connected to the core unit 41 via an output unit (not shown), and further, a gate of a PMOS 43a and an NMOS 43b. The third signal line 46 for inputting the selected data signal SID is commonly connected to the gates of the first and second gates. An input / output circuit 50 is connected to the signal lines 44 to 46.

  The input / output circuit 50 is a circuit that operates with the I / O power source V 2, and is a first selection unit (for example, output enable) connected to the terminal 51 for inputting the second power source switching signal STB and the first signal line 44. Signal fixing circuit) 60, second selection means (for example, output data signal fixing circuit) 70 connected to the second signal line 45, and third selection means (for example, input data) connected to the third signal line 46. Signal fixing circuit 80) and these output enable signal fixing circuit 60, output data signal fixing circuit 70, and input data signal fixing circuit 80 are connected via first, second and third signal lines 63, 73, 83. I / O buffer circuit 90.

  The output enable signal fixing circuit 60 includes first signal lines 44 and 63, a first power source (for example, a fixed signal output circuit) 61 that supplies a first fixed signal (for example, a signal of “H” level), 1 signal lines 44 and 63 and a selector 62 connected to the fixed signal output circuit 61. The selector 62 outputs on the signal line 44 on the input side connected to the electrode “0” side when the second power supply switching signal STB input from the terminal 51 is at the third potential (eg, “L” level). The enable signal OE is selected and output to the signal line 63 on the output side. When the second power supply switching signal STB is at the fourth potential (eg, “H” level), the input connected to the electrode “1” side This is a circuit that selects an “H” level signal output from the fixed signal output circuit 61 on the side and outputs it to the signal line 63 on the output side.

  The output data signal fixing circuit 70 includes first signal lines 45 and 73, a second power source (for example, a fixed signal output circuit) 71 for supplying a second fixed signal (for example, a signal of “H” level), It is composed of two signal lines 45 and 73 and a selector 72 connected to the fixed signal output circuit 71. The selector 72 selects the output data signal OD on the input-side signal line 45 connected to the electrode “0” when the second power supply switching signal STB input from the terminal 51 is “L” level. “H” output from the fixed signal output circuit 71 on the input side connected to the electrode “1” when the second power supply switching signal STB is “H” level. This is a circuit that selects a level signal and outputs it to the signal line 73 on the output side.

  The input data signal fixing circuit 80 includes third signal lines 46 and 83, a third power source (for example, an L level signal output circuit) 81 for supplying a third fixed signal (for example, an “L” level signal), The third signal lines 46 and 83 and the selector 82 connected to the L level signal output circuit 81 are included. The selector 82 selects the input data signal ID on the input-side signal line 83 connected to the electrode “0” when the second power supply switching signal STB input from the terminal 51 is “L” level. The selected data signal SID is output to the signal line 46 on the output side, and when the second power supply switching signal STB is at “H” level, the input side L level signal output circuit 81 connected to the electrode “1” side. This is a circuit that selects the “L” level signal output from, and outputs the selected data signal SID to the signal line 46 on the output side.

  The I / O buffer circuit 90 includes an output buffer 91 connected between the signal lines 63 and 73 and the I / O pad 95, and an input buffer 92 connected between the I / O pad 95 and the signal line 83. It is comprised by. The output buffer 91 is configured by, for example, a tri-state buffer, and is turned on when the signal on the signal line 63 output from the selector 62 is at “H” level, for example, and the signal on the signal line 73 output from the selector 72. Is driven to output to the I / O pad 95. When the signal on the signal line 63 is at "L" level, a high impedance state is established, and the circuit between the signal line 73 and the I / O pad 95 is released. It is. The input buffer 92 is a circuit that drives the input data signal ID input from the I / O pad 95 and outputs it to the signal line 83.

  As shown in FIG. 1B, the output enable signal fixing circuit 60 is configured by, for example, a pull-up circuit. This pull-up circuit includes a resistor 61a and an NMOS 61b to which a power supply switching signal STB is applied to the gate. The source and drain of the resistor 61a and NMOS 61b correspond to the output signal of the fixed signal output circuit 61. The H ″ level I / O power source V2 and the signal lines 44 and 63 are connected in series. In such a configuration, when the power supply switching signal STB is at “L” level, the NMOS 61b is turned off, the output enable signal OE on the input signal line 44 is output as it is to the signal line 63, and the power supply switching signal STB is “ When it is at the “H” level, the NMOS 61b is turned on, and the “H” level of the I / O power supply V2 is output to the signal line 63 through the resistor 61a and the NMOS 61b.

  Similarly, as shown in FIG. 1B, the output data signal fixing circuit 70 is constituted by, for example, a pull-up circuit including a resistor 71a and an NMOS 71b. In such a configuration, when the power switch signal STB is at “L” level, the NMOS 71b is turned off, the output data signal OD on the input signal line 45 is output to the signal line 73 as it is, and the power switch signal STB is “ When it is at the “H” level, the NMOS 71b is turned on, and the “H” level of the I / O power supply V2 is output to the signal line 73 through the resistor 71a and the NMOS 71b.

  As shown in FIG. 1C, the input data signal fixing circuit 80 is configured by, for example, a pull-down circuit. This pull-down circuit has a resistor 81a and an NMOS 81b to which a power supply switching signal STB is applied to the gate. The source and drain of these resistor 81a and NMOS 81b are connected to signal lines 46 and 83 and an L level signal output circuit 81. Are connected in series with the “L” level ground corresponding to the output signal of the above. In such a configuration, when the power supply switching signal STB is at the “L” level, the NMOS 81b is turned off, and the input data signal ID on the input signal line 83 is directly output to the signal line 46 as the selected data signal SID. When the power supply switching signal STB is at “H” level, the NMOS 81b is turned on, and the “L” level of the ground potential is output to the signal line 46 through the NMOS 81b and the resistor 81a.

(Operation of Example 1)
In the semiconductor integrated circuit device of FIG. 1, operations in (1) input mode, (2) output mode, and (3) standby mode will be described.

(1) Input mode When the core power supply V1 and the I / O power supply V2 are applied, the switching signal generation circuit 30 and the input / output circuit 50 are activated. In the input mode, the “L” level power supply switching signal STB is output from the signal generation unit 31 in the switching signal generation circuit 30 and supplied to the terminal 51 of the input / output circuit 50. Then, the electrode “0” side of each selector 62, 72, 82 is selected in the input / output circuit 50, the signal lines 44 and 63 are conductive, the signal lines 45 and 73 are conductive, and the signal lines 83 and 46 becomes conductive.

  On the other hand, the “L” level power switching signal STB output from the signal generator 31 is latched by the latch circuit 32, and the “L” level power switching signal ST is output from the latch circuit 32 with a predetermined delay. The Then, the PMOS 42 in the semiconductor integrated circuit 40 is turned on, and internal circuits such as the core unit 41 and the input unit 43 in the semiconductor integrated circuit 40 are activated. When the internal circuit of the semiconductor integrated circuit 40 is activated, an “L” level output enable signal OE is output from the core unit 41 via an output unit (not shown). The “L” level output enable signal OE is supplied to the output buffer 91 via the signal line 44, the selector 62, and the signal line 63, and the output buffer 91 enters a high impedance state.

  When an input data signal ID is input from the outside to the I / O pad 95, the input data signal ID is driven by the input buffer 92, and the selected data signal is transmitted via the signal line 83, the selector 82, and the signal line 46. The SID is input to the input unit 43 in the semiconductor integrated circuit 40. As a result, a predetermined logical operation or the like is performed in the core unit 41.

(2) Output Mode In the output mode, the “H” level output enable signal OE and the “H” or “L” level output data signal OD are output from the core unit 41 in the semiconductor integrated circuit 40 through an output unit (not shown). Are output. The “H” level output enable signal OE is supplied to the output buffer 91 via the signal line 44, the selector 62 and the signal line 63, and the output buffer 91 is turned on. The “H” or “L” level output data signal OD output from the semiconductor integrated circuit 40 is sent to the output buffer 91 via the signal line 45, the selector 72 and the signal line 73, and is driven by this output buffer 91. To the I / O pad 95.

(3) Standby Mode FIG. 2 is a waveform diagram for explaining a standby mode setting method in the semiconductor integrated circuit device of FIG.

  When the standby mode is set while the core power source V1 and the I / O power source V2 are applied, the power source switching signal STB output from the signal generation unit 31 rises from the “L” level to the “H” level and is turned on. It is supplied to the terminal 51 of the output circuit 50. Then, the electrode “1” side of each selector 62, 72, 82 is selected in the input / output circuit 50, and the signal line 63 is fixed to the “H” level by the output of the fixed signal output circuit 61. The signal line 73 is fixed to “H” level by the output of 71, and the signal line 46 is fixed to “L” level by the output of the L level signal output circuit 81.

  When the power switching signal STB rises from the “L” level to the “H” level, it is latched by the latch circuit 32, and the power switching signal ST output from the latch circuit 32 is delayed for a predetermined time from the “L” level to the “H” level. Stand up to the H ”level. As a result, the PMOS 42 in the semiconductor integrated circuit 40 is turned off, the supply of the core power supply V1 is stopped, the operation of the semiconductor integrated circuit 40 is stopped, and the power consumption state is set. At this time, the output enable signal OE and the output data signal OD from the semiconductor integrated circuit 40 become indefinite outputs. However, since the signal lines 63 and 73 are fixed at the “H” level, the output of the output buffer 91 is fixed. The signal appearing on the I / O pad 95 is stable and no noise is generated.

  In this standby mode, for example, even if an “H” level signal is input from the I / O pad 95, the signal line 46 is fixed at the “L” level. Is supplied to the input unit 43 in the semiconductor integrated circuit 40. Therefore, the NMOS 43b of the input unit 43 is turned off, and generation of a large current due to latch-up or the like can be prevented in the internal circuit of the semiconductor integrated circuit 40.

(Effect of Example 1 etc.)
The first embodiment has the following effects (a) and (b).

(A) In the standby mode, the power supply switching signal STB input to the terminal 51 is set to “H” level, and then the PMOS 42 is turned off after a predetermined time delay. Therefore, before the core power supply V1 is turned off, The signal state appearing on the I / O pad 95 can be fixed to one specific state among the input state, the “H” level signal output state, and the “L” level signal output state. In addition, since the signal line 46 connected to the input unit 43 in the semiconductor integrated circuit 40 is fixed to the “L” level before the core power source V1 is turned off, the I / I is maintained with the core power source 40 turned off. When an “H” level signal is applied from the O pad 95, it is possible to prevent a large current from flowing through the semiconductor integrated circuit 40 due to latch-up or the like.

  (B) Although FIG. 1 illustrates a circuit configuration example in which data is fixed by inputting an “H” level power supply switching signal STB to the terminal 51, the present invention is not limited to this. For example, the PMOS 42 is replaced with an NMOS, and the electrodes “0” and “1” of the selectors 62, 72, and 82 are reversed, and the “L” level switching signal output from the signal generator 31 in the standby mode. By inputting the STB to the terminal 51, even if the circuit configuration is changed to fix the data, substantially the same operation and effect as in FIG. 1 can be obtained. Each fixed signal output circuit 61, 71 outputs an “L” level signal and fixes the signal lines 63, 73 to the “L” level, respectively. Action and effect are obtained.

(Configuration of Example 2)
3A and 3B are schematic configuration diagrams of a semiconductor integrated circuit device showing a second embodiment of the present invention. FIG. 3A is an overall configuration diagram, and FIG. 2 is a circuit diagram of an input data signal fixing circuit in FIG. In FIG. 3, elements common to the elements in FIG. 1 illustrating the first embodiment are denoted by common reference numerals.

  In the semiconductor integrated circuit device of FIG. 3A showing the second embodiment, a switching signal generating circuit 30A having a different configuration is provided in place of the switching signal generating circuit 30 of FIG. Instead of the input / output circuit 50, an input / output circuit 50A having a different configuration is provided.

  The switching signal generation circuit 30A is a circuit that is operated by, for example, the I / O power source V2, and includes a signal generation unit 31A having a configuration different from that of the first embodiment, a latch circuit 32 having the same configuration as that of the first embodiment, and the like. . The signal generation unit 31 uses the control signal output from the semiconductor integrated circuit 40 or the like to set the first fixed signal STB_OE of “H” or “L” level and “H” or “L” at a predetermined timing before switching to the standby mode. The second fixed signal STB_O of the level is generated and output, and the second power supply switching signal STB of the “L” level is set in the input mode and the output mode, and the “H” level is set and set in the standby mode. It has a function. The latch circuit 32 is a circuit that latches the “L” or “H” level second power supply switching signal STB output from the signal generator 30A and outputs the first power supply switching signal ST delayed by a predetermined time.

  The input / output circuit 50A is a circuit that operates with the I / O power supply V2, and receives the terminal 51 for inputting the same second power supply switching signal STB as in the first embodiment and the newly added first fixed signal STB_OE. A terminal 52, a terminal 53 for receiving a newly added second fixed signal STB_O, a first selection means (for example, an output enable signal fixing circuit) 60A having a configuration different from that of the first embodiment, and a configuration different from that of the first embodiment. Second selection means (for example, output data signal fixing circuit) 70A, third selection means (for example, input data signal fixing circuit) 80 having the same configuration as in the first embodiment, output enable signal fixing circuit 60A, output data An I / O buffer circuit 90 having the same configuration as that of the first embodiment connected to the signal fixing circuit 70A and the input data signal fixing circuit 80 via the first, second, and third signal lines 63, 73, and 83. Yes To have.

  In the output enable signal fixing circuit 60A, the fixed signal output circuit 61 of the first embodiment is deleted, and is configured by the first signal lines 44 and 63 and the selector 62 connected to the first signal lines 44 and 63 and the terminal 52. Has been. The selector 62 selects the output enable signal OE on the input-side signal line 44 connected to the electrode “0” when the second power supply switching signal STB input from the terminal 51 is “L” level. When output to the signal line 63 on the output side and the second power switching signal STB is at “H” level, it is at “H” or “L” level input from the terminal 52 connected to the electrode “1” side. This is a circuit that selects the first fixed signal STB_OE and outputs it to the signal line 63 on the output side.

  In the output data signal fixing circuit 70A, the fixed signal output circuit 71 of the first embodiment is deleted, and is constituted by the first signal lines 45 and 73 and the selector 72 connected to the second signal lines 45 and 73 and the terminal 53. Has been. The selector 72 selects the output data signal OD on the input-side signal line 45 connected to the electrode “0” when the second power supply switching signal STB input from the terminal 51 is “L” level. When output to the signal line 73 on the output side and the second power supply switching signal STB is at “H” level, it is at “H” or “L” level input from the terminal 53 connected to the electrode “1” side. This is a circuit that selects the second fixed signal STB_O signal and outputs it to the signal line 73 on the output side.

  As in the first embodiment, the input data signal fixing circuit 80 includes signal lines 46 and 83, an L level signal output circuit 81, and a selector 82. The input signal fixing circuit 80 is constituted by, for example, a pull-down circuit as shown in FIG.

(Operation of Example 2)
In the semiconductor integrated circuit device of FIG. 3, operations in (1) input mode, (2) output mode, and (3) standby mode will be described.

(1) Input mode When the core power supply V1 and the I / O power supply V2 are applied, the switching signal generation circuit 30A and the input / output circuit 50A are activated. In the input mode, the “L” level power supply switching signal STB is output from the signal generator 31A and supplied to the terminal 51 in substantially the same manner as in the first embodiment. Then, the electrode “0” side of each selector 62, 72, 82 is selected, the signal lines 44 and 63 are turned on, the signal lines 45 and 73 are turned on, and the signal lines 83 and 46 are turned on. On the other hand, the “L” level power switching signal STB output from the signal generator 31A is latched by the latch circuit 32, and the “L” level power switching signal ST is output from the latch circuit 32 with a predetermined delay. The Then, the PMOS 42 is turned on, and internal circuits such as the core unit 41 and the input unit 43 in the semiconductor integrated circuit 40 are activated.

  When the internal circuit of the semiconductor integrated circuit 40 is activated, an “L” level output enable signal OE is output from the core unit 41 via an output unit (not shown), and the output buffer 91 enters a high impedance state. When the input data signal ID is input from the outside to the I / O pad 95, the input data signal ID is driven by the input buffer 92, and the selected data signal SID is input to the input unit 43 in the semiconductor integrated circuit 40. The As a result, a predetermined logical operation or the like is performed in the core unit 41.

(2) Output Mode In the output mode, substantially in the same manner as in the first embodiment, the “H” level output enable signal OE and “H” or “ The output data signal OD at the L ″ level is output. The output buffer 91 is turned on by the “H” level output enable signal OE, the “H” or “L” level output data signal OD output from the semiconductor integrated circuit 40 is driven by the output buffer 91, and I / O pad 95 is output.

(3) Standby Mode FIG. 4 is a waveform diagram for explaining a standby mode setting method in the semiconductor integrated circuit device of FIG.

  With the core power source V1 and the I / O power source V2 applied, fixed signal STB_OE, STB_O of “H” level (or “L” level) is output in advance from the signal generator 31A and supplied to the terminals 52, 53. After that, when the standby mode is set, the power switch signal STB output from the signal generation unit 31A rises from the “L” level to the “H” level and is supplied to the terminal 51. Then, the electrode “1” side of each selector 62, 72, 82 is selected, and the signal line 63 is fixed to the “H” level (or “L” level) by the fixed signal STB_OE input from the terminal 52. The signal line 73 is fixed to the “H” level (or “L” level) by the fixed signal STB_O input from the signal, and the signal line 46 is fixed to the “L” level by the output of the L level signal output circuit 81. .

  When the power switching signal STB rises from the “L” level to the “H” level, it is latched by the latch circuit 32 as in the first embodiment, and the power switching signal ST output from the latch circuit 32 is delayed by a predetermined time. Then, the signal rises from the “L” level to the “H” level. As a result, the PMOS 42 is turned off, the supply of the core power supply V1 is stopped, the operation of the semiconductor integrated circuit 40 is stopped, and a low power consumption state is entered. At this time, the output enable signal OE and the output data signal OD from the semiconductor integrated circuit 40 become indefinite outputs. However, since the signal lines 63 and 73 are fixed at the “H” level (or “L” level), the output is performed. The output of the buffer 91 is fixed, the signal appearing on the I / O pad 95 is stable, and no noise is generated.

  Similarly to the first embodiment, in the standby mode, for example, even if an “H” level signal is input from the I / O pad 95, the signal line 46 is fixed at the “L” level. An “L” level signal is applied to the input unit 43 in the semiconductor integrated circuit 40. Therefore, the NMOS 43b of the input unit 43 is turned off, and generation of a large current due to latch-up or the like can be prevented in the internal circuit of the semiconductor integrated circuit 40.

(Effect of Example 2 etc.)
In Example 2, there are the following effects (A) to (C).
(A) There is an effect similar to (a) of the first embodiment.

  (B) The fixed signal output circuits 61 and 71 of the first embodiment are deleted from the input / output circuit 50A, and instead of this, the terminals 52 and 53 for inputting the fixed signals STB_OE and STB_O are provided. The circuit configuration of 50A can be simplified, and the power consumption in the input / output circuit 50A can be reduced.

  (C) As in the first embodiment, FIG. 3 illustrates a circuit configuration example in which data is fixed by inputting a power switching signal STB of “H” level to the terminal 51, but is not limited thereto. For example, the PMOS 42 is replaced with an NMOS, and the electrodes “0” and “1” of the selectors 62, 72, and 82 are reversed so that the “L” level switching signal STB output from the signal generator 31A in the standby mode. 3 is input to the terminal 51, even if the circuit configuration is changed to fix the data, substantially the same operation and effect as in FIG. 3 can be obtained.

  The present invention is not limited to the first and second embodiments, and various modifications can be made. As a third embodiment which is this modification, for example, there are the following (1) to (4).

  (1) The switching signal generation circuits 30 and 30A may be provided in the semiconductor integrated circuit 40 or may be changed to other circuit configurations. For example, instead of the latch circuit 32, a signal delay means composed of a plurality of stages of inverters or the like may be provided.

  (2) The PMOS 42 in the semiconductor integrated circuit 40 may be replaced with other switch means, or the input unit 43 may have another circuit configuration.

  (3) In the input / output circuits 50 and 50A, the selectors 62, 72, and 82 can be composed of various circuits such as a gate circuit. Alternatively, the fixed signal output circuits 61 and 71 may be replaced with “H” level or “L” level power supplies, or the L level signal output circuit 81 may be replaced with “L” level power supplies. Thereby, a circuit configuration can be simplified and power consumption can be reduced. Similarly, in the input / output circuit 50A, the terminals 52 and 53 may be replaced with a power supply of “H” level or “L” level, whereby the number of terminals can be reduced.

  (4) In the I / O buffer circuit 90 in the input / output circuits 50 and 50A, the output buffer 91 constituted by a tristate buffer is constituted by other elements such as a tristate inverter in which an input signal is inverted in an ON state. You may do it.

BRIEF DESCRIPTION OF THE DRAWINGS It is a schematic block diagram of the semiconductor integrated circuit device which shows Example 1 of this invention. FIG. 2 is a waveform diagram for explaining a standby mode setting method in the semiconductor integrated circuit device of FIG. 1. It is a schematic block diagram of the semiconductor integrated circuit device which shows Example 2 of this invention. FIG. 4 is a waveform diagram for explaining a standby mode setting method in the semiconductor integrated circuit device of FIG. 3. It is a schematic block diagram which shows the conventional semiconductor integrated circuit device.

Explanation of symbols

30, 30A switching signal generation circuit 40 semiconductor integrated circuit 50, 50A input / output circuit 51, 52, 53 terminal 60, 60A output enable signal fixing circuit 61, 71 fixed signal output circuit 62, 72, 82 selector 70 output data signal fixing circuit 80 input data signal fixing circuit 81 L level signal output circuit 90 I / O buffer circuit 91 output buffer 92 input buffer 95 I / O pad

Claims (5)

The first power supply switching signal having the first potential and the second potential is operated by applying a main power source that is turned on by the first potential or turned off by the second potential, and outputs an output enable signal and an output data signal And a semiconductor integrated circuit that inputs a selected data signal and performs a predetermined operation;
An input / output terminal for inputting an external signal and outputting an external signal;
It is connected between the semiconductor integrated circuit and the input / output terminal, and when the first power supply switching signal is the first potential, it becomes a third potential, and the first power supply switching signal is changed from the first potential to the second potential. When switching to the potential, the second power source switching signal that becomes the fourth potential is applied before switching the second potential, and the input / output power source is applied, and the operation is performed by the application of the input / output power source. An input / output circuit that exchanges signals between a semiconductor integrated circuit and the input / output terminals;
The input / output circuit is
When the second power supply switching signal is at the third potential, the output enable signal output from the semiconductor integrated circuit is selected, and when the second power supply switching signal is at the fourth potential, a first fixed signal of a predetermined level is selected. First selecting means for selecting;
When the second power supply switching signal is at the third potential, the output data signal output from the semiconductor integrated circuit is selected. When the second power supply switching signal is at the fourth potential, a second fixed signal of a predetermined level is selected. A second selection means for selecting;
When the second power supply switching signal is at the third potential, the input data signal is selected, and when the previous second power supply switching signal is at the fourth potential, the third fixed signal of “L” level is selected, Third selection means for supplying the selected data signal to be selected to the semiconductor integrated circuit;
Connected between the second selection means and the input / output terminal, and is turned on or in a high impedance state by a signal selected by the first selection means, and is selected by the second selection means in the on state. An output buffer that drives the output signal to output to the input / output terminal, and when in the high impedance state, releases the space between the second selection means and the input / output terminal;
An input buffer connected between the input / output terminal and the third selection means, and driving the input data signal input from the input / output terminal to supply to the third selection means;
A semiconductor integrated circuit device comprising: The semiconductor integrated circuit device according to claim 1.
The first selection means includes
A first signal line that transmits the output enable signal output from the semiconductor integrated circuit, a first power source that supplies the first fixed signal, and a first power line that is connected between the first signal line and the first power source. When the second power supply switching signal is at the third potential, the first signal line is disconnected from the first power supply. When the second power supply switching signal is at the fourth potential, the first signal line and the first power supply are disconnected. It is composed of a pull-up circuit or a pull-down circuit that connects to the first power source,
The second selection means includes
A second signal line for transmitting the output data signal output from the semiconductor integrated circuit; a second power source for supplying the second fixed signal; and a second power line connected between the second signal line and the second power source. When the second power supply switching signal is the third potential, the second signal line is disconnected from the second power supply, and when the second power supply switching signal is the fourth potential, the second signal line and the second power supply are disconnected. It is composed of a pull-up circuit or a pull-down circuit that connects to the second power source,
The third selection means includes
A third signal line for transmitting the input data signal output from the input buffer, a third power supply for ground potential for supplying the third fixed signal, and between the third signal line and the third power supply. When the second power source switching signal is at the third potential, the third signal line is disconnected from the third power source, and when the second power source switching signal is at the fourth potential, the third signal line is disconnected. And a third pull-down circuit connecting the third power source. The semiconductor integrated circuit device according to claim 1.
A first fixed signal output circuit for supplying the first fixed signal; a second fixed signal output circuit for supplying the second fixed signal; and a third fixed signal output circuit for supplying the third fixed signal; A semiconductor integrated circuit device provided in an input / output circuit . The semiconductor integrated circuit device according to claim 1.
A semiconductor integrated circuit comprising: a terminal for inputting the second power supply switching signal; a terminal for inputting the first fixed signal; and a terminal for inputting the second fixed signal. apparatus. The semiconductor integrated circuit device according to claim 3.
The first fixed signal output circuit and the second fixed signal output circuit are constituted by a power source having a predetermined potential, and the third fixed signal output circuit is constituted by a power source having a ground potential. apparatus.

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