CN102478872B - Electronic device and method - Google Patents
Electronic device and method Download PDFInfo
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- CN102478872B CN102478872B CN201010566316.9A CN201010566316A CN102478872B CN 102478872 B CN102478872 B CN 102478872B CN 201010566316 A CN201010566316 A CN 201010566316A CN 102478872 B CN102478872 B CN 102478872B
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Abstract
The invention discloses an electronic device and a method. The electronic device comprises a first module, a second module and a signal converter, wherein the first module comprises an input/output pad (I/O pad) so as to serve as an input/output interface of the electronic device with an external device; the first module supplies power as a first bias power source; the second module is coupled with the first module and comprises a buffer; the second module supplies power as a second bias power source; the signal converter is coupled between the first module and the second module; and the signal converter outputs a first preset bias value when one of the first and second bias power sources has reached the stable state and the other power source has not reached the stable state.
Description
Technical field
The present invention relates to a kind of electronic installation, relate in particular to a kind of electronic installation of definable initial steady state.
Background technology
In chip design, input and output pad (I/O PAD) is the path that chip is externally linked up.But; progress due to technique; the voltage of chip internal circuit can be different from the voltage of interface imput output circuit; that is inside may be supplied by different power supplys from the bias voltage at interface; but imput output circuit can be controlled its operation by chip internal circuit conventionally; so the necessary and sufficient condition that imput output circuit can come into operation is the used bias voltage of chip internal circuit and the bias voltage of imput output circuit is all stablized, is just unlikely to have misoperation and occurs.
Edge this, the inventor of this case works out a kind of electronic installation that voltage preset value is set that has, in particular to a kind of electronic installation with the setting of unstable state voltage preset value, it is that the signal that can improve imput output circuit in prior art need determine that the used bias voltage of chip internal circuit and the bias voltage of imput output circuit all reach the stable present situation that just can bring into use.
Summary of the invention
One of object of the present invention is to operate about providing a defined voltage reference value to give the stable circuit of power supply for unstabilized power unit still between each different bias voltage of imput output circuit, to guarantee to be coupled in the interlock circuit of stabilized power source, can first substantially operate, need not wait for unstabilized power supply, and after all power is stable, can normally use the repertoire of digital IO pad, to solve the problem of prior art, the time that so can also accelerate start or restart power supply.
The present invention discloses a kind of electronic installation, and it comprises:
The first module, comprises the interface that input and output pad (I/O pad) is usingd as this electronic installation and external device (ED) input and output, and this first module is powered with the first grid bias power supply;
The second module, couples this first module, comprises buffer,
This second module is powered with the second grid bias power supply; And
Signal converter, couples between this first module and the second module;
Wherein, this signal converter reaches stable state at this one of them power supply of first and second bias generator, and when wherein another power supply does not reach stable state, the default bias value of output first.
The present invention discloses a kind of method for electronic installation, and its step comprises:
Provide the first grid bias power supply to the first module, and this first module comprises the interface that input and output pad (I/Opad) is usingd as this electronic installation and external device (ED) input and output;
Provide the second grid bias power supply to the second module coupling with this first module, and this second module comprise buffer;
When this one of them power supply of first and second grid bias power supply reaches stable state, and when wherein another power supply does not reach stable state, be coupled to the default bias value of signal converter output first of this first and second intermodule.
For making your juror have further understanding and approval for structure object of the present invention and effect, hereby coordinate accompanying drawing example to be described in detail as follows.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of an embodiment of electronic installation of the present invention;
Fig. 2 is the schematic diagram of an embodiment of the preset value initialization circuit of original definition circuit of the present invention;
Fig. 3 A/ Fig. 3 B is the schematic diagram of embodiment of the power supply stable state testing circuit of original definition circuit of the present invention; And
Fig. 4 is the schematic diagram of an embodiment of the chip with original definition circuit of the present invention.
Primary clustering symbol description
101 first bias voltage 101a chip imput output circuits
102 second bias voltage 102a chip internal circuit
103 first original definition circuit 104 second original definition circuit
20 preset value initialization circuit 201 first reversers
202 second reverser 203 the first transistors
204 transistor secondses 205 the 3rd transistor
206/207 rejection gate 30 power supply stable state testing circuits
301 reverser 302 the first transistors
303 resistance 304 transistor secondses
305 reverser 40 chips
401 enable pin 402 resistance
403P transistor npn npn 404 first signal converters
405 first impact damper 406 secondary signal converters
407 the 3rd signal converter 408 the 4th signal converters
409 chip internal circuit 410 chip imput output circuits
411 second impact dampers
Embodiment
One of object of the present invention is the imput output circuit framework that proposes definable initial steady state, to solve the problem of prior art.
Fig. 1 is an embodiment of the electronic installation of definable initial steady state of the present invention, and it has two power supplys, i.e. the first bias voltage (IO Power) the 101, second bias voltage (CORE Power) 102.The power supply that wherein the first bias voltage 101 is used for chip imput output circuit 101a; The power supply that the second bias voltage 102 is used for chip internal circuit 102a; And the voltage quasi position of common the first bias voltage 101 can be than the second bias voltage 102 height.First signal Sig_IO2CORE represents to be offered by chip imput output circuit 101a the signal of chip internal circuit 102a, and secondary signal Sig_CORE2IO represents to be offered by chip internal circuit 102a the signal of chip imput output circuit 101a.Wherein, chip internal circuit 102a can be chip internal circuit miscellaneous, can comprise as processor, totalizer, internal memory, buffer, impact damper or various mimic channel ... etc.
Before the first bias voltage 101 is not yet stable, first signal Sig_IO2CORE can not be used as the input of chip internal circuit 102a, for example, so apply initial preset value (voltage) that the first original definition circuit (DefinedInitial Circuit) 103 sets the first initialize signal Ini_Sig_IO2CORE to provide chip internal circuit 102a to use at us, so as long as the second bias voltage 102 is to steady state (SS), the circuit of chip internal circuit 102a part can start to operate, and does not need to wait for that the first bias voltage 101 is stable.Identical, when the first bias voltage 101 is to steady state (SS), and before the second bias voltage 102 is not yet stable, secondary signal Sig_CORE2IO can not be used as the input of chip imput output circuit 101a, therefore, now chip imput output circuit 101a can also for example, can start to operate with the initial preset value (voltage) that application the second original definition circuit 104 is set the second initialize signal Ini_Sig_CORE2IO, does not need to wait the second bias voltage 102 stable.The present invention can see through original definition circuit and completely cut off unstable grid bias power supply to using the impact of the circuit (as one of chip internal circuit 102a or chip imput output circuit 101a) of stable grid bias power supply, the time that further can accelerate start or restart power supply.At this, grid bias power supply is unstable refer to grid bias power supply still unstabilized be maintained at can critical (threshold) voltage of operate high voltage on.
Original definition signal of destination that original definition circuit can be when coming source voltage terminal not yet to stablize gives voltage stabilization according to specification definition is to carry out circuit operation.The second original definition circuit of take is example, and it carrys out source voltage terminal is the second bias voltage, and its destination voltage is the first bias voltage.
Preferably, original definition circuit can be realized among chip imput output circuit.
Same, if electronic system has three kinds of above different bias voltages, an alternative embodiment of the invention can be separately positioned on original definition circuit between the imput output circuit and internal circuit of different bias voltages.
Original definition circuit can comprise preset value initialization circuit and stable state testing circuit.Fig. 2 is an embodiment of the preset value initialization circuit 20 of original definition circuit of the present invention, preset value initialization circuit 20, see through detecting chip internal circuit 102a or chip imput output circuit 101a whether in the power supply supply of stable state, can be when the accurate skew in position (level shift) be provided, at grid bias power supply or while being input as unstable state automatically the default initial value of output (in this example, initial value is 1, is also the bias voltage level of destination).
Preset value initialization circuit 20, comprises: the first reverser 201; The second reverser 202, the input/output terminal of its input/output terminal and the first reverser 201 oppositely joins; The first transistor 203, in order to the input voltage of drop-down (pull down) the first reverser 201; Transistor seconds 204, in order to the input voltage of drop-down (pull down) this second reverser 202; And many groups the 3rd transistor 205 and two rejection gates 206,207, in order to receive stable state testing circuit (after a while diagram) output (for example come source power supply not during stable state this power supply stable state detect be output as noble potential) and (carrying out source) input signal, to determine this first transistor 203 and the whether drop-down reverser 201 of this transistor seconds 204 or reverser 202.In this embodiment, when the detection of power supply stable state is output as noble potential, why no matter input, be output as default initial value 1.
Fig. 3 A is an embodiment of the stable state testing circuit 30 of original definition circuit of the present invention, take the first bias voltage 101 of the present invention and the second bias voltage 102 is example, it comprises: the first reverser 301, accept the bias voltage (as the first bias voltage 101) of this stable state testing circuit 30; The first transistor 302 (in this case P type), its grid is controlled by the output of reverser 301, and its drain feedback signal is to the input of reverser 301; Resistance 303, its one end is connected to the bias voltage of this stable state testing circuit 30, in order to set the initial value of reverser 301 inputs; And transistor seconds 304 (in this case N-type), the power supply that its grid is not selected by this (as the second bias voltage 102) is controlled, with the input of this reverser 301 that discharges; The second reverser 305, in order to couple the grid of this reverser 301 and this first transistor 302.Wherein the breadth length ratio of transistor seconds 304 can select the stable state that is beneficial to greatly the second bias voltage 102 compared with the first transistor 302 correctly to be learnt.In this embodiment, when the first bias voltage 101 is 1 and the second bias voltage 102 while being not 1, power supply stable state detects and is output as 1.
Fig. 3 B is another embodiment of stable state testing circuit 30 of the present invention, and wherein one end of resistance 303 is connected to the bias voltage of this stable state testing circuit 30, in order to set the initial value of reverser 301 outputs; The first transistor 302 (in this case N-type), its grid is controlled by the output of reverser 301, and its drain feedback signal is to the input of reverser 301; And the power supply that transistor seconds 304 its grids are not selected by this (as the second bias voltage 102) is controlled, with the output of this reverser 301 that discharges.In this embodiment, when the first bias voltage 101 is 1 and the second bias voltage 102 while being not 1, power supply stable state detects and is output as 1.
Also can phase double replacement at this first bias voltage 101/ second bias voltage 102, repeat no more.
Fig. 4 is the schematic diagram of an embodiment of the chip with original definition circuit of the present invention, it comprises the first module (chip imput output circuit 410), it comprises the interface that input and output pad (IO pad) is usingd as this electronic installation and external device (ED) input and output, and can accept the power supply that the first grid bias power supply provides, the second module (chip internal circuit 409), couple this first module and comprise buffer (not shown), it can receive power supply and signal converter (404 that the second grid bias power supply provides, 406, 407 or 408), be coupled between this first module and the second module, and wherein signal converter reaches stable state at one of them power supply of this first and second grid bias power supply (101 and 102), and when wherein another power supply does not reach stable state, the default bias value of output first.More particularly, the present embodiment discloses the chip 40 with enable pin 401, chip 40 is coupled to main device (host) or external circuit 40a via enable pin 401, and has chip internal circuit 409 and chip imput output circuit 410 and by the second bias voltage 102 and the first bias voltage 101, provide required power supply respectively.
Chip imput output circuit 410 further includes resistance 402 and P transistor npn npn 403 is coupled to the first bias voltage, and the grid of this P transistor npn npn 403 is coupled to first signal converter 404 and is controlled by the output of 404 original definition circuit.In Fig. 4 signal converter (404,406,407 or 408) low/high and high/low be represent an accurate off-centre circuit, in order to accept the input signal by this first or second one of them Power supply of grid bias power supply, and input signal is converted to by another power supply wherein and is powered.Chip imput output circuit 410 can separately comprise input and output pad (not shown) and using the interface with external circuit input and output as chip 40 at enable pin 401 places.
Preferably, chip 40 further comprises the first impact damper 405, can drive this enable pin 401.The first impact damper 405 is to receive the output of original definition circuit of secondary signal converter 406 output of accepting the 3rd signal converter 407 to drive this enable pin 401 by this impact damper.
Preferably, chip 40 further comprises the second impact damper 411, to receive signal to drive the 4th signal converter 408, the four signal converters 408 can provide initial set value to supply this chip internal circuit as enabling initial setting when the second bias voltage does not enter stable state by this enable pin 401.
Original definition circuit in this signal converter 404,406,407 and 408, its initial preset value can enable specification and set according to different integrated circuit, does not repeat them here.
Preferably, can replace with the preset value initialization circuit of Fig. 2 and the power supply stable state testing circuit of Fig. 3 the function of position accurate off-centre circuit and original definition circuit in above-mentioned signal converter.
Only as described above, be only example embodiment of the present invention, when can not with the scope implemented of restriction the present invention.The equalization generally done according to the present patent application the scope of the claims changes and modifies, and all should still belong in the scope that patent of the present invention contains, sincerely please your juror's explicit example for reference, and pray Hui Zhun, be to praying.
Claims (12)
1. an electronic installation, it comprises:
One first module, comprises the interface that an input and output pad (I/O pad) is usingd as described electronic installation and external device (ED) input and output, and described the first module is powered with one first grid bias power supply;
One second module, couples described the first module, comprises a buffer, and described the second module is powered with one second grid bias power supply; And
One signal converter, couples between described the first module and the second module;
Wherein, described signal converter reaches stable state at described one of them power supply of first and second grid bias power supply, and when wherein another power supply does not reach stable state, the default bias value of output one first.
2. electronic installation according to claim 1, wherein, described signal converter comprises:
One stable state testing circuit chooses a kind ofly as its bias voltage, to detect another bias voltage not being selected, whether arrive stable state in described the first grid bias power supply or described the second grid bias power supply, to produce a power supply stable state, detects output; And
One original definition circuit, when described power supply stable state detection output represents not arrive stable state, exports the described first default bias value.
3. electronic installation according to claim 2, wherein, described signal converter is accepted the one second module input from described the second module, when described power supply stable state detection output represents that described the second grid bias power supply does not arrive stable state, described the second module input is converted to the described first default bias value.
4. electronic installation according to claim 2, wherein, when described power supply stable state detects output and represents that described the second grid bias power supply does not arrive stable state, described the first module receives sets described buffer from an external device (ED) input of described external device (ED).
5. electronic installation according to claim 2, wherein, described signal converter separately comprises:
An accurate off-centre circuit, in order to accept the input signal by described first or second one of them Power supply of grid bias power supply, and is converted to input signal by another power supply wherein and powers.
6. electronic installation according to claim 1, wherein, described electronic installation is established in a chip.
7. electronic installation according to claim 2, wherein, described stable state testing circuit comprises:
One first reverser, accepts the bias voltage of described stable state testing circuit;
One the first transistor, its grid is controlled by the output of described reverser, and its drain feedback signal is to the input of described reverser;
One resistance, its one end is connected to the bias voltage of described stable state testing circuit, in order to set the initial value of described reverser output or input;
One transistor seconds, its grid is controlled by the described power supply not being selected, with output or the input of the described reverser that discharges; And
One second reverser, is coupled to the grid of described the first reverser and described the first transistor.
8. electronic installation according to claim 2, wherein, described original definition circuit comprises:
One first reverser;
One second reverser, the input/output terminal of the input/output terminal of described the second reverser and described the first reverser oppositely joins;
One the first transistor, in order to the input voltage of drop-down (pull down) described the first reverser;
One transistor seconds, in order to the input voltage of drop-down described the second reverser; And
The 3rd transistor of group more than, detects output and an input signal in order to receive described power supply stable state, to determine whether drop-down described first, second reverser of described the first transistor and described transistor seconds.
9. for a method for electronic installation, its step comprises:
Provide one first grid bias power supply to the first module, and described the first module comprises the interface that an input and output pad is usingd as described electronic installation and external device (ED) input and output;
Provide one second grid bias power supply to one second module coupling with described the first module, and described the second module comprise a buffer;
When described one of them power supply of first and second grid bias power supply reaches stable state, and when wherein another power supply does not reach stable state, the default bias value of output one first.
10. method according to claim 9, wherein also comprises:
In described the first grid bias power supply or described the second grid bias power supply, choose a kind ofly as its bias voltage, to detect another bias voltage not being selected, whether arrive stable state, to produce a power supply stable state, detect output; And
When described power supply stable state detection output represents not arrive stable state, export the described first default bias value.
11. methods according to claim 10, also comprise:
Acceptance is inputted from one second module of described the second module, and when described power supply stable state detection output represents that described the second grid bias power supply does not arrive stable state, described the second module input is converted to described first and presets bias value.
12. methods according to claim 10, also comprise:
When described power supply stable state detection output represents that described the second grid bias power supply does not arrive stable state, described the first module receives sets described buffer from an external device (ED) input of described external device (ED).
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| Application Number | Priority Date | Filing Date | Title |
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| CN201010566316.9A CN102478872B (en) | 2010-11-29 | 2010-11-29 | Electronic device and method |
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| CN201010566316.9A CN102478872B (en) | 2010-11-29 | 2010-11-29 | Electronic device and method |
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| CN102478872A CN102478872A (en) | 2012-05-30 |
| CN102478872B true CN102478872B (en) | 2014-07-16 |
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| CN115686164A (en) * | 2021-07-26 | 2023-02-03 | 瑞昱半导体股份有限公司 | Power supply terminal device, power supply system and non-transitory computer readable medium |
| CN115328252B (en) * | 2022-08-29 | 2023-11-03 | 复旦大学 | Operational amplifier circuit and LDO circuit |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6342802B1 (en) * | 1999-10-28 | 2002-01-29 | Seagate Technology Llc | Multi-voltage power-up stable input/output buffer circuit in a disc drive |
| CN101488748A (en) * | 2009-02-13 | 2009-07-22 | 电子科技大学 | Field programmable gate array |
| JP4416682B2 (en) * | 2005-03-15 | 2010-02-17 | Ｏｋｉセミコンダクタ株式会社 | Semiconductor integrated circuit device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100609039B1 (en) * | 2004-06-30 | 2006-08-10 | 주식회사 하이닉스반도체 | Input/output line circuit |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6342802B1 (en) * | 1999-10-28 | 2002-01-29 | Seagate Technology Llc | Multi-voltage power-up stable input/output buffer circuit in a disc drive |
| JP4416682B2 (en) * | 2005-03-15 | 2010-02-17 | Ｏｋｉセミコンダクタ株式会社 | Semiconductor integrated circuit device |
| CN101488748A (en) * | 2009-02-13 | 2009-07-22 | 电子科技大学 | Field programmable gate array |
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