JP4855283B2 - Semiconductor integrated circuit design equipment - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit design apparatus, and more particularly to a semiconductor integrated circuit design apparatus having a plurality of power supply systems.

  In recent semiconductor integrated circuit designs, there is an increasing demand for low power consumption. As a technique for realizing low power consumption, a semiconductor integrated circuit is configured using a plurality of power supply systems, and power is supplied. However, technologies that cut power supply to the relevant part to reduce leakage current, reduce the power supply voltage value, reduce the circuit activation rate, and reduce charging / discharging power at unnecessary parts. Has been developed.

  When creating logic connection information (netlist) for semiconductor integrated circuits, it is a logic synthesis tool that creates logic connection information at the gate level when designing large-scale and complex semiconductor integrated circuits (LSIs). The system is only used to express a logical value of 0 or 1, and has no concept of distinguishing power sources.

  For example, in Patent Document 1, as a simulation method of a multi-power supply circuit, cells called pseudo power supply cells are embedded in each logic hierarchy, and the power supply cutoff or supply state is determined. A technique is disclosed in which the propagation of input patterns is suppressed and the logic simulation is executed only in the logic hierarchy to which power is supplied to reduce the logic simulation time.

  To perform layout verification, power consumption analysis, voltage drop analysis, and timing analysis in the design of large-scale and complicated semiconductor integrated circuits with multiple power supply systems, the potential information for each power supply system is distinguished from each other. Power connection information such as giving is required.

  For example, in layout verification, circuit connection information is created by treating a plurality of power sources as a single power source in a pseudo manner, and verification is performed by comparing with circuit connection information extracted from layout data. However, since it is not possible to verify that the power supply system is a multi-power supply system, an electrical connection verification (Electrical Rule Checker: ERC) method or the like is used to verify whether or not they are electrically separated.

  Also, in the physical layout, the power supply system is often not separated for each logical hierarchy, and it is not possible to set what kind of power is supplied for each logical hierarchy or instance even in the delay calculation executed during timing analysis. Since it is difficult, delay calculation is performed for each module with different power supply systems.

  The same applies to the power consumption analysis, and it is difficult to set what kind of power is supplied for each logical hierarchy or instance, so power consumption is calculated for each module of a different power system.

  Therefore, in the design of an SOC (System On a Chip) having a plurality of power supply systems, even if there are a plurality of power supply systems, they are treated as a single power supply system in a pseudo manner and information indicating that there are a plurality of power supplies is provided. In order to be reflected in layout verification, power consumption analysis, voltage drop analysis, timing analysis, etc., the designer must process the data for each design process and prepare the setting file manually each time. It was.

  In addition, the information that there are a plurality of power supply systems can only be given for each logical hierarchy when the logical connection information is handled as logical circuit diagram data as in the conventional case, and the power supply closed in the intermediate hierarchy cannot be expressed. For a large-scale and complicated semiconductor integrated circuit, the work is complicated and it is difficult to accurately define the power supply system.

JP 2002-259487 A

  As described above, in designing a semiconductor integrated circuit having a plurality of power supply systems, it is difficult to separate the power supply systems and provide potential information for each power supply system. Etc., and there is a problem that verification according to the actual circuit configuration cannot be performed.

  The present invention has been made to solve the above problems, and in designing a semiconductor integrated circuit having a plurality of power supply systems, a semiconductor integrated circuit design apparatus capable of performing verification according to an actual circuit configuration. The purpose is to provide.

  In one embodiment of the present invention, the following semiconductor integrated circuit design apparatus is disclosed. That is, the netlist generation / conversion device is given a netlist output from the logic synthesis device and a power supply specification file read from the power supply specification file storage unit. The power supply specification file is a file set in advance based on the design specification, and defines connection information for a plurality of power supply systems.

  The netlist generation / conversion device generates and converts a netlist based on the netlist and the power supply specification file, and outputs a netlist with a power supply net name and a power supply net generation command as a netlist for layout.

  The net list with the power net name and the power net generation command are given to the automatic placement and routing apparatus, and automatic placement and routing is executed.

  According to the above embodiment, it is possible to automatically define power connection information not only in the logical hierarchy but also in the physical hierarchy, preventing the occurrence of mistakes caused by manual labor so far, which has been difficult until now. Therefore, it is possible to define the power supply connection for a large-scale and complicated semiconductor integrated circuit.

<A. Embodiment 1>
With reference to the configuration of the semiconductor integrated circuit design apparatus 100 shown in FIG. 1, the operation of the semiconductor integrated circuit design apparatus 100 according to the first embodiment of the present invention will be described with reference to the flowchart shown in FIG.

  As shown in FIG. 1, a semiconductor integrated circuit design device 100 includes a logic synthesis device 1, a netlist generation / conversion device 2, an automatic placement and routing device 3, a power specification file storage unit 4, and an HDL data storage unit 5. Yes.

  The logic synthesis device 1 reads design data D1 of a level (RTL: Register Transfer Level) in which a circuit is expressed by a combination of a flip-flop and a logic circuit in hardware description language (HDL) from the HDL data storage unit 5. Based on the design data D1, logical synthesis (step S101) is performed to create logical connection information (netlist) D2.

  Further, the netlist generation / conversion device 2 is given a netlist D2 output from the logic synthesis device 1 and a power supply specification file D3 read from the power supply specification file storage unit 4. The power supply specification file D3 is a file set in advance based on the design specification, and defines connection information of a plurality of power supply systems.

  The netlist generation / conversion device 2 generates and converts a netlist based on the netlist D2 and the power supply specification file D3 (step S102), and generates a netlist D4 with a power supply net name and a power supply net as a layout netlist. Command D5 is output.

  The net list with power net name D4 and the power net generation command D5 are given to the automatic placement and routing apparatus 3, and automatic placement and routing are executed (step S103).

  The netlist D2 does not include power supply information about individual cells. Conventionally, the operator changed the power supply information into a format that can be read by the automatic placement and routing apparatus based on the power supply specifications, together with the netlist, Although given to the automatic placement and routing apparatus, in the present invention, the power connection information can be automatically defined.

  Here, an example of content defined in the power supply specification file D3 will be described with reference to FIG. As shown in FIG. 3, the power supply specification file D3 includes a power supply region defining unit, a power supply connection defining unit, and an additional cell information defining unit.

  The power source region defining unit defines a power source region on the layout of the semiconductor integrated circuit, and defines a module name or instance name belonging to each power source region. Here, a module is a block indicating a predetermined function. The module is composed of a plurality of basic units (cells), and each cell is given a unique name for identification, which is referred to as an instance name. Yes.

  In the example of FIG. 3, X4, X5, etc. represent module names, SW * represents an instance having an instance name beginning with SW, and modules X4 and X5 are arranged in power supply areas Area1 and 2, respectively. An instance having an instance name starting with "" is defined to be arranged in the power supply area Area3.

  In the power connection specification definition section, for each power supply area defined in the power supply area definition section, the power supply terminal name and ground terminal name in the area, and the power supply net name and ground net name to be connected to them are assigned to them. Define connection information such as voltage values and other control information. In addition, the additional cell information definition unit defines a power control cell such as a power shut-off switch cell that is required when the power is shut off.

  In the netlist generation / conversion device 2, based on the information in the power supply specification file D3, any of the plurality of cells having a terminal to which the input logic level is always “0” or always “1” is applied. A power supply net generation command D5 that defines which power supply terminal and ground terminal of each cell are connected is created. .

  As described above, the semiconductor integrated circuit design apparatus 100 according to the first embodiment uses the power supply specification file D3 in which connection information of a plurality of power supply systems is defined, so that the power supply network is based on the netlist. The named netlist D4 and the power supply net generation command D5 can be automatically acquired. Therefore, it is possible to automatically define the power connection information not only for the logical hierarchy but also for the physical hierarchy, preventing the occurrence of mistakes due to manual labor, which has been difficult until now. It is possible to define a power supply connection for a complicated semiconductor integrated circuit.

<Modification>
Next, with reference to the configuration of the semiconductor integrated circuit design apparatus 100A shown in FIG. 4, the operation of the semiconductor integrated circuit design apparatus 100A will be described with reference to the configuration of the semiconductor integrated circuit design apparatus 100A shown in FIG. . In addition, the same code | symbol is attached | subjected about the structure same as Embodiment 1 demonstrated using FIG. 1 and FIG. 2, and the overlapping description is abbreviate | omitted.

  As shown in FIG. 4, in the semiconductor integrated circuit design device 100A, a unique instance name of a cell to be added is defined in advance in the power supply specification file D3 as necessary, and in the netlist generation / conversion device 2, the netlist D2 A netlist is generated and converted based on the power supply specification file D3 (step S102), and a power supply net named netlist D4, a power supply net generation command D5, and an additional cell insertion command D6 are output.

  The net list with power net name D4, the power net generation command D5, and the additional cell insertion command D6 are given to the automatic placement and routing apparatus 3, and automatic placement and routing are executed (step S103).

  An example of the unique instance name of the cell added by the user is shown in the additional cell information definition part of the power specification file D3 described with reference to FIG. Based on the above, an additional cell insertion command D6 is generated that defines in which power supply area the additional cell is arranged and to which power supply net is connected.

  Here, the unique instance name is used because it is not allowed to duplicate the instance name in the same design, so it is necessary to give a name that does not overlap with the other. In the example shown in FIG. 3, SW1 in the additional cell information definition unit corresponds.

  The additional cell information having a unique instance name includes information on which power supply region the cell is added to, and in the example shown in FIG. 3, the cell PSW given the instance name SW1 is added to the power supply region Area3. Become. The cell PSW is a cell constituting the module X7.

  Since the netlist (logical connection information) D2 does not include power supply information, the netlist generation / conversion device 2 can generate a power supply net generation command that can be recognized by the automatic placement and routing apparatus 3 in accordance with the specifications defined in the power supply specification file D3. D5 and additional cell insertion command D6 are generated.

  The automatic placement and routing apparatus 3 generates power connection information (power net) according to the power net generation command D5, and adds a cell according to the additional cell insertion command D6.

  Note that the additional cell assumed here changes only the power connection information without changing the logical connection information.

  As described above, in the semiconductor integrated circuit design apparatus 100A according to the modification of the first embodiment, the net list generation / conversion apparatus 2 generates the additional cell insertion command D6 and gives it to the automatic placement and routing apparatus 3. Therefore, in the automatic placement and routing apparatus 3, it becomes possible to additionally place necessary cells as specified in a specific power supply region.

  The cells defined in the additional cell information definition section of the power specification file D3 are not limited to the power control cells, but are the capacities arranged in the gap region for the purpose of reducing noise generated in the power wiring. In order to satisfy the cell and the design rule, a gap cell arranged in the gap area may be defined.

  These are cells that are not included in the initial netlist and are added as needed in a layout process such as automatic placement and routing. By defining the instance names of these additional cells in advance in the power supply specification file D3, the netlist generation / conversion device 2 generates an additional cell insertion command D6 for adding the specified cell to the specified power supply area. The automatic placement and routing apparatus 3 can be arranged according to the power supply specifications.

<B. Second Embodiment>
With reference to the configuration of the semiconductor integrated circuit design apparatus 200 shown in FIG. 6, the operation of the semiconductor integrated circuit design apparatus 200 according to the second embodiment of the present invention will be described with reference to the flowchart shown in FIG.

  As shown in FIG. 6, a semiconductor integrated circuit design device 200 includes a logic synthesis device 1, a netlist generation / conversion device 2, a power specification file storage unit 4, an HDL data storage unit 5, a logic simulation device 6, and a test pattern storage. Unit 7 and cell library storage unit 8. In addition, the same code | symbol is attached | subjected about the structure same as Embodiment 1 demonstrated using FIG. 1 and FIG. 2, and the overlapping description is abbreviate | omitted.

  The netlist generation / conversion device 2 generates and converts a netlist based on the netlist D2 and the power supply specification file D3 (step S102), and outputs a power supply net named netlist D4 as a layout netlist.

  The netlist D4 with power net name is a logic simulation device 6 together with the cell library with power information D8 that defines the behavior of each logic cell when the power is cut off and when the power is supplied, read from the cell library storage unit 8 with power information. And the logic simulation in the power-off state is executed in the logic simulation device 6 (step S104). In the logic simulation, the test pattern D7 read from the test pattern storage unit 7 is used.

  The logic simulation in the logic simulation device 6 is normally performed to confirm the operation of the logic circuit in the power supply state, and is a necessary step in circuit design. In this embodiment, in order to simulate whether the logic circuit is properly controlled without causing malfunction even when the power supply that should have been supposed is cut off, such as when the power is cut off, The behavior information of each logic cell in the power-off state included in the library D8 is used.

  Note that the cell library with power information D8 is prepared in advance as necessary, like a normally used library, and that with power information is a power supply state or a power shut-off state. It means that it has the power supply information.

  As described above, in the semiconductor integrated circuit design apparatus 200 according to the second embodiment, from the netlist D4 with power supply net name and the cell library storage section 8 with power supply information output from the netlist generation / conversion apparatus 2 By performing a logic simulation based on the read cell library with power information D8, it is possible to verify how the logic cells belonging to each power supply region behave when the power is shut off.

<C. Embodiment 3>
With reference to the configuration of the semiconductor integrated circuit design apparatus 300 shown in FIG. 8, the operation of the semiconductor integrated circuit design apparatus 300 according to the third embodiment of the present invention will be described with reference to the flowchart shown in FIG.

  As shown in FIG. 8, the semiconductor integrated circuit design apparatus 300 includes a netlist generation / conversion apparatus 2, an automatic placement and routing apparatus 3, a power specification file storage unit 4, and a layout verification apparatus 9. In addition, the same code | symbol is attached | subjected about the structure same as Embodiment 1 demonstrated using FIG. 1 and FIG. 2, and the overlapping description is abbreviate | omitted.

  The semiconductor integrated circuit design apparatus 300 shown in FIG. 8 performs LVS (Layout vs Schematic) verification for verifying whether the layout of the semiconductor integrated circuit created by the automatic placement and routing apparatus 3 is created according to the circuit connection information. It is a design device to perform.

  The netlist generation / conversion device 2 receives the post-layout netlist D11 output from the automatic placement and routing device 3 after automatic placement and routing (step S201) and the power supply specification file D3 read from the power supply specification file storage unit 4 to receive the netlist. A list is generated and converted (step S202), and a power-information-added netlist D13 including power-connection information is generated according to the power-supply specifications.

  The automatic placement and routing apparatus 3 performs the layout based on the net list. However, the logic may be changed by the process in the automatic placement and routing apparatus 3, and the net list D11 after the layout includes the logic change described above. Therefore, the net list with power information D13 created based on the netlist D11 after the layout and the power specification file D3 has a format in which the power connection information is added to the changed logical connection information.

  The net list with power information D13 is given to the layout verification device 9, which uses the post-layout physical information D12 read from the automatic placement and routing device 3 for layout verification (step S203).

  The layout verification device 9 verifies the logical connection state using the net list with power information D13 and the post-layout physical information D12.

  Conventionally, when performing LVS verification of a semiconductor integrated circuit having a plurality of power supply systems, the verification is performed without distinguishing between the power supplies because it is treated as a single power supply system. This has been verified by another verification means such as the ERC method.

  However, in the semiconductor integrated circuit design device 300, the layout verification device 9 uses the information in the netlist with power supply information D13, so that in a semiconductor integrated circuit having a plurality of power supply systems, each power supply is handled as a separate signal. Verification that distinguishes between power sources becomes possible.

  In addition, as described with reference to FIG. 3, the netlist generation / conversion device 2 can shut off the power supply by setting an additional cell information definition section that defines, for example, a power supply control cell in the power supply specification file D3. In addition, it is possible to create the net list D13 with power information in which the power shut-off switch cells for controlling the supply are set according to the power specifications.

  Next, an example of circuit connection after layout to be verified in the layout verification apparatus 9 will be described with reference to FIGS. 10 and 11.

  FIG. 10 is a layout diagram of each module created based on the power supply specification file D3, and shows a state before the power supply system is assigned. As shown in FIG. 10, a module X4 belonging to the power supply area Area1, a module X5 belonging to the power supply area Area2, and a module X7 belonging to the power supply area Area3 are arranged independently.

  Module X5 includes cell 110, module X4 includes cell 120, and module X7 includes switch cell. The module X5 is also configured to be electrically connected to the external terminal 109.

  FIG. 11 shows a state in which the power supply system is assigned to each module. In the module X5, the VCC external terminal 21 and the external VDD2 are connected to the VCCQ terminal, the VDD terminal, the VSSQ terminal, and the VSS terminal of the cell 110, respectively. The terminal 22, the VSSC external terminal 23, and the VSS2 external terminal 24 are wired so as to be connected.

  Further, the E terminal, the RE terminal, and the CDN terminal of the cell 110 are commonly connected to the VDD terminal and also connected to the external terminal 109, and the SE terminal is connected to the VCC external terminal 21.

  In the module X4, the VBP terminal, the VDD terminal, and the VBN terminal of the cell 120 are wired so as to be connected to the VBP external terminal 31, the VDD1 external terminal 32, and the VBN external terminal 33, respectively. The VSS terminal of the cell 120 is connected to the VSSM terminal of the switch cell 130, and the VSS terminal of the switch cell 130 is connected to the VSS external terminal 34. The ctl terminal of the switch cell 130 is connected to the XXX terminal of the module X7 via the power supply net net1.

  As described above, by using the netlist with power supply information D13 created in the netlist generation / conversion device 2, the power shutoff switch cell that does not exist in the initial netlist can be used as circuit connection information after layout. It can be set according to the power supply specifications. Since the information on the power shutoff switch cell is included in the power connection information, it does not originally exist in the netlist that does not include the power information.

  As described above, in the semiconductor integrated circuit design apparatus 300 according to the third embodiment, the layout verification apparatus 9 uses the information in the power supply information-added netlist D13. Therefore, in the semiconductor integrated circuit having a plurality of power supply systems. By treating each power supply as a separate signal, it is possible to verify the power supply system separately.

  Further, since the power connection information of the power specification file D3 created separately from the layout creation process is used, the validity of the verification result is also guaranteed.

<D. Embodiment 4>
The operation of the semiconductor integrated circuit design apparatus 400 according to the fourth embodiment of the present invention will be described with reference to the configuration of the semiconductor integrated circuit design apparatus 400 shown in FIG. 12 and the flowchart shown in FIG.

  As shown in FIG. 12, a semiconductor integrated circuit design device 400 includes a net list generation / conversion device 2, an automatic placement and routing device 3, a power specification file storage unit 4, a layout parameter extraction device 10, a delay library storage unit 11, a delay A calculation device 12 and a static timing verification device 13 are provided. In addition, the same code | symbol is attached | subjected about the structure same as Embodiment 1 demonstrated using FIG. 1 and FIG. 2, and the overlapping description is abbreviate | omitted.

  A semiconductor integrated circuit design apparatus 400 shown in FIG. 12 is a design apparatus capable of automatically generating information necessary for timing analysis.

  The netlist generation / conversion device 2 receives the post-layout netlist D11 output from the automatic placement and routing device 3 after automatic placement and routing (step S201) and the power supply specification file D3 read from the power supply specification file storage unit 4 to receive the netlist. The list is generated and converted (step S202), and supply potential information D14 that defines the power supply net name and voltage value defined in the power supply specification file D3 for each cell belonging to each power supply region is generated. By specifying the potential for each cell in the supply potential information D14, it is possible to recognize the connection between different potentials.

  Further, the layout parameter extraction apparatus 10 extracts layout parameters related to the resistance value (R) and the capacitance value (C) from the post-layout physical information D12 read from the automatic placement and routing apparatus 3 (step S204), and RC information (resistance and resistance). (Capacity information) is output as D15.

  That is, the post-layout physical information D12 includes graphic information (that is, mask pattern) for each layer created by a layout tool such as the automatic placement and routing apparatus 3, and based on this information, the layout parameter extracting apparatus 10 Then, the parasitic capacitance value and the parasitic resistance value between the wirings are calculated.

  The supply potential information D14 is given to the delay calculation device 12, and the delay calculation device 12 uses it together with the RC information D15 output from the layout parameter extraction device 10 for delay calculation (step S205).

  The delay calculation device 12 uses the delay library D16, RC information D15, and supply potential information D14 corresponding to the power supply voltage variable read from the delay library storage unit 11, based on the parasitic capacitance value and resistance value of the signal line. And delay calculation which calculates time required for a signal to propagate between cells is performed (step S205).

  In the delay library D16 for variable power supply voltage, a delay value corresponding to the voltage value supplied to the cell is defined, and it is possible to include information in which the delay value varies depending on the voltage value. For example, a delay value at an arbitrary voltage value may be obtained by multiplying a delay value defined at a reference point by a predetermined coefficient, and a delay value may be defined for each voltage value. That is, if the voltage value supplied to the cell is known, the delay value in each cell according to the voltage value can be calculated.

  After executing the delay calculation, the delay value information generated by the delay calculation device 12 (the time required for the signal to propagate within and between cells) is input to the static timing verification device 13.

  In the static timing verification device 13, based on the power supply voltage variable-compatible delay library D 16 read from the delay library storage unit 11 and the delay value information, the signal is correctly propagated in the circuit, or according to the assumed specifications. Static timing verification (step S206) is performed to verify whether the timing performance is satisfied.

  In the semiconductor integrated circuit design apparatus 400 according to the fourth embodiment, the netlist generation / conversion apparatus 2 generates supply potential information D14 that defines a power supply net name and a voltage value for each cell belonging to each power supply region. Since the delay calculation device 12 performs delay calculation using the supply potential information D14, RC information D15, and the power supply voltage variable corresponding delay library D16, delay calculation and timing analysis are collectively performed in all power supply regions on the semiconductor integrated circuit. Can be implemented.

<E. Embodiment 5>
The operation of the semiconductor integrated circuit design apparatus 500 according to the fifth embodiment of the present invention will be described with reference to the configuration of the semiconductor integrated circuit design apparatus 500 shown in FIG. 14 and the flowchart shown in FIG.

  As shown in FIG. 14, a semiconductor integrated circuit design device 500 includes a netlist generation / conversion device 2, an automatic placement and routing device 3, a power specification file storage unit 4, a layout parameter extraction device 10, and a power consumption value library storage unit 14. A power consumption analysis device 15 and a voltage drop analysis device 16 are provided. In addition, the same code | symbol is attached | subjected about the structure same as Embodiment 4 demonstrated using FIG. 12 and FIG. 13, and the overlapping description is abbreviate | omitted.

  A semiconductor integrated circuit design apparatus 500 shown in FIG. 14 is a design apparatus capable of automatically generating information necessary for power consumption analysis and voltage drop analysis.

  The netlist generation / conversion device 2 receives the post-layout netlist D11 output from the automatic placement and routing device 3 after automatic placement and routing (step S201) and the power supply specification file D3 read from the power supply specification file storage unit 4 to receive the netlist. The list is generated and converted (step S202), and supply potential information D14 that defines the power supply net name and voltage value defined in the power supply specification file D3 for each cell belonging to each power supply region is generated.

  Further, the layout parameter extraction device 10 extracts layout parameters relating to the resistance value (R) and the capacitance value (C) from the post-layout physical information D12 read from the automatic placement and routing device 3 (step S204), and outputs it as RC information D15. To do.

  The supply potential information D14 is given to the power consumption analysis device 15, which is used for the power consumption analysis (step S207) of the semiconductor integrated circuit together with the RC information D15 output from the layout parameter extraction device 10. To do.

  The power consumption analyzer 15 uses the power consumption value library D17 read from the power consumption value library storage unit 14, the RC information D15, and the supply potential information D14, and the power supply voltage value supplied to the cell, and the cell is driven. Based on the capacitance value and operating frequency of the signal line to be charged (that is, charge / discharge), the power value required when the cell is driven, that is, when the signal line is charged / discharged, is calculated.

  The power consumption value library D17 defines the power consumed by the cell, and the power consumption analyzer 15 adds the obtained charge / discharge power and the power consumed by the cell (penetration power and leakage power). Thus, the power consumption for each instance is obtained and output as power consumption information D18. Note that the current value consumed by each instance can be obtained from the power consumption of each instance, and if the current value consumed by each instance is known, the current value flowing on the power supply wiring can be obtained.

  The power consumption information D18 for each instance is given to the voltage drop analysis device 16. In the voltage drop analysis device 16, how much the voltage value supplied to each instance is from the ideal voltage value together with the RC information D15. It is calculated whether a voltage drop has occurred (step S208).

  In the semiconductor integrated circuit design apparatus 500 according to the fifth embodiment, the netlist generation / conversion apparatus 2 generates supply potential information D14 that defines a power supply net name and a voltage value for each cell belonging to each power supply region. Since the power consumption analysis device 15 performs the power consumption analysis using the supply potential information D14, the RC information D15, and the power consumption value library D17, the power consumption analysis and the voltage drop analysis are performed on all power supply regions on the semiconductor integrated circuit. It becomes possible to carry out all at once.

  In realizing the semiconductor integrated circuit design apparatuses 100 to 500 according to the first to fifth embodiments described above, a computer system may be used.

  That is, the logic synthesis device 1, netlist generation / conversion device 2, automatic placement and routing device 3, logic simulation device 6, layout verification device 9, layout parameter extraction device 10, delay calculation device 12, and static timing verification device 13, consumption The functions of the power analysis device 15 and the voltage drop analysis device 16 can be realized by executing a computer program (layout generation program) on the computer, in which case the program is stored on a recording medium such as a magnetic recording medium or an optical disk. Supplied by Further, the program can be supplied in the form of a signal through a communication line, and further downloaded to a recording medium.

  The power specification file storage unit 4, the HDL data storage unit 5, the test pattern storage unit 7, the cell library storage unit 8, the delay library storage unit 11 and the power consumption value library storage unit 14 use a storage device of a computer system. Various data to be stored in the storage device can be input through a recording medium or a communication line.

It is a figure explaining the structure of the design apparatus of the semiconductor integrated circuit of Embodiment 1 which concerns on this invention. 5 is a flowchart for explaining the operation of the semiconductor integrated circuit design apparatus according to the first embodiment of the present invention; It is a figure which shows an example of a power supply specification file. It is a figure explaining the structure of the modification of the design apparatus of the semiconductor integrated circuit of Embodiment 1 which concerns on this invention. 7 is a flowchart for explaining the operation of a modification of the semiconductor integrated circuit design apparatus according to the first embodiment of the present invention; It is a figure explaining the structure of the design apparatus of the semiconductor integrated circuit of Embodiment 2 which concerns on this invention. 6 is a flowchart for explaining the operation of the semiconductor integrated circuit design apparatus according to the second embodiment of the present invention; It is a figure explaining the structure of the design apparatus of the semiconductor integrated circuit of Embodiment 3 which concerns on this invention. It is a flowchart explaining operation | movement of the design apparatus of the semiconductor integrated circuit of Embodiment 3 which concerns on this invention. It is a figure which shows arrangement | positioning of each module before allocation of a power supply system. It is a figure which shows arrangement | positioning of each module after the allocation of a power supply system. It is a figure explaining the structure of the design apparatus of the semiconductor integrated circuit of Embodiment 4 which concerns on this invention. It is a flowchart explaining operation | movement of the design apparatus of the semiconductor integrated circuit of Embodiment 4 which concerns on this invention. It is a figure explaining the structure of the design apparatus of the semiconductor integrated circuit of Embodiment 5 which concerns on this invention. It is a flowchart explaining operation | movement of the design apparatus of the semiconductor integrated circuit of Embodiment 5 which concerns on this invention.

Claims (4)

A device for designing a semiconductor integrated circuit having a plurality of power supply systems,
For a plurality of power supply regions on the layout of the semiconductor integrated circuit, a power supply region definition section in which module names or instance names belonging to the respective power supply regions are defined, and for each of the plurality of power supply regions, a power supply terminal name in each region And a power supply specification file having a power supply specification definition section in which power supply connection information including at least a ground terminal name, a power supply net name connected to them, a ground net name, and a voltage value assigned to them is defined;
A plurality of cells, which are basic units constituting the semiconductor integrated circuit, having a terminal to which an input logic level is always given “0” or “1” is received in response to a net list indicating logical connection information. Create a power net named net list that defines which power net is connected, and generate a power net that defines which power net and ground terminal of the cell are connected to A netlist generator / converter for creating commands;
An apparatus for designing a semiconductor integrated circuit, comprising: an automatic placement and routing apparatus that performs automatic placement and routing in response to the power supply net named netlist and the power supply net generation command. The power specification file is
Including an additional cell information definition section that defines which of the plurality of power supply regions a power control cell to which a unique instance name is assigned,
2. The netlist generation / conversion device also generates an additional cell insertion command that defines which power supply net a power control cell is connected to and supplies the command to the automatic placement and routing device. Semiconductor integrated circuit design equipment. A device for designing a semiconductor integrated circuit having a plurality of power supply systems,
For a plurality of power supply regions on the layout of the semiconductor integrated circuit, a power supply region definition section in which module names or instance names belonging to the respective power supply regions are defined, and for each of the plurality of power supply regions, a power supply terminal name in each region And a power supply specification file having a power supply specification definition section in which power supply connection information including at least a ground terminal name, a power supply net name connected to them, a ground net name, and a voltage value assigned to them is defined;
A plurality of cells, which are basic units constituting the semiconductor integrated circuit, having a terminal to which an input logic level is always given “0” or “1” is received in response to a net list indicating logical connection information. A netlist generation / conversion device that creates a netlist with a power net name that defines which power net is connected to,
Design of a semiconductor integrated circuit comprising a logic library and a logic simulation apparatus that receives a cell library with power information defining a behavior of a logic cell at the time of power shutoff and power supply and a netlist with a power net name apparatus. A device for designing a semiconductor integrated circuit having a plurality of power supply systems,
Automatic placement and routing equipment;
For a plurality of power supply regions on the layout of the semiconductor integrated circuit, a power supply region definition section in which module names or instance names belonging to the respective power supply regions are defined, and for each of the plurality of power supply regions, a power supply terminal name in each region And a power supply specification file having a power supply specification definition section in which power supply connection information including at least a ground terminal name, a power supply net name connected to them, a ground net name, and a voltage value assigned to them is defined;
A net that generates a netlist with power supply information in which the power connection information is added to the logical connection information after layout in response to the post-layout net connection information indicating the logical connection information after layout output from the automatic placement and routing apparatus A list generator / converter;
A layout verification device that receives the post-layout physical information output from the automatic placement and routing apparatus and the net list with power supply information, and performs layout verification ; and
The power specification file is
An additional cell information defining unit that defines which of the plurality of power supply regions a power cutoff switch cell for controlling power supply cutoff and supply includes:
The netlist generator-converter system, the apparatus for designing a semiconductor integrated circuit you additional information of the power cut-off switch cell in the netlist with the power supply information.

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