JP2004094402A - Delay simulation netlist creation system and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a system creating a simulation netlist having a small data quantity without marring the precision in delay simulation. <P>SOLUTION: This delay simulation netlist creating system is provided with a delay model creation means 4 inputting a pre-layout netlist 1, an LPE (Layout Parasitic Extraction) netlist 3 as the result of the extraction of layout parasitic elements, an LPE information linking property 2 corresponding the LPE netlist 3 with the pre-layout netlist 1 and creating a delay model file 5 from the pre-layout netlist 1 and the LPE netlist 3 according to the contents of the LPE information linking property 2; and a delay simulation netlist creation means 6 creating the delay simulation netlist 7 from the delay model file 5 and the pre-layout netlist 1. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a simulation (post-layout simulation) technique in which a parasitic capacitance and a parasitic resistance of a design after a layout design in a semiconductor integrated circuit are considered.
[0002]
[Prior art]
In recent years, device factors that must be considered at the design stage have been increasing with the miniaturization of processes. Further, in a memory block or the like, since the size of the block itself tends to be large, it is difficult to perform a delay simulation with high accuracy on the entire block scale. Therefore, when evaluating the characteristics of a semiconductor integrated circuit, it is important to select a verification environment and a verification method that accurately reflect parasitic element information such as a parasitic resistance and a parasitic capacitance component included in the layout design data. Is coming. Therefore, the delay simulation by the post-layout simulation is important. At that time, it is important how to keep the accuracy of the parasitic element information and suppress the data amount of the simulation netlist.
[0003]
For example, in a memory block, a netlist (a critical path netlist) in which a delay propagation path or a path that has a characteristic influence on the delay propagation path is separately generated in the memory block, so that a simulation with a small data amount is first performed. A method of generating a netlist was adopted. At that time, for example, how to handle information about cells that are not to be accessed sharing a word line or a bit line governs accuracy and simulation efficiency. For example, as a first method, there is a method in which the dummy cell portion has the same layout parasitic element information as the cell to be accessed. As a second method, there is a method of reflecting parasitic information (resistance, capacitance) roughly calculated from a wiring shape for a dummy cell portion. Further, as a third method, there is a method of preparing a dummy cell for a wiring portion and returning a parasitic RC component extracted from layout data to the dummy cell.
[0004]
[Problems to be solved by the invention]
The above three conventional methods have the following problems. According to the first method, as the circuit size increases, the data amount exceeds the amount that the simulator can handle. Alternatively, a problem arises in that even if the measures can be taken, a large amount of simulation time is required. Further, the second and third methods have a problem that sufficient accuracy cannot be obtained. That is, in the above-described conventional method, it is difficult to balance the accuracy and the data amount of the simulation netlist when targeting the signal line. Therefore, in order to simulate the voltage effect in a large-scale circuit, it is extremely difficult to reflect parasitic information such as a power supply line.
[0005]
The present invention has been made in view of these problems, and an object of the present invention is to provide a simulation netlist generation system with a small amount of data without impairing accuracy in delay simulation. This provides an environment in which delay simulation efficiency is higher than before, and enables highly accurate block-level delay simulation even for large-scale blocks.
[0006]
[Means for Solving the Problems]
In order to solve the above problems, a delay simulation netlist generation system according to the present invention includes a prelayout netlist, an LPE netlist resulting from layout parasitic element extraction, and the LPE netlist and the prelayout netlist. A delay model generating means for inputting an associated LPE information association property and generating a delay model file from the pre-layout netlist and the LPE netlist in accordance with the contents of the LPE information association property; A delay simulation netlist generating means for generating a delay simulation netlist from the pre-layout netlist.
[0007]
BEST MODE FOR CARRYING OUT THE INVENTION
A delay simulation netlist generation system according to the present invention forms a delay model of an LPE netlist for each arbitrarily set basic circuit unit constituting a prelayout netlist (first configuration).
[0008]
Thus, delay modeling can be performed while taking into account the required accuracy for each basic circuit unit, so that a delay simulation netlist with a small amount of data can be generated while maintaining the required accuracy. As a result, even in a large-scale circuit, it is possible to perform delay simulation for the entire block, and it is possible to execute a simulation at a higher speed than in the conventional method.
[0009]
The delay simulation netlist generation system according to the present invention may further include, in addition to the first configuration, a netlist conversion processing unit that generates the pre-layout netlist and the LPE information association property from circuit data. Preferred (second configuration).
[0010]
According to this configuration, in addition to the effect of the first configuration described above, the pre-layout netlist and the LPE information association property can be easily associated at the circuit diagram level. Has the effect of being able to perform efficiently.
[0011]
The delay simulation netlist generation system according to the present invention, in addition to the second configuration, obtains information of the LPE information association property from layout data including at least one or more leaf cells corresponding to the circuit data as a configuration unit. It is preferable to further include LPE control means for generating the LPE netlist based on the layout data extracted based on (3rd configuration).
[0012]
According to this configuration, in addition to the effect of the above-described second configuration, it is possible to easily and reliably select the LPE data corresponding to the pre-layout netlist, and to generate the delay simulation netlist. There is an effect that it can be performed efficiently.
[0013]
In the delay simulation netlist generation system according to the present invention, the delay simulation netlist generation means in the first configuration refers to configuration parameter information of a configuration parameter file when generating the delay simulation netlist. Is preferable (fourth configuration).
[0014]
According to this configuration, in addition to the effect of the first configuration, when a plurality of delay simulation netlists having different configurations such as the number of bits, the number of words, and the number of columns are generated, the delay simulation netlist which is a final process is generated. By repeating the processing from the generation unit, it is possible to efficiently generate a delay simulation netlist according to a desired memory configuration.
[0015]
In the delay simulation netlist generation system according to the present invention, it is preferable that the delay model generation means in the first configuration refers to configuration parameter information of a configuration parameter file when generating the delay model file. 5 configuration).
[0016]
According to this configuration, in addition to the effect of the first configuration, by having information on configuration parameters such as the number of bits, the number of words, and the number of columns at the stage of generating a delay model file, a plurality of regularly arranged Since delay modeling can be performed on a cell basis, it is possible to generate a delay simulation netlist with a small data amount. In addition, when a plurality of delay simulation netlists having different configurations are generated, a delay simulation netlist corresponding to a desired memory configuration is efficiently generated by repeating the process from the delay modeling unit which is an intermediate step. It is also possible to do.
[0017]
In the delay simulation netlist generation system according to the present invention, in the first configuration, it is preferable that configuration parameter information is previously given to the prelayout netlist from a configuration parameter file (sixth configuration).
[0018]
According to this configuration, in addition to the effects of the first configuration, when the memory configuration is determined in advance, or when designing a circuit having no configuration variation, it is necessary to use configuration parameters as variables unnecessarily. Therefore, it is possible to reduce the complexity of subsequent processing steps, and it is possible to efficiently generate a delay simulation netlist according to a target memory configuration.
[0019]
In the delay simulation netlist generation system according to the present invention, the circuit data in the second configuration is circuit-equivalent to the layout data actually used for the mask processing, and the circuit unit configuring the circuit data. Preferably have the LPE information association property individually (seventh configuration). In the seventh configuration, it is more preferable that the circuit data includes only cells including an active node and an active related node necessary for performing a delay simulation. In the seventh configuration, it is further preferable that the basic unit of the LPE information association property includes at least a name of an LPE cell having layout parasitic element extraction result information and modeling type information.
[0020]
According to these configurations, in addition to the effect of the second configuration, the configuration in which the LPE information association property is provided in the smallest circuit unit constituting the circuit data can be associated with the LPE data in the smallest circuit unit. Therefore, it is possible to generate a highly accurate delay model.
[0021]
In the delay simulation netlist generation system according to the present invention, the circuit data in the seventh configuration is configured to include a cell previously modeled with a parasitic element instead of a circuit unit configuring the circuit data. Is preferable (the eighth configuration). In an eighth configuration, it is more preferable that the circuit data includes a cell modeled by a parasitic element in advance, instead of a circuit unit constituting the circuit data. The eighth configuration is characterized in that, as a basic unit of the LPE information association property, the name of an active node for which signal propagation is newly performed in a delay simulation, the name of a pin on the active node, and the parasitic node between the active node and the active node More preferably, it comprises the name of the active association node where the element resides.
[0022]
According to these configurations, in addition to the effect of the seventh configuration, by considering an access path in an actual delay simulation, it is possible to perform a modeling process according to a node requiring accuracy in units of cells. Become. At this time, even if the modeling type information does not exist in the information of the LPE information association property, modeling can be performed at least from the active node information.
[0023]
The delay simulation netlist generation system according to the present invention preferably further includes layout arrangement direction information as a basic unit of the LPE information association property (a ninth configuration).
[0024]
According to this configuration, in addition to the effect of the seventh configuration, even when a specific delay model is used a plurality of times and the actual layout data corresponding to the delay model adopts an inverted or rotated arrangement. The parasitic element model can be correctly expressed in consideration of the arrangement direction of the own cell and the adjacent cell.
[0025]
The delay simulation netlist generation system according to the present invention preferably includes at least an LPE cell name and a modeling coefficient calculation formula as basic units of the LPE information association property in the eighth configuration (tenth configuration). .
[0026]
According to this configuration, in addition to the seventh effect, by replacing all or a part of the circuit unit constituting the circuit data with the parasitic element model, the circuit data is equivalent in circuit and has a small data amount. Can be configured. Further, since the configuration is such that the data amount is small, each processing time for generating the delay simulation netlist can be shortened.
[0027]
The delay simulation netlist generation system according to the present invention may further include an active node name, a pin name on the active node, and an active related node name as basic units of the LPE information association property in the tenth configuration. Preferred (eleventh configuration).
[0028]
According to this configuration, in addition to the effect of the tenth configuration, even in a configuration in which all or a part of a circuit unit configuring circuit data is replaced with a parasitic element model, an access path in an actual delay simulation is considered. This makes it possible to perform a modeling process according to a node requiring accuracy in units of cells.
[0029]
The delay simulation netlist generation system according to the present invention, wherein the seventh configuration has at least the name of the LPE cell having the layout parasitic element extraction result information and the modeling type information as basic units of the LPE information association property, The delay model generation unit includes a modeling information storage unit that stores at least a modeling coefficient calculation formula and modeling type information, the LPE information association property, the LPE netlist, and the modeling information storage unit. LPE parasitic element merge processing means for generating an LPE parasitic element merge result file using the information, and the LPE parasitic element merge result file and the information held by the modeling information storage means. Model variable calculation processing to generate a delay model file It is preferred that a means (12 configuration).
[0030]
According to this configuration, it is possible to more reliably generate a delay model for a pre-layout netlist including an LPE information association property in a minimum circuit unit cell.
[0031]
In the delay simulation netlist generation system according to the present invention, the delay model generation means in the tenth configuration generates an LPE parasitic element merge result file using the LPE information association property and information included in the LPE netlist. LPE parasitic element merge processing means, and model variable calculation processing means for generating the delay model file for each cell using the LPE parasitic element merge result file and information of the LPE information association property. Is preferable (the thirteenth configuration).
[0032]
According to this configuration, it is possible to more reliably generate a delay model for a pre-layout netlist including an LPE information association property in an LPE parasitic element model.
[0033]
In the delay simulation netlist generation system according to the present invention, the delay model generation means in the first configuration preferably generates a delay model having information on parasitic elements existing between adjacent cells (a fourteenth configuration). .
[0034]
According to this configuration, since the parasitic information existing between the cells constituting the actual layout data can be reflected in the delay model, a highly accurate delay simulation can be performed.
[0035]
A delay simulation netlist generation system according to the present invention is configured by arranging a plurality of delay models in the fourteenth configuration in an array, wherein each delay model is provided between LPE data corresponding to the delay model and adjacent LPE data. Is preferably expressed in association with the LPE data arrangement information (a fifteenth configuration).
[0036]
According to this configuration, a simulation simulation netlist including a configuration in which a plurality of delay models are arranged in an array is modeled with a table in which parasitic information existing between cells is previously associated with placement information, and simulation is performed. It is possible to obtain a netlist for use. For this reason, since the parasitic information existing between the cells constituting the actual layout data can be reflected in the delay model in consideration of the respective cell arrangement directions, a highly accurate delay simulation can be performed.
[0037]
In the delay simulation netlist generation system according to the present invention, the delay model generation means in the first configuration may generate the delay model by modeling notation including power supply line and ground line parasitic element information. Preferred (sixteenth configuration).
[0038]
This makes it possible to perform a simulation in which the effects of the voltage effect and the like are taken into account by modeling the information including the parasitic element information of the power supply line and the ground line. Further, since the modeling of the parasitic element information of the power supply line and the ground line is performed at the cell level, it is possible to generate a delay simulation netlist with a reduced data amount.
[0039]
The delay simulation netlist generation system according to the present invention preferably generates a simulation netlist including the delay model in the sixteenth configuration (a seventeenth configuration).
[0040]
According to this configuration, by modeling the information including the parasitic element information of the power supply line and the ground line, the simulation netlist in which the models are arranged has a small data amount, and the parasitic information of the power supply line and the ground line is reduced. A highly accurate delay simulation can be performed in consideration of the delay simulation.
[0041]
In order to achieve the above object, a method for generating a delay simulation netlist according to the present invention includes a prelayout netlist, an LPE netlist resulting from layout parasitic element extraction, the LPE netlist and the prelayout net. A delay model generating step of inputting an LPE information association property for associating with a list, and generating a delay model file from the pre-layout netlist and the LPE netlist according to the content of the LPE information association property; Generating a delay simulation netlist from a file and the pre-layout netlist.
[0042]
Thus, delay modeling can be performed while taking into account the required accuracy for each basic circuit unit, so that a delay simulation netlist with a small amount of data can be generated while maintaining the required accuracy. As a result, even in a large-scale circuit, it is possible to perform delay simulation for the entire block, and it is possible to execute a simulation at a higher speed than in the conventional method.
[0043]
Hereinafter, specific embodiments of the present invention will be described with reference to the drawings.
[0044]
(Embodiment 1)
FIG. 1 is a block diagram showing a delay simulation netlist generation system according to the first embodiment of the present invention. In the figure, 1 is a netlist before layout design (hereinafter, referred to as a pre-layout netlist), 2 is an LPE information association property, and 3 is a netlist obtained as a layout parasitic element extraction result (hereinafter, referred to as an LPE netlist). ), 4 is a delay model generating means, 5 is a delay model file, 6 is a delay simulation netlist generating means, and 7 is a delay simulation netlist. It is assumed that the LPE information association property 2 has information for associating the cells constituting the pre-layout netlist 1 with the LPE netlist 3 in cell units.
[0045]
Next, a processing flow in the first embodiment of the present invention will be described. The delay model generating means 4 that performs processing using the pre-layout netlist 1, the LPE information association property 2, and the LPE netlist 3 forms a basic element that configures the prelayout netlist 1 and has the LPE information association property 2. Processing is performed for the unit. The delay model generation means 4 performs modeling processing of the corresponding LPE netlist 3 according to the information of the LPE information association property 2 of each basic unit, and generates a delay model file 5. Then, the delay simulation netlist generating means 6 generates the delay simulation netlist 7 by performing a process of associating the delay model file 5 for each basic unit based on the pre-layout netlist 1.
[0046]
As described above, according to the first embodiment of the present invention, the LPE netlist is delay modeled for each arbitrarily set basic circuit unit constituting the pre-layout netlist, so that the LPE netlist is required for each basic circuit unit Delay modeling can be performed while taking into account accurate accuracy. Therefore, it is possible to generate a delay simulation netlist with a small amount of data while maintaining necessary accuracy. As a result, even in a large-scale circuit, it is possible to perform delay simulation for the entire block, and it is possible to execute a simulation at a higher speed than in the conventional method.
[0047]
(Embodiment 2)
FIG. 2 is a block diagram showing a delay simulation netlist generation system according to the second embodiment of the present invention. This figure is obtained by adding circuit data 8 to the first embodiment described above.
[0048]
Next, with respect to the processing flow in the second embodiment of the present invention, only the differences from the first embodiment of the present invention will be described. In the second embodiment, the processing of preparing the pre-layout netlist 1 and the LPE information association property 2 by converting the netlist by providing the information of the LPE information association property 2 in units of cells constituting the circuit data 8. Is provided.
[0049]
As described above, according to the second embodiment of the present invention, in addition to the effects of the above-described first embodiment of the present invention, the pre-layout netlist 1 and the LPE information association property 2 can be easily set at the circuit diagram level. The delay simulation netlist can be efficiently generated.
[0050]
(Embodiment 3)
FIG. 3 is a block diagram showing a delay simulation netlist generation system according to the third embodiment of the present invention. In the figure, the layout data 9 and the LPE control means 10 are added to the second embodiment described above.
[0051]
Next, a processing flow according to the third embodiment of the present invention will be described only with respect to differences from the second embodiment of the present invention. In the figure, the LPE control means 10 controls the generation of the LPE netlist 3 by selecting the information of the layout data 9 necessary for each cell using the information of the LPE information association property 2. is there.
[0052]
As described above, according to the third embodiment of the present invention, in addition to the effects of the above-described second embodiment, the LPE netlist 3 corresponding to the pre-layout netlist 1 is easily and reliably selected. This is advantageous in that the delay simulation netlist of the present invention can be efficiently generated.
[0053]
(Embodiment 4)
FIG. 4 is a block diagram showing a delay simulation netlist generation system according to the fourth embodiment of the present invention. In the figure, a configuration parameter file 11 is added to the first embodiment described above. The configuration parameter file 11 has information on configuration parameters such as the number of bits, the number of words, and the number of columns that determine the configuration of the memory.
[0054]
Next, the processing flow in the fourth embodiment of the present invention will be described only for the differences from the first embodiment of the present invention. As shown in the figure, information on the configuration parameters included in the configuration parameter file 11 is given to the delay simulation netlist generation means 6. As a result, the delay simulation netlist generation means 6 generates a delay simulation netlist 7 reflecting configuration information such as the number of bits, the number of words, and the number of columns.
[0055]
As described above, according to the fourth embodiment of the present invention, in addition to the effects of the above-described first embodiment, a plurality of delay simulation netlists having different configurations such as the number of bits, the number of words, and the number of columns are generated. In this case, the delay simulation netlist 7 according to a desired memory configuration can be efficiently generated by repeating the processing by the delay simulation netlist generation unit 6 which is the final step.
[0056]
(Embodiment 5)
FIG. 5 is a block diagram showing a delay simulation netlist generation system according to a fifth embodiment of the present invention. In this figure, a delay simulation netlist is generated by using the configuration parameter file 11 in the same manner as in the fourth embodiment described above. It differs from the fourth embodiment in that it is provided to the delay model generating means 4.
[0057]
Next, the processing flow in the fifth embodiment of the present invention will be described only for differences from the fourth embodiment of the present invention. The delay model generation means 4 performs delay modeling by reflecting configuration information such as the number of bits, the number of words, and the number of columns provided from the configuration parameter file 11. Thus, for example, when cells constituting a memory block are regularly arranged in accordance with the configuration parameters, modeling is performed not in terms of cells alone but in units of cell shapes arranged in an array. It is also possible to do.
[0058]
As described above, according to the fifth embodiment of the present invention, in addition to the effects of the above-described fourth embodiment, at the stage of generating the delay model file, the configuration parameters such as the number of bits, the number of words, and the number of columns are used. By referring to this information, delay modeling can be performed in units of a plurality of cells that are regularly arranged, so that a delay simulation netlist with a small amount of data can be generated. In addition, when a plurality of delay simulation netlists having different configurations are generated, the processing by the delay modeling means 4 which is an intermediate process is repeated to efficiently generate a delay simulation netlist corresponding to a desired memory configuration. It can also be generated.
[0059]
(Embodiment 6)
FIG. 6 is a block diagram showing a delay simulation netlist generation system according to a sixth embodiment of the present invention. In this figure, a delay simulation netlist is generated by using the configuration parameter file 11 in the same manner as in the fourth embodiment described above. It differs from the fourth embodiment in that it is provided to the pre-layout netlist 1.
[0060]
Next, a processing flow according to the sixth embodiment of the present invention will be described, focusing only on differences from the fourth embodiment. In the fourth embodiment, configuration information such as the number of bits, the number of words, and the number of columns included in the configuration parameter file 11 is given to the prelayout netlist 1 as a constant in advance.
[0061]
Thus, according to the sixth embodiment, in addition to the effects of the above-described fourth embodiment, when the memory configuration is determined in advance, or when a circuit having no configuration variation is designed, there is no waste. Since it is not necessary to treat configuration parameters as variables, it is possible to reduce the complexity of subsequent processing, and to efficiently generate a delay simulation netlist according to the target memory configuration. Become.
[0062]
(Embodiment 7)
A delay simulation netlist generation system according to a seventh embodiment of the present invention will be described with reference to FIGS. 7 and 11A and 11B. In the present embodiment, the method of providing the LPE information association property of the circuit data 8 and the contents thereof will be described based on the processing flow shown in FIG. 2 in the second embodiment.
[0063]
7, reference numeral 70 denotes a control circuit region formed in units of control circuits, 71 denotes an address decoder region formed in units of a plurality of types of address decoder circuits, 72 denotes a memory array region formed in units of memory cell circuits, and 73 denotes a memory array region. This is an input / output circuit area formed for each input / output circuit. The circuit data shown here is circuit-equivalent to the layout data actually used for the mask processing, and the circuit units constituting the circuit data individually have LPE information association properties.
[0064]
Next, FIG. 11A is an example of the content of the LPE information association property of the circuit unit as shown in FIG. 7, and includes at least information of the LPE cell name and the modeling type. FIG. 11B shows an example in which each circuit unit specifically describes an LPE information association property.
[0065]
In the information of the LPE information association property shown in FIGS. 11A and 11B, circuit data and LPE data are first associated with LPE cell name information. Further, a model specification for modeling LPE data is set based on the modeling type information.
[0066]
As described above, according to the seventh embodiment of the present invention, in addition to the effects of the above-described second embodiment, by adopting a configuration including an LPE information association property in a minimum circuit unit constituting circuit data, Since it is possible to associate LPE data with the minimum circuit unit, it is possible to generate a highly accurate delay model.
[0067]
In the description of the present embodiment, the basic processing flow is as shown in FIG. 2, but instead of the flow of FIG. 2, a processing flow based on any of FIG. 1 or FIG. In each case, the same effect can be obtained even if the pre-layout netlist 1 inherits the way of giving the LPE information association property of the circuit data 8 described in the present embodiment and the contents thereof.
[0068]
Alternatively, the above-described basic processing flow is replaced with the configuration processing flow shown in FIGS. 1, 3, 4, 5, and 6 in place of FIG. 2, and in each case, the circuit data shown in FIG. The same effect can be obtained even if the pre-layout netlist 1 has the circuit data configuration shown in FIG. 8 instead of the configuration, and the pre-layout netlist 1 inherits the way of assigning the LPE information association property of the circuit data 8 and its contents. Is obtained.
[0069]
FIG. 8 shows a configuration in which only cells including an active node and an active related node necessary for performing a delay simulation are left, and other cells are removed from FIG.
[0070]
(Embodiment 8)
The delay simulation netlist generation system according to the eighth embodiment of the present invention will be described with reference to FIG. 7 and FIGS. 12A and 12B. Further, the present embodiment has a configuration in which the content of the LPE information association property included in the circuit data 8 in the above-described seventh embodiment is changed. Note that the description of FIG.
[0071]
FIG. 12A shows an example of the content of the LPE information association property included in the circuit unit as shown in FIG. 7, and in addition to the content shown in FIG. And the names of the pins on the active node and the names of the active related nodes. Further, FIG. 12B shows an example in which each circuit unit specifically describes an LPE information association property, where net_WL is an active node name, WL and WL_2 are pin names on the active node, and active It is assumed that net_B and net_NB are set as related node names.
[0072]
At this time, using the information of the LPE information association property, the LPE data to be subjected to delay modeling and the modeling specification are determined as described above. Then, when modeling the LPE data using the information of the newly provided active node name and the pin name on the active node, the parasitic element information on the node (active node) where signal propagation is performed on the delay simulation is modeled. Perform modeling with emphasis on accuracy. At this time, the parasitic element information can be consciously modeled accurately using information on the partner node (active related node) when there is a parasitic element to be considered between the active node and the active node.
[0073]
In this figure, for the memory cell (LPE_CNTCELL1), the wiring of the pin (WL) and the pin (WL_2) on the net (net_WL) is accurately extracted according to the specification of the modeling type 2. At this time, for example, the coupling capacitance between the net (net_WL) and the net (net_B) and the net (net_NB) that are active related nodes can be modeled without lowering the accuracy.
[0074]
As described above, according to the eighth embodiment of the present invention, in addition to the effect of the above-described seventh embodiment, by considering an access path in an actual delay simulation, a node which requires a high degree of accuracy can be used. The modeling process can be performed on a cell-by-cell basis. At this time, even when the modeling type information does not exist in the information of the LPE information association property, modeling can be performed at least from the active node information.
[0075]
In the description of the present embodiment, the basic processing flow is as shown in FIG. 2, but instead of the flow of FIG. 2, a processing flow based on any of FIG. 1 or FIG. In each case, the same effect can be obtained even if the pre-layout netlist 1 inherits the way of giving the LPE information association property of the circuit data 8 described in the present embodiment and the contents thereof.
[0076]
Alternatively, the above-described basic processing flow is replaced with the configuration processing flow shown in FIGS. 1, 3, 4, 5, and 6 in place of FIG. 2, and in each case, the circuit data shown in FIG. The same effect can be obtained even if the pre-layout netlist 1 has the circuit data configuration shown in FIG. 8 instead of the configuration, and the pre-layout netlist 1 inherits the way of assigning the LPE information association property of the circuit data 8 and its contents. Is obtained.
[0077]
(Embodiment 9)
The delay simulation netlist generation system according to the ninth embodiment of the present invention will be described with reference to FIGS. 7, 13A and 13B. This embodiment describes a configuration in which the content of the LPE information association property of the circuit data 8 in the processing flow shown in the above-described eighth embodiment is changed. Note that FIG. 7 has already been described and thus will not be described.
[0078]
First, FIG. 13A shows the contents of the LPE information association property of the circuit unit as shown in FIG. 7, and in addition to the contents shown in FIG. It has information. FIG. 13B shows an example in which each circuit unit specifically describes an LPE information association property and the like. In this example, MY (arranged symmetrically with respect to the Y axis) is set according to the layout arrangement direction information control table shown in FIG. 13C, for example.
[0079]
Using the information of the LPE information association property shown in FIG. 13A and FIG. 13C, delay modeling is performed in the same manner as described above. By considering the layout arrangement direction information, it is possible to cope with a case where the LPE data is inverted or rotated as shown in FIGS. 14A and 14B or FIGS. 15A and 15B, for example. This is information for FIG. 14A shows a case where both memory cells are arranged without rotation, while FIG. 14B shows a case where the arrangement directions are different between left and right. Similarly, FIG. 15A shows a case where both memory cells are arranged without rotation, and FIG. 15B shows a case where the arrangement directions are different between the upper and lower sides.
[0080]
When modeling, for example, a coupling capacitance generated between adjacent cells in this way, it is necessary to distinguish the model expression by arrangement. In such a case, the above-described coupling capacitance can be correctly expressed according to the arrangement direction of the user and the partner.
[0081]
As described above, according to the ninth embodiment of the present invention, in addition to the effects of the above-described eighth embodiment, a specific delay model is used a plurality of times, and an actual layout corresponding to the delay model is used. Even when the data adopts an inverted or rotated arrangement, the parasitic element model can be correctly expressed in consideration of the arrangement direction of the own cell and the adjacent cell.
[0082]
In the description of the present embodiment, the basic processing flow is as shown in FIG. 2, but instead of the flow of FIG. 2, a processing flow based on any of FIG. 1 or FIG. In each case, the same effect can be obtained even if the pre-layout netlist 1 inherits the way of giving the LPE information association property of the circuit data 8 described in the present embodiment and the contents thereof.
[0083]
Alternatively, the above-described basic processing flow is replaced with the configuration processing flow shown in FIGS. 1, 3, 4, 5, and 6 in place of FIG. 2, and in each case, the circuit data shown in FIG. The same effect can be obtained even if the pre-layout netlist 1 has the circuit data configuration shown in FIG. Is obtained.
[0084]
(Embodiment 10)
A delay simulation netlist generation system according to the tenth embodiment of the present invention will be described with reference to FIGS. 9, 16A and 16B. In the present embodiment, the method of providing the LPE information association property of the circuit data 8 and the contents thereof will be described on the premise of the processing flow shown in FIG. 2 in the second embodiment.
[0085]
First, FIG. 9 shows a configuration in which all or a part of the circuit unit configuring the circuit data shown in FIG. 8 described above is replaced with a model in which all or a part is previously expressed by a parasitic element. Is a parasitic element model constituting an address decoder area, 91 to 94 are parasitic element models constituting a memory array area, and particularly 91 and 92 are parasitic element models emphasizing word lines, and 93 and 94 are bit element lines. This is a parasitic element model that is emphasized. Reference numeral 95 denotes a parasitic element model forming the input / output circuit area. As shown here, in the present embodiment, all the circuit units or the parasitic element models constituting the circuit data have LPE information association properties.
[0086]
FIG. 16A shows the content of the LPE information association property of the parasitic element model as shown in FIG. 9 and includes at least the LPE cell name and the parasitic element modeling coefficient calculation formula. FIG. 16B shows an example in which each parasitic element model specifically describes an LPE information association property. In the information of the LPE information association property shown in FIGS. 16A and 16B, the LPE cell name information is for associating circuit data with LPE data, and the parasitic element modeling coefficient calculation formula is a parasitic element model. Is a conversion formula for calculating the value of each parasitic element forming the above from the LPE data.
[0087]
As described above, according to the tenth embodiment of the present invention, in addition to the effects shown in the above-described seventh embodiment of the present invention, all or a part of the circuit unit constituting the circuit data is included in the parasitic element model. By replacing, circuit data that is equivalent in circuit and has a small data amount can be configured. Further, since the configuration is such that the data amount is small, each processing time for generating the delay simulation netlist can be shortened.
[0088]
In the description of the present embodiment, the basic processing flow is as shown in FIG. 2, but instead of the flow of FIG. 2, a processing flow based on any of FIG. 1 or FIG. In each case, the same effect can be obtained even if the pre-layout netlist 1 inherits the way of giving the LPE information association property of the circuit data 8 described in the present embodiment and the contents thereof.
[0089]
Alternatively, the above basic processing flow is replaced with the configuration processing flow shown in FIGS. 1, 3, 4, 5, and 6 in place of FIG. 2, and in each case, the circuit data shown in FIG. The same effect can be obtained even if the pre-layout netlist 1 has a configuration in which the configuration of the circuit data shown in FIG. Is obtained.
[0090]
In FIG. 10, 100 is a parasitic element model constituting an address decoder area, 101 to 105 are parasitic element models constituting a memory array area, and particularly 101, 103 and 105 are parasitic element models emphasizing bit lines. On the other hand, reference numerals 102 and 104 denote parasitic element models emphasizing the word lines. Reference numeral 106 denotes a parasitic element model constituting the input / output circuit area.
[0091]
(Embodiment 11)
With reference to FIGS. 9, 17A and 17B, a description will be given of a delay simulation netlist generation system according to an eleventh embodiment of the present invention. This embodiment has a configuration in which the content of the LPE information association property included in the circuit data 8 in the processing flow shown in the tenth embodiment is changed. Note that FIG. 9 has already been described, and will not be described.
[0092]
First, FIG. 17A shows the contents of the LPE information association property of each parasitic element model as shown in FIG. 9, and in addition to the contents shown in FIG. It has a node name, a pin name on the active node, and an active related node name. Further, FIG. 17B shows an example in which each parasitic element model specifically describes an LPE information association property. A net (net_WL) is used as an active node, and a pin (WL) is used as a pin on the active node. ) And a pin (WL_2), and a net (net_B) and a net (net_NB) are set as active related nodes.
[0093]
At this time, the LPE data to be subjected to delay modeling and the modeling specification are determined using the information of the LPE information association property as described in the above embodiment. Then, when LPE data is modeled using information of the newly provided active node name and pin names on the active node, the parasitic element information on the active node is modeled with high accuracy. Also, at this time, the active related node can be used to model a parasitic element existing between the active node and the active node in consideration of accuracy. In this figure, a net (net_WL), which is an active node of LPE data (LPE_CNTCELL1), is modeled with emphasis on wiring between a pin (WL) and a pin (WL_2) on the node, and is used for a parasitic element model. This shows that the coefficients (Rm1, Rm2 and CGm1, CGm2, CGm3) are set to be obtained. At the same time, the accuracy of the coupling capacitance between the net (net_WL) and the active related node (net_WLX) is also obtained. Are set so as to obtain the coefficients (CCm1 to CCm3) for the parasitic element model.
[0094]
As described above, according to the eleventh embodiment of the present invention, in addition to the effects shown in the above-described tenth embodiment, all or some of the circuit units constituting the circuit data are replaced with the parasitic element model. Also in the configuration, by considering an access path in an actual delay simulation, it becomes possible to perform a modeling process corresponding to a node requiring high accuracy in a cell unit. Here, even if the modeling type information does not exist among the information possessed by the LPE information association property, modeling can be performed based on at least the active node information.
[0095]
In the description of the present embodiment, the basic processing flow is as shown in FIG. 2, but instead of the flow of FIG. 2, a processing flow based on any of FIG. 1 or FIG. In each case, the same effect can be obtained even if the pre-layout netlist 1 inherits the way of giving the LPE information association property of the circuit data 8 described in the present embodiment and the contents thereof.
[0096]
Alternatively, the above basic processing flow is replaced with the configuration processing flow shown in FIGS. 1, 3, 4, 5, and 6 in place of FIG. 2, and in each case, the circuit data shown in FIG. The same effect can be obtained even if the pre-layout netlist 1 has a configuration in which the configuration of the circuit data shown in FIG. Is obtained.
[0097]
(Embodiment 12)
A delay simulation netlist generation system according to a twelfth embodiment of the present invention will be described with reference to FIGS. 18 and 19A to 19D. First, FIG. 18 shows a circuit configuration for realizing the delay model generating means 4 based on the configuration shown in FIG. 1 described above. In the figure, 41 is an LPE parasitic element merge processing unit, 42 is an LPE parasitic element merge result file, 43 is a model variable calculation processing unit, 44 is a delay model generation unit, 45 is modeling type information, and 46 is a modeling coefficient. This is a calculation formula.
[0098]
On the other hand, 171 shown in FIG. 19A is an example of information included in the LPE netlist, and 172 shown in FIG. 19B is an example of information included in the LPE parasitic element merge result file. 173 illustrated in c) is an example of information included in the modeling coefficient calculation formula, and 174 illustrated in FIG. 19D is an example of information included in the modeling type information.
[0099]
Next, the processing flow in the present embodiment will be described. It is assumed that the LPE information association file 2 has at least the information shown in FIGS. 11A and 11B as components. In the present embodiment, a description will be given focusing on a part not mentioned in the first embodiment, that is, a processing flow of the delay model generating unit 4.
[0100]
First, the LPE parasitic element merge processing unit 41 inputs the pre-layout netlist 1, the LPE information association property 2 and the LPE netlist 3 (171 in FIG. 19A), and outputs the LPE parasitic element merge result file 42 (FIG. 172) of 19 (b) is generated. First, the LPE parasitic element merge processing unit 41 selects the corresponding LPE netlist 3 (171 in FIG. 19A) from the LPE data name information included in the LPE information association property 2, and similarly sets the modeling type name information. Thus, the corresponding modeling type information 45 (174 in FIG. 19D) is obtained. At this time, it is assumed that the modeling type information 45 (174 in FIG. 19D) and the modeling coefficient calculation formula 46 (173 in FIG. 19C) are associated by the delay modeling information storage unit 44. . As described above, the LPE parasitic element merge processing unit 41 that has obtained the information for performing the processing on a cell basis can generate the LPE parasitic element merge result file 42 (172 in FIG. 19B) for each cell. .
[0101]
Next, the model variable calculation processing unit 43 generates the delay model file 5 for each cell from the LPE parasitic element merge result file 42 (172 in FIG. 19B) and the modeling coefficient calculation formula 45.
[0102]
As described above, by configuring the delay model generating means 4 as shown in the twelfth embodiment of the present invention, it is ensured that the pre-layout netlist having the LPE information association property in the minimum circuit unit cell is targeted. It is possible to generate a delay model.
[0103]
In the description of the present embodiment, the basic processing flow of the delay model generating means is as shown in FIG. 1, but instead of the flow of FIG. 1, a processing flow based on any of FIGS. The same effect can be obtained.
[0104]
Further, the above basic processing flow is changed to the basic processing flow based on any of FIGS. 2 to 6 in place of FIG. 1, and in each case, the LPE information association file 2 corresponds to the basic processing flow shown in FIGS. 13), and the case where the information shown in FIGS. 13A and 13B is included, the same effect can be obtained.
[0105]
(Embodiment 13)
The delay simulation netlist generation system according to the thirteenth embodiment of the present invention will be described with reference to FIG. This embodiment has a circuit configuration for realizing the delay model generation means 4 in the delay simulation netlist generation system according to the tenth embodiment.
[0106]
In the present embodiment, a description will be given focusing on a part not mentioned in the tenth embodiment, that is, a processing flow of the delay model generating unit 4. However, among the units forming the pre-layout netlist 1 and having the LPE information association property, the modeling process in units of the cell composed of the smallest circuit has been described in the twelfth embodiment, and therefore will not be described. , The flow of the delay model generation means will be described specifically for modeling of LPE parasitic elements.
[0107]
FIG. 20 shows the configuration of the delay model generating means required for the delay modeling process for the parasitic element model constituting the pre-layout netlist 1, and includes the components of FIG. 18 described above. , A modeling coefficient calculation formula 45 and modeling information storage means 44 including modeling type information 46 are omitted.
[0108]
Next, a processing flow in the present embodiment will be described. First, the LPE parasitic element merge processing unit 41 receives the pre-layout netlist 1, the LPE information association property 2 and the LPE netlist 3, and generates an LPE parasitic element merge result file 42. At this time, it is assumed that the LPE information association property 2 has the information shown in FIGS. 16A and 16B described in the above embodiment. That is, the LPE parasitic element unit constituting the pre-layout netlist 1 in the present embodiment has the information of the modeling information storage unit 44 shown in FIG. 18 in the twelfth embodiment. Will be.
[0109]
First, the LPE parasitic element merge processing unit 41 selects the corresponding LPE netlist 171 from the LPE data name information included in the LPE information association property 2. Then, an LPE parasitic element merge result file is generated in association with the modeling type information of each LPE parasitic element unit constituting the pre-layout netlist 1. Then, the model variable calculation processing unit 43 generates the delay model file 5 for each cell from the LPE parasitic element merge result file 42 and the modeling coefficient calculation formula of the LPE information association property 2.
[0110]
As described above, by configuring the delay model generation means 4 as shown in the present embodiment, the modeling information of each LPE parasitic element model constituting the pre-layout netlist 1 and the information of the LPE information association property 2 Can be associated with each other, and it is possible to reliably generate a delay model.
[0111]
In the description of the present embodiment, the basic processing flow of the delay model generating means is as shown in FIG. 1, but instead of the flow of FIG. 1, a processing flow based on any of FIGS. The same effect can be obtained.
[0112]
Further, the above basic processing flow is changed to the basic processing flow based on any of FIGS. 2 to 6 in place of FIG. 1, and in each case, the LPE information association file 2 corresponds to FIG. 17 (a) and FIG. The same effect can be obtained even when the information has any of the above conditions.
[0113]
(Embodiment 14)
A delay simulation netlist generation system according to a fourteenth embodiment of the present invention will be described with reference to FIG. This embodiment shows a specific example of the contents of the delay model file 5 based on the processing flow shown in the first embodiment. FIG. 21 conceptually illustrates a state in which LPE data corresponding to the delay model forming the pre-layout netlist 1 is arranged as instances 190 to 193 on actual layout data. The parasitic capacitance Cb between the node of the B pin of the instance 190 and the node of the NB pin of the instance 191, the parasitic capacitance Cnb between the node of the NB pin of the instance 190 and the node of the B pin of the instance 193, and the WL1 pin of the instance 190 The case where the parasitic capacitance Cw exists between the node of the instance 192 and the node of the WL2 pin of the instance 192 is shown as an example.
[0114]
As described above, by reflecting the parasitic information existing between the cells constituting the actual layout data in the delay model, the accuracy of the delay simulation netlist can be increased, and a highly accurate delay simulation can be performed.
[0115]
In the description of the present embodiment, the basic processing flow of the delay model generating means is as shown in FIG. 1, but instead of the flow of FIG. 1, a processing flow based on any of FIGS. The same effect can be obtained.
[0116]
(Embodiment 15)
A delay simulation netlist generation system according to a fifteenth embodiment of the present invention will be described with reference to FIGS. In the present embodiment, the value of the parasitic capacitance Cb existing between the node of the B pin of the instance 190 and the node of the NB pin of the instance 191 in the delay model of the fourteenth embodiment described above is shown in FIG. As shown in an example of a), it has as information modeled in association with the arrangement information of each cell. In FIG. 22A, for example, between the node of the pin B of the instance 190 arranged without rotation and inversion and the node of the pin NB of the instance 191 arranged without rotation and inversion, This indicates that a parasitic capacitance of .0 fF exists. The arrangement direction in FIG. 22A follows the definition of the LPE cell arrangement direction information control table in FIG. 13C described above. In a simulation netlist including a configuration in which a plurality of delay models are arranged in an array, the LPE data corresponding to the delay model indicates that the parasitic element information existing between adjacent LPE data is the LPE data. Correlate with the data arrangement information.
[0117]
As described above, in the present embodiment, by using the delay model file having the above-described contents, in the simulation simulation netlist including the configuration in which a plurality of delay models are arranged in an array, the parasitic information existing between cells is provided. Can be modeled with a table that is previously associated with placement information, and a simulation netlist can be obtained. This allows the parasitic information existing between the cells constituting the actual layout data to be reflected in the delay model while considering the cell arrangement directions of each other, so that a highly accurate delay simulation can be performed.
[0118]
In the description of the present embodiment, the basic processing flow of the delay model generating means is as shown in FIG. 1, but instead of the flow of FIG. 1, a processing flow based on any of FIGS. The same effect can be obtained.
[0119]
(Embodiment 16)
A delay simulation netlist generation system according to a sixteenth embodiment of the present invention will be described with reference to FIG. This embodiment shows a specific example of the contents of the delay model file 5 based on the processing flow shown in the first embodiment. In FIG. 23, Rvdd1 to Rvdd4 indicate the parasitic information of the power supply line in the delay model, and Rvss1 to Rvss4 indicate the parasitic information of the ground line in the delay model.
[0120]
As described above, in the present embodiment, the effects such as the voltage effect are taken into account by modeling using the delay model file having the contents shown in FIG. 23 and including the parasitic element information of the power supply line and the ground line. A simulation can be performed. Further, since the modeling of the parasitic element information of the power supply line and the ground line is performed at the cell level, it is possible to generate a delay simulation netlist with a reduced data amount.
[0121]
In the description of the present embodiment, the basic processing flow of the delay model generating means is as shown in FIG. 1, but instead of the flow of FIG. 1, a processing flow based on any of FIGS. The same effect can be obtained.
[0122]
(Embodiment 17)
A delay simulation netlist generation system according to a seventeenth embodiment of the present invention will be described with reference to FIG. In the present embodiment, a simulation netlist for a delay model formed by arranging the delay models of the sixteenth embodiment described above is arranged. FIG. 24 shows the voltage effect from the input point (VDDin) of the power supply line of the block to the input point (VDDn) of the power supply line of the furthest cell and the source terminal of the MOS transistor inside the furthest cell. It is a figure which shows typically the case where it is going to confirm by delay simulation.
[0123]
Conventionally, for example, in order to confirm a voltage effect by a simulation, a huge amount of parasitic information on a power supply line needs to be included in a simulation netlist, and thus there has been a problem that a long simulation time is required. Alternatively, there were cases where LPE data extraction itself could not be performed. However, in the present embodiment, as shown in FIG. 24, by repeatedly modeling the power supply lines inside the cells, in the case where the same cells are arranged in an array, the advantage of the layout configuration is taken advantage of. A simulation netlist can be generated by modeling the parasitic information of the power supply line and the ground line while keeping the data amount small.
[0124]
As described above, according to the contents of the delay model file shown in the seventeenth embodiment of the present invention, the modeling is performed including the parasitic element information of the power supply line and the ground line, and the simulation net having the models arranged side by side. The list has a small amount of data and can perform a highly accurate delay simulation in consideration of parasitic information of the power supply line and the ground line.
[0125]
In the description of the present embodiment, the basic processing flow of the delay model generating means is as shown in FIG. 1, but instead of the flow of FIG. 1, a processing flow based on any of FIGS. The same effect can be obtained.
[0126]
【The invention's effect】
As described above, according to the present invention, the LPE netlist is delay-modeled for each arbitrarily set basic circuit unit that constitutes the pre-layout netlist, thereby taking into account the accuracy required for each basic circuit unit. Since delay modeling can be performed, a delay simulation netlist with a small amount of data can be generated while maintaining necessary accuracy. As a result, even in a large-scale circuit, it is possible to perform delay simulation for the entire block, and it is possible to execute a simulation at a higher speed than in the conventional method.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a delay simulation netlist generation system according to a first embodiment of the present invention.
FIG. 2 is a block diagram showing a delay simulation netlist generation system according to a second embodiment of the present invention.
FIG. 3 is a block diagram showing a delay simulation netlist generation system according to a third embodiment of the present invention.
FIG. 4 is a block diagram illustrating a delay simulation netlist generation system according to a fourth embodiment of the present invention.
FIG. 5 is a block diagram showing a delay simulation netlist generation system according to a fifth embodiment of the present invention.
FIG. 6 is a block diagram illustrating a delay simulation netlist generation system according to a sixth embodiment of the present invention.
FIG. 7 is an example of circuit data used in a delay simulation netlist generation system according to seventh to ninth embodiments of the present invention.
FIG. 8 is another example of circuit data used in the delay simulation netlist generation system according to the seventh to ninth embodiments of the present invention.
FIG. 9 is an example of circuit data used in the delay simulation netlist generation systems according to the tenth and eleventh embodiments of the present invention.
FIG. 10 is another example of circuit data used in the delay simulation netlist generation system according to the tenth and eleventh embodiments of the present invention.
FIGS. 11A and 11B are examples of LPE information association properties according to the seventh embodiment of the present invention.
FIGS. 12A and 12B are examples of LPE information association properties according to the eighth embodiment of the present invention.
FIGS. 13A and 13B are examples of LPE information association properties according to the ninth embodiment of the present invention, and FIG. 13C is an example of an LPE cell arrangement direction control information table.
FIGS. 14A and 14B are explanatory diagrams showing an example in which LPE data adopts an inverted or rotated arrangement.
FIGS. 15A and 15B are explanatory diagrams showing an example of a case where LPE data adopts an inverted or rotated arrangement.
FIGS. 16A and 16B are explanatory diagrams illustrating an example of the content of an LPE information association property according to the tenth embodiment of the present invention.
FIGS. 17A and 17B are explanatory diagrams illustrating an example of the content of an LPE information association property according to the eleventh embodiment of the present invention.
FIG. 18 is a block diagram showing a delay simulation netlist generation system according to a twelfth embodiment of the present invention.
FIGS. 19A to 19D are explanatory diagrams respectively showing examples of an LPE netlist, an LPE parasitic element merge result file, modeling coefficient calculation formula information, and modeling type information in the twelfth embodiment. .
FIG. 20 is a block diagram showing a delay simulation netlist generation system according to a thirteenth embodiment of the present invention.
FIG. 21 is a diagram showing contents of a delay model file in a delay simulation netlist generation system according to a fourteenth embodiment of the present invention.
FIGS. 22A and 22B are diagrams showing contents of a delay model file in a delay simulation netlist generation system according to a fifteenth embodiment of the present invention.
FIG. 23 is a diagram showing the contents of a delay model file in the delay simulation netlist generation system according to the sixteenth embodiment of the present invention.
FIG. 24 is a diagram showing contents of a delay model file in the delay simulation netlist generation system according to the seventeenth embodiment of the present invention.
[Description of sign]
1 Pre-layout netlist
2 LPE information association property
3 LPE netlist
4 Delay model generation means
5 Delay model file
6. Netlist generation means for delay simulation
7 Netlist for delay simulation
8 Circuit data
9 Layout data
10 LPE control means
11 Configuration parameter file
41 LPE parasitic element merge processing unit,
42 LPE parasitic element merge result file
43 Model Variable Calculation Processing Unit
44 Delay Model Generation Means
45 Modeling type information
46 Modeling coefficient calculation formula
70 Control circuit area
71 Address decoder area
72 Memory array area
73 I / O circuit area
80 Memory array area deleted due to circuit configuration
90 Parasitic element model of address decoder area
91,92 Parasitic element model with emphasis on word lines in memory array area
93, 94 Parasitic element model with emphasis on bit lines in memory array area
95 Parasitic element model of input / output circuit area
100 Parasitic element model of address decoder area
101, 103, 105 Parasitic element models emphasizing bit lines in the memory array area 102, 104 Parasitic element models emphasizing word lines in the memory array area
106 Parasitic element model constituting input / output circuit area
171 Information that the LPE netlist has
172 LPE parasitic element merge result file information
173 Information that the modeling coefficient calculation formula has
174 Information of Modeling Type Information
190 to 193 Instance consisting of LPE data

Claims (36)

A pre-layout netlist, an LPE netlist of a layout parasitic element extraction result, and an LPE information association property for associating the LPE netlist with the prelayout netlist are input, and according to the contents of the LPE information association property, Delay model generating means for generating a delay model file from the pre-layout netlist and the LPE netlist;
A delay simulation netlist generation system for a semiconductor integrated circuit, comprising: a delay simulation netlist generation unit configured to generate a delay simulation netlist from the delay model file and the pre-layout netlist. 2. The delay simulation netlist generation system according to claim 1, further comprising netlist conversion processing means for generating the pre-layout netlist and the LPE information association property from circuit data. LPE control means for generating the LPE netlist from layout data based on information of the LPE information association property from layout data including at least one leaf cell corresponding to the circuit data as a constituent unit. 3. The delay simulation netlist generation system according to claim 2. 2. The delay simulation netlist generation system according to claim 1, wherein the delay simulation netlist generation means refers to configuration parameter information of a configuration parameter file when generating the delay simulation netlist. 2. The delay simulation netlist generation system according to claim 1, wherein the delay model generation means refers to configuration parameter information of a configuration parameter file when generating the delay model file. 2. The delay simulation netlist generation system according to claim 1, wherein configuration parameter information from a configuration parameter file is given to said pre-layout netlist in advance. 3. The delay simulation according to claim 2, wherein the circuit data is circuit-equivalent to layout data actually used for mask processing, and circuit units configuring the circuit data individually have the LPE information association property. 4. Netlist generation system. 8. The delay simulation netlist generation system according to claim 7, wherein said circuit data is constituted only of cells including an active node and an active related node required for performing a delay simulation. 8. The delay simulation netlist generation system according to claim 7, wherein the circuit data includes a cell modeled in advance with a parasitic element, instead of a circuit unit constituting the circuit data. 9. The delay simulation netlist generation system according to claim 8, wherein the circuit data includes a cell modeled in advance with a parasitic element, instead of a circuit unit constituting the circuit data. 8. The netlist generation system for delay simulation according to claim 7, comprising, as basic units of the LPE information association property, at least a name of an LPE cell having layout parasitic element extraction result information and modeling type information. As a basic unit of the LPE information association property, a name of an active node on which signal propagation is newly performed in a delay simulation, a pin name on the active node, and a name of an active related node having a parasitic element between the active node 12. The delay simulation netlist generation system according to claim 11, comprising a name. 13. The delay simulation netlist generation system according to claim 12, further comprising layout arrangement direction information as a basic unit of the LPE information association property. 10. The delay simulation netlist generation system according to claim 9, comprising at least an LPE cell name and a modeling coefficient calculation formula as basic units of the LPE information association property. 15. The netlist generation system for delay simulation according to claim 14, further comprising an active node name, a pin name on the active node, and an active related node name as basic units of the LPE information association property. The delay model generation means,
Modeling information storage means that stores at least a modeling coefficient calculation formula and modeling type information,
LPE parasitic element merge processing means for generating an LPE parasitic element merge result file using the LPE information association property, the LPE netlist, and the information of the modeling information storage means;
12. The delay according to claim 11, further comprising: a model variable calculation processing unit configured to generate the delay model file for each cell using the LPE parasitic element merge result file and information included in the modeling information storage unit. Simulation netlist generation system. The delay model generation means,
LPE parasitic element merge processing means for generating an LPE parasitic element merge result file using the LPE information association property and information of the LPE netlist;
15. The delay simulation according to claim 14, further comprising: a model variable calculating unit configured to generate the delay model file for each cell using the LPE parasitic element merge result file and information included in the LPE information association property. Netlist generation system. 2. The delay simulation netlist generation system according to claim 1, wherein said delay model generation means generates a delay model having information on parasitic elements existing between adjacent cells. A plurality of the delay models are arranged in an array, and each delay model is configured such that parasitic element information existing between LPE data corresponding to the delay model and adjacent LPE data is associated with the arrangement information of the LPE data. 19. The delay simulation netlist generation system according to claim 18, wherein the system is expressed. 2. The delay simulation netlist generation system according to claim 1, wherein the delay model generation means generates the delay model by modeling notation including parasitic element information of a power supply line and a ground line. 21. The delay simulation netlist generation system according to claim 20, wherein a simulation netlist including the delay model is generated. 8. The delay simulation netlist generation system according to claim 7, wherein a pre-layout netlist associated with a cell configuration unit level and an LPE information association property are used instead of the circuit data. 8. The delay simulation netlist generation system according to claim 7, wherein the circuit data includes only cells including an active node and an active related node required for performing a delay simulation. 9. The delay simulation netlist generation system according to claim 8, wherein a prelayout netlist and an LPE information association property associated at a cell configuration unit level are used instead of the circuit data. 9. The delay simulation netlist generation system according to claim 8, wherein the circuit data includes only cells including an active node and an active related node necessary for performing a delay simulation. 10. The delay simulation netlist generation system according to claim 9, wherein a pre-layout netlist associated with a cell configuration unit level and an LPE information association property are used instead of the circuit data. 10. The delay simulation netlist generation system according to claim 9, wherein the circuit data includes only cells including an active node and an active related node necessary for performing a delay simulation. 11. The delay simulation netlist generation system according to claim 10, wherein a prelayout netlist associated with a cell configuration unit level and an LPE information association property are used instead of the circuit data. The netlist generation system for delay simulation according to claim 10, wherein the circuit data includes only cells including an active node and an active related node required for performing a delay simulation. 12. The delay simulation netlist generation system according to claim 11, wherein a pre-layout netlist associated with a cell configuration unit level and an LPE information association property are used instead of the circuit data. 12. The delay simulation netlist generation system according to claim 11, wherein the circuit data includes only cells including an active node and an active related node required for performing a delay simulation. 17. The delay simulation netlist generation system according to claim 16, wherein a prelayout netlist associated with a cell configuration unit level and an LPE information association property are used instead of the circuit data. 17. The delay simulation netlist generation system according to claim 16, wherein the circuit data includes only cells including an active node and an active related node necessary for performing a delay simulation. 18. The delay simulation netlist generation system according to claim 17, wherein a prelayout netlist and an LPE information association property associated at a cell configuration unit level are used instead of the circuit data. 18. The delay simulation netlist generation system according to claim 17, wherein the circuit data is constituted only of cells including an active node and an active related node necessary for performing a delay simulation. A pre-layout netlist, an LPE netlist of a layout parasitic element extraction result, and an LPE information association property for associating the LPE netlist with the prelayout netlist are input, and according to the contents of the LPE information association property, A delay model generating step of generating a delay model file from the pre-layout netlist and the LPE netlist;
A delay simulation netlist generating step of generating a delay simulation netlist from the delay model file and the pre-layout netlist.

Images