CN110795899A - Chip power-on control device - Google Patents
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Abstract
The invention provides an on-chip electric control device which comprises a power supply shutoff PSO chain, wherein the PSO chain comprises a plurality of PSO sub-chains distributed according to the power-on sequence, each PSO sub-chain in the plurality of PSO sub-chains is provided with an adjustable delay circuit corresponding to the PSO sub-chain, and the delay signal output end of the adjustable delay circuit is connected with the input end of the first PSO unit of the PSO sub-chain corresponding to the adjustable delay circuit; the delay signal input end of the adjustable delay circuit corresponding to the first PSO sub-chain in the PSO sub-chains is connected with the power-on control signal output port of the PSO chain, and the delay signal input end of the adjustable delay circuit corresponding to each other PSO sub-chain except the first PSO sub-chain in the PSO sub-chains is connected with the output end of the last PSO unit of the previous PSO sub-chain of the other PSO sub-chains. The invention can reduce the use of always-on units in the turn-off module, reduce the design area of the turn-off module and the cost of routing resources, further reduce the iteration times of low-power design and accelerate the convergence of the low-power design.
Description
Technical Field
The invention relates to the technical field of low-power-consumption design of integrated circuits, in particular to an on-chip electric control device.
Background
The Power Shutdown (PSO) technology is a low power consumption design technology commonly used in the field of integrated circuit design, and can realize fine-grained power consumption control, and reduce leakage and dynamic power consumption in a chip by shutting down power supply to a module circuit in an idle state in the chip, and a circuit basic structure of the technology is shown in fig. 1: in this configuration, the logic function transistor operates to supply power from a large PMOS transistor connected to a power supply, the gate of which is controlled by an enable control signal. When the enable signal is turned on, current flows from the power supply through the PMOS tube and is supplied to the logic circuit; when the enable signal is turned off, the power supply to the logic function circuit is cut off, and the logic circuit stops operating.
In a module design implementation of a low power consumption design, a large number of PSO cells are generally uniformly scattered, and gate terminals of the PSO cells are connected in series to form a power-on control chain, i.e., a PSO chain, as shown in fig. 2. Before the circuit works normally, the power-on control module of the chip sends an instruction, the instruction is transmitted to Npwr _ in, the enable end of the PSO is controlled to be opened according to a set organization sequence, and the power-on process is completed within a limited time. And a response signal Npwr _ out after electrification is finished is fed back to the control module, and the control module dispatches the functional circuit to normally work.
The power-on process is a process that PMOS tubes on the PSO enabling control link are opened one by one. At the initial stage of electrification, the electrification module has a large demand on electric quantity, and along with the rapid and one-by-one opening of PMOS tubes on a control link, a large amount of current flows into the electrification module in a short time, so that a surge current with a high peak value is generated, and at the moment, the change rate of the current in unit time is high, so that high inductance is caused, the fluctuation of the working voltage of a chip is caused, and the chip is unstable in work; in addition, a large amount of current is inrush into the power-on module, and the circuit voltage of the normal working modules around the power-on module can be reduced, so that the normal work of the chip is affected, and even the chip makes mistakes.
The current solution to this problem is to insert an appropriate amount of delay cells into the link, which slows down the power-up process. After the delay unit is inserted, the opening speed of the PMOS of the PSO chain is reduced, the current which can flow into the power-on module in unit time is limited, and the current change rate is reduced, so that the adverse effect of quick power-on is weakened.
In low power designs, the PSO cells on the PSO chain need to operate within the always-on voltage threshold, so inserting delay cells on the PSO chain within the switchable module necessitates the use of cells of the always-on attribute. The unit has two groups of power supplies and grounds, and the property can cause the design area of the turn-off module to be increased; in addition, a set of power and ground lines need to be connected to the always-on power plane in the form of signal lines, which will increase the overhead of designing the routing resources, and these problems represent extraordinary prominence in high-speed and high-density designs, which will seriously affect the convergence of low-power designs.
Disclosure of Invention
The invention provides an on-chip electric control device, and aims to solve the problems that an always-on attribute unit in a turn-off module occupies a large area, routing resource overhead is high, and convergence of low-power-consumption design is influenced.
In order to achieve the above object, an embodiment of the present invention provides an on-chip electronic control device, which includes a power-off PSO chain, where the PSO chain includes a plurality of PSO sub-chains distributed in an electrifying sequence, each PSO sub-chain of the PSO sub-chains is provided with an adjustable delay circuit corresponding to the PSO sub-chain, a delay signal output end of the adjustable delay circuit is connected to an input end of a first PSO unit of the PSO sub-chain corresponding to the adjustable delay circuit, and a delay control signal input end of the adjustable delay circuit is connected to a delay control signal output port;
the delay signal input end of the adjustable delay circuit corresponding to the first PSO sub-chain of the PSO sub-chains is connected with the power-on control signal output port of the PSO chain, the delay signal input end of the adjustable delay circuit corresponding to each other PSO sub-chain except the first PSO sub-chain of the PSO sub-chains is connected with the output end of the last PSO unit of the previous PSO sub-chain of the other PSO sub-chains, and the output end of the last PSO unit of the last PSO sub-chain of the PSO sub-chains is connected with the power-on completion signal output port.
Wherein the adjustable delay circuit comprises: the decoder comprises a first decoder, a first delay circuit, a second decoder and a second delay circuit;
an address input signal end of the first decoder and an address input signal end of the second decoder are both connected to the delay control signal output port, an output end of the first decoder is connected to an enable signal input end of the first delay circuit, an output end of the second decoder is connected to an enable signal input end of the second delay circuit, a delay signal input end of the second delay circuit is a delay signal input end of the adjustable delay circuit, a delay signal output end of the second delay circuit is connected to a delay signal input end of the first delay circuit, and a delay signal output end of the first delay circuit is a delay signal output end of the adjustable delay circuit;
the minimum delay output by the delayed signal output of the first delay circuit is equal to the maximum delay output by the delayed signal output of the second delay circuit.
Wherein the first decoder and the second decoder are both 3-input decoders.
The delay control signal output port is an output port of a register.
The scheme of the invention has at least the following beneficial effects:
in the embodiment of the invention, the PSO chain is divided into a plurality of PSO sub-chains which are independent and distributed according to the power-on sequence, and each PSO sub-chain is provided with an adjustable delay circuit with configurable delay, so that the output delay of each PSO sub-chain can be configured according to the actual power-on requirement, meanwhile, the delay signal input end of the adjustable delay circuit corresponding to the first PSO sub-chain in the PSO sub-chains is connected with the power-on control signal output port of the PSO chain, the delay signal input end of the adjustable delay circuit corresponding to each other PSO sub-chain except the first PSO sub-chain is connected with the output end of the last PSO unit of the previous PSO sub-chain in the other PSO sub-chains, the output end of the last PSO unit of the last PSO sub-chain is connected with the power-on completion signal output port, all PSO sub-chains are connected in series to form a complete link, and therefore, for the switchable module, the input end of the first PSO unit and the last PSO unit of each PSO sub-chain are led out to the output end of the switchable module And at the boundary, the adjustable delay circuit corresponding to each PSO sub-chain is positioned in a non-turn-off region outside the turn-off module, so that the use number of always-on units in the turn-off module is reduced, the design area of the turn-off module and the cost of routing resources are reduced, the iteration times of low-power design are reduced, and the convergence of the low-power design is accelerated. In addition, in the post-silicon debugging, if the power-on time is too fast, the value of the delay control signal input end of the adjustable delay circuit can be changed in a software debugging mode, so that more reasonable power-on time configuration is obtained. With the increase of the working time of the chip after silicon, when the power supply battery is aged gradually, the internal resistance of the battery is increased gradually, and the power supply current is attenuated gradually, so that the power-on time is deviated, the configuration of software can be adjusted in a mode of combining software and hardware, more reasonable power-on control chain delay is obtained on the hardware, and the power-on of the chip is more reasonable.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
FIG. 1 is a power consumption control schematic based on PSO technology;
FIG. 2 is a prior art PSO chain organization scheme;
FIG. 3 is a schematic structural diagram of a power-on-chip control apparatus according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of an embodiment of an adjustable delay circuit;
fig. 5 is a schematic structural diagram of a delay circuit according to an embodiment of the present invention.
[ description of reference ]
31. An adjustable delay circuit; 32. a power-on control signal output port; 33. a power-up completion signal output port; 41. a first decoder; 42. a first delay circuit; 43. a second decoder; 44. a second delay circuit; 45. an address input signal terminal; 46. a delayed signal input; and 47 delay the signal output.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
As shown in fig. 3, an embodiment of the present invention provides an on-chip electronic control device, which includes a power-off PSO chain, where the PSO chain includes a plurality of PSO sub-chains distributed according to a power-on sequence, each PSO sub-chain of the PSO sub-chains is provided with an adjustable delay circuit 31 corresponding to the PSO sub-chain, a delay signal output end of the adjustable delay circuit 31 is connected to an input end of a first PSO unit of the PSO sub-chain corresponding to the adjustable delay circuit 31, and a delay control signal input end of the adjustable delay circuit 31 is connected to a delay control signal output port.
A delay signal input end of the adjustable delay circuit 31 corresponding to a first PSO sub-chain of the PSO sub-chains is connected to the power-on control signal output port 32 of the PSO chain, a delay signal input end of the adjustable delay circuit 31 corresponding to each other PSO sub-chain of the PSO sub-chains except the first PSO sub-chain is connected to an output end of a last PSO unit of a previous PSO sub-chain of the other PSO sub-chains, and an output end of a last PSO unit of the last PSO sub-chain of the PSO sub-chains is connected to the power-on completion signal output port 33.
It should be noted that, since the plurality of PSO sub-chains are ordered according to the power-on sequence, the previous PSO sub-chain of another PSO sub-chain is the PSO sub-chain that is ranked one bit before the other PSO sub-chain. As shown in fig. 3, the first PSO subchain is a previous PSO subchain of the intermediate PSO subchain 1, and the intermediate PSO subchain 1 is a previous PSO subchain of the intermediate PSO subchain 2, wherein the intermediate PSO subchain 1 and the intermediate PSO subchain 2 in fig. 3 are PSO subchains between the first PSO subchain and the last PSO subchain. It will be appreciated that a plurality of PSO sub-chains are connected in series into a complete chain by a corresponding plurality of adjustable delay circuits 31.
In the embodiment of the present invention, the number of PSO units included in the PSO sub-chains may be different. Preferably, the PSO units included in the first PSO sub-chain of the PSO sub-chains may be appropriately smaller, so as to facilitate control of the number of PSO units opened in the early stage of power-on.
In the embodiment of the present invention, in order to reduce the number of always-on units in the turn-off module, the input end of the first PSO unit and the output end of the last PSO unit of each PSO sub-chain are led out to the boundary of the turn-off module, and the adjustable delay circuit 31 corresponding to each PSO sub-chain is located in a non-turn-off region outside the turn-off module, so that the number of always-on units in the turn-off module is reduced, and accordingly, the design area and routing resource overhead of the turn-off module are reduced, thereby reducing the iteration number of the low power consumption design and accelerating the convergence of the low power consumption design.
It should be noted that the structures of the adjustable delay circuits corresponding to the PSO sub-chains are the same, and in the embodiment of the present invention, the delay time output by the adjustable delay circuits may be configured as needed, so that the delay time of each PSO sub-chain may be configured as needed. The delay time of the output of the adjustable delay circuit is specifically determined by a delay control signal received by a delay control signal input end of the adjustable delay circuit. It should be noted that the delay control signal is output from a delay control signal output port. As a preferred example, the delay control signal output port may be an output port of a register.
In the embodiment of the invention, the electrifying current waveform of the whole PSO chain can be obtained by a simulation tool in the early stage of design, and the surge current is reduced by adjusting the delay time between two adjacent PSO sub-chains to obtain a better electrifying current waveform, so that reference is provided for setting the actual delay of the adjustable delay circuit. When all the PSO subchains are connected by the adjustable delay circuit, the power consumption of the design changes along with the depth of the design, and at the moment, if the best electrifying current waveform is to be achieved, only the configuration of the relevant register needs to be adjusted, so that the iteration of the design is avoided.
As is well known, in a power supply system of a chip, as operating time goes by, a power supply battery may gradually age, a resistance in the battery may gradually increase, and a power supply current may gradually decay, thereby causing power-on time variation of a power-on module of the chip. If the power-on system is not designed to be adjustable, the reliability of the chip operation gradually decreases as the power supply system ages. Regarding to the problem, after the chip adopts the on-chip electronic control device provided by the embodiment of the invention, when the chip suffers from the problem of power supply aging during operation, the chip can also operate in a more perfect state by adjusting the configuration of the delay time of the adjustable delay circuit.
In an embodiment of the present invention, as shown in fig. 4, the adjustable delay circuit includes: a first decoder 41, a first delay circuit 42, a second decoder 43, and a second delay circuit 44.
Wherein, the address input signal terminal 45 of the first decoder 41 and the address input signal terminal 45 of the second decoder 43 are both connected to the delay control signal output port, the output terminal of the first decoder 41 (the output terminal is used for outputting the enable signal generated by the first decoder) is connected to the enable signal input terminal of the first delay circuit 42, the output terminal of the second decoder 43 (the output terminal is used for outputting the enable signal generated by the second decoder) is connected to the enable signal input terminal of the second delay circuit 44, the delay signal input terminal 46 of the second delay circuit 44 is the delay signal input terminal of the adjustable delay circuit, the delay signal output terminal of the second delay circuit 44 (the delay signal output terminal is used for outputting the delay signal generated by the second delay circuit) is connected to the delay signal input terminal of the first delay circuit 42, the delayed signal output 47 of the first delay circuit 42, which is used for outputting the delayed signal generated by the first delay circuit, is the delayed signal output of the adjustable delay circuit.
Wherein the minimum delay output from the delayed signal output terminal of the first delay circuit 42 is equal to the maximum delay output from the delayed signal output terminal of the second delay circuit 44.
The number of delay stages of the first delay circuit 42 is determined by the number of inputs of the first decoder 42, and the number of delay stages of the second delay circuit 44 is determined by the number of inputs of the second decoder 43. As a preferred example, the first decoder 41 and the second decoder 43 are both 3-input decoders, and then the first decoder 41 can control the first delay circuit 42 to generate 8 adjustable delays, and the second decoder 43 can control the second delay circuit 44 to generate 8 adjustable delays. The minimum step delay output by the first delay circuit 42 corresponds to the maximum step delay output by the second delay circuit 44 (i.e., the minimum step delay output by the first delay circuit 42 is slightly greater than or equal to the maximum step delay output by the second delay circuit 44), and each step delay of the second delay circuit 44 corresponds to one eighth of the minimum step delay of the first delay circuit 42.
It should be noted that the specific structures of the first delay circuit 42 and the second delay circuit 44 can be implemented by using existing delay circuits, and the basic structures are identical, the difference lies in the size of the delay buffer chain on the gear, and the specific structure of the delay circuit is shown in fig. 5. The circuit structure of each stage is shown in the dashed block diagram of fig. 5, wherein Dly _ in is an input delay signal (i.e., a signal received by a delay signal input terminal of the adjustable delay circuit), En [0: m ] is an enable signal generated by decoding, m is the input number of the decoder, Dly _ out is a delay signal output by the delay circuit, and Buf _ chain is a buffer chain formed by delay buffers inserted according to design requirements. It should be further noted that, in the actual use process, the register connected to the adjustable delay circuit may be configured to complete the adjustment of the enable signal generated by decoding, so as to complete the selection of the delay stage of the adjustable delay circuit.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (4)
1. An on-chip electric control device comprises a power supply turn-off PSO chain, and is characterized in that the PSO chain comprises a plurality of PSO sub-chains distributed according to a power-on sequence, each PSO sub-chain in the PSO sub-chains is provided with an adjustable delay circuit corresponding to the PSO sub-chain, a delay signal output end of the adjustable delay circuit is connected with an input end of a first PSO unit of the PSO sub-chain corresponding to the adjustable delay circuit, and a delay control signal input end of the adjustable delay circuit is connected with a delay control signal output end;
the delay signal input end of the adjustable delay circuit corresponding to the first PSO sub-chain of the PSO sub-chains is connected with the power-on control signal output port of the PSO chain, the delay signal input end of the adjustable delay circuit corresponding to each other PSO sub-chain except the first PSO sub-chain of the PSO sub-chains is connected with the output end of the last PSO unit of the previous PSO sub-chain of the other PSO sub-chains, and the output end of the last PSO unit of the last PSO sub-chain of the PSO sub-chains is connected with the power-on completion signal output port.
2. The on-chip power-on control device of claim 1, wherein the adjustable delay circuit comprises: the decoder comprises a first decoder, a first delay circuit, a second decoder and a second delay circuit;
an address input signal end of the first decoder and an address input signal end of the second decoder are both connected to the delay control signal output port, an output end of the first decoder is connected to an enable signal input end of the first delay circuit, an output end of the second decoder is connected to an enable signal input end of the second delay circuit, a delay signal input end of the second delay circuit is a delay signal input end of the adjustable delay circuit, a delay signal output end of the second delay circuit is connected to a delay signal input end of the first delay circuit, and a delay signal output end of the first delay circuit is a delay signal output end of the adjustable delay circuit;
the minimum delay output by the delayed signal output of the first delay circuit is equal to the maximum delay output by the delayed signal output of the second delay circuit.
3. The on-chip power-on control device of claim 2, wherein the first decoder and the second decoder are both 3-input decoders.
4. The on-chip power-on control device according to claim 1, wherein the delay control signal output port is an output port of a register.
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| CN113935273A (en) * | 2021-09-17 | 2022-01-14 | 东科半导体(安徽)股份有限公司 | Control signal connection method of low-power-consumption module |
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