CN213751053U - Testability framework of chip - Google Patents
Testability framework of chip Download PDFInfo
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- CN213751053U CN213751053U CN202022636637.3U CN202022636637U CN213751053U CN 213751053 U CN213751053 U CN 213751053U CN 202022636637 U CN202022636637 U CN 202022636637U CN 213751053 U CN213751053 U CN 213751053U
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Abstract
The utility model discloses a testability framework of chip relates to integrated circuit technical field. The utility model provides a testability framework includes test logic module and functional logic module, test logic module includes independent test unit and mixed test unit, independent test unit with functional logic module separates each other; the testability architecture has a functional mode in which power to the individual test units is disconnected and a test mode; in a test mode, the power supplies of the independent test unit, the hybrid test unit and the functional logic module are in a connection state. The utility model discloses on the basis that uses clock gate to reduce testable design chip dynamic power consumption, through the method in many power domains, to test logic module outage, reach the purpose that reduces static consumption by a wide margin for the overall consumption of the during operation of chip is lower.
Description
[ technical field ] A method for producing a semiconductor device
The utility model relates to an integrated circuit technical field, concretely relates to testability framework of chip.
[ background of the invention ]
Today, as the size and complexity of integrated circuits increase, and the relative gate count of pins in a chip decreases, the controllability and observability of the circuits decrease dramatically. The traditional test method is difficult to comprehensively and effectively verify the design and manufacture correctness of the complex integrated circuit. The design of the testability method provides a solution for the problem, and the purpose of improving the controllability and observability of the circuit is achieved by properly adding some special test circuits, so that the difficulty and complexity of circuit test are reduced, the efficiency of the circuit test is improved, and the cost is reduced. However, these integrated circuits dedicated to testing also generate a lot of power consumption when the chip is operating normally. With the increasing scale and speed of digital circuit chips, the power consumption of the chips is higher and higher. In many applications, power consumption has become a primary consideration in chip design. Most of the existing testable designs adopt a clock gating structure to achieve the purpose of eliminating the dynamic Power consumption of a test circuit, but cannot eliminate the leakage current Power consumption caused by the leakage current, namely Static Power consumption (Static Power). Although the working voltage of the chip is already at a lower level nowadays, the leakage current of a single MOS transistor is very small, but with the increase of the transistor scale of the chip, some of the transistors can reach hundreds of millions or even billions, the circuit scale introduced by the testability design also increases at the same time, and the leakage current power consumption becomes an important component of the power consumption in the testability chip. How to reduce or even eliminate the leakage current power consumption of the testable integrated circuit is an unsolved problem which is not negligible at present.
[ Utility model ] content
In order to solve the problem, the utility model provides a testability framework of chip uses the clock gate to reduce the basis of testable design chip dynamic power consumption, through the method in many power domains, to the outage of test logic module, reaches the purpose that reduces static consumption by a wide margin for the whole consumption of the during operation of chip is lower.
In order to achieve the above purpose, the utility model adopts the following technical scheme:
a testability framework of a chip comprises a test logic module and a functional logic module, wherein the test logic module comprises an independent test unit and a mixed test unit, the mixed test unit and the functional logic module are mutually mixed, and the independent test unit and the functional logic module are mutually separated;
the testability architecture has a functional mode in which the power supply of the independent test unit is switched off and the power supply of the hybrid test unit and the functional logic module is switched on; in a test mode, the power supplies of the independent test unit, the hybrid test unit and the functional logic module are in an on state.
Optionally, the testability architecture has a test power domain and a functional power domain, the independent test unit is powered by VDD _ test in the test power domain, and the hybrid test unit and the functional logic module are powered by VDD _ func in the functional power domain.
Optionally, the testability architecture further includes a power switch controller unit and a power switch cells unit, where the power switch controller unit is in signal connection with the power switch cells unit, and in a functional mode, the power switch controller unit sends a turn-off control signal to the power switch cells unit, and the power switch cells unit disconnects power supply between VDD _ test and the independent test unit.
Optionally, the power switch controller unit and the power switch cells are powered by VDD _ func in the functional power domain.
Optionally, the power switch cells have an input end and an output end, the input end is connected to VDD _ func, and the output end is connected to VDD _ test.
Optionally, the power switch cells have a plurality of switch cells, the plurality of switch cells are connected end to end around the independent test unit to form a closed loop, or the plurality of switch cells are uniformly distributed around the independent test unit in a dot matrix manner.
Optionally, the functional mode and the test mode of the testability architecture are determined according to a test _ mode signal;
the default value of the test _ mode signal is 0, the testability architecture is in a functional mode, and the power switch controller unit sends a turn-off control signal to the power switch cells after receiving the test _ mode signal;
the test _ mode signal is set to be 1, the testability architecture is in a test mode, the power switch controller unit receives the test _ mode signal and sends an opening control signal to the power switch cells unit, and the power switch cells unit restores power supply between VDD _ test and the independent test unit.
Optionally, the test _ mode signal is input from the outside of the chip through an I/O port or generated inside the chip.
Optionally, the testability architecture further includes an isolation cells unit;
in the functional mode, the isolation cells are in an enabled state after receiving a test _ mode signal of 0, and the signal output by the independent test unit is locked as a fixed value to isolate the functional logic module;
in the test mode, the isolation cells are in a disabled state after receiving a test _ mode signal of 1, and the independent test unit is in signal connection with the functional logic module.
Optionally, the isolation cells are powered by VDD _ function in the functional power domain.
The utility model discloses following beneficial effect has:
in the prior art, most of chips with testable designs adopt a clock gating structure to achieve the purpose of reducing the dynamic power consumption of circuits, but leakage current cannot be eliminated, and still larger static power consumption exists. According to the technical scheme, on the basis of the prior art, through division of multiple power supply domains, independent test logic modules are divided into as many test logics as possible, the divided parts are distributed to different voltage domains for power supply, the independent test logic modules can be completely powered off when a chip works, the purpose of greatly reducing static power consumption is achieved, and the overall power consumption of a circuit is lower. Meanwhile, when the chip needs to be tested, the test power domain can normally supply power, the independent test logic module can normally work, and no adverse effect can be caused on the normal work of the test mode.
These features and advantages of the present invention will be disclosed in more detail in the following detailed description and the accompanying drawings. The best mode or means of the present invention will be described in detail with reference to the accompanying drawings, but not limited thereto. In addition, the features, elements and components appearing in each of the following and in the drawings are plural and different symbols or numerals are labeled for convenience of representation, but all represent components of the same or similar construction or function.
[ description of the drawings ]
The present invention will be further explained with reference to the accompanying drawings:
fig. 1 is a schematic view of the working flow of the embodiment of the present invention;
fig. 2 is a block diagram of the embodiment of the present invention.
[ detailed description ] embodiments
The technical solutions of the embodiments of the present invention are explained and explained below with reference to the drawings of the embodiments of the present invention, but the embodiments described below are only preferred embodiments of the present invention, and not all embodiments. Based on the embodiments in the embodiment, other embodiments obtained by those skilled in the art without any creative work belong to the protection scope of the present invention.
Reference in the specification to "one embodiment" or "an example" means that a particular feature, structure or characteristic described in connection with the embodiment itself may be included in at least one embodiment of the patent disclosure. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.
Example (b):
the embodiment provides a testability architecture of a chip.
As shown in fig. 2, in terms of logic modules, the testability architecture provided in this embodiment includes a test logic module, a functional logic module, a power switch controller unit, a power switch cells unit, and an isolation cells unit, where the test logic module includes an independent test unit and a hybrid test unit, and the specific circuits of the logic units and the logic modules are well known in the prior art and will not be described herein again. The hybrid test unit and the functional logic module are mixed with each other, and the independent test unit and the functional logic module are separated from each other. Because the test logic module and the functional logic module in the prior art have overlapped parts, the test logic module needs to be divided into an independent test unit and a mixed test unit as much as possible on the premise of not influencing the functional logic module, so that the independent test unit can use an independent power domain, the power supply of the independent test unit is controlled independently, and the power consumption of a chip is reduced to the maximum extent. The power switch controller unit is connected with the power switch cells through signals. A power switch cell has several switch cells. The cell is implemented by a CMOS circuit, and since the on current of a MOS is small, the current required is relatively large when the logic controlled by the MOS operates normally, and therefore a large number of cells are required to work together to carry this current. Therefore, in the embodiment, the plurality of switch cells are connected end to end around the independent test unit to form a closed loop, and in other embodiments, the plurality of switch cells may also be uniformly distributed around the independent test unit in a dot matrix manner, which is not limited herein. The functional logic module and the independent test unit have a signal transmission relationship, when the power supply of the independent test unit is turned off, the output signal of the independent test unit can be in an unstable state, namely an unpredictable value, and the circuit function is influenced, so that the isolation cells are used for isolating the output signal of the independent test unit with the power supply turned off from the functional logic module.
In terms of power supply, the testability architecture provided by the embodiment has a test power domain and a functional power domain. The independent test unit is powered by VDD _ test in the test power domain; the hybrid test unit, the functional logic module, the power switch controller unit, the power switch cells and the isolation cells are all powered by VDD _ func in the functional power domain. The power switch cells have input terminals connected to VDD _ func and output terminals connected to VDD _ test. On the premise of not changing functional logic, the independent test unit is separated, so that power supply of an independent power domain is conveniently realized, and the purpose of independently turning off the part of test logic is achieved.
As shown in fig. 1, the testability architecture provided by this embodiment has a functional mode and a test mode, the functional mode and the test mode are determined according to the test _ mode signal, and the test _ mode signal may be input from the outside of the chip through the I/O port or generated inside the chip, which is not limited herein.
the default value of the test _ mode signal is 0, the testability architecture is in a functional mode at the moment, the power switch controller unit sends a turn-off control signal to the power switch cells after receiving the test _ mode signal of 0, the power switch cells receive the turn-off control signal and then disconnect the power supply between VDD _ test and the independent test unit, so that the power supply of the independent test unit is cut off, the power supply of the hybrid test unit and the functional logic module is in a turn-on state, and the power supply of the logic is independently controlled in different working modes. The logic module in the functional power domain works normally, the independent test unit is powered off completely, no power consumption is generated, and the power consumption of the chip only comes from the logic module in the functional power domain. Meanwhile, the isolation cells are in an enabling state after receiving a test _ mode signal of 0, and the signal output by the independent test unit is locked as a fixed value so as to isolate the functional logic module and ensure that the output of the functional logic module does not interfere with the normal work of the functional logic module;
when the testability architecture needs to be tested, the test _ mode signal is set to be 1, the testability architecture is in a test mode at the time, the power switch controller unit sends an opening control signal to the power switch cells after receiving the test _ mode signal which is 1, the power switch cells unit recovers power supply between the VDD _ test and the independent test unit after receiving the opening control signal, the power supply of the independent test unit, the mixed test unit and the functional logic module is in a connection state, and all the logic modules work normally. Meanwhile, the isolation cells are in a disabled state after receiving the test _ mode signal of 1, and the independent test unit is in signal connection with the functional logic module to perform normal data transmission.
In the prior art, most of chip architectures of testable designs adopt a clock gating structure to achieve the purpose of reducing the dynamic power consumption of circuits, but leakage current cannot be eliminated, and still larger static power consumption exists. According to the technical scheme provided by the embodiment, on the basis of the prior art, through division of multiple power supply domains, independent test logic modules are divided from as many test logics as possible, and the divided parts are distributed to different voltage domains for power supply, so that the independent test logic modules can be completely powered off when a chip works, the purpose of greatly reducing static power consumption is achieved, and the overall power consumption of a circuit is lower. Meanwhile, when the chip needs to be tested, the test power domain can normally supply power, the independent test logic module can normally work, and no adverse effect can be caused on the normal work of the test mode.
While the present invention has been described with reference to the particular illustrative embodiments, it will be understood by those skilled in the art that the present invention is not limited thereto, and may be embodied in many different forms without departing from the spirit and scope of the present invention as set forth in the following claims. Any modification which does not depart from the functional and structural principles of the present invention is intended to be included within the scope of the claims.
Claims (10)
1. A testability framework of a chip comprises a test logic module and a functional logic module, and is characterized in that the test logic module comprises an independent test unit and a mixed test unit, the mixed test unit and the functional logic module are mutually mixed, and the independent test unit and the functional logic module are mutually separated;
the testability architecture has a functional mode in which the power supply of the independent test unit is switched off and the power supply of the hybrid test unit and the functional logic module is switched on; in a test mode, the power supplies of the independent test unit, the hybrid test unit and the functional logic module are in an on state.
2. The testability architecture of claim 1, wherein: the testability architecture has a test power domain and a functional power domain, the independent test unit is powered by VDD _ test in the test power domain, and the hybrid test unit and the functional logic module are powered by VDD _ func in the functional power domain.
3. The testability architecture of claim 2, wherein: the testability framework further comprises a power switch controller unit and a power switch cells unit, wherein the power switch controller unit is in signal connection with the power switch cells unit, in a functional mode, the power switch controller unit sends a turn-off control signal to the power switch cells unit, and the power switch cells unit disconnects power supply between VDD _ test and the independent test unit.
4. The testability architecture of claim 3, wherein: the power switch controller unit and power switch cells are powered by VDD _ func within the functional power domain.
5. The testability architecture of claim 3, wherein: the power switch cells are provided with input ends and output ends, wherein the input ends are connected with VDD _ func, and the output ends are connected with VDD _ test.
6. The testability architecture of claim 3, wherein: the power switch cells are provided with a plurality of switch cells, the switch cells are connected end to end around the independent test unit to form a closed loop, or the switch cells are uniformly distributed around the independent test unit in a dot matrix manner.
7. The testability architecture of one of claims 3 to 6, wherein: the functional mode and the test mode of the testability framework are determined according to the test _ mode signal; the default value of the test _ mode signal is 0, the testability architecture is in a functional mode, and the power switch controller unit sends a shutdown control signal to the power switch cells after receiving the test _ mode signal;
the test _ mode signal is set to be 1, the testability architecture is in a test mode, the power switch controller unit receives the test _ mode signal and sends an opening control signal to the power switch cells unit, and the power switch cells unit restores power supply between VDD _ test and the independent test unit.
8. The testability architecture of claim 7, wherein: the test _ mode signal is input from the outside of the chip through an I/O port or generated inside the chip.
9. The testability architecture of claim 7, wherein: the testability architecture further comprises an isolation cells unit; in the functional mode, the isolation cells are in an enabled state after receiving a test _ mode signal of 0, and the signal output by the independent test unit is locked as a fixed value to isolate the functional logic module;
in the test mode, the isolation cells are in a disabled state after receiving a test _ mode signal of 1, and the independent test unit is in signal connection with the functional logic module.
10. The testability architecture of claim 9, wherein: the isolation cells are powered by VDD _ func within the functional power domain.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115061032A (en) * | 2022-06-14 | 2022-09-16 | 无锡华大国奇科技有限公司 | Function test method and device for multi-clock-domain chip |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115061032A (en) * | 2022-06-14 | 2022-09-16 | 无锡华大国奇科技有限公司 | Function test method and device for multi-clock-domain chip |
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