JP5004566B2 - 設計を検証するシステム - Google Patents
設計を検証するシステム Download PDFInfo
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- JP5004566B2 JP5004566B2 JP2006317794A JP2006317794A JP5004566B2 JP 5004566 B2 JP5004566 B2 JP 5004566B2 JP 2006317794 A JP2006317794 A JP 2006317794A JP 2006317794 A JP2006317794 A JP 2006317794A JP 5004566 B2 JP5004566 B2 JP 5004566B2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/3668—Software testing
- G06F11/3672—Test management
- G06F11/3688—Test management for test execution, e.g. scheduling of test suites
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Quality & Reliability (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Tests Of Electronic Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Description
1つの実装では、設計の検証を実施するために、BOMを構築する。一実施例として、BOMは、ICの設計を検証するのに必要とされる項目のリストを含む。実装時に、このリストは、チップ・インテグレータによって提供される1組の共通必須要素と、特定のテスト・ケース用の特定のハードウェア・リソースのリストとを含み得る。そのため、一実施形態では、このシステムおよび方法は、チップの基本要素とテスト・ケース固有要素とを組み合わせることによってBOMを構築し、それによって、シミュレーション・モデルについての必要な最小限のBOMが生成される。
本発明の方法およびシステムでは、スタブ・ファイルを用いてモデル・ビルド・プロセスに命令することができる。すなわち、スタブ・ファイルを使用すると、BOMモデル・ビルド・ファイルを実装すべきファイルを、モデル・ビルド環境内に含めることができる。実施形態の一例として、以下でより詳細に論じるように、これらのスタブ・ファイルは、各ビルディング・ブロック(例えば、設計の機能ブロック)ごとに実モデル表現、または空モデル表現をインストールするようにモデル・ビルド・プロセスに命令することができる。
Claims (1)
- 設計を検証するシステムであって、
(a)1組の共通必須要素を提供する手段と、
(b)1組のキーワードとして、テスト・ケース必須リソースを指定するのに用いるハードウェア・リソースを指定する手段と、
(c)後続のシミュレーションの実行に関連するテスト・ケースまたは1組のテスト・ケースごとに前記1組のキーワードをパースする手段と、
(d)前記パースされた1組のキーワードと前記共通必須要素を組み合わせて、BOMモデル・ビルド・ファイルを生成する手段と、
(e)前記BOMビルド・ファイルを使用してスタブ・ファイルを生成する手段とを備え、
前記スタブ・ファイルは、設計の離散的な機能を検証するためのシミュレーション・モデルのコンパイルを指示するものであって、前記シミュレーション・モデル内に実モデル表現および空モデル表現をインストールするようにモデル・ビルド・プロセスに命令し、
前記実モデル表現は、シミュレーション中に正確に振る舞い、設計全体ではなく、検証すべき機能を表す前記テスト・ケースの仕様について合成することができ、
前記空モデル表現は、前記設計のシミュレーションも検証もされない残りの部分を表し、かつ前記空モデル表現のすべての出力を不活動状態にアサートすることにより、前記空モデル表現が前記シミュレーション・モデル内で用いられないことを保証するためのタイ・オフを含む、システム。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/275093 | 2005-12-09 | ||
US11/275,093 US7711534B2 (en) | 2005-12-09 | 2005-12-09 | Method and system of design verification |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007164780A JP2007164780A (ja) | 2007-06-28 |
JP5004566B2 true JP5004566B2 (ja) | 2012-08-22 |
Family
ID=36075160
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006317794A Expired - Fee Related JP5004566B2 (ja) | 2005-12-09 | 2006-11-24 | 設計を検証するシステム |
Country Status (3)
Country | Link |
---|---|
US (1) | US7711534B2 (ja) |
JP (1) | JP5004566B2 (ja) |
CN (1) | CN101008963B (ja) |
Families Citing this family (9)
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US8219947B2 (en) * | 2008-09-15 | 2012-07-10 | Synopsys, Inc. | Method and apparatus for merging EDA coverage logs of coverage data |
KR20100084036A (ko) * | 2009-01-15 | 2010-07-23 | 삼성전자주식회사 | 소프트웨어의 에러 검출 장치 및 방법 |
US20130096901A1 (en) * | 2011-10-12 | 2013-04-18 | International Business Machines Corporation | Verifying Simulation Design Modifications |
EP2720149A3 (en) * | 2012-09-07 | 2018-01-24 | Samsung Electronics Co., Ltd | Apparatus and method for generating assertion based on user program code, and apparatus and method for verifying processor using assertion |
KR102166663B1 (ko) * | 2014-02-14 | 2020-10-19 | 삼성전자주식회사 | 시스템 온 칩의 테스트 시스템 및 그것의 테스트 방법 |
US10042747B2 (en) | 2014-11-12 | 2018-08-07 | International Business Machines Corporation | System and method for determining requirements for testing software |
CN104615810A (zh) * | 2015-01-20 | 2015-05-13 | 北京航空航天大学 | 一种基于函数型数据分析的仿真模型验证方法 |
CN112731117A (zh) * | 2021-01-11 | 2021-04-30 | Oppo广东移动通信有限公司 | 芯片的自动验证方法和系统,及存储介质 |
CN116467211B (zh) * | 2023-04-26 | 2023-09-26 | 北京计算机技术及应用研究所 | 一种基于数字化仿真环境的系统级测试验证方法 |
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-
2005
- 2005-12-09 US US11/275,093 patent/US7711534B2/en not_active Expired - Fee Related
-
2006
- 2006-11-15 CN CN2006101465942A patent/CN101008963B/zh not_active Expired - Fee Related
- 2006-11-24 JP JP2006317794A patent/JP5004566B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
CN101008963A (zh) | 2007-08-01 |
US7711534B2 (en) | 2010-05-04 |
CN101008963B (zh) | 2012-06-27 |
US20060064296A1 (en) | 2006-03-23 |
JP2007164780A (ja) | 2007-06-28 |
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