JP4990419B1 - Substrate reference hole processing method - Google Patents

Substrate reference hole processing method Download PDF

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JP4990419B1
JP4990419B1 JP2012030133A JP2012030133A JP4990419B1 JP 4990419 B1 JP4990419 B1 JP 4990419B1 JP 2012030133 A JP2012030133 A JP 2012030133A JP 2012030133 A JP2012030133 A JP 2012030133A JP 4990419 B1 JP4990419 B1 JP 4990419B1
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substrate
layer
filler
conductor
hole
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JP2013168459A (en
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主 松澤
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Eastern KK
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  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

The present invention provides a method for forming a fixation hole on the substrate of the package by inserting a pin between a substrate fixation hole and a wiring pattern formed on the substrate surface so as to acquire a highly precise fixation hole for the substrate. Wherein an incident laser beam L is introduced to scan a filler layer 5 which is exposed to a first port pattern 8, from a first conductor pattern 6a side along the edge 8a of the first port pattern 8 so as to eliminate the filler layer 5 and form a bottomed ditch 11 with a second conductor layer 7 as its bottom. Afterwards the dummy part of the substrate 12 the region where the filler layer 5 being encircled by the bottomed ditch 11 and the region where the second conductor layer 7 being laminated are eliminated by squeezing operation thereby forming the sophisticated substrate fixation hole 10.

Description

本発明は、例えばプリント配線基板に設けられ部品実装時や加工時に基板を位置決めするための基板基準孔の加工方法に関する。   The present invention relates to a method for processing a substrate reference hole provided on a printed wiring board, for example, for positioning the substrate during component mounting or processing.

近年、半導体パッケージ用のプリント配線板には、一般に非スルーホールといわれる孔壁面にめっきを施していない導通用ではない貫通孔が設けられる。この貫通孔は、プリント配線板の製造工程において基板を切断したりザグリ加工したりする場合に基板の位置を決めるための位置決めピンの挿入孔であり、各種加工の基準として用いられる。また、基板に電子部品を実装する場合の、基板位置をセットする位置決めピンの挿入孔として用いられる。   In recent years, a printed wiring board for a semiconductor package is provided with a through-hole that is not electrically conductive and is not plated on a hole wall surface that is generally referred to as a non-through hole. This through hole is an insertion hole for a positioning pin for determining the position of the substrate when the substrate is cut or counterbored in the manufacturing process of the printed wiring board, and is used as a reference for various processing. Moreover, when mounting an electronic component on a board | substrate, it is used as an insertion hole of the positioning pin which sets a board | substrate position.

従来、基準となる非スルーホールの加工はNC制御されたメカニカルドリルで行われることが一般的であるが、非スルーホールと配線パターンのズレは50μm以上ある。基板の外形あるいはザグリ加工と配線パターンのズレを更に小さくできれば、配線パターンと加工部の距離を小さくすることができ、基板の外形にパターンを近づけたり製品サイズを小さくしたりすることができる。また、電子部品の実装工程においても、基板をセットした時のパターン位置が安定するために、実装機の画像認識が安定しアライメントがしやすくなる。そのため、加工の基準となる基板基準孔と配線パターン間のズレを小さくすることが要求されている。   Conventionally, processing of a non-through hole serving as a reference is generally performed by an NC-controlled mechanical drill, but there is a deviation of 50 μm or more between the non-through hole and the wiring pattern. If the deviation between the outer shape of the substrate or the counterbore processing and the wiring pattern can be further reduced, the distance between the wiring pattern and the processed portion can be reduced, and the pattern can be brought closer to the outer shape of the substrate and the product size can be reduced. Also, in the electronic component mounting process, the pattern position when the substrate is set is stable, so that the image recognition of the mounting machine is stable and alignment is easy. Therefore, it is required to reduce the deviation between the substrate reference hole serving as a processing reference and the wiring pattern.

一例として、配線基板にレーザー加工で貫通孔を開ける方法としては、配線パターンによる開口を設けたコンフォーマルマスクと該開口と重なる開口を設けたコンタクトマスクを重ね合わせてレーザー光を走査して孔開けする方法が提案されている(特許文献1)。   As an example, a method for forming a through hole in a wiring board by laser processing is to form a hole by scanning a laser beam with a conformal mask provided with an opening by a wiring pattern and a contact mask provided with an opening overlapping the opening. A method to do this has been proposed (Patent Document 1).

特開2001−127397号公報JP 2001-127397 A

パッケージ用のプリント基板は、部品実装時の反りや歪み或いは寸法変化を可能な限り小さくするため、剛性を高める傾向にある。このため、基板材料にフィラーと言われる無機物の微粒子を高濃度に混ぜ込んだり膨張係数が小さな結晶性の高いガラス繊維を使用したりする。その結果、ピン挿入孔を基板にレーザーを照射して加工する場合、ガラスクロスと樹脂の加工性の違いによりレーザー照射部、特に孔壁面は樹脂がえぐられた状態になるため非常に荒れた状態になり孔の寸法がばらついてしまう。また、プレス金型によりパンチング加工をする場合は、パンチが欠けたり磨耗したりしやすいという問題がある。   A printed circuit board for a package tends to increase rigidity in order to minimize warping, distortion, or dimensional change during component mounting. For this reason, inorganic fine particles called fillers are mixed in the substrate material at a high concentration, or glass fibers with high crystallinity having a small expansion coefficient are used. As a result, when processing the pin insertion hole by irradiating the substrate with a laser, the laser irradiation part, especially the hole wall surface, is in a very rough state due to the difference in processability between the glass cloth and the resin. And the hole dimensions will vary. Further, when punching is performed using a press die, there is a problem that the punch is easily chipped or worn.

また、パッケージ用基板に電子部品を実装する際に基板を金型等に位置決めピンで固定するが、基板の伸縮に対応するためにピンの挿入孔を長孔にすることがある。基板への長孔の加工もメカニカルドリルで行われている。その場合、ドリルの加工位置をずらして穴明けをするが、すでにあけた孔の近傍に孔あけをするためドリルの位置がぶれて精度の良い加工ができない。金型でパンチング加工をする方法もあるが高価な金型を作成する必要がある。位置精度の高い長孔を低コストで作成することが要求されている。   Further, when mounting electronic components on a package substrate, the substrate is fixed to a mold or the like with a positioning pin, but the pin insertion hole may be a long hole in order to cope with expansion and contraction of the substrate. Machining of long holes in the substrate is also performed with a mechanical drill. In that case, drilling is performed by shifting the drilling position, but since the drilling is performed in the vicinity of the hole that has already been drilled, the position of the drill is fluctuated and high-precision machining cannot be performed. Although there is a method of punching with a mold, it is necessary to create an expensive mold. It is required to produce a long hole with high positional accuracy at a low cost.

本発明の目的は、上記従来技術の課題を解決し、パッケージ用基板に要求される剛性を維持しながらレーザー光による穴開け加工性が向上し、基板の位置決めをする基板基準孔と基板表面の配線パターン間の位置精度が高い基板基準孔の加工方法を提供することにある。   The object of the present invention is to solve the above-mentioned problems of the prior art, improve the drilling workability by laser light while maintaining the rigidity required for the package substrate, and improve the substrate reference hole for positioning the substrate and the substrate surface. An object of the present invention is to provide a method for processing a substrate reference hole with high positional accuracy between wiring patterns.

上記目的を達成するため、本発明に係る基板基準孔の加工方法は以下の構成を備えることを特徴とする。
即ち、絶縁樹脂基材の両面に導電層を有する基板に貫通孔を穿孔する孔開け工程と、前記貫通孔を埋める充填剤を充填して当該貫通孔を閉塞する工程と、前記充填剤を研磨して前記基板両面に形成された導電層と面一に平坦化する工程と、前記基板両面に無電解金属めっき及び電界金属めっきを連続して行い前記充填剤を覆う第1,第2導体層を形成する工程と、前記充填剤層に積層する前記第1導体層をエッチングにより除去することで第1導体パターンの形成と同時に第1開口パターンを形成して下地の前記充填剤層を露出させる工程と、前記第2導体層をエッチングにより除去することで下地の前記充填剤層を露出させた第2開口パターンを形成して前記第1開口パターンと対向する第2導体パターンを形成する工程と、前記第1導体層側から当該第1導体層をマスクとして前記第1開口パターンより露出する前記充填剤層にレーザー光を当該第1開口パターンのエッジ部に沿って走査させて照射することにより除去し、前記第2導体層を底部とする有底溝を形成する工程と、前記有底溝で囲まれた少なくとも前記充填剤層及び前記第2導体層が積層された基板不要部分を押圧して除去し基板基準孔を形成する工程と、を含み、前記基板基準孔の寸法と位置は前記充填剤層を除去した前記有底溝の前記第1開口パターンが形成された前記第1導体層の孔の寸法と位置で決まることを特徴とする。
In order to achieve the above object, a substrate reference hole processing method according to the present invention comprises the following arrangement.
That is, a step of drilling a through hole in a substrate having a conductive layer on both surfaces of an insulating resin base material, a step of filling a filler filling the through hole and closing the through hole, and polishing the filler Flattening with the conductive layers formed on both sides of the substrate, and the first and second conductor layers covering the filler by successively performing electroless metal plating and electric field metal plating on both sides of the substrate. And forming the first opening pattern simultaneously with the formation of the first conductor pattern to expose the underlying filler layer by removing the first conductor layer laminated on the filler layer by etching. Forming a second opening pattern exposing the underlying filler layer by removing the second conductor layer by etching, and forming a second conductor pattern facing the first opening pattern; The first conductor Using the first conductor layer as a mask from the side, the filler layer exposed from the first opening pattern is removed by scanning and irradiating the filler light along the edge portion of the first opening pattern. A step of forming a bottomed groove having the conductor layer as a bottom, and a substrate reference hole by pressing and removing at least the unnecessary portion of the substrate on which the filler layer and the second conductor layer are laminated surrounded by the bottomed groove; The size and position of the substrate reference hole is the size and position of the hole in the first conductor layer in which the first opening pattern of the bottomed groove from which the filler layer has been removed is formed. It is determined by.

上記構成によれば、貫通孔に充填された充填剤層に積層する第1導体層を第1導体パターンの形成と同時に除去することで所望する形状の基板基準孔を加工するための第1開口パターンを形成するので、配線パターンとの位置精度が非常に高い(±15μm以下)基板基準孔(非スルーホール)の加工をすることができる。特に、基板基準孔の位置は、充填剤層を除去した有底溝の第1開口パターンが形成された第1導体層の寸法と位置で決まるので、基板基準孔と第1導体パターンとの位置精度を高くすることができる。
また、第1導体層側から当該第1導体層をマスクとして第1開口パターンより露出する充填剤層にレーザー光を第1開口パターンのエッジ部に沿って走査させて照射することにより除去するだけで有底溝を形成し、該有底溝で囲まれた少なくとも充填剤層及び第2導体層が積層された基板不要部分を押圧して除去して基板に所望の形状の孔を形成することができるので、レーザー光のスポット径よりも大きな丸孔、長孔等を効率良く形成することができる。
また、第1開口パターンが形成された第1導体層をマスクとしてレーザー光を照射して有底溝を形成し、該有底溝で囲まれた基板不要部分を押圧して除去し基板基準孔を形成することで、加工形状が設計値とほとんど同じ孔開け加工を、金型を使わずに簡単に行うことができる。また、レーザー加工しやすい充填剤層を形成することで基板基準孔の孔壁面が荒れたりすることがなく、配線パターンの形成と共に位置精度及び仕上がりの良い基板基準孔を形成することができる。
また、第2導体パターンを有底溝の底部とすることにより、レーザー加工を行っても有底溝で囲まれた充填剤層が基板から脱落しないので、脱落した充填剤層がゴミとなって次にレーザー加工する基板の加工位置へのセットに悪影響を及ぼすことがない。
According to the above configuration, the first opening for processing the substrate reference hole having a desired shape by removing the first conductor layer laminated on the filler layer filled in the through hole simultaneously with the formation of the first conductor pattern. Since the pattern is formed, it is possible to process the substrate reference hole (non-through hole) with very high positional accuracy with respect to the wiring pattern (± 15 μm or less). In particular, the position of the substrate reference hole is determined by the size and position of the first conductor layer in which the first opening pattern of the bottomed groove from which the filler layer has been removed is formed. The accuracy can be increased.
Further, the filler layer exposed from the first opening pattern with the first conductor layer as a mask from the first conductor layer side is simply removed by irradiating the laser beam along the edge portion of the first opening pattern. Forming a bottomed groove, and pressing and removing at least the unnecessary portion of the substrate on which the filler layer and the second conductor layer are laminated surrounded by the bottomed groove to form a hole of a desired shape in the substrate. Therefore, it is possible to efficiently form a round hole, a long hole or the like larger than the spot diameter of the laser beam.
Further, a bottomed groove is formed by irradiating a laser beam using the first conductor layer having the first opening pattern as a mask, and a substrate unnecessary portion surrounded by the bottomed groove is pressed and removed to remove the substrate reference hole. By forming the hole, it is possible to easily perform a drilling process in which the machining shape is almost the same as the design value without using a mold. In addition, by forming a filler layer that can be easily laser processed, the hole wall surface of the substrate reference hole is not roughened, and the substrate reference hole with good positional accuracy and finish can be formed along with the formation of the wiring pattern.
In addition, by using the second conductor pattern as the bottom of the bottomed groove, the filler layer surrounded by the bottomed groove does not fall off the substrate even when laser processing is performed, so the dropped filler layer becomes dust. Next, there is no adverse effect on the setting of the substrate to be processed to the laser processing position.

前記充填剤はフィラー入りの熱硬化型穴埋めインキがスクリーン印刷により塗布され、加熱硬化して充填剤層を形成するのが好ましい。熱硬化型穴埋めインクは、穴埋めするスルーホール内の銅めっきの接続信頼性を高めるため、シリカなどの無機物の粒子(フィラー)を含有させることで熱膨張係数をガラスクロスを使用した絶縁樹脂基材に近づけている。インクに充填されるフィラーは一般にはシリカなどの無機物であるため、フィラーと樹脂とのレーザーによる加工性は大きく異なる。しかしながら、フィラーの大きさが小さく(例えば50μm以下)レーザー加工性に差がある領域が非常に小さいために、ガラスクロスと樹脂からなる基板に比べてレーザー加工後の加工面の荒れが小さく良好な加工性を示す。   The filler is preferably formed by applying a thermosetting-type hole-filling ink containing a filler by screen printing, followed by heat curing to form a filler layer. Thermosetting hole-filling ink is an insulating resin base material that uses glass cloth with a coefficient of thermal expansion by containing inorganic particles (fillers) such as silica in order to increase the connection reliability of copper plating in the through-hole to be filled. It is close to. Since the filler filled in the ink is generally an inorganic substance such as silica, the processability of the filler and the resin by the laser is greatly different. However, since the size of the filler is small (for example, 50 μm or less) and the region where the laser workability is different is very small, the roughness of the processed surface after laser processing is small and good compared to the substrate made of glass cloth and resin. Shows workability.

前記基板基準孔は、前記第1開口パターンが形成された前記第1導体層の孔寸法が最小寸法となるように形成されるのが好ましい。
即ち、レーザーの加工条件を調整して第1開口パターンが形成された第1導体層の孔の寸法を基板基準孔の最小寸法として形成することにより、基板基準孔にピンを挿入する際に最小寸法である第1開口パターンの開口部が基準となるので、基板を固定するピンに対して基板に形成された第1導体パターンを高精度に位置決めすることができる。
The substrate reference hole is preferably formed such that a hole size of the first conductor layer in which the first opening pattern is formed is a minimum size.
That is, by adjusting the laser processing conditions to form the hole size of the first conductor layer in which the first opening pattern is formed as the minimum size of the substrate reference hole, it is minimized when inserting a pin into the substrate reference hole. Since the opening portion of the first opening pattern that is the dimension serves as a reference, the first conductor pattern formed on the substrate can be positioned with high accuracy with respect to the pin that fixes the substrate.

前記有底溝の底部を形成する前記第2導体パターンの外形寸法は対向する前記第1開口パターンの外形寸法より大きく形成されることが望ましい。
これにより、第2導体パターンと充填剤層又は充填剤層及び絶縁樹脂基材の接着を剥がすだけで有底溝に囲まれた基板不要部分を容易に除去することができる。ここで外形寸法は、導体パターン若しくは開口パターンの外側の輪郭線で囲まれた形状の対比する部分の長さをいう。
It is preferable that an outer dimension of the second conductor pattern forming the bottom portion of the bottomed groove is larger than an outer dimension of the first opening pattern facing each other.
Thereby, the board | substrate unnecessary part enclosed by the bottomed groove | channel can be easily removed only by peeling off adhesion | attachment of a 2nd conductor pattern, a filler layer or a filler layer, and an insulating resin base material. Here, the external dimension refers to the length of the contrasted portion of the shape surrounded by the outer contour line of the conductor pattern or the opening pattern.

前記基板不要部分は、押圧部材による押圧、エアー圧の印加、或いは振動を含むいずれかの外力を加えることにより前記第2導体パターンと前記充填剤層又は前記充填剤層及び絶縁樹脂基材とが剥離して除去されるようにしてもよい。これにより、基板不要部分を容易に除去することできる。   The unnecessary portion of the substrate has the second conductor pattern and the filler layer or the filler layer and the insulating resin base material by applying any external force including pressing by a pressing member, application of air pressure, or vibration. It may be peeled off and removed. Thereby, a board | substrate unnecessary part can be removed easily.

前記第1開口パターン及び第2導体パターンを形成した後、少なくとも前記第1導体層にニッケルめっき層及び金めっき層を各々積層形成してから前記第1開口パターンを形成された前記第1導体層をマスクとして前記充填剤層にレーザー光を照射するようにしてもよい。
これにより、第1開口パターンの周囲の導体層の反射率が向上するため、レーザー光照射部の第1導体層およびその下の充填剤層のダメージが小さくなり第1導体層を薄くすることができる。
After forming the first opening pattern and the second conductor pattern, the first conductor layer in which the first opening pattern is formed after forming a nickel plating layer and a gold plating layer on at least the first conductor layer. The filler layer may be irradiated with a laser beam using as a mask.
Thereby, since the reflectance of the conductor layer around the first opening pattern is improved, damage to the first conductor layer of the laser light irradiation portion and the filler layer therebelow is reduced, and the first conductor layer can be thinned. it can.

上述した本発明によれば、パッケージ用基板に要求される剛性を維持しながらレーザー光による穴開け加工性が向上し、基板の位置決めをする基板基準穴と基板表面の配線パターン間の位置精度が高い基板基準孔の加工方法を提供することができる。   According to the present invention described above, the drilling workability by the laser beam is improved while maintaining the rigidity required for the package substrate, and the positional accuracy between the substrate reference hole for positioning the substrate and the wiring pattern on the substrate surface is improved. A high substrate reference hole processing method can be provided.

パッケージ用基板に基板基準孔の加工工程を示す断面図である。It is sectional drawing which shows the process process of a board | substrate reference | standard hole in the board | substrate for packages. 基準孔の断面写真図である。It is a cross-sectional photograph figure of a reference hole.

以下、本発明の実施形態について図面を参照しながら具体的に説明する。
図1(A)〜(J)を参照してパッケージ用基板に基準孔を形成する加工方法についてその製造工程と共に説明する。
Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings.
A processing method for forming a reference hole in a package substrate will be described with reference to FIGS.

図1(A)に示すように絶縁樹脂基材1(例えばエポキシ樹脂基板)の両面に導電層(銅箔層)2を有する両面銅張基板3を準備する。この両面銅張基板3に、図1(B)に示すようにドリル等の機械加工により貫通孔4を穿孔する(孔開け工程)。   As shown in FIG. 1A, a double-sided copper-clad substrate 3 having conductive layers (copper foil layers) 2 on both sides of an insulating resin base material 1 (for example, an epoxy resin substrate) is prepared. As shown in FIG. 1B, through holes 4 are drilled in this double-sided copper-clad substrate 3 by machining such as a drill (drilling step).

次に、図1(C)に示すように貫通孔4を埋める充填剤を充填して当該貫通孔4を閉塞する。充填剤5はフィラー入りの熱硬化型穴埋めインキがスクリーン印刷により塗布され、加熱硬化して充填剤層5を形成する。次いで図1(D)に示すように、充填剤層5を研磨して基板両面に形成された導電層2と面一に平坦化する。充填剤としては貫通孔充填性と研磨性に優れた粒径の細かい(例えば50μm以下)フィラーが高充填された穴埋めインキが好適に用いられる。   Next, as shown in FIG. 1C, a filler that fills the through hole 4 is filled to close the through hole 4. The filler 5 is formed by applying a thermosetting type hole-filling ink containing a filler by screen printing and curing by heating to form the filler layer 5. Next, as shown in FIG. 1D, the filler layer 5 is polished and flattened with the conductive layer 2 formed on both surfaces of the substrate. As the filler, a hole-filling ink that is highly filled with a filler having a fine particle diameter (for example, 50 μm or less) excellent in through-hole filling and polishing properties is preferably used.

次に図1(E)に示すように、基板両面に無電解銅めっき及び電界銅めっきを連続して行い、充填剤層5及びこれに隣接する導電層2の両面を覆う第1,第2導体層6,7を各々形成する(ふためっき)。導体層2に厚付された第1,第2導体層6,7には以下に説明するように第1開口パターンと第2導体パターンが形成される。   Next, as shown in FIG. 1E, electroless copper plating and electrolytic copper plating are continuously performed on both surfaces of the substrate to cover both surfaces of the filler layer 5 and the conductive layer 2 adjacent thereto. Conductive layers 6 and 7 are respectively formed (lid plating). A first opening pattern and a second conductor pattern are formed on the first and second conductor layers 6 and 7 thickened on the conductor layer 2 as described below.

次に図1(F)において、第1,第2導体層6,7を形成した後、エッチングを行って、基板両面に配線パターンと第1開口パターン8及び第2導体パターン7bを同時に形成する。具体的には、第1,第2導体層6,7にエッチング用のマスク(ドライフィルム等)を積層してから配線パターンと第1開口パターン8(例えば円形)を同時に露光し、次に第2導体パターン7b(例えば円形)を露光した後現像によりエッチング用マスクのパターンを形成する。その後、エッチングを行って第1開口パターン8と第2導体パターン7b及び第1,2導体パターン6a,7aを形成する。即ち、貫通孔4に充填された充填剤層5に積層する第1導体層6を除去することで基準孔10を加工するための第1開口パターン8を形成して下地の充填剤層5を露出させ、第2導体層7を除去することでそれより大径の第2導体パターン7bを形成する。これにより、基板両面に配線パターンの形成と同時に第1開口パターン8および第2導体パターン7bを形成することができる。   Next, in FIG. 1F, after forming the first and second conductor layers 6 and 7, etching is performed to simultaneously form the wiring pattern, the first opening pattern 8 and the second conductor pattern 7b on both surfaces of the substrate. . Specifically, an etching mask (dry film or the like) is laminated on the first and second conductor layers 6 and 7, and then the wiring pattern and the first opening pattern 8 (for example, a circle) are simultaneously exposed, and then the first After the two-conductor pattern 7b (for example, a circle) is exposed, an etching mask pattern is formed by development. Thereafter, etching is performed to form the first opening pattern 8, the second conductor pattern 7b, and the first and second conductor patterns 6a and 7a. That is, by removing the first conductor layer 6 laminated on the filler layer 5 filled in the through hole 4, the first opening pattern 8 for processing the reference hole 10 is formed, and the underlying filler layer 5 is formed. The second conductor pattern 7b having a larger diameter is formed by exposing and removing the second conductor layer 7. Thereby, the first opening pattern 8 and the second conductor pattern 7b can be formed simultaneously with the formation of the wiring pattern on both surfaces of the substrate.

尚、第1,2導体パターン6a,7aを形成した後、更に第1導体層6にニッケルめっき層及び金めっき層を積層形成してもよい。これにより、第1開口パターン8の周囲の第1導体層6の反射率が向上するため後述する充填剤層5にレーザー光を照射して穴開け加工をするとき、レーザー照射部である第1導体層6およびその下の充填剤層5のダメージが小さくなり第1導体層6を薄く形成することができる。その結果、配線パターンを形成する銅の厚さが薄くなり、より細かい配線パターンのエッチングができるようになる。尚、ニッケルめっき層及び金めっき層は、少なくともレーザー加工を行う第1導体層6側に積層形成すればよいが、めっき加工上第2導体層7側にも積層形成されていてもよい。   In addition, after forming the first and second conductor patterns 6a and 7a, a nickel plating layer and a gold plating layer may be further laminated on the first conductor layer 6. Thereby, since the reflectance of the first conductor layer 6 around the first opening pattern 8 is improved, when the drilling process is performed by irradiating the filler layer 5 to be described later with a laser beam, it is the first laser irradiation portion. Damage to the conductor layer 6 and the filler layer 5 therebelow is reduced, and the first conductor layer 6 can be formed thin. As a result, the thickness of the copper forming the wiring pattern is reduced, and a finer wiring pattern can be etched. The nickel plating layer and the gold plating layer may be laminated at least on the first conductor layer 6 side where laser processing is performed, but may also be laminated on the second conductor layer 7 side for plating.

次に、図1(G)において、第1導体層6側から第1開口パターン8より露出する充填剤層5に当該第1導体層6をマスクとして当該第1開口パターン8のエッジ部8a(図1(F)参照)に沿ってレーザー光Lを走査させて照射することにより除去し、第2導体パターン7b(導電層2を含む)を底部とする有底溝11を形成する。レーザー加工には、エキシマレーザー、YAGレーザー、炭酸ガスレーザー等が用いられる。   Next, in FIG. 1G, the edge portion 8a (first edge pattern 8a) of the first opening pattern 8 is formed on the filler layer 5 exposed from the first opening pattern 8 from the first conductor layer 6 side using the first conductor layer 6 as a mask. The bottomed groove 11 having the second conductor pattern 7b (including the conductive layer 2) as the bottom is formed by removing the laser beam L by scanning and irradiating it along the line (see FIG. 1F). For laser processing, an excimer laser, a YAG laser, a carbon dioxide gas laser, or the like is used.

次に、図1(H)において、レーザー加工後の基板断面を示す。有底溝11の底部である第2導体パターン7b側の外径は、第1開口パターン8の外形寸法(内径)より大きく第2導体パターン7bの外形寸法(直径)より小さく形成される。このように基板基準孔10の孔の寸法は、第1開口パターン8が形成された第1導体層6の孔の寸法(外形寸法)が最小径となる。その結果、基板基準孔10に位置決め用のピンを挿入する際に最小径である第1開口パターン8が形成された第1導体層6の開口部を基準として第1導体パターン6aとの高精度な位置決めを行うことができる。   Next, FIG. 1H shows a cross section of the substrate after laser processing. The outer diameter on the second conductor pattern 7b side, which is the bottom of the bottomed groove 11, is larger than the outer dimension (inner diameter) of the first opening pattern 8 and smaller than the outer dimension (diameter) of the second conductor pattern 7b. As described above, the size of the hole of the substrate reference hole 10 is the minimum diameter (outer dimension) of the hole of the first conductor layer 6 in which the first opening pattern 8 is formed. As a result, when the positioning pin is inserted into the substrate reference hole 10, the first conductor pattern 6 a and the first conductor pattern 6 a on the basis of the opening of the first conductor layer 6 in which the first opening pattern 8 having the minimum diameter is formed as a reference. Positioning can be performed.

次に、図1(I)に示すように、有底溝11で囲まれて積層された充填剤層5、第2導体層7が積層された基板不要部分(孔中央部)12を押圧して除去し基板基準孔10を形成する。基板不要部分12は、押圧部材15(押圧ピン)による押圧のほか、エアー圧の印加、或いは振動を含むいずれかの外力を加えることにより第2導体層7と充填剤層5とが剥離して除去される。このとき、図1(H)に示すように、第2導体パターン7bは充填剤層5とわずかな重なり領域で積層(接着)された状態にある。これにより、基板不要部分12を容易に除去することできる。尚、レーザーの加工条件や第2導体パターン7bの配置によって第2導体パターン7bが充填剤層5及び絶縁樹脂基材1と積層される場合がある。   Next, as shown in FIG. 1 (I), the substrate unnecessary portion (hole central portion) 12 where the filler layer 5 and the second conductor layer 7 which are surrounded by the bottomed groove 11 and laminated are pressed is pressed. Then, the substrate reference hole 10 is formed. The unnecessary portion 12 of the substrate peels off the second conductor layer 7 and the filler layer 5 by applying any external force including application of air pressure or vibration in addition to pressing by the pressing member 15 (pressing pin). Removed. At this time, as shown in FIG. 1H, the second conductor pattern 7b is in a state of being laminated (adhered) to the filler layer 5 in a slight overlapping region. Thereby, the board | substrate unnecessary part 12 can be removed easily. The second conductor pattern 7b may be laminated with the filler layer 5 and the insulating resin substrate 1 depending on the laser processing conditions and the arrangement of the second conductor pattern 7b.

以上の工程を経て、第1開口パターン8より露出する充填剤層5にレーザー光を照射して除去し、第2導体パターン7bを底部とする有底溝11を形成し、有底溝11で囲まれた充填剤層5、第2導体層7が積層された基板不要部分12を除去する。これにより、図1(J)に示すように基板基準孔10及び配線パターン13が共に形成されたパッケージ用基板14が製造される。   Through the above steps, the filler layer 5 exposed from the first opening pattern 8 is removed by irradiating a laser beam to form a bottomed groove 11 having the second conductor pattern 7b as a bottom portion. The unnecessary substrate portion 12 on which the filler layer 5 and the second conductor layer 7 are laminated is removed. As a result, as shown in FIG. 1J, a package substrate 14 in which the substrate reference hole 10 and the wiring pattern 13 are both formed is manufactured.

また、エッチングにより形成された導体パターンをマスクにして有底溝11を加工し、該有底溝11で囲まれて積層された充填剤層5及び第2導体層7が積層された基板不要部分12を押圧して除去することで基板基準孔10が形成されるので、丸孔のみならず長孔その他所望する形状の孔加工を、高価な金型を作成せずに簡単に行うことができる。   Further, the substrate-unnecessary portion in which the bottomed groove 11 is processed using the conductor pattern formed by etching as a mask, and the filler layer 5 and the second conductor layer 7 stacked by being surrounded by the bottomed groove 11 are stacked. Since the substrate reference hole 10 is formed by pressing and removing 12, not only a round hole but also a long hole or other desired shape can be easily processed without creating an expensive mold. .

図2(a)はパッケージ用基板14の基板基準孔10のレーザー光入射面側の平面写真図、図2(b)(c)は基板基準孔10を含む半断面写真図、図2(d)は基板基準孔10のレーザー光入射面側の平面写真図である。   2A is a plan photograph of the laser light incident surface side of the substrate reference hole 10 of the package substrate 14, FIGS. 2B and 2C are half-sectional photograph views including the substrate reference hole 10, and FIG. ) Is a plan view of the substrate reference hole 10 on the laser beam incident surface side.

図2(b)(C)に示すように、レーザー加工しやすい充填剤層5を形成することで基板基準孔10の孔壁面が荒れたりすることがなく、基準孔10と配線パターン14の位置精度が良く仕上がりの良い基準孔10を形成することができた。
尚、充填剤としては、熱硬化型穴埋めインキを用いたが、粒径の細かいフィラーが高充填された貫通孔充填性、研磨性及びレーザー加工性が良い絶縁樹脂材であれば、他の部材であってもよい。
As shown in FIGS. 2B and 2C, the hole wall surface of the substrate reference hole 10 is not roughened by forming the filler layer 5 that can be easily laser-processed, and the positions of the reference hole 10 and the wiring pattern 14 can be reduced. The reference hole 10 with good accuracy and good finish could be formed.
As the filler, thermosetting type hole filling ink was used, but other members can be used as long as the insulating resin material is highly filled with a fine particle size filler and has good through hole filling, polishing and laser processability. It may be.

1 絶縁樹脂基材 2 導電層(銅箔層) 3 両面銅張基板 4 貫通孔 5 充填剤 6 第1導体層 6a 第1導体パターン 7 第2導体層 7a,7b 第2導体パターン 8 第1開口パターン 8a エッジ部 9 第2開口パターン 10 基準孔 11 有底切断穴 12 基板不要部分 13 配線パターン 14 パッケージ用基板 15 押圧部材   DESCRIPTION OF SYMBOLS 1 Insulation resin base material 2 Conductive layer (copper foil layer) 3 Double-sided copper-clad board 4 Through-hole 5 Filler 6 1st conductor layer 6a 1st conductor pattern 7 2nd conductor layer 7a, 7b 2nd conductor pattern 8 1st opening Pattern 8a Edge portion 9 Second opening pattern 10 Reference hole 11 Bottomed cut hole 12 Substrate unnecessary portion 13 Wiring pattern 14 Package substrate 15 Press member

Claims (6)

絶縁樹脂基材の両面に導電層を有する基板に貫通孔を穿孔する孔開け工程と、
前記貫通孔を埋める充填剤を充填して当該貫通孔を閉塞する工程と、
前記充填剤を研磨して前記基板両面に形成された導電層と面一に平坦化する工程と、
前記基板両面に無電解金属めっき及び電界金属めっきを連続して行い前記充填剤を覆う第1,第2導体層を形成する工程と、
前記充填剤層に積層する前記第1導体層をエッチングにより除去することで第1導体パターンの形成と同時に第1開口パターンを形成して下地の前記充填剤層を露出させる工程と、
前記第2導体層をエッチングにより除去することで下地の前記充填剤層を露出させた第2開口パターンを形成して前記第1開口パターンと対向する第2導体パターンを形成する工程と、
前記第1導体層側から当該第1導体層をマスクとして前記第1開口パターンより露出する前記充填剤層にレーザー光を当該第1開口パターンのエッジ部に沿って走査させて照射することにより除去し、前記第2導体層を底部とする有底溝を形成する工程と、
前記有底溝で囲まれた少なくとも前記充填剤層及び前記第2導体層が積層された基板不要部分を押圧して除去し基板基準孔を形成する工程と、を含み、
前記基板基準孔の寸法と位置は前記充填剤層を除去した前記有底溝の前記第1開口パターンが形成された前記第1導体層の孔の寸法と位置で決まることを特徴とする基板基準孔の加工方法。
A drilling step of drilling through holes in a substrate having a conductive layer on both sides of an insulating resin base;
Filling the through hole with a filler and closing the through hole;
Polishing the filler to planarize the conductive layers formed on both sides of the substrate,
Continuously forming electroless metal plating and electric field metal plating on both sides of the substrate to form first and second conductor layers covering the filler;
Removing the first conductor layer laminated on the filler layer by etching to form a first opening pattern simultaneously with the formation of the first conductor pattern to expose the underlying filler layer;
Removing the second conductor layer by etching to form a second opening pattern that exposes the underlying filler layer and forming a second conductor pattern opposite to the first opening pattern;
Removing the filler layer exposed from the first opening pattern from the first conductor layer side by using the first conductor layer as a mask by scanning and irradiating the filler layer along the edge portion of the first opening pattern. And forming a bottomed groove having the second conductor layer as a bottom,
Forming a substrate reference hole by pressing and removing at least the unnecessary portion of the substrate on which the filler layer and the second conductor layer are stacked surrounded by the bottomed groove,
The size and position of the substrate reference hole is determined by the size and position of the hole of the first conductor layer in which the first opening pattern of the bottomed groove from which the filler layer is removed is formed. Hole processing method.
前記充填剤はフィラー入りの熱硬化型穴埋めインキがスクリーン印刷により塗布され、加熱硬化して充填剤層を形成する請求項1記載の基板基準孔の加工方法。   The substrate reference hole processing method according to claim 1, wherein the filler is filled with a thermosetting hole-filling ink containing a filler by screen printing and is cured by heating to form a filler layer. 前記基板基準孔は、前記第1開口パターンが形成された前記第1導体層の孔の寸法が最小寸法となるように形成される請求項1又は請求項2記載の基板基準孔の加工方法。   3. The substrate reference hole processing method according to claim 1, wherein the substrate reference hole is formed such that a hole of the first conductor layer in which the first opening pattern is formed has a minimum dimension. 前記有底溝の底部を形成する前記第2導体パターンの外形寸法は対向する前記第1開口パターンの外形寸法より大きく形成される請求項1乃至請求項3のいずれか1項記載の基板基準孔の加工方法。   4. The substrate reference hole according to claim 1, wherein an outer dimension of the second conductor pattern forming a bottom portion of the bottomed groove is formed larger than an outer dimension of the first opening pattern facing each other. 5. Processing method. 前記基板不要部分は、押圧部材による押圧、エアー圧の印加、或いは振動を含むいずれかの外力を加えることにより前記第2導体パターンと前記充填剤層又は前記充填材層及び絶縁樹脂基材とが剥離して除去される請求項1乃至請求項4のいずれか1項記載の基板基準孔の加工方法。   The unnecessary portion of the substrate includes the second conductor pattern and the filler layer or the filler layer and the insulating resin base material by applying any external force including pressing by a pressing member, application of air pressure, or vibration. The substrate reference hole processing method according to any one of claims 1 to 4, wherein the substrate reference hole is removed by peeling. 前記第1開口パターンおよび第2導体パターンを形成した後、少なくとも前記第1導体層にニッケルめっき層及び金めっき層を各々積層形成してから前記第1開口パターンを通じて前記充填剤層にレーザー光を照射する請求項1乃至請求項5のいずれか1項記載の基板基準孔の加工方法。   After forming the first opening pattern and the second conductor pattern, a nickel plating layer and a gold plating layer are laminated on at least the first conductor layer, and then laser light is applied to the filler layer through the first opening pattern. The method for processing a substrate reference hole according to any one of claims 1 to 5, wherein irradiation is performed.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08111309A (en) * 1994-10-11 1996-04-30 Sumitomo Special Metals Co Ltd Production of r-fe-b based sintered magnet
JP2001135941A (en) * 1999-08-26 2001-05-18 Matsushita Electric Works Ltd Method for manufacturing printed wiring board
JP2003060356A (en) * 2001-08-09 2003-02-28 Ngk Spark Plug Co Ltd Manufacturing method of multilayer printed wiring board
JP2006024699A (en) * 2004-07-07 2006-01-26 Cmk Corp Method of manufacturing multilayer printed wiring board

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1318274A (en) * 1998-09-17 2001-10-17 伊比登株式会社 Multilayer build-up wiring board
TWI417018B (en) * 2010-07-29 2013-11-21 Unimicron Technology Corp Circuit board and manufacturing method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08111309A (en) * 1994-10-11 1996-04-30 Sumitomo Special Metals Co Ltd Production of r-fe-b based sintered magnet
JP2001135941A (en) * 1999-08-26 2001-05-18 Matsushita Electric Works Ltd Method for manufacturing printed wiring board
JP2003060356A (en) * 2001-08-09 2003-02-28 Ngk Spark Plug Co Ltd Manufacturing method of multilayer printed wiring board
JP2006024699A (en) * 2004-07-07 2006-01-26 Cmk Corp Method of manufacturing multilayer printed wiring board

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