KR101811941B1 - Embedded printed circuit board manufacturing method - Google Patents

Embedded printed circuit board manufacturing method Download PDF

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Publication number
KR101811941B1
KR101811941B1 KR1020160010106A KR20160010106A KR101811941B1 KR 101811941 B1 KR101811941 B1 KR 101811941B1 KR 1020160010106 A KR1020160010106 A KR 1020160010106A KR 20160010106 A KR20160010106 A KR 20160010106A KR 101811941 B1 KR101811941 B1 KR 101811941B1
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KR
South Korea
Prior art keywords
chip
bump
inner layer
mounting portion
substrate
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Application number
KR1020160010106A
Other languages
Korean (ko)
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KR20170090007A (en
Inventor
조하나
장헌우
전현찬
Original Assignee
주식회사 코리아써키트
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Priority to KR1020160010106A priority Critical patent/KR101811941B1/en
Publication of KR20170090007A publication Critical patent/KR20170090007A/en
Application granted granted Critical
Publication of KR101811941B1 publication Critical patent/KR101811941B1/en

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1461—Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
    • H05K2203/1469—Circuit made after mounting or encapsulation of the components

Abstract

The method includes the steps of: a) providing an inner layer substrate; b) forming an innerlayer circuit pattern and a chip mounting portion on the innerlayer substrate; c) mounting a chip on the chip mounting portion of the innerlayer substrate; d) A step of forming an insulating layer on the inner layer board on which the chip is mounted, e) forming a via hole so as to expose the bumps of the chip mounted on the inner layer board, f) Thereby minimizing the effect of resin flow due to the bump of the chip being fixed through the inner layer substrate and minimizing the influence of the resin flow due to the bump hole penetrating the bump and the conductive coating formed in the bump hole It is easy to align during the via hole process, and the through interconnection accuracy between the bump of the chip and the outer layer circuit pattern is increased, so that the cost reduction and the stable yield can be secured, The conductive coating of the bump hole, which is not electrically connected to the inner layer circuit pattern, minimizes the defect rate because there is no tolerance between the bump and the via due to the drilling process out of the designated position, and the manufacturing process is simple The present invention also provides a method of manufacturing a chip-embedded circuit board which can reduce manufacturing cost and productivity by making a manufacturing process simple due to a batch hot pressing process.

Description

[0001] Embedded printed circuit board manufacturing method [0002]

The present invention relates to a method of manufacturing a chip-embedded circuit board, and more particularly, to a method of manufacturing a chip-embedded circuit board by minimizing the influence of resin flow due to fixation of chip bumps through an inner- The via interconnection accuracy between the bump of the chip and the outer layer circuit pattern is increased by the formed conductive film and the chips fixed by face down can be stacked in a lump, To a method of manufacturing a chip-embedded circuit board capable of reducing a cost and securing a stable yield by simplifying a manufacturing process because there is no cavity process for incorporating a chip.

With the development of the electronic industry, there is a growing demand for high-performance and miniaturization of electronic components, along with the demand for thinner printed circuit boards on which electronic devices (chips) are mounted.

Accordingly, a new type of electronic device mounting method different from the existing SMT (Surface Mount Technology) for mounting an electronic device on the surface of a printed circuit board is emerging.

In other words, for printed circuit boards with electronic elements (active and passive elements) that seek to increase the densification and reliability of components by embedding passive components such as active components or capacitors, such as semiconductor chips, Research is underway.

As a background art, there is a method of inserting a part of an electronic device into one surface of a first insulating layer and a process of pressing a remaining part of the electronic device on one surface of a second insulating layer, as in Patent No. 10-0867954 And a step of laminating and pressing a second insulating layer on the first insulating layer.

Hereinafter, the operation of the prior art will be described with reference to FIG.

First, a circuit board on which the copper foil layers are formed on both the upper and lower sides with respect to the base layer is prepared, and the copper foil layer of the chip mounting portion is removed while the inner layer circuit pattern is formed of the copper foil layer of the circuit board.

And forming a cavity for receiving the chip by removing the base layer of the chip mounting portion. When a cavity is formed in the base layer, a bonding film is laminated on the lower side of the base layer, .

Subsequently, the upper insulating layer is laminated on the upper surface of the circuit board in which the chip is embedded by hot pressing (primary hot pressing process), and then the bonding film fixing the chip is peeled off and removed. When the bonding film is removed , A lower insulating layer is laminated on the lower surface of the circuit board by a hot press (secondary hot pressing process), drilling is performed on the copper foil layer and the insulating layer where the bumps of the chip are located, so as to expose the bumps .

Then, the hole is filled with copper and electrically connected to the bump, and then the copper foil layer is etched according to the designated circuit pattern to form an outer layer circuit.

In the above-described conventional technique, two hot presses are separately laminated to laminate the upper insulating layer and the lower insulating layer. The resin flow generated by the continuous hot press process and the peeling of the bonding film for fixing the chips there arises tolerance such as chip mounting tolerance due to distortion of the chip due to the influence of resin flow and positional movement, tolerance of laser drilling using a circuit guide formed on the outer layer substrate, and so on, And there is a problem that the manufacturing cost for correcting the problem increases.

The present invention minimizes the effect of resin flow due to the bump of the chip being fixed through the inner layer substrate and minimizes the influence of the resin flow due to the bump hole passing through the bump and the conductive coating formed on the bump hole, It is easy to align and the via interconnection accuracy between the bump of the built-in chip and the outer layer circuit pattern is increased, the cost can be reduced and a stable yield can be ensured, and the bump which is not electrically connected to the inner layer circuit pattern The tolerance between the bump and the via does not occur due to the drilling process deviating from the designated position by the conductive film of the hole and the defect rate is minimized and the manufacturing process is simplified because there is no cavity processing step for embedding the chip, Chip circuit that can simplify the manufacturing process and reduce the cost and productivity. And a method for manufacturing a substrate.

A method of manufacturing a chip-embedded circuit substrate according to the present invention includes the steps of: a) providing an inner layer substrate; b) forming an inner layer circuit pattern and a chip mounting portion on the innerlayer substrate; and c) D) laminating an insulating layer on both the lower and both sides of the inner layer board on which the chip is mounted; e) removing the bumps of the chip mounted on the inner layer board, Forming a via hole at a position corresponding to the position of the bump hole in the lower insulating layer in the opposed direction, and f) forming an outer layer circuit pattern and a via on the surface of the insulating layer, wherein the inner layer In the step of forming the inner layer circuit pattern and the chip mounting portion on the substrate, the chip mounting portion forms a bump hole through which the bumps of the chip pass through the inner layer substrate.

delete

Then, copper plating is performed around the bump hole according to the present invention to form a conductive coating film on the bump hole.

In the step of mounting the chip on the chip mounting portion of the inner layer substrate according to the step c) of the present invention, the bonding ink is pre-printed on the chip mounting portion, and then the chip is mounted on the bonding ink printed on the chip mounting portion .

Here, it is preferable that the bonding ink according to the present invention is printed only between the bump holes formed in the chip mounting portion.

In addition, in the step of laminating the insulating layer on the inner layer board on which the chip of step d) according to the present invention is mounted, it is preferable that a copper foil is bonded to the surface of the insulating layer.

The chip-embedded circuit board manufacturing method according to the embodiment of the present invention has the following effects.

First, since the bump of the chip is fixed to the inner layer substrate by the bonding ink while penetrating the inner layer substrate, the effect of the resin flow on the chip embedded in the circuit board is minimized.

Second, when the chip is mounted using a guide formed on the inner layer circuit, the bump of the chip is disposed at the center of the bump hole in which the conductive film is formed. Therefore, via hole processing is performed based on the bump hole and the conductive film center at the time of via hole processing, It is possible to minimize the defective rate by reducing the tolerance due to the drilling operation out of the designated position by the easy operation.

Third, the bump-to-vias can be conducted by the conductive film of the bump hole that is not electrically connected to the inner-layer circuit pattern even though the alignment between the bump and the vias of the chip is somewhat matched. (Via interconnection accuracy), the cost reduction and the stable yield can be secured.

Fourth, when laser drilling is performed with a conventional bump, the range of the laser target is small and the laser processing is not easy. However, according to the embodiment of the present invention, the conductive film of the bump hole increases the laser target range, It has an effect.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view showing a conventional chip embedded circuit board manufacturing process.
2 is a schematic view illustrating a process of manufacturing a chip-embedded circuit board according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Prior to this, terms and words used in the present specification and claims should not be construed as limited to ordinary or dictionary terms, and the inventor should appropriately interpret the concepts of the terms appropriately The present invention should be construed in accordance with the meaning and concept consistent with the technical idea of the present invention.

Therefore, the embodiments described in the present specification and the configurations shown in the drawings are merely the most preferred embodiments of the present invention, and not all of the technical ideas of the present invention are described. Therefore, at the time of the present application, It should be understood that variations can be made.

The present invention minimizes the effect of resin flow when bumps of a chip are fixed through an inner layer substrate and reduces the influence of bump holes through which the bumps penetrate and the bumps of chips embedded by the conductive coating formed on the bump holes The present invention relates to a chip-embedded circuit board manufacturing method capable of reducing cost and securing a stable yield by increasing via interconnection accuracy between outer layer circuit patterns, and will be described with reference to the drawings.

First, in step a), an innerlayer substrate 10 is provided.

The inner layer substrate 10 is a CCL in which a copper foil 12 is bonded to the upper and lower surfaces of the base plate 11 with respect to a base plate 11 disposed at the center of the plate.

At this time, the base plate 11 may be made of polyimide or coverlay having a thickness of micrometers, made of a resin having good insulating property, and having excellent impact resistance, dimensional stability, and abrasion resistance.

The copper foil layers 12 formed on the upper and lower sides of the base plate 11 are formed by laminating thin copper foils on the upper and lower sides of the base plate 11 to form the upper copper foil layer 12 and the lower copper foil layer 12).

Next, in step b), the inner layer circuit pattern 13 and the chip mounting portion 14 are formed on the inner layer substrate 10 provided by the step a).

The inner layer circuit pattern 13 and the chip mounting portion 14 use the copper foil 12 bonded to the surface of the base plate 11. The inner layer circuit pattern 13 and the chip mounting portion 14 will be described with reference to FIG. The bump hole 15 is formed through the portion corresponding to the bump position of the chip to be mounted later.

It is preferable that the bump hole 15 is formed by drilling the inner layer substrate 10 with a laser or a drill bit. In the process of forming the inner layer circuit pattern 13, (16) is formed.

It is preferable that the conductive coating 16 is formed as a separate member that is not electrically connected to the inner layer circuit pattern 13. [

The formation process of the inner layer circuit pattern 13 and the conductive coating 16 according to an embodiment of the present invention will be described below.

First, a dry film is laminated on the surface of the copper foil 12, a mask for forming an image pattern corresponding to the inner layer circuit pattern 13 and the chip mounting portion 14 is laminated, ) Or light energy is supplied to perform an exposure operation in which a dry film as a monomer is reacted with a polymer to reproduce a necessary pattern image.

Then, in the exposure operation, the portion which has not changed into the polymer is removed by using sodium carbonate to form an image pattern of a pattern corresponding to the inner-layer circuit pattern 13 and the chip-mounting portion 14.

When the dry film having the image pattern corresponding to the inner layer circuit pattern 13 and the conductive film 16 is completed through the developing operation and copper plating and etching are performed through the dry film, A pattern 13 and a conductive coating 16 are formed.

Then, the dry film may be peeled off from the copper foil 12 and then soft-etched, if necessary, so that insulation between the conductive patterns is achieved.

Thus, the inner layer circuit pattern 13 and the chip mounting portion 14 are formed on the inner layer substrate 10 by the above-described process.

Next, in step c), the chip 20 is mounted on the chip mounting portion 14 of the inner layer substrate 10 by the step b).

The bonding ink 21 having the specified adhesive strength is printed in the chip mounting portion 14 so that the chip mounted on the mounting portion is not separated from the chip mounting portion 14, bumps 22 are inserted into the bump holes 15 so that the chip 20 is mounted on the chip mounting portion 14 so that one surface of the chip 20 is completely bonded to the bonding ink 21 .

Here, the bumps 22 of the chip 20 may be in close proximity to or in contact with the conductive coating 16 of the bump hole 15.

As described above, since the bumps 22 of the chip 20 are fixed by the bonding ink 21 while penetrating the inner layer substrate 10, the influence of the resin flow on the embedded chip 20 is minimized , The bump 22 of the chip 20 is disposed at the center of the bump hole 15 where the conductive coating 16 is formed.

Next, in step d), the insulating layer 30 is laminated on the inner layer substrate 10 on which the chip 20 is mounted by the above step c).

At this time, the insulating layer 30 according to an embodiment of the present invention is bonded to both the upper and lower sides of the inner layer substrate 10 by a single process with an ajinomoto build-up film (ABF) or a prepreg .

Therefore, the insulating layer 30 is bonded to both the upper and lower surfaces of the inner layer substrate 10, so that the inner layer circuit pattern 13 of the inner layer substrate 10 and the chip (not shown) mounted on the chip mounting portion 14 20).

A copper foil 31 may be provided on the surface of the insulating layer 30. The copper foil 31 may be formed on the outer surface of the insulating layer 30 so as to form an outer layer circuit pattern, It is preferable to form the surface of the insulating layer 30.

The insulating layer 30 bonded to the inner layer substrate 10 may be bonded by a press method when laminated, wherein the pressing is preferably performed by a hot press applying heat and pressure at a preset temperature, It is preferable that the insulating layer 30 located on both the upper and lower sides of the inner layer substrate 10 are bonded at the same time by a single hot press process so as to minimize the influence of the resin flow.

The bump hole 15 through which the bumps 22 of the chip 20 pass is formed in the inner layer substrate 10 and then the bonding ink 21 is printed on the chip mounting portion 14, The influence of the resin flow on the chip 20 can be minimized by fixing the chip 20 on the printed bonding ink 21 and then laminating the insulating layer 30 with a single hot press fixation , A stable chip packaging yield can be obtained.

Next, in step e), a via hole 32 is formed by exposing the bumps 22 of the chip 20 mounted on the inner layer substrate 10 by the step d).

As the insulating layer 30 is laminated on the inner layer substrate 10, the chip 20 embedded in the inner layer substrate 10 is removed by the insulating layer 40 stacked on the upper surface of the inner layer substrate 10 The via hole 32 is formed by removing the insulation layer 30 to a specified thickness so that the bumps 22 of the chip 30 are partially exposed to the outside.

The via hole 32 is formed in the insulating layer 30 in the opposite direction of the chip mounting portion 14 so that the bump 22 of the chip 20 mounted on the chip mounting portion 14 can be exposed. Only the portion located in the hole is removed by laser drilling or plasma etching to form the via hole 32.

Here, the removal depth of the insulating layer 30 is preferably removed so that the ends of the bumps 22 of the chip 20 are completely exposed.

Therefore, the bump hole 15 and the conductive coating 16, which are alignment marks formed on the inner layer circuit 10, are processed on the basis of the bump hole 15 and the conductive coating 16 at the time of processing the via hole 32. Thus, It is easy to align the bumps 22 of the semiconductor chip 20 and the via holes 32 to improve the bump and via interconnection accuracy of the chip.

Next, in step f), when the via hole 32 is formed in the insulating layer 30 by the step d), the outer layer circuit pattern 40 and the via 41 are formed on the surface of the insulating layer 30 .

At this time, the outer layer circuit pattern 40 and the vias 41 use the copper foil 31 bonded to the surface of the insulating layer 30. Electroless copper plating can be performed for copper plating of the via hole 32 A thin electroless copper plating layer is formed on the via hole 32 formed in the insulating layer 30 so that the bump 22 of the chip 20 located in the via hole 32 and the The conductivity between the vias 41 to be formed is improved.

After laminating a dry film on the surface of the copper foil 31, a mask for forming an image pattern corresponding to the outer layer circuit pattern 40 and the vias 41 is laminated, and ultraviolet rays (UV) or Light energy is supplied to perform an exposure operation in which a dry film as a monomer is reacted with a polymer to reproduce a necessary pattern image.

Then, in the exposure operation, a portion which is not changed into a polymer is peeled off using sodium carbonate to form an image pattern of a pattern corresponding to the outer layer circuit pattern 40 and the via 41.

When the portion excluding the image pattern portion of the dry film is removed through the developing operation, electroplating is performed on the exposed portion of the copper foil 31 except the portion where the image pattern is formed.

Then, the dry film is peeled off from the copper foil 31, and then the copper foil 31, which is not subjected to electrolytic copper plating, is removed by soft etching so that insulation between the conductive patterns is achieved.

The outer layer circuit pattern 40 is formed on the insulating layer 30 by the above process and the via hole 32 is formed not only in the electrolytic copper plating but also in the via hole 32 by the conductive The paste may also be filled.

The outer layer circuit pattern 40 and the via 41 are partially covered with the solder resist 42 to partially protect the outer layer circuit pattern 40 and the via 41.

Therefore, by the above-described series of processes, the influence of the resin flow due to fixing of the bumps of the chip through the inner layer substrate is minimized, and the bump hole through which the bumps penetrate and the conductive film formed in the bump hole, (Via interconnection accuracy) between the bump of the integrated chip and the outer layer circuit pattern is increased, cost reduction and stable yield can be secured, and the bump hole electrical connection with the inner layer circuit pattern It is possible to provide a method of manufacturing a chip-embedded circuit board in which a tolerance between a bump and a via does not occur due to drilling processing out of a designated position by a coating, thereby minimizing a defect rate and simplifying a manufacturing process, .

While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

10: Inner layer substrate 11: Base plate
12, 31: copper foil 13: inner layer circuit pattern
14: chip mounting part 15: bump hole
16: conductive film 20: chip
21: bonding ink 22: bump
30: insulating layer 32: via hole
40: outer layer circuit pattern 41: via
42: Solder resist

Claims (6)

a) providing an innerlayer substrate;
b) forming an inner layer circuit pattern and a chip mounting portion on the innerlayer substrate;
c) mounting a chip on a chip mounting portion of the innerlayer substrate;
d) depositing an insulating layer on both sides of the lower layer on the inner layer board on which the chip is mounted;
e) forming a via hole at a position corresponding to the bump hole position in the lower insulating layer in the opposed direction of the chip mounting portion of the innerlayer substrate so that the bumps of the chip mounted on the innerlayer substrate are exposed;
f) forming an outer layer circuit pattern and a via on the surface of the insulating layer,
In the step of forming the inner layer circuit pattern and the chip mounting portion on the inner layer substrate which is the step b)
Wherein the chip mounting portion forms a bump hole through which the bumps of the chip pass through the inner layer substrate.
delete The method according to claim 1,
And a copper plating is performed around the bump hole to form a conductive coating film on the bump hole.
The method according to claim 1,
In the step of mounting the chip on the chip mounting portion of the inner layer substrate which is the step c)
Wherein the bonding ink is linearly printed on the chip mounting portion, and then the chip is mounted on the bonding ink printed on the chip mounting portion.
The method of claim 4,
Wherein the bonding ink is printed only between the bump holes formed in the chip mounting portion.
The method according to claim 1,
In the step (d) of stacking the insulating layer on the inner layer board on which the chip is mounted,
A method of manufacturing a chip embedded circuit board having a copper foil bonded to a surface thereof.
KR1020160010106A 2016-01-27 2016-01-27 Embedded printed circuit board manufacturing method KR101811941B1 (en)

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Application Number Priority Date Filing Date Title
KR1020160010106A KR101811941B1 (en) 2016-01-27 2016-01-27 Embedded printed circuit board manufacturing method

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KR101811941B1 true KR101811941B1 (en) 2017-12-26

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004335641A (en) * 2003-05-06 2004-11-25 Canon Inc Method of manufacturing substrate having built-in semiconductor element
JP2014192354A (en) * 2013-03-27 2014-10-06 Nippon Mektron Ltd Method for manufacturing component mounting printed-wiring board and component mounting printed-wiring board

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004335641A (en) * 2003-05-06 2004-11-25 Canon Inc Method of manufacturing substrate having built-in semiconductor element
JP2014192354A (en) * 2013-03-27 2014-10-06 Nippon Mektron Ltd Method for manufacturing component mounting printed-wiring board and component mounting printed-wiring board

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