JP4980655B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which defective products are extracted at an electrical test stage before shipment.

  In recent years, as semiconductor devices have higher functionality and higher integration, miniaturization in semiconductor manufacturing and an increase in the number of processes have progressed, and adhesion of foreign matters in the manufacturing process has further increased the potential for defects in semiconductor devices. On the other hand, the types of products using semiconductor devices and the number of semiconductor devices in each final product have increased, and improving the quality of semiconductor devices has become an important point.

  As shown in FIG. 6, in the conventional method for manufacturing a semiconductor device, a pre-process of a semiconductor device wafer is performed (step S1), and an electrical test of the wafer processed in the pre-process is performed (step S2). If the wafer electrical test determines that the product is good (YES in step S3), the process proceeds to the assembly process (step S4). If it is determined to be defective (NO in step S3), it is removed from the product.

  In addition, after the assembly process (step S4), an electrical test of the semiconductor device is performed (step S5). If the semiconductor device is determined to be non-defective by the electrical test of the semiconductor device (YES in step S6), it is shipped (step S7). If it is determined to be defective (NO in step S6), it is removed from the product.

As a technique for detecting and removing fine particles on a wafer without damaging the wafer, there is one described in Patent Document 1. In addition, there is a device described in Patent Document 2 as a small-sized stress application device that can be installed on a wafer stage in order to measure electrical characteristics related to stress on a semiconductor wafer with a probe.

  By the way, when an initial failure factor of a product returned from a client as a defective product is analyzed after the product is shipped, it has been found that there are many cases due to a metal foreign object placed across the metal wiring. That is, a product that has passed the electrical test (YES in step S3 and YES in step S6 in FIG. 6) as a non-defective product at the time of product shipment is subject to thermal and mechanical stress before mounting on the client. It can be considered that electrical contact by metal foreign objects between the metal wirings was promoted by adding them to the product.

  That is, simply placing a foreign object between metal wires does not lead to an electrical short between the metal wires. A non-defective product is determined in the electrical test of the wafer (YES in step S3 in FIG. 6), and a non-defective product is determined in the electrical test (step S5) of the semiconductor device after the assembly and encapsulation process (step S4 in FIG. 6) in which thermal stress due to resin is applied In spite of this, it is considered that one of the factors that cause an electrical short between the foreign material and the metal wiring is that the thermal stress until the subsequent mounting by the client is further added.

  Therefore, in the prior art, there is room for improvement in that there is a possibility that the quality of the semiconductor device is deteriorated by a product having such a potential defect.

According to the present invention, a multi-layer film is formed on a wafer, a pre-process for forming a circuit pattern, and the wafer processed in the pre-process is diced, divided into semiconductor chips, mounted on a lead frame, a wire A semiconductor device manufacturing method including a post-process for encapsulating resin after bonding;
A stress applying step of applying a predetermined thermal and mechanical stress to the wafer or the semiconductor device during the pre-process or after the post-process;
After the stress application step, an electrical test step of performing an electrical test of the wafer or the semiconductor device;
A method for manufacturing a semiconductor device is provided.

According to the present invention, by applying a predetermined thermal and mechanical stress to the wafer or the semiconductor device, the stress that causes the initial failure of the product that occurs in the potential defective product having the foreign matter between the metal wirings. Can be detected as a defective product by an electrical test of a wafer or a semiconductor device. Thereby, the detected potential defective product can be eliminated in advance, and the product quality can be improved.

  It should be noted that any combination of the above-described constituent elements and a conversion of the expression of the present invention between a method, an apparatus, a system, a recording medium, a computer program, etc. are also effective as an aspect of the present invention.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the semiconductor device which can extract the potential defective product in advance and can improve the reliability of a product is provided.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

(First embodiment)
FIG. 1 is a flowchart showing an example of a processing flow of a method for manufacturing a semiconductor device according to an embodiment of the present invention. In FIG. 1, the configuration of parts not related to the essence of the present invention is omitted.

In the semiconductor device manufacturing method according to the embodiment of the present invention, a multi-layer film is formed on a wafer, a pre-process (step S11) for forming a circuit pattern, a wafer processed in the pre-process is diced, and each semiconductor chip A semiconductor device manufacturing method including a post-process (step S19) that is mounted on a lead frame, wire-bonded, and encapsulated with resin, and the wafer or semiconductor device is heated during or after the pre-process. Stress application step (step S13) for applying a predetermined mechanical and mechanical stress, and an electrical test step (step S15) for conducting an electrical test of the wafer or semiconductor device after the stress application step.

Specifically, as shown in FIG. 1, a wafer pre-process of a semiconductor device is performed (step S11), and a process of applying thermal and mechanical stress to the wafer between the pre-process and the wafer electrical test process is performed. Implement (step S13). The predetermined thermal and mechanical stress can be, for example, the same level as the thermal and mechanical stress applied to the semiconductor chip when the resin is encapsulated in a later process. Alternatively, the predetermined thermal and mechanical stress can be approximately the same as the sum of stresses applied before the pre-process, the post-process, and the mounting of the semiconductor device. The stress application conditions will be described later.

After step S13, an electrical test is performed on the wafer to which stress is applied (step S15). When it is determined that the product is non-defective in the test of step S15 (YES in step S17), the process proceeds to the next assembly process (step S19). If it is determined to be defective (NO in step S17), it is removed from the product. The assembly process includes, for example, a resin sealing process.

  Then, an electrical test of the semiconductor device manufactured in the assembly process (step S19) is performed (step S21). When it is determined that the product is non-defective in the test of step S21 (YES in step S23), the product is shipped (step S25). When it is determined as defective in the test in step S21 (NO in step S23), it is removed from the product.

FIG. 2 is a flowchart showing a detailed flow of the stress application step of FIG.

In the present embodiment, the apparatus for performing the stress application step is a pressure cooker capable of setting a wafer placed in a carrier. Autoclave is approximately the same stress as the resin sealing step, for example, can be applied to 100 kg / cm ² or less degree of stress. Furthermore, the pressure cooker can replace a liquid at a high temperature, for example, about 150 ° C., or at a low temperature, for example, about −10 ° C. Alternatively, an apparatus capable of heating and cooling at high and low temperatures using an inert gas or the like instead of the liquid can be used. Alternatively, a HAST (High Accelerated Stress Test) apparatus used in a semiconductor device test can also be used.

First, the carrier containing the wafer is set in the pressure cooker (step S101). Then, the pressure lid is closed (step S103). Since the stress application step is repeated several times as necessary, a preset value n is set as the number of repeats. Further, the loop counter i is set to 1 and initialized (step S105).

  Then, a low-temperature liquid is introduced into the pressure cooker and left for a predetermined time (step S107). Here, for example, a low-temperature liquid at −10 ° C., for example, a fluorine-based inert liquid such as Florinart (trademark) is introduced into the pressure cooker and left for 10 minutes.

Thereafter, a set pressure, for example, a stress of about 100 kg / cm ² or less is applied by the pressure cooker (step S109). Thereafter, after removing the liquid introduced in step S107 from the pressure cooker, a high-temperature liquid is introduced into the pressure cooker and left for a predetermined time (step S111). Here, for example, a high-temperature liquid at 150 ° C., for example, a fluorine-based inert liquid such as Florinart (trademark) is introduced into the pressure cooker and left for 10 minutes.

Thereafter, a set pressure, for example, a stress of about 100 kg / cm ² or less is applied by the pressure cooker (step S113). Thereafter, the liquid introduced in step S113 is removed from the pressure cooker (step S115). Then, the loop counter i is incremented (step S117), and it is determined whether or not the loop counter i> the repeat count n (step S119). If the loop counter i is equal to or less than the repeat count n (NO in step S119), the process returns to step S107, and steps S107 to S115 are repeated. On the other hand, if the loop counter i exceeds the repeat count n (YES in step S119), the process is terminated.

The stress applying step is preferably performed in the previous step before forming a protective film on the uppermost layer of the wafer by applying polyimide or the like. That is, the pre-process of FIG. 1 includes a protective film forming process formed on the uppermost layer of the wafer, and the stress applying process can be performed before the protective film forming process of the pre-process. According to this, the stress application effect can be obtained more than the stress application step after the protective film is formed on the wafer.

FIG. 3 is a flowchart showing an example of a processing flow for determining an application condition in the stress application step of the method for manufacturing a semiconductor device of the present embodiment. FIG. 4 is a diagram illustrating an example of the stress application condition table 10 according to the present embodiment.

As shown in FIG. 4, the stress application condition table 10 of the present embodiment includes the number of repeats for repeating the processing loop of FIG. 2, the set temperature during low temperature processing, the standing time, the set stress, and the set temperature during high temperature processing. , The standing time and the set stress are stored. The operator performs each process according to the conditions stored in the stress application condition table 10.

As shown in FIG. 3, first, the stress application condition table 10 is initialized (step S201). For example, the number of repeats is 3, the set temperature during low temperature treatment is -10 ° C, the standing time is 10 minutes, the stress is 100 kg / cm ² , the set temperature during high temperature processing is 150 ° C, the standing time is 10 minutes, and the stress is 100 kg. / cm ² The initial value can be set for each product under conditions that simulate the stress applied during the resin encapsulation process that is actually performed in the assembly process, and conditions that simulate the stress applied during mounting by the client.

Then, the pre-process (step S11), the thermal and mechanical stress application process (step S13), and the wafer electrical test process (step S15) shown in FIG. 1 are performed. Then, the determination result of the electrical test of the wafer is recorded (step S203). Then, the determination result is analyzed (step S205). The analysis of the determination result includes, for example, statistically counting and analyzing the number of defective products detected by the test after the stress application process based on the determination result record.

Based on the analysis result, the conditions are optimized (step S207), the conditions are corrected to the optimized values, and the set values in the stress application condition table 10 are updated (step S209). By repeating this process, the conditions can be corrected, and for example, conditions such as the stress application condition table 10 shown in FIG. 4 can be obtained. Here, the number of repeats is 3, the set temperature during low temperature treatment is −5 ° C., the standing time is 10 minutes, the stress is 80 kg / cm ² , the set temperature during high temperature processing is 130 ° C., the standing time is 10 minutes, and the stress is 80 kg / cm ² .

Then, the process proceeds to step S17 in FIG. Note that steps S205 to S209 are not performed every time, but are preferably performed after the determination result is recorded and the history is accumulated in step S203. That is, it can be performed after the history has accumulated to such an extent that statistical aggregation and analysis can be performed. In this way, the optimum application condition can be determined, and the reliability of the product can be improved efficiently.

As described above, according to the method of manufacturing a semiconductor device of the embodiment of the present invention, a potential defective product having foreign matters between metal wirings by applying a predetermined thermal and mechanical stress to the wafer. The stress that causes the initial failure of the product that occurs in the process is added to the product in a simulated manner in advance, and can be detected as a defective product by the electrical test of the wafer. Thereby, the detected potential defective product can be eliminated in advance, and the product quality can be improved.

(Second embodiment)
FIG. 5 is a flowchart showing an example of a processing flow of a method for manufacturing a semiconductor device according to another embodiment of the present invention. The semiconductor device manufacturing method of this embodiment differs from the semiconductor device manufacturing method of the above-described embodiment of FIG. 1 in place of the thermal and mechanical stress application step (step S13) after the previous step (step S11). The difference is that the thermal and mechanical stress application step (step S20) is performed after the assembly step (step S19).

The manufacturing method of the semiconductor device according to the present embodiment includes a multi-layered film formation on a wafer, a pre-process (step S11) for forming a circuit pattern, and a wafer processed in the pre-process is diced and divided into semiconductor chips, A semiconductor device manufacturing method including a post-process (step S19) that is mounted on a lead frame, wire-bonded, and encapsulated with a resin, wherein the wafer and the semiconductor device are thermally and mechanically processed during or after the pre-process. A stress applying step (step S20) for applying a predetermined stress and an electrical test step (step S21) for performing an electrical test on the wafer or the semiconductor device after the stress applying step.

In the present embodiment, the predetermined stress applied in the stress application step (step S20) is, for example, the sum of stresses applied before the pre-process, the post-process, and the mounting of the semiconductor device, or the semiconductor device after the post-process. The thermal and mechanical stress applied to the semiconductor chip before mounting can be set. Moreover, in this embodiment, as an apparatus which implements a stress application process, it can be set as the pressure cooker which can set a semiconductor chip.

According to the method of manufacturing a semiconductor device of the embodiment of the present invention, a product that occurs in a potential defective product having foreign matters between metal wirings by applying a predetermined thermal and mechanical stress to the semiconductor device. The stress that causes the initial failure is added to the product in advance in a simulated manner, and can be detected as a defective product by an electrical test of the semiconductor device before shipment. Thereby, the detected potential defective product can be eliminated in advance, and the product quality can be improved.

(Third embodiment)
In another embodiment of the present invention, in addition to the thermal and mechanical stress application step (step S13) after the previous step (step S11) of the method of manufacturing the semiconductor device of the above embodiment of FIG. After (Step S19), a thermal and mechanical stress application step (Step S20) can also be performed. That is, the thermal and mechanical stress application steps (step S13 and step S20) can be performed after both the pre-process (step S11) and the assembly process (step S19), respectively.

The manufacturing method of the semiconductor device according to the present embodiment includes a multi-layered film formation on a wafer, a pre-process (step S11) for forming a circuit pattern, and a wafer processed in the pre-process is diced and divided into semiconductor chips, A semiconductor device manufacturing method including a post-process (step S19) that is mounted on a lead frame, wire-bonded, and encapsulated with a resin, wherein the wafer and the semiconductor device are thermally and mechanically processed during or after the pre-process. A stress applying process (step S13 and step S20) for applying a predetermined stress and an electrical test process (step S15 and step S21) for performing an electrical test of the wafer or the semiconductor device after the stress applying process.

In the present embodiment, the predetermined stress applied by the stress applying step (step S20), for example, thermal and mechanical stresses comparable applied to the semiconductor chip and before mounting the semiconductor device after the assembly process It can be.
Also in this embodiment, the same effect as the above-described embodiment can be obtained.

  As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable.

For example, in the example of FIG. 2, the same setting value is used in the iterative process, but the present invention is not limited to this. Application conditions includes a number of applications of stress in the stress applying step (step S13), and in accordance with application condition, the number of times of application, can be repeated application of a given stress. That is, the set value can be changed for each processing loop. For example, it is possible to set different values for the conditions that simulate the stress applied in the resin encapsulation process that is actually performed in the assembly process for each product, and the conditions that simulate the stress that is applied during mounting on the client. it can.

It is a flowchart which shows an example of the processing flow of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is a flowchart which shows the detailed flow of the stress application process of FIG. It is a flowchart which shows the processing flow of the stress application condition determination process in the manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is a figure which shows an example of the table which memorize | stores the stress application conditions determined by the stress application condition determination process of FIG. It is a flowchart which shows an example of the processing flow of the manufacturing method of the semiconductor device which concerns on other embodiment of this invention. It is a flowchart which shows the processing flow of the manufacturing method of the conventional semiconductor device.

Explanation of symbols

10 Stress application condition table

Claims (6)

A pre-process including a step of forming a multilayer film on a wafer and forming a circuit pattern, and a protective film forming step of forming a protective film on the uppermost layer of the wafer ;
The wafer processed in the previous process is diced, divided into semiconductor chips, mounted on a lead frame, wire bonding, and a post-process for encapsulating resin, and a method for manufacturing a semiconductor device,
A stress applying step of applying a predetermined thermal and mechanical stress to the wafer or the semiconductor device before the protective film forming step of the previous step;
After the stress application step, an electrical test step of performing an electrical test of the wafer or the semiconductor device;
A method of manufacturing a semiconductor device including: In the manufacturing method of the semiconductor device according to claim 1 ,
The predetermined thermal and mechanical stress is the thermal and mechanical stress applied to the semiconductor chip at the time of resin encapsulation in the post process or the semiconductor chip after the post process and before the semiconductor device is mounted. A method for manufacturing a semiconductor device, which is comparable to thermal and mechanical stresses applied to the semiconductor device. In the manufacturing method of the semiconductor device according to claim 2 ,
The method for manufacturing a semiconductor device, wherein the predetermined thermal and mechanical stresses are approximately equal to a sum of stresses applied before the pre-process, the post-process, and the mounting of the semiconductor device. In the manufacturing method of the semiconductor device according to claim 1 ,
A method of manufacturing a semiconductor device, wherein in the stress applying step, the wafer or the semiconductor device is housed in a pressure chamber capable of controlling temperature, and the predetermined thermal and mechanical stress is applied to the wafer or the semiconductor device. In the manufacturing method of the semiconductor device according to claim 1 ,
A method for manufacturing a semiconductor device, comprising: determining a stress application condition in the stress application step based on a determination result in the electrical test step. In the manufacturing method of the semiconductor device according to claim 5 ,
The application condition includes a number of applications of stress in the stress applying step, according to the applied conditions, the number of times of application, the production method of the predetermined semiconductor device repeating the application of stress.

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