JP2003218144A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable a semiconductor wafer to be reduced in warpage after a sealing resin layer is formed in a wafer-level package manufacturing method. <P>SOLUTION: Bonding pads 3, a final insulating layer 5, a re-wiring layer 7, and metal posts 9 are formed on a silicon wafer 1 on which a plurality of semiconductor elements are formed (A), and then a sealing resin 11 is formed (B). The silicon wafer 1 is much warped due to the shrinkage of the sealing resin 11 after the sealing resin 11 is formed. The sealing resin is removed from regions where cutting lines at which the silicon wafer 1 is cut into semiconductor chips in an after process are located to form notches 11a in the sealing resin 11 (C). The notches 11a are provided in the sealing resin 11, so that stress imposed on the silicon wafer 1 due to the shrinkage of the sealing resin can be relaxed, and the silicon wafer 1 is less warped. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including a step of resin sealing in a wafer state.

[0002]

2. Description of the Related Art In recent years, a wafer-level package has attracted attention as a package structure of a semiconductor device in which a sealing process can be performed in a wafer state without cutting the semiconductor chip into individual pieces from a semiconductor wafer on which a plurality of semiconductor chips are formed. Has been done. A wafer level package is disclosed in, for example, Japanese Patent Laid-Open No.
No. 000-260910.

FIG. 4 is a top view showing a semiconductor wafer on which a plurality of semiconductor chips are formed and before a sealing resin is formed. A plurality of semiconductor chips 17 before division are formed in a matrix on a silicon wafer 1 which is a semiconductor wafer. In the manufacturing process of the wafer level package, the semiconductor chip 1
Before separating 7 into individual pieces, resin sealing is performed in a wafer state.

FIG. 5 is a process sectional view showing a part of a manufacturing process of a wafer level package. FIG. 5 shows only one semiconductor chip. A conventional method of manufacturing a wafer level package will be described with reference to FIG. (A) A final insulating layer 5 is formed on a silicon wafer 1 on which a plurality of semiconductor elements are formed and on which a metal wiring layer including a bonding pad 3 is formed via an insulating film.

The final insulating layer 5 on the bonding pad 3 is removed to form a through hole on the bonding pad 3. A rewiring layer 7 made of Cu (copper) for electrically connecting the bonding pad 3 and an external connection terminal described later is formed on the final insulating layer 5 and in the through hole. A metal post 9 made of Cu is formed on the rewiring layer 7 in the region where the external connection terminal is arranged.

(B) The sealing resin 11 is formed on the final insulating layer 5, the redistribution layer 7 and the side surface of the metal post 9 by, for example, an injection molding method. The thickness of the sealing resin 11 is metal
The upper surface of the post 9 is exposed, for example, 50 to 1
It is about 00 μm. After arranging the solder balls 13 as external connection terminals on the exposed upper surfaces of the metal posts 9, heat treatment is performed to mechanically fix the upper surfaces of the metal posts 9 and the solder balls 13.

After that, before cutting the semiconductor chip from the silicon wafer 1, a final test of the semiconductor chip is performed in a wafer state. In the final test, electrical characteristics are measured for each semiconductor chip to determine whether or not the specifications are satisfied. Normally, the final test is performed using a wafer prober and a semiconductor tester.

FIG. 6 is a schematic diagram for explaining the final test of the semiconductor chip. The wafer prober 19 includes a stage 21 for vacuum-sucking and carrying the resin-sealed silicon wafer 1, and a probe card 23 having needle-shaped contacts 23 corresponding to the positions of the external connection terminals of the semiconductor chip. Is equipped with. The contact 23 is a semiconductor tester (not shown) via the wiring in the probe card 25.
Electrically connected to. Here is a silicon wafer 1
Illustration of the sealing resin formed above is omitted.

During the final test, the silicon wafer 1 is vacuum-sucked on the stage 21, and the external connection terminals (not shown) of the semiconductor chip to be tested are aligned with the contacts 23 of the probe card 25. The stage 21 is raised to bring the external connection terminal of the semiconductor chip to be tested into contact with the contact 23 of the probe card 25, and the electrical characteristics of the semiconductor chip are measured.

In the wafer level package manufacturing process,
Since the package processing steps can be collectively performed on a plurality of semiconductor chips formed in a matrix on a semiconductor wafer, there is an advantage that the package cost can be reduced. Furthermore, since the package size can be made the same as the chip size, the semiconductor device can be downsized, and the final test after packaging can be performed in the wafer state, so that the final test can be performed regardless of the type of semiconductor device as a product. There is also an advantage that the handling mechanism for this can be unified.

[0011]

In the process of manufacturing a wafer level package, a plurality of semiconductor elements (not shown) are formed on the surface of the silicon wafer 1 as shown in FIG. 7 (A).
In the state after the formation of the insulating film (not shown) thereon and before the formation of the sealing resin, the silicon wafer 1 is not largely warped. As the silicon wafer 1, for example, the diameter is 8 inches and the thickness is 500 μ.
In the case of using m, the warp amount of the silicon wafer 1 before forming the sealing resin is 0.5 mm (millimeter) or less.

However, in the silicon wafer 1 on which the sealing resin has been formed, as shown in FIG.
A large warp occurs due to the stress caused by the contraction of the. FIG. 8 is a graph showing the relationship between the warp amount (mm) of the silicon wafer 1 after forming the sealing resin 11 and the frequency (sheets). Here, for example, the silicon wafer 1 has a diameter of 8
Inch and thickness of 500 μm are used. Sealing resin 11
As a substrate having a thickness of 100 μm. As can be seen from FIG. 8, the silicon wafer 1 after the encapsulation resin 11 is formed has a warp of about 1.8 mm on average and 2 mm or more at the maximum.

If the thickness of the silicon wafer 1 is thin, problems such as cracking of the silicon wafer 1 occur during the manufacturing process. Therefore, the silicon wafer 1 having a thickness of 500 μm or more is generally used. However, even if the silicon wafer 1 is not broken during the manufacturing process of the wafer level package, as shown in FIG. 7B and FIG.
There is a problem that a large warp occurs in the silicon wafer 1 after forming the sealing resin 11.

When the warp of the silicon wafer 1 is large, in the final test described with reference to FIG. 6, when the silicon wafer 1 is vacuum-sucked to the stage 21 for transportation, a vacuum is generated due to the warp of the silicon wafer 1. Causes a problem that it cannot be vacuum-adsorbed. Further, when the external connection terminal formed on the silicon wafer 1 and the contact 23 of the probe card 25 are brought into contact with each other in a state where the silicon wafer 1 is not completely vacuum-adsorbed on the stage 21, the external connection terminal and the contact 23 are separated from each other. This also causes a problem that the contact pressure becomes non-uniform and accurate measurement cannot be performed.

Therefore, an object of the present invention is to reduce the warp of a semiconductor wafer after forming a sealing resin in a method of manufacturing a semiconductor device including a step of sealing a resin in a wafer state.

[0016]

The present invention is a method of manufacturing a semiconductor device including a step of resin-sealing in a wafer state, which includes the following steps (A) to (D). (A) A step of forming a sealing resin on one surface of a semiconductor wafer on which a plurality of semiconductor chips are formed, (B) a step of forming a cut in the sealing resin, (C) the above formed on the semiconductor wafer A step of testing a semiconductor chip, (D)
A step of cutting the semiconductor chip from the semiconductor wafer.

After forming the sealing resin on one surface of the semiconductor wafer (A), a notch is formed in the sealing resin (B). Thereby, the stress on the semiconductor wafer due to the shrinkage of the sealing resin can be relieved, and the warp of the semiconductor wafer can be reduced. By reducing the warp of the semiconductor wafer, it is possible to perform a good test in the step (C).

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION In the step (A), it is preferable to form the notch formed in the sealing resin on the cutting line in the step (D). As a result, without forming a notch in the sealing resin in the region of the semiconductor chip, and without providing a dedicated region for forming the notch,
Notches can be formed in the sealing resin.

In the step (A), it is preferable that the notches are formed in the sealing resin on all the cutting lines. As a result, it is possible to increase the area where the notch is formed in the encapsulating resin without forming the notch in the encapsulating resin in the area of the semiconductor chip and without providing a dedicated area for forming the notch. The stress on the semiconductor wafer due to the contraction of the stop resin can be further alleviated, and the warp of the semiconductor wafer can be further reduced.

In the step (A), it is preferable that the sealing resin in the region where the notch is formed is entirely removed in the thickness direction to form the notch. As a result, the stress on the semiconductor wafer due to the shrinkage of the sealing resin can be further alleviated, and the warp of the semiconductor wafer can be further reduced.

In the step (A), it is preferable to remove at least half of the sealing resin in the region where the notch is formed in the thickness direction to form the notch. By removing at least half of the sealing resin in the region where the notch is formed in the thickness direction, the stress on the semiconductor wafer due to the shrinkage of the sealing resin can be reduced to at least half, so that the warp of the semiconductor wafer can be sufficiently ensured. It can be reduced.

[0022]

EXAMPLE FIG. 1 is a process sectional view showing an example. (A) A final insulating layer on a silicon wafer 1 on which a plurality of semiconductor elements (not shown) are formed and on which a metal wiring layer including a bonding pad 3 is formed via an insulating film (not shown) 5 is formed. As the material of the final insulating layer 5, photosensitive polyimide having a film thickness of about 5 μm was used as in the general case. Here, as the silicon wafer 1, for example, a wafer having a diameter of 8 inches and a thickness of 500 μm was used.

The final insulating layer 5 on the bonding pad 3 is removed to form a through hole on the bonding pad 3. A rewiring layer 7 for electrically connecting the bonding pad 3 and an external connection terminal described later is formed on the final insulating layer 5 and in the through hole. Here, the rewiring layer 7
For this, Cu wiring having a film thickness of, for example, about 1 to 10 μm was used.

A metal post 9 made of, for example, Cu is formed on the rewiring layer 7 in the region where the external connection terminal is arranged. The thickness of the metal post 9 is, for example, 50 to 100 μm
Degree is general. Here, a metal post 9 having a thickness of 100 μm was formed. For the silicon wafer 1, FIG.
As described with reference to (A), warpage does not occur much. The warp amount of the silicon wafer 1 in this state is 0.5 mm or less.

(B) The sealing resin 11 is formed on the final insulating layer 5, the rewiring layer 7 and the side surface of the metal post 9 by, for example, an injection molding method. The thickness of the sealing resin 11 is metal
The upper surface of the post 9 is exposed, for example, 50 to 1
It is about 00 μm. Here, the sealing resin 11 having a thickness of 100 μm was formed. As a method for forming the sealing resin 11, for example, the thickness of the sealing resin 11 is controlled so that the upper surface of the metal post 9 is exposed, or after the sealing resin 11 is formed thicker than the metal post 9, There is a method of polishing the sealing resin 11 to expose the upper surface of the metal post 9.

After arranging the solder balls 13 as external connection terminals on the exposed upper surfaces of the metal posts 9, heat treatment is applied to the upper surfaces of the metal posts 9 and the solder balls 13.
Mechanically fix. As described with reference to FIGS. 7B and 8, the silicon wafer 1 on which the sealing resin 11 is formed has a warp of about 1.8 mm.

(C) With respect to the silicon wafer 1 after the encapsulation resin 11 is formed, the thickness of the encapsulation resin 11 in the region on the cutting line in the step of cutting a semiconductor chip from the silicon wafer 1 which is a post-process using, for example, a dicer. All are removed in the direction to form a cut 11a in the sealing resin 11. Here, the notch 11a is formed in the sealing resin 11 in all the regions on the cutting line, and only the sealing resin 11 is separated for each semiconductor chip.

FIG. 2 is a graph showing the relationship between the warp amount (mm) and the frequency (sheet) of the silicon wafer 1 after the notch 11a is formed in the sealing resin 11. As can be seen from FIG. 2, the silicon wafer 1 after the notch 11a is formed in the sealing resin 11 has an average of about 0.7 mm and a maximum of 0.9 m.
Only warpage of m has occurred. In this way, the sealing resin 1
By forming the notch 11a in the sealing resin 11
The stress on the silicon wafer 1 due to the shrinkage of the silicon wafer 1 can be relieved, and the warp of the silicon wafer 1 can be reduced.

Then, in the state of the silicon wafer 1, as shown in FIG.
The final test of the semiconductor chip is performed in the same manner as the final test described with reference to FIG. In the final test, since the warp amount of the silicon wafer 1 is reduced to about 0.7 mm, the silicon wafer 1 can be satisfactorily vacuum-sucked to the stage 21 for transportation, and the problem of transportation is solved. be able to. Further, the fluctuation of the contact pressure between the external connection terminal formed on the silicon wafer 1 and the contact 23 of the probe card 25 due to the problem of the adsorption of the silicon wafer 1 on the stage 21 is suppressed to suppress the external connection terminal and the contact 23. The contact pressure with can be made uniform, and accurate measurement can be performed. After the final exam,
The silicon wafer 1 is cut along the cutting lines to cut semiconductor chips.

In this embodiment, the notch 1 is formed in the sealing resin 11.
Although the sealing resin 11 is entirely removed in the thickness direction in the region where 1a is formed, the present invention is not limited to this, and a part of the sealing resin is removed in the thickness direction to form the sealing resin. A notch may be formed.

FIG. 3 is a sectional view showing a part of the process of another embodiment. Step (A) of the embodiment described with reference to FIG.
After forming the sealing resin 11 on the silicon wafer 1 in the same manner as in (B) and (B) (see FIG. 1B), as shown in FIG. It is removed to form the cut 11b. Here, for example, the sealing resin 1
1 has a thickness of 100 μm, and the depth of the cut 11b is 5
It is 0 μm.

By forming the cut 11b in the sealing resin 11, the stress on the silicon wafer 1 due to the contraction of the sealing resin 11 can be at least halved, so that the warp of the silicon wafer 1 can be sufficiently reduced. can do. After performing a final test of the semiconductor chip on the silicon wafer 1, the sealing resin 11 and the silicon wafer 1 remaining on the cutting line are cut along the cutting line to cut out the semiconductor chip.

When the notch is formed by partially removing the sealing resin in the region where the notch is formed as in this embodiment, at least half the encapsulating resin is removed in the thickness direction to form the notch. It is preferable. However, the present invention is not limited to this, and a warp of the semiconductor wafer may be reduced by forming a notch having a depth smaller than half the thickness of the sealing resin.

In the above-mentioned embodiment, the cuts 11a or 11b are formed in the sealing resin 11 in the regions on all the cutting lines, but the present invention is not limited to this, and some cutting lines are formed. Notches may be formed in the sealing resin in the region. Further, the region where the cut is formed in the sealing resin is not limited to the cutting line, and may be another region such as a region dedicated to forming the cut.

Although the embodiment of the present invention has been described above, the present invention is not limited to this, and various modifications can be made within the scope of the present invention described in the claims.

[0036]

According to the method of manufacturing a semiconductor device described in claim 1, in the method of manufacturing a semiconductor device including a step of resin-sealing in a wafer state, one surface of a semiconductor wafer having a plurality of semiconductor chips formed thereon. Step (A) of forming a sealing resin on the substrate, step (B) of forming a cut in the sealing resin, step (C) of testing a semiconductor chip formed on a semiconductor wafer, and step of cutting a semiconductor chip from the semiconductor wafer Since (D) is included, the stress on the semiconductor wafer due to the shrinkage of the sealing resin can be relaxed and the warp of the semiconductor wafer can be reduced. By reducing the warp of the semiconductor wafer, it is possible to perform a good test in the step (C).

In the method of manufacturing a semiconductor device according to the second aspect, in the step (A), the notch formed in the sealing resin is formed on the cutting line in the step (D). It is possible to form a notch in the sealing resin in the region of (1) without forming a notch in the sealing resin and without providing a dedicated region for forming the notch.

In the method of manufacturing a semiconductor device according to the third aspect, in the step (A), the notches are formed in the encapsulating resin on all the cut lines, so that the encapsulation in the region of the semiconductor chip is performed. It is possible to increase the area where the notch is formed in the sealing resin without forming the notch in the resin and without providing a dedicated area for forming the notch. The stress can be more relaxed and the warp of the semiconductor wafer can be further reduced.

In the method of manufacturing a semiconductor device according to the fourth aspect, in the step (A), the sealing resin in the region where the cut is formed is entirely removed in the thickness direction to form the cut. The stress on the semiconductor wafer due to the shrinkage of the sealing resin can be further alleviated, and the warp of the semiconductor wafer can be further reduced.

In the method for manufacturing a semiconductor device according to the fifth aspect, in step (A), at least half of the sealing resin in the region where the cut is formed is removed in the thickness direction to form the cut. The stress on the semiconductor wafer due to the shrinkage of the sealing resin can be reduced to at least half, and the warp of the semiconductor wafer can be sufficiently reduced.

[Brief description of drawings]

FIG. 1 is a process sectional view showing an example.

FIG. 2 is a graph showing a relationship between a warp amount (mm) of a semiconductor wafer after forming a notch in a sealing resin and a frequency (sheet).

FIG. 3 is a cross-sectional view showing a part of the process of another embodiment.

FIG. 4 is a top view showing a semiconductor wafer on which a plurality of semiconductor chips are formed.

FIG. 5 is a process sectional view showing a part of the manufacturing process of the wafer level package.

FIG. 6 is a schematic diagram for explaining a final test of a semiconductor chip.

7A and 7B are side views showing a warp degree of a semiconductor wafer in a manufacturing process of a wafer level package, in which (A) a state before forming a sealing resin and (B) a state after forming the sealing resin. Show.

FIG. 8 is a graph showing a relationship between a warp amount (mm) of a semiconductor wafer after forming a sealing resin and a frequency (sheet).

[Explanation of symbols]

1 Silicon wafer 3 Bonding pad 5 Final insulation layer 7 Rewiring layer 9 Metal Post 11 Sealing resin 11a, 11b notch 13 Solder balls

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 23/12 H01L 21/78 L

Claims (5)

[Claims] 1. A method of manufacturing a semiconductor device, including a step of resin-sealing in a wafer state, including the following steps (A) to (D). (A) a step of forming a sealing resin on one surface of a semiconductor wafer on which a plurality of semiconductor chips are formed, (B) a step of forming a notch in the sealing resin, (C) the step formed on the semiconductor wafer A step of testing a semiconductor chip, (D)
A step of cutting the semiconductor chip from the semiconductor wafer. 2. The manufacturing method according to claim 1, wherein in the step (A), the notch formed in the sealing resin is formed on a cutting line in the step (D). 3. The manufacturing method according to claim 2, wherein in the step (A), the cuts are formed on all the cutting lines in the sealing resin. 4. The manufacturing method according to claim 1, wherein in the step (A), the notch is formed by completely removing the sealing resin in a region where the notch is formed, in the thickness direction. Method. 5. The process according to claim 1, wherein in the step (A), at least half of the sealing resin in the region where the cut is formed is removed in the thickness direction to form the cut. Production method.