JPH04175671A - Semiconductor evaluation method - Google Patents

Abstract

PURPOSE:To enable evaluation based on the expectation of thermal stress, etc. from a printed board being mounted by exerting a semiconductor package with thermal stress and mechanical stress simultaneously, and determining the quantity of the mechanical stress. CONSTITUTION:Both of the right and left sides of a semiconductor package 1 are held by a jig 5 while the semiconductor package 1 is immersed in molten solder 2. Thermal stress caused by the molten solder 2 is thus applied to the semiconductor package 1. Under these conditions a jig 6 used for applying mechanical stress and formed integrally with the jig 5 is moved inward and outward as indicated by the arrows whereby the semiconductor package 1 is exerted with mechanical stress. As to the mechanical stress the amount of bending of the semiconductor package 1 can be determined by means of a scale 7 which fluctuates with movement of the jig 6 used for applying mechanical stress.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a semiconductor evaluation method capable of quantitatively evaluating mechanical stress by adding mechanical stress to a semiconductor package at the same time as thermal stress during surface mounting.

BACKGROUND OF THE INVENTION A conventional semiconductor evaluation method will be explained using a solder dipping method as an example with reference to FIG.

Fig. 2 is an example of a mounting evaluation method for a semiconductor package using conventional solder dipping.
2 is molten solder, 3 is a bottle set, and 4 is a solder bath.

This involves sandwiching the semiconductor package 1 between bin sets 3 and
This is a mounting evaluation method in which the semiconductor package 1 is immersed in molten solder 2 and thermal stress is applied.

Problems to be Solved by the Invention However, in this method, it is possible to apply thermal stress to the semiconductor package 1, but at the same time, mechanical stress (from warping of the printed circuit board (not shown) due to heat) to the semiconductor package 1 can be applied. mechanical stress, etc.) cannot be applied.

An object of the present invention is to provide a semiconductor evaluation method that solves the above-mentioned drawbacks.

Means for Solving the Problems In order to achieve the above object, the present invention applies thermal stress and mechanical stress to a semiconductor package at the same time in a semiconductor device evaluation test, and quantitatively evaluates this mechanical stress. be.

By doing this, it is possible to evaluate mechanical stress, which assumes stress from the printed circuit board when a semiconductor device is mounted on the printed circuit board, at the same time as thermal stress evaluation.

Embodiment Next, an embodiment of the present invention will be explained with reference to FIG. 1st
In the figure, the right and left sides of the semiconductor package 1 are sandwiched between the jig 5, and in this state, the semiconductor package 1 is applied to the molten solder 2.
Soak. In this way, thermal stress due to the molten solder 2 is applied to the semiconductor package 1. In this state, a mechanical stress applying jig 6 formed integrally with the jig 5 is moved inward and outward as shown by arrows in FIG. 1 to apply mechanical stress to the semiconductor package 1. This mechanical stress can be used to quantify the amount of bending of the semiconductor package 1 using a scale 7 that is passively applied according to the movement of a jig 6 for applying mechanical stress.

Effects of the Invention As described above, according to the present invention, thermal stress and mechanical stress can be applied to a semiconductor package at the same time, and this mechanical stress can be quantitatively evaluated. It is possible to perform evaluations assuming stress etc. from the substrate.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing a semiconductor evaluation method according to an embodiment of the present invention, and FIG. 2 is a sectional view showing a conventional semiconductor evaluation method. 1...Semiconductor package, 2...Melted solder, 3...Bin set, 4...Solder bath, 5...Package up and down Jig for pinching, 6... Jig for applying mechanical stress, 7
・・・・・・Scale for quantifying mechanical stress.

Claims (1)

[Claims] A semiconductor evaluation method characterized by applying mechanical stress to a semiconductor package while simultaneously applying thermal stress to the semiconductor package, and quantifying the mechanical stress.