JP4977324B2 - Bus system, bus connection device, and reset method - Google Patents

Description

  The present invention relates to a bus system and a bus connection device, and more particularly, a bus system in which an initiator that issues a reset and a bus connection device are connected via a bus, and a bus that can be used in such a bus system. Related to connected devices. The present invention also relates to a reset method in a bus connection device.

  There is a bus system in which a plurality of devices and devices are connected and used via a bus line. Examples of the bus system include a SCSI bus and a PCI bus. In such a bus system, if a data transfer is not completed due to some problem during data transfer and the bus hangs or if a data error such as a parity error occurs, the initiator (controller) Is asserted to issue a bus reset and attempt to recover the target device. However, in this case, by issuing a bus reset, all devices connected to the same bus, including devices that have not failed, are reset, so that each device can be restarted and used normally. There is a problem that it takes a long time to obtain a state. Further, all the commands waiting for execution are canceled by the bus reset, and it is necessary to interrupt and restart the processing, which has a problem that the performance of the recovery processing is greatly affected.

  As a technique capable of selectively resetting only one of a plurality of devices connected to the same bus, there is a technique described in Patent Document 1. FIG. 4 shows a configuration of a reset ID identification circuit included in the SCSI device described in Patent Document 1. The selector 201 in the SCSI device inputs the eight signal lines DT0 to DT07 constituting the data line of the SCSI bus, selects one of DT0 to DT7 according to the device ID of the own device, and selects this. Output to the AND circuit 202. The AND circuit 202 calculates the logical product of the reset signal line and the output of the selector 201 and outputs this to the SPC (SCSI protocol controller) 203 as a reset signal.

For example, when the device having the device ID of 3 is selectively reset, the initiator side activates the reset signal line to H level and activates only the data line DT3 among the data lines DT0 to DT7 to H level. To do. In this case, in the device whose device ID is 3, the selector 201 outputs the signal of the data line DT3 to the AND circuit 202, and the AND circuit 202 inputs the activated reset signal to the SPC 203. As a result, the device whose device ID is 3 is reset. On the other hand, in a device having a device ID other than 3, the selector 201 outputs a signal of a non-activated data line to the AND circuit 202, and therefore no reset signal is input to the SPC 203. For this reason, devices other than device ID 3 are not reset.
JP-A-7-84899 (FIG. 1, paragraphs 0025 to 0029)

  Here, consider a case where a SCSI device fails while driving a data line of a SCSI bus. In this case, the technique described in Patent Document 1 has a problem that when the initiator side drives the data line in order to recover the failed SCSI device, a bus fight occurs. For this reason, in such a case, the technique described in Patent Document 1 cannot selectively reset one of the plurality of devices.

  The present invention solves the above-mentioned problems of the prior art, and can selectively reset any device among the devices connected to the same bus even when the device fails while driving the bus line. The object is to provide bus connection equipment.

In order to achieve the above object, a bus system of the present invention includes a bus to which a plurality of bus connection devices can be connected, a device reset signal connected to the bus, and a device ID for designating a bus connection device to be reset. An initiator that transmits a target reset command including serial data via a reset signal line; and a decoder that decodes serial data transmitted via the reset signal line into parallel data when the target reset command is received; The device ID decoded by the decoder is collated with its own device ID, and a coincidence determination circuit that generates an in-device reset signal when both match is detected, and the bus-connected device is reset when the in-device reset signal is generated and a said bus connection device and a controller for the bus connection device, before Reset signal line is asserted, is fixed to a predetermined period a low level of the clock signal, after the predetermined period has elapsed, at a given time, a high level signal is latched reset type is a target reset command The initiator transmits the serial data again after transmitting the target reset command, and if the serial data cannot be transmitted within a predetermined time, a bus reset command for resetting the plurality of bus connection devices at the same time. It transmits to the said bus connection apparatus, It is characterized by the above-mentioned .

  In the bus system of the present invention, the bus-connected device compares the ID of the reset-target bus-connected device transmitted as serial data with its own device ID, and executes a reset when the two match. For this reason, even when a plurality of bus connection devices are connected to the same bus, only a specific bus connection device can be reset without affecting the entire system. In addition, since the ID of the bus connection device to be reset is transmitted as serial data, there is no need to add a new signal line, and the ID of the bus connection device to be reset is transmitted using the data line of the bus. There is no bus fight problem.

  In the bus system of the present invention, the initiator selects either the target reset command or a bus reset command for simultaneously resetting a plurality of bus connection devices connected to the bus via the reset signal line. It is preferable that transmission is possible. In this case, the initiator can reset only a specific bus connection device or can reset the bus connection devices all at once according to the situation.

  In the bus system of the present invention, when the initiator detects that a failure has occurred in the bus connection device, the initiator transmits a target reset command including a device ID of the bus connection device in which the failure has occurred, and after the transmission, for a predetermined time. It is preferable to transmit the bus reset command when the failure is not recovered. In this case, the initiator sends a target reset command to reset the bus connection device that caused the failure, so that the failure can be made without resetting the bus connection device other than the bus connection device that caused the failure. It can be recovered. In addition, if the bus failure cannot be recovered simply by resetting the bus connection device that caused the failure, the bus connection device connected to the bus is reset all at once by the bus reset command. Can be recovered.

The bus connection device of the present invention is a device that specifies a device reset signal and a bus connection device to be reset, transmitted via the reset signal line, in a bus connection device connected to a bus and an initiator including a reset signal line. A decoder that decodes serial data including an ID, a device ID decoded by the decoder and a device ID of the device, and a coincidence determination circuit that generates an in-device reset signal when a match between the devices is detected; When the internal reset signal is generated, the controller that resets the bus connection device and the serial data sent via the reset signal line are either the target reset command that specifies the reset target or the bus reset command that resets the bus connection device all at once and determining the reset type determination circuit or is, wherein the reset species Judgment circuit is the asserted reset signal line is fixed to a predetermined period a low level of the clock signal, after the predetermined period has elapsed, at a given time, a high level signal is latched reset type targets The initiator determines that the command is a reset command, and the initiator transmits the serial data again after transmitting the target reset command. If the serial data cannot be transmitted within a predetermined time, the initiator resets the plurality of bus connection devices all at once. A bus reset command to be transmitted is transmitted to the bus-connected device, and when the reset type determination circuit determines that the target reset command is received, the decoder decodes the serial data into parallel data.

  The bus-connected device of the present invention compares the ID of the reset-target bus-connected device transmitted as serial data with its own device ID, and executes a reset of its own device when they match. By doing so, when the device itself is not designated as the reset target, the operation can be continued without executing the reset, and the process is not interrupted. Therefore, for example, when a reset is issued by specifying the ID of the bus connection device that caused the failure at the time of failure recovery, only the specified bus connection device can be reset, and the time required for recovery can be reduced. Can be shortened.

Bus connection device of the present invention, when the reset type determination circuit determines that the a target reset command, it is preferable that the coincidence judgment circuit collates the device ID of the decoded device ID and its own in the decoder. In this case, if the reset type is a bus reset command, the bus connected device executes a reset, and if the reset type is a target reset command, the bus connected device executes a reset when the match determination circuit determines that the IDs match. .

The reset method of the present invention is a method of resetting a bus connected device connected to a bus, and a target reset command including a reset signal and a device ID designating a reset target bus connected device is serially transmitted via a reset signal line. Transmitting as data, and when receiving the target reset command, decoding the transmitted serial data into parallel data, and collating the decoded device ID with the device ID of each bus connected device; the result of collation, the step of resetting the bus connection device a match is detected in both a device ID, is asserted before Symbol reset signal line is fixed to a low level by a predetermined period of the clock signal, the predetermined period elapses after, at a given time, and when a high-level signal is latched reset type A step of determining a target reset command, and a plurality of bus connections connected to the bus when the serial data is transmitted again after the transmission of the target reset command and the serial data cannot be transmitted within a predetermined time. Transmitting a bus reset command for resetting the devices all at once to the bus-connected device .

  In the reset method of the present invention, the bus connection device compares the ID of the bus connection device to be reset transmitted as serial data with its own device ID, and executes a reset when the two match. For this reason, even when a plurality of bus connection devices are connected to the same bus, only a specific bus connection device can be reset without affecting the entire system. In addition, since the ID of the bus connection device to be reset is transmitted as serial data, there is no need to add a new signal line, and the ID of the bus connection device to be reset is transmitted using the data line of the bus. There is no bus fight problem.

  The reset method of the present invention includes a step of transmitting a bus reset command for simultaneously resetting a plurality of bus connection devices connected to the bus via the reset signal line, and a step of resetting the bus connection devices all at once. It is possible to adopt a configuration further comprising: In this case, when the occurrence of a failure in the bus connection device is detected, the target reset command designating the bus connection device is transmitted, and when the failure is not recovered within a predetermined time after the transmission, the bus reset command is transmitted. Is preferred. By doing so, for example, when a failure such as a bus hang occurs, the failure can be recovered by selectively resetting only the bus connection device that caused the failure. In addition, if the failure is not recovered by resetting only the bus connection device that caused the failure, the failure can be recovered by simultaneously resetting the bus connection devices connected to the bus. Can do.

  In the bus system and the reset method of the present invention, the ID of the bus connection device to be reset is transmitted as serial data via the reset signal line, so that even if the device fails while driving the bus line, the specific bus connection The device can be selectively reset. In addition, when the bus connection device of the present invention is not designated as a reset target, the bus connection device can continue to operate without performing a reset even when another bus connection device is reset.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a state of bus connection of a bus connection device according to an embodiment of the present invention. In the figure, only the reset signal line 11 of the bus lines connecting the initiator 10 and the n bus connection devices 20-1 to 20-n is shown, and the bus lines constituting the data lines and the like are omitted. It is illustrated. Each bus connection device 20 is configured as a data storage device such as a hard disk or an optical disk device. The initiator 10 transmits / receives data to / from each bus connection device 20 via a bus line.

  The initiator 10 monitors the status of data transfer when transferring data to and from the bus connection device 20. If the initiator 10 determines that the data transfer is not completed due to some problem and the bus hangs, the initiator 10 transmits a reset command to each bus connection device 20 via the reset signal line 11 and issues a reset. In the reset command transmitted by the initiator 10, the target reset command for specifying the bus connection device 20 to be reset among the plurality of bus connection devices 20 and resetting all of the plurality of bus connection devices 20 are reset. There is a bus reset command to that effect.

  When the initiator 10 transmits a reset command, the initiator 10 includes information specifying whether the reset command is a target reset command or a bus reset command. Further, when transmitting the target reset command, the initiator 10 transmits the ID of the bus connection device 20 to be reset to each bus connection device 20 as serial data via the reset signal line.

  The bus connection device 20 includes a reset signal decoding circuit 21, a device controller 22, and a target ID register 23. The target ID register 23 holds the ID of its own device. The reset signal decoding circuit 21 receives a reset command from the initiator 10 and determines whether the reset command is a target reset command or a bus reset command.

  When the reset signal decoding circuit 21 determines that the received reset command is a target reset command, the reset signal decoding circuit 21 compares the ID of the bus connection device 20 to be reset transmitted as serial data with the ID held in the target ID register 23. Then, it is determined whether or not the device is a reset target. When the reset signal decoding circuit 21 determines that the initiator 10 has designated itself as a reset target and has transmitted a target reset command, or determines that the initiator 10 has transmitted a bus reset command, the reset signal decoding circuit 21 activates the device controller 22. A reset signal is transmitted to instruct execution of the reset. The device controller 22 resets its own device based on the instruction.

  The initiator 10 monitors the response of the bus connection device 20 with a timer when transferring data to and from the target bus connection device 20. When the target bus connection device 20 becomes unable to respond due to some failure during data transfer, the initiator 10 sends a target reset command for resetting the bus connection device 20 to each bus connection via the reset signal line 11. Send to device 20. In this case, only the bus connection device 20 to be reset among the plurality of bus connection devices 20 is reset.

  The initiator 10 attempts to retry the interrupted data transfer after transmitting the target reset command. The initiator 10 monitors this retry with a timer, and determines that the bus connection device 20 designated as the reset target by the target reset command has failed to be reset and has become inoperable when data transfer is not resumed within a predetermined time. Then, a bus reset command is transmitted. In this case, all the bus connection devices 20 are reset.

  FIG. 2 is a block diagram showing the configuration of the reset signal decoding circuit 21. The reset signal decoding circuit 21 includes a reset condition determination unit 31, a serial / parallel conversion unit 32, a comparison / reset generation unit 33, an OR circuit 34, and a clock source 35. The clock source 35 generates a clock signal to be supplied to the reset condition determination unit 31 and the serial / parallel conversion unit 32.

  When the initiator 10 transmits a reset command, the reset condition determination unit 31 determines the reset type of the transmitted reset command. If the reset condition determination unit 31 determines that the reset type is target reset, the reset condition determination unit 31 enables the serial / parallel conversion unit 32. If the reset condition determination unit 31 determines that the reset type is a bus reset, the reset condition determination unit 31 outputs an activated signal Rst_Bus.

  When enabled by the reset condition determination unit 31, the serial / parallel conversion unit 32 converts the ID of the bus connection device 20 to be reset transmitted as serial data via the reset signal line 11 into parallel data. The comparison / reset generation unit 33 compares the ID of the bus connection device 20 to be reset converted into parallel data by the serial / parallel conversion unit 32 with the ID held by the target ID register 23. When the comparison / reset generation unit 33 determines that the two match, the comparison / reset generation unit 33 outputs the activated signal RST.

  The OR circuit 34 outputs a logical sum of the signal Rst_Bus output from the reset condition determination unit 31 and the signal RST output from the comparison / reset generation circuit 33. The output of the OR circuit 34 is connected to the device controller 22 (FIG. 1). When the OR circuit 34 outputs an activation level signal, the device controller 22 resets its own device.

  FIG. 3 is a timing chart showing how the reset signal line 11 changes when a reset command is transmitted. In the same figure, (A) shows how the signal level of the reset signal line 11 changes when the initiator 10 sends a target reset command, and (B) shows the reset signal when sending a bus reset command. The state of the signal level change of the line 11 is shown. When the reset signal line 11 is asserted and fixed to the L level for a predetermined period (T_rst) of the clock signal CLK, the reset condition determination unit 31 (FIG. 2) determines that a reset has been issued, and the next clock At the rising timing (time t1) of the signal CLK, the signal level of the reset signal line 11 is latched to determine whether the reset type is a target reset or a bus reset.

  When the reset condition determination unit 31 latches the H level signal at time t1, the reset condition determination unit 31 determines that the reset type is target reset (FIG. 3A). In this case, the reset condition determination unit 31 asserts the Ser_Par_En output and enables the serial / parallel conversion unit 32. Further, the Rst_Bus output is negated, and the deactivated signal is input to the OR circuit 34. When enabled by the reset condition determination unit 31, the serial / parallel conversion unit 32 latches the reset signal line 11 in synchronization with the rising timing of the clock signal CLK, and the bus connection to be reset transmitted as serial data. The ID of the device 20 is converted into parallel data.

  In the example of FIG. 3A, the serial / parallel converter 32 latches 4-bit serial data and outputs 4-bit parallel data “1101” from the output terminals OUT0 to OUT3. The serial / parallel converter 32 latches the valid bit transmitted following the ID at time t2, and when the latched valid bit is 0 (valid), asserts the EN output and sets the comparison / reset generation unit 33. Enable. When enabled by the serial / parallel converter 32, the comparison / reset generator 33 compares the ID held by the target ID register 23 with the ID output by the serial / parallel converter 32.

  The comparison / reset generation unit 33 asserts the RST output and inputs the activated signal to the OR circuit 34 when the two match as a result of the comparison. When the two do not match, the RST output is negated and the deactivated signal is input to the OR circuit 34. As a result, among the plurality of bus connection devices 20 connected to the same bus, the bus connection device 20 having the ID designated as the reset target by the initiator 10 is reset and is different from the reset target ID. The bus connection device 20 having the ID cannot be reset.

  When the reset condition determination unit 31 latches the L level signal at time t1, the reset condition determination unit 31 determines that the reset type is a bus reset (FIG. 3B). In this case, the reset condition determination unit 31 asserts the Rst_Bus output and inputs the activated signal to the OR circuit 34. In addition, the Ser_Par_En output is negated to disable the serial / parallel converter 32. As a result, in each bus connection device 20, a reset is applied regardless of the value of the ID held in the target ID register 23, and all the bus connection devices 20 connected to the same bus are reset.

  In the present embodiment, in the target reset, the initiator 10 transmits the ID of the bus connection device 20 to be reset via the reset signal line 11. When the transmitted ID and its own ID match, the bus connection device 20 executes a reset. By doing in this way, even when the several bus connection apparatus 20 is connected to the same bus | bath, the specific bus connection apparatus 20 can be reset separately. At this time, the reset does not propagate to a normal bus-connected device 20 in which no failure has occurred, so that the failure can be recovered without affecting the entire system, compared to a case where all the bus-connected devices 20 are reset. Thus, performance degradation can be minimized.

  In this embodiment, when the target is reset, the ID of the bus connection device 20 to be reset is transmitted as serial data via the existing reset signal line 11, and therefore it is necessary to provide a new signal line for transmitting the ID. The existing signal lines can be used effectively. In addition, there is no bus fight that becomes a problem when the ID of the bus connection device to be reset is transmitted via the data line.

  Although the present invention has been described based on the preferred embodiment, the bus connection device of the present invention is not limited to the above embodiment example, and various modifications and changes can be made from the configuration of the above embodiment. Those applied are also included in the scope of the present invention.

The block diagram which shows the mode of the bus connection of the bus connection apparatus of one Embodiment of this invention. 3 is a block diagram showing a configuration of a reset signal decoding circuit 21. FIG. The timing chart which shows the mode of a change of the reset signal line when a reset command is transmitted. The block diagram which shows the structure of the reset ID identification circuit which the SCSI apparatus described in patent document 1 has.

Explanation of symbols

10: Initiator 11: Reset signal line 20: Bus connection device 21: Reset signal decoding circuit 22: Device controller 23: Target ID register 31: Reset condition determination unit 32: Serial / parallel conversion unit 33: Comparison / reset generation unit 34: OR circuit 35: clock source

Claims (8)

A bus to which multiple bus connection devices can be connected;
An initiator connected to the bus and transmitting a target reset command including a device reset signal and a device ID designating a bus connection device to be reset as serial data via a reset signal line;
When the target reset command is received, a decoder that decodes serial data transmitted via the reset signal line into parallel data, a device ID decoded by the decoder and a device ID of the device are collated, The bus connection device having a match determination circuit that generates an in-device reset signal when a match is detected, and a controller that resets the bus connection device when the in-device reset signal is generated,
Said bus connection device, the reset signal line is asserted, it is fixed to a predetermined period a low level of the clock signal, after the predetermined period has elapsed, at a predetermined time, resetting the type of a high level signal is latched Is a target reset command,
The initiator transmits the serial data again after transmitting the target reset command, and if the serial data cannot be transmitted within a predetermined time, a bus reset command for simultaneously resetting the plurality of bus connected devices is connected to the bus. Send to device,
A bus system characterized by this.   The initiator can selectively transmit either the target reset command or a bus reset command for simultaneously resetting a plurality of bus connection devices connected to the bus via the reset signal line. The bus system according to claim 1.   When the initiator detects that a failure has occurred in the bus connection device, the initiator transmits a target reset command including the device ID of the bus connection device in which the failure has occurred, and the failure is not recovered within a predetermined time after the transmission. The bus system according to claim 2, wherein the bus reset command is transmitted to the bus system. In the bus connection device connected to the bus and initiator including the reset signal line,
A decoder that decodes serial data that is transmitted via the reset signal line and includes a device reset signal and a device ID that designates a bus connection device to be reset, a device ID decoded by the decoder, and its own device ID And a match determination circuit that generates an in-device reset signal when both match is detected, a controller that resets the bus-connected device when the in-device reset signal is generated, and the reset signal line A reset type determination circuit that determines whether the serial data is a target reset command that designates a reset target or a bus reset command that resets bus-connected devices all at once.
The reset type determination circuit is reset to a low level for a predetermined period of the clock signal when the reset signal line is asserted, and when a high level signal is latched at a predetermined time after the predetermined period elapses . Judge that the type is target reset command,
The initiator transmits the serial data again after transmitting the target reset command, and if the serial data cannot be transmitted within a predetermined time, a bus reset command for simultaneously resetting the plurality of bus connected devices is connected to the bus. To the device,
When the reset type determination circuit determines the target reset command, the decoder decodes the serial data into parallel data.
A bus connection device characterized by that.   The bus connection device according to claim 4, wherein when the reset type determination circuit determines that the target reset command is issued, the match determination circuit collates the device ID decoded by the decoder with its own device ID. In a method of resetting a bus connection device connected to a bus,
Transmitting a target reset command including a reset signal and a device ID for designating a bus connection device to be reset as serial data via a reset signal line;
When receiving the target reset command, decoding the transmitted serial data into parallel data, and collating the decoded device ID with the device ID of each bus connection device;
Resetting the bus connection device in which the matching of both device IDs is detected as a result of the verification ; and
Is asserted before Symbol reset signal line is fixed to a predetermined period a low level of the clock signal, after the predetermined period has elapsed, at a given time, a high level signal is latched reset type on the target reset command A step of judging that there is,
After the transmission of the target reset command, the serial data is transmitted again, and when the serial data cannot be transmitted within a predetermined time, a bus reset command for resetting a plurality of bus connection devices connected to the bus at the same time Transmitting to the connected device,
The reset method characterized by the above-mentioned.   The method further comprises: a step of transmitting a bus reset command for simultaneously resetting a plurality of bus connection devices connected to the bus via the reset signal line; and a step of resetting the bus connection devices all at once. 6. The resetting method according to 6.   8. When a failure occurrence of a bus connection device is detected, the target reset command designating the bus connection device is transmitted, and when the failure is not recovered within a predetermined time after the transmission, the bus reset command is transmitted. Reset method as described in.

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