GB2457147A

GB2457147A - Reading back data on an I2C bus to detect transmission errors

Info

Publication number: GB2457147A
Application number: GB0900800A
Authority: GB
Inventors: Thomas Hess; Giovanni Cautillo; Ulrich Weiss; Michael Andres
Original assignee: International Business Machines Corp
Current assignee: International Business Machines Corp
Priority date: 2008-02-08
Filing date: 2009-01-19
Publication date: 2009-08-12
Anticipated expiration: 2029-01-19
Also published as: GB0900800D0; GB2457147B

Abstract

Data is written by a master device to a slave device using an I2C bus and then read back to verify that there were no transmission errors. The data may be transferred from a command register 21 on the master into one or more staging registers 23 on the slave, read back from the staging registers and verified by the master. If the data is successfully verified, the master may send a commit command 24 to cause the slave to transfer the data to the corresponding device register 22. After the data is processed, the master may send a copy back command 25 to copy the data back to the staging register. The master may then read the data once more and verify that it is still valid.

Description

DESCRIPTION

Method to write data from an 12C master to an 12C slave

Technical field:

The present invention relates to Inter-Integrated Circuit bus (12C bus) data transfr and more particularly to a Method for failure tolerant data communication via an 12C bus.

Background of the invention:

The 12C bus is a standard developed by Philips that is used to attach low-speed peripherals to a motherboard, embedded system, or celiphone. In the document "The 12C-Bus specification, Version 2.1, January 2000" is given some introduction to the running of such 12C-Bus. This protocol has no error detection or error correction implemented.

Thereby attention must be paid that such error detection or correction is different to collision detection, which is a standard mechanism implemented in 12C to allow multiple 12C masters to access to the same bus. The collision detection is used for arbitration if more than one 12C masters access the 12C bus at the same time. But this cannot help to correct errors in case of electrical disturbances, which is one possibility that 12C data transfers can be tampered due to errors in the signal path. If such erroneous or corrupted data is then used unchecked in the 12c device it can create a major malfunction of the device or even the whole system.

Thus today I2C is used in applications, which can accept failures during operation. If failsafe systems are designed, 12C cannot be used of the shelf or the system must be designed for maximum signal integrity.

From EP 1 607 864 A]. it is known to implement a watchdog timer for the data communication via the 12C bus in order to provide an efficient and convenient way of ensuring that the 12C bus will not be stuck low during data communication between a master and a slave, e.g. between a TV microprocessor and a DVD module microprocessor in a TV-DVD combo device.

Object of the invention: It is thus an object of the invention to develop a method to write data from an 12C master to an 12C slave via an 12C bus, which method and device allow to detect and correct possible corrupted data before using such data for operation.

Summary of the invention:

The shortcomings of the prior art are overcome and

additional advantages are provided by a method to write data from an 12C master to an 12C slave, according to which method in order to detect and correct possible corrupted data before being used for operation, on the master side the data gets sent and read back.

A main idea of the invention is to detect and correct possible corrupted data before being used for operation. The proposed solution is based on the standard 12C protocol.

Data are transferred into a slave staging register before being read back. It is possible to increase the safety of the operation by adding some verification step.

According to a preferred embodiment of the invention, the data are transferred into a slave staging register before being read back.

According to another preferred embodiment of the invention, the safety of the operation is increased by adding at least one verification step.

Thereby it is thinkable that a verification step is performed by comparing the sent and read back data, wherein in case of a match a commit command is sent to the slave, telling the slave to issue the requested transaction.

According to an additional preferred embodiment of the invention, to perform the sending and back reading as well as the comparison, the 12C protocol is expanded. According to the state of the art the 12C protocol schedules an 12C frame comprising a start bit, which defines a start condition, a device address byte and one or more data bytes plus a stop bit which is the 12C stop condition. According to the invention the 12C protocol preferably is at least expanded in a way that two device address bytes are foreseen, wherein in order to allow failure detection, the first device address byte is e.g. error coded and the second device address byte is inverted. The same is performed with the data bytes. Thus regarding the device address bytes only, in comparison to the state of the art, where if an 12C device only needs one device address byte, the second device address byte does not exist and is used as a data byte, according to the invention both device address bytes comprise the same information, wherein e.g. the bits of the second device address byte are inverted to allow an error detection. The same is foreseen for the data bytes. Thereby according to the invention at least some of the data bytes can also be used for other purposes, like e.g. addressing the staging registers and the like.

This extension preferably on both sides, the master and the slave sides, is implemented either in hardware or firmware.

Preferably in small 12C slave devices this change will be implemented in hardware.

According to a particularly preferred embodiment of the invention, the method comprises the following steps: -in a first step data is written to one or more specified slave staging registers; -in a second step data is read from said one or more specified slave staging registers data is written to in step; -in a third step a comparison of the written and read data takes place, wherein in case of a compare error during this verification step the first, the second and the third steps can be retried several times; -in a fourth step a commit command is sent which copies the data from the at least one slave staging register to at least one slave device register; -in a fifth step a copy back command is sent which copies the data from the at least one slave device register back to the at least one slave staging register.

It can be foreseen that in an additional sixth step the data is read from the slave device register which in a seventh step is compared with the data written in the first step, wherein if this comparison is error-free, the procedure ends, and wherein the procedure starts again with the first step if the comparison shows an error, i.e. a data corruption.

The foregoing, together with other objects, features, and advantages of this invention can be better appreciated with reference to the following specification, claims and drawings.

Brief description of the drawings, with:

Fig. 1 showing a high level flow diagram of a method to write data from an 12C master to an 12C slave.

Fig. 2 showing a slave staging-register mechanism performing a method to write data from an 12C master to an 12C slave.

Fig. 3 showing an abstract view of an 12C frame 30.

Detailed description of the drawings:

12c data can be corrupted during transfer via the 12C bus and issue unwanted actions on an 12C device. To make 12C controlled devices safe, according to the invention the handling of the data transmitted according to the 12C protocol is expanded. This expansion concerns two necessary changes: (I) On the master side the data gets sent and read back.

(II) The sent and read back values are compared and in case of a match a commit command is sent to a slave device. This commit command tells the device to issue the requested transaction.

The extension on both sides can either be implemented in hardware or firmware.

A high level flow diagram 10 of a method to write data from an 12C master to an 12C slave is shown in Fig. 1. In the following, said method is described with reference to Figs. 1 and 2.

In a first step 01 it is foreseen that a command Write_data() writes data to one or more specified slave staging registers 23.

In a second step 02 it is foreseen that a command Read_data() reads data from said one or more specified slave staging registers 23 data is written to in step 01.

In a third step 03 a comparison of the written and read data takes place. In case of a compare error during this verification step 03 the first step 01, the second step 02 and the third step 03 can be retried several times.

Since an error, i.e. a data corruption, can also occur during read, it is thinkable to read several times, e.g. two times data from said one or more specified slave staging registers 23 data is written to in step 01 and to compare said data read. If the read data are identical, it is assumed that no read error occurred. If the data read differ, a read error is assumed and preferably the reading is retried or the first step 01 and the second step 02 are repeated.

In a fourth step 04 it is foreseen that a command Send_commjt() sends a commit command 24 which copies the data from the at least one slave staging register 23 to at least one slave device register 22.

In a fifth step 05 it is foreseen that a command Send_copy_back() sends a copy back command 25 which Copies the data from the at least one slave device register 22 back to the at least one slave staging register 23.

In a sixth step 06 a command Read_data() reads the data from the slave staging register 23 which in a seventh step 07 are compared with the data written in the first step 01. If this comparison is error-free, the procedure ends in an eight step 08. If the comparison in the seventh step 07 shows an error, i.e. a data corruption, the procedure starts again with the first step 01.

In the sixth step 06 also a reading error can occur as already described with reference to the second step 02. Thus it is also thinkable to read several times, e.g. two times data from said one or more specified slave staging registers 23 and to compare said data read. If the read data are identical, it is assumed that no read error occurred. If the data read differ, a read error is assumed and preferably the reading is retried.

An abstract view of a slave staging register mechanism 20 performing the method described above is shown in Fig. 2.

Thereby the commit command 24 and the copy back command 25 are write sequences to a command register 21.

In order to make the transfer to the command register 21 safe, the first half of a command 24, 25 is bit coded and all bits are inverted in the second half of the command 24, 25.

Fig. 3 represents an 12C frame 30 comprising data to be transmitted via the 12C bus. Each frame 30 for example consists of a two byte device address 31, 32, a two byte register offset 33, 34 and one or more data bytes 35. The frame 30 starts with the 12C start condition 36 and ends with the 12C stop condition 37. Preferably the device address 31, 32 and the register offset 33, 34 are sent twice, for example the second part 32, 34 can be inverted or not. It is also thinkable to send the device address only once, i.e. that the device address 32 is not necessary, i.e. is optional.

It is important to mention that also additional commands can be exchanged between 12C master and slave.

While the present invention has been described in detail, in conjunction with specific preferred embodiments, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art in light of the foregoing description. it is therefore contemplated that the appended claims will embrace any such alternatives, modifications and variations as falling within the true scope and spirit of the present invention.

Claims

CLAIMS1. Method to write data from an 12C master to an 12C slave characterized in that in order to detect and correct possible corrupted data before being used for operation, on the master side the data gets sent and read back.
2. Method according to claim 1, characterized in that the data are transferred into a slave staging register (23) before being read back.
3. Method according to claim 1 or 2, characterized by increasing the safety of the operation by adding at least one verification step.
4. Method according to claim 3, characterized in that a verification step is performed by comparing the sent and read back data, wherein in case of a match a commit command is sent to the slave, telling the slave to issue the requested transaction.
5. Method according to one of the previous claims, characterized in that to perform the sending and back reading as well as the comparison, the 12C protocol is expanded.
6. Method according to claim 5, characterized in that the extension on the master and the slave sides is implemented either in hardware or firmware.
7. Method according to one of the previous claims, characterized in that: -10 - -in a first step (01) data is written to one or more specified slave staging registers (23); -in a second step (02) data is read from said one or more specified slave staging registers (23) data is written to in step 01; -in a third step (03) a comparison of the written and read data takes place, wherein in case of a compare error during this verification step (03) this can be retried several times; -in a fourth step (04) a commit command (24) is sent which copies the data from the at least one slave staging register (23) to at least one slave device register (22); -in a fifth step (05) a copy back command (25) is sent which copies the data from the at least one slave device register (22) back to the at least one slave staging register (23).
8. Method according to claim, 7, characterized in that in an additional sixth step (06) the data is read from the slave staging register (23) which in a seventh step (07) is compared with the data written in the first step (01), wherein if this comparsion is error-free, the procedure ends, and wherein the procedure starts again with the first step (01) if the comparsion shows an error.