JP4972907B2 - Dot clock recovery circuit - Google Patents

Description

  The present invention relates to a multi-scan display and television signal processing circuit capable of displaying video signals of various personal computers and workstations, and more particularly to a dot clock of a video display device having a sampling circuit system such as a matrix display device. Regarding playback.

  The video signal of a personal computer or workstation is generated by an internal video clock, and the video signal level changes at a cycle that is an integral multiple of one cycle of this clock, and is written into a matrix display element or memory for signal processing. In order to perform the above, a sampling clock that matches the cycle of the video clock is required. However, in general, the video clock is not output to the output terminal of the video signal of a personal computer or the like. On the other hand, the horizontal synchronization signal and the vertical synchronization signal generated at the same time as the video signal are output. Since this is generated by dividing the video clock inside the personal computer or the like, the PLL ( (Phase Locked Loop)) The sampling clock was regenerated by multiplying the horizontal synchronization signal by a circuit.

  FIG. 9 shows a conventional circuit configuration. In FIG. 9, reference numeral 901 denotes a synchronization signal input terminal, 902 a clock multiplication means, 903 a phase adjustment means, and 904 a clock signal output terminal.

As described above, conventionally, the clock signal is generated directly from the input synchronization signal. As a document describing a conventional example, there is, for example, JP-A-9-62222.
JP-A-9-62222

  However, in the configuration described above, it is necessary to multiply the horizontal synchronizing signal directly to the dot clock frequency. Normally, the horizontal synchronizing signal is on the order of several tens to hundreds of tens of kHz, whereas the dot clock is on the order of several tens of MHz, so the multiplication factor of the PLL is several thousand times.

  In general, the higher the multiplication rate, the larger the jitter (the jitter characteristic becomes worse) in the PLL. Therefore, a high technical capability is required to realize a PLL with a high multiplication rate and low jitter, and is expensive.

  Further, since the DLL is used as the phase adjustment means, there is a problem that the phase adjustment accuracy is poor. Or there existed a subject that cost will become high when DLL with sufficient precision is used.

  The present invention has been made in view of the above-described problems of the prior art, and an object of the present invention is to provide a dot clock recovery circuit using a low multiplication PLL which is inexpensive and has good jitter characteristics.

  It is another object of the present invention to provide a dot clock recovery circuit that realizes phase adjustment without using a DLL.

The first invention of the present application includes at least a synchronization signal input terminal, an A / D conversion unit, a phase frequency comparison unit, an oscillation unit, and a clock multiplication unit, and the synchronization signal input from the synchronization signal input terminal Input to the A / D conversion means, an output of the A / D conversion means is input to the phase frequency comparison means, an output of the phase frequency comparison means is input to the oscillation means, and is generated by the oscillation means A clock signal is input to the clock multiplication means;
Further, in the clock recovery circuit in which the clock signal output from the clock multiplication means is connected to the A / D conversion means and the phase frequency comparison means, depending on the frequency comparison result detected by the phase frequency comparison means The oscillating means is controlled.

  The second invention of the present application includes at least a synchronization signal input terminal, an A / D conversion unit, a phase frequency comparison unit, an oscillation unit, a clock multiplication unit, and further includes a low-pass filter. A synchronization signal from a terminal is input to the low-pass filter, an output of the low-pass filter is input to the A / D conversion unit, an output of the A / D conversion unit is input to the phase frequency comparison unit, and the phase frequency The output of the comparison means is input to the oscillation means, the clock signal generated by the oscillation means is input to the clock multiplication means, and the clock signal output from the clock multiplication means is the A / Detected by the phase frequency comparison means in the clock recovery circuit connected to the D conversion means and the phase frequency comparison means It said oscillating means by the frequency comparison result in which is configured to be controlled.

  According to the first invention of the present application, at least the synchronization signal input terminal, the A / D conversion means, the phase frequency comparison means, the oscillation means, and the clock multiplication means are provided, and the frequency detected by the phase frequency comparison means By adopting a configuration in which the oscillating means is controlled according to the detection result, it is possible to use a PLL with a low multiplication factor, and it is possible to realize a dot clock recovery circuit with low jitter characteristics. Furthermore, phase adjustment can be performed without using a DLL by incorporating a phase adjustment circuit in the phase frequency comparison means.

  Further, according to the second invention of the present application, in addition to the configuration of the first invention of the present application, the low-pass filter is arranged in front of the A / D conversion means, thereby increasing the number of samples in the A / D conversion means and reproducing. There is an effect that the frequency accuracy of the dot clock is improved. The same effect as that of the first invention of the present application can be realized at the same time.

  Hereinafter, embodiments of the present invention will be described with reference to FIGS.

(Embodiment 1)
FIG. 1 is a block diagram of a dot clock recovery circuit according to the present invention.

  In FIG. 1, 101 is a synchronization signal input terminal, 102 is an A / D conversion means for converting an analog signal into a digital signal, 103 is a comparison means for comparing clock phases, and 104 is in accordance with a signal from 103. Oscillating means 105 that can change the frequency of the clock, and 105 is a clock multiplying means for generating a clock having a higher frequency based on the input clock signal. Examples of the oscillation means 104 include a VCO (voltage controlled oscillator), and examples of the clock multiplication means 105 include a PLL (Phase Locked Loop). Reference numeral 106 denotes an oscillation control signal, and 107 denotes a clock signal generated by the circuit of the present application. Reference numeral 108 denotes an output terminal for the generated clock signal. Reference numeral 109 denotes an input terminal for inputting various setting signals to be described later. The setting signal may be input from the outside as shown in FIG. 1 or may be incorporated inside.

  In FIG. 1, the synchronization signal input from the synchronization signal input terminal 101 is input to the A / D conversion means 102. The A / D conversion means 102 converts the input synchronization signal into a digital signal. A clock generated by the clock multiplication means 105 is used as the sampling clock at that time.

  A signal from the A / D conversion means 102 is input to the phase frequency comparison means 103. The phase frequency comparison means 103 compares the inputted synchronization signal with the internally generated phase comparison signal. In order to explain more specifically, FIG. 2 shows an example of the phase frequency comparison means 103.

  First, the components of the phase frequency comparison means shown in FIG. 2 will be briefly described.

  Reference numeral 201 denotes a slice circuit for removing noise from the synchronization signal, and performs slice processing according to the magnitude relationship with the slice reference signal.

  A counter circuit 202 counts up when a clock signal is input. In addition to the clock, a clock number setting value is input to the counter circuit. The clock number setting value is used to set whether to generate from one synchronization signal to the next synchronization signal. For example, if the clock number setting value is set to 1000, 1000 clocks are generated from one synchronization signal to the next synchronization signal. The counter circuit outputs a pulse of one clock width (hereinafter referred to as a lamp reset pulse) every time the counter value reaches the clock number set value. This situation is shown in FIG. In FIG. 3, (A) represents a clock number setting value, (B) an input clock signal, and (C) represents an output pulse (lamp reset pulse). Here, x is a clock number setting value. In this way, the counter circuit counts up every clock, and when it reaches the value set by the clock setting value, it outputs a ramp reset pulse having a width of one clock and resets the counter value to zero.

  Reference numeral 203 denotes a ramp waveform generation circuit. FIG. 4 shows the operation of the ramp waveform generation circuit. In FIG. 4, (A) is a lamp reset pulse, and (B) is an output waveform (ramp waveform). The run preset pulse is generated by the counter circuit. As shown in FIG. 4, the ramp waveform generation circuit 203 resets the output when a lamp reset pulse is input, and generates a waveform that monotonously increases until the next lamp reset pulse is input. In the example of FIG. 4, the case where the value at the time of reset is 0 is shown, but it goes without saying that this is not limited to this depending on the circuit configuration.

  Reference numeral 204 denotes a phase adjustment circuit. The phase adjustment circuit 204 shifts the phase of the ramp waveform generated by the ramp waveform generation circuit 203, and the phase is determined by a phase control signal input from the outside. The internal configuration of the phase adjustment circuit 204 will be described later.

  Reference numeral 205 denotes a multiplier. The multiplier 205 receives the synchronization signal output from the slice circuit 201 and the ramp waveform output from the phase adjustment circuit 204, and multiplies each of them.

  Reference numeral 206 denotes a low-pass filter that removes high-frequency components.

  Reference numeral 207 denotes an inverting circuit. Reference numeral 208 denotes an offset circuit.

  Next, the operation of the circuit shown in FIG. 2 will be described.

  First, the counter circuit 202 generates a lamp reset pulse for determining the lamp generation timing from the input clock signal.

  Next, the ramp generation circuit 203 generates a ramp waveform based on the reset pulse generated by the counter circuit.

  Next, the phase of the ramp waveform generated by the ramp generation circuit 203 is adjusted by the phase adjustment circuit 204. The magnitude to be adjusted can be realized by adding the phase control signal to the ramp waveform. If the phase control signal is a positive or negative value, the phase can be adjusted in either the positive or negative direction.

  On the other hand, the synchronization signal input from the outside is sliced by the slice circuit 201. The synchronization signal subjected to the slice processing is input to the multiplier 205.

  A multiplier 205 multiplies the sliced synchronization signal and the ramp waveform phase-adjusted by the phase adjustment circuit 204.

  Next, the output of the multiplier is input to the low-pass filter 206, and high-frequency components are removed by the low-pass filter.

  Next, the output of the low-pass filter 206 is inverted by the inverting circuit 207, and further, the DC offset is added by the offset circuit 208 and output as an oscillator control signal. The pull-in range of this circuit can be adjusted by the offset circuit 208.

  The operation of the phase frequency comparison unit shown in FIG. 2 has been described above.

  Returning to the description of FIG.

  The oscillator control signal output from the phase frequency comparison unit 103 is input to the oscillation unit 104. The oscillating means 104 has a function capable of changing the output frequency in proportion to the magnitude of the input value. FIG. 5 shows the input / output characteristics of the oscillation means 104. Examples of the oscillation means 104 include a voltage controlled oscillator (VCO) and a digital voltage controlled oscillator (DVCO). Here, VCO indicates that the input value is an analog signal, and DVCO indicates that the input value is a digital signal. In the example of the present application, since the phase frequency adjusting circuit is realized by a digital circuit, a digital voltage controlled oscillator (DVCO) is assumed to be used, and the following description will be given. A D / A converter that converts a digital signal into an analog signal is described below. It goes without saying that a voltage controlled oscillator (VCO) can be used if used.

  The oscillating means 104 outputs a clock signal based on the oscillator control signal from the phase frequency comparing means 103.

  Finally, the clock multiplying unit 105 multiplies the frequency of the clock signal from the oscillating unit 104 by a predetermined multiplication factor. The clock signal output from the clock multiplier 105 becomes a dot clock signal regenerated from the synchronization signal. The clock signal output from the clock multiplier 105 is also input to the A / D converter 102 and the phase frequency comparator 103.

  The connection relation of the clock recovery circuit shown in FIG. 1 and the basic operation description of each component have been described above.

  Next, the operation principle of this circuit will be described. In order to explain in time series, the concept of an arbitrary continuous period is used.

  Here, it is assumed that the frequency of the clock signal in the initial state is the frequency f0.

  First, at the first timing, a clock signal having a frequency f0 (referred to as “107 (f0)”) is input to the A / D conversion unit 102 and the phase frequency comparison unit 103. Further, the synchronization signal input from the outside is A / D converted by the clock signal 107 (f 0) and input to the phase frequency comparison means 103.

  Inside the phase frequency comparison means 103, the ramp waveform generated by the clock signal 107 (f0) and the synchronization signal are subjected to the above-described processing, and the first oscillation control signal (referred to as “106 (1)”). Is called). Further, a first clock signal (referred to as “107 (f1)”) having a first frequency (referred to as f1) is obtained by 106 (1) through the oscillation means 104 and the clock multiplication means 105. . Here, the period of the clock signal (Tclock), the period of the synchronization signal (Tsync), and the clock number setting value satisfy Expression (1).

Tsync = Tclock × clock number setting value (1)
Next, at a second timing subsequent to the first timing, processing similar to the operation at the first timing described above is performed, and a second oscillation control signal (referred to as 106 (2)), A second clock signal (referred to as 107 (f2)) having a frequency of 2 (referred to as f2) is obtained.

  Here, when 106 (2)> 106 (1), the relationship between f2 and f1 is f2> f1, and when 106 (1)> 106 (2), the relationship between f2 and f1 is f1>. f2.

  Similarly, at the n-th timing, an arbitrary oscillation control signal 106 (n) is output, and at the same time, a clock signal 107 (fn) having a certain frequency fn is generated. The frequency comparison is performed again by the phase frequency comparison means using this clock signal 107 (fn), and an oscillation control signal 106 (n + 1) is obtained.

  If the frequency of fn is too high, the oscillation control signal 106 (n + 1) is output with a value smaller than that of the oscillation control signal 106 (n), so that the next generated clock signal 107 (fn + 1) is the clock. The frequency is lower than that of the signal 107 (fn).

  On the other hand, when the frequency of fn is too low, the oscillation control signal 106 (n + 1) is output with a larger value than the oscillation control signal 106 (n), so that the next generated clock signal 107 (fn + 1) is The frequency is higher than that of the clock signal 107 (fn).

  Thus, a loop is formed such that the output result from the phase frequency comparison means converges to a constant value, and the frequency of the clock signal 107 is stabilized so as to satisfy the expression (1).

  Here, if a PLL with a small multiplication rate is used as the clock multiplication means, the generated jitter can be suppressed to a low level and can be realized at low cost. For example, if a multiplication factor of 100 or less is used, the jitter can be suppressed small.

  Next, a method for adjusting the phases of the synchronization signal and the clock signal will be described. The reason for adjusting the phase of the clock signal has been described in the conventional example, and is omitted here. Conventionally, a DLL (Delay Locked Loop) is used to adjust the phase of the clock signal. In this method, since the phase adjustment accuracy is affected by individual variations of a plurality of delay elements existing in the DLL, it is expensive to obtain a highly accurate phase adjustment performance. Therefore, in the present invention, a phase adjustment mechanism is built in the phase frequency comparison means. The internal configuration of the phase frequency comparison means will be specifically described with reference to FIGS.

  In FIG. 6, 601 is an adder, and 602 is a limiter circuit. The input ramp waveform and phase control signal are added by the adder 601, and the result is output after being limited by the limiter circuit 602. FIG. 7 shows an output waveform of the circuit of FIG. In FIG. 7, (B) is the original ramp waveform, and (A) and (C) are the ramp waveforms after being offset. (A) is obtained by adding the phase control signal to the waveform of (B), and (C) is obtained by subtracting the phase control signal from the waveform of (B). Here, L and (-L) represent a positive limit value and a negative limit value limited by the limit circuit, respectively. In this way, the phase of the ramp waveform can be adjusted by the adder and the limiter circuit. If the ramp waveform generated by the phase adjustment circuit is used, the phase adjustment between the synchronization signal and the clock signal 107 can be performed accurately. Therefore, by using this circuit, it is possible to realize the accuracy of phase adjustment at low cost and high accuracy.

  As described above, according to the first configuration of the present application, a dot clock recovery circuit having a low jitter characteristic and an inexpensive A / D converter, a voltage oscillator (or a digital voltage oscillator), and a low multiplication PLL is provided. Can be realized.

  Also, the phase adjustment of the sync signal and the clock signal can be realized with high accuracy and at low cost.

  Further, the synchronization signal in the text may be a horizontal synchronization signal or a vertical synchronization signal, but is more preferably a horizontal synchronization signal.

(Embodiment 2)
FIG. 8 shows a block diagram of a dot clock recovery circuit according to the second invention of the present application. In FIG. 8, since 101-107 are as having already been described, description is abbreviate | omitted. Reference numeral 801 denotes a low-pass filter (hereinafter referred to as LPF). Since the operation of the low-pass filter is as described above, description thereof is omitted.

  A feature of the present application is that an LPF 801 is disposed in front of the A / D conversion means 102. As a result, the edge of the input synchronization signal is smoothed, and the number of points sampled by the A / D conversion means increases. This increases the number of sample points when multiplying the ramp waveform in the phase comparison means 103, thereby improving the accuracy of the oscillation control signal 106 and improving the operational stability and accuracy of this circuit.

  The dot clock recovery circuit according to the present invention comprises at least a synchronization signal input terminal, an A / D conversion means, a phase frequency comparison means, an oscillation means, and a clock multiplication means, and is detected by the phase frequency comparison means. By adopting a configuration in which the oscillation means is controlled according to the frequency detection result, it is possible to use a low multiplication rate PLL, and it is possible to realize a dot clock recovery circuit with low cost and low jitter characteristics. Furthermore, by incorporating a phase adjustment circuit in the phase frequency comparison means, it becomes possible to adjust the phase without using DLL, and it is possible to display video signals of various personal computers and workstations. Display, especially dot clock recovery for video display devices with sampling circuit such as matrix display devices Oite is useful.

Block diagram of the dot clock recovery circuit in the first embodiment of the present application Block diagram of phase frequency comparison means in Embodiments 1 and 2 of the present application Operational diagram of counter circuit inside phase frequency comparison means in Embodiments 1 and 2 of the present application Operational diagram of ramp waveform generation circuit inside phase frequency comparison means in Embodiments 1 and 2 of the present application I / O characteristics diagram of oscillation means in embodiments 1 and 2 of the present application Block diagram of phase adjustment circuit inside phase frequency comparison means in first and second embodiments of the present application Operation diagram of phase adjustment circuit inside phase frequency comparison means in Embodiments 1 and 2 of the present application Block diagram of a dot clock recovery circuit in the second embodiment of the present application Block diagram of conventional example

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Synchronization signal input terminal 102 A / D conversion means 103 Phase frequency comparison means 104 Oscillation means 105 Clock multiplication means 106 Oscillation control signal 107 Clock signal 108 Clock signal output terminal 109 Set value input terminal

Claims (5)

A / D conversion means for A / D converting the synchronization signal;
Phase frequency comparison means for comparing the frequency of the output of the A / D conversion means and a dot clock signal described later to generate an oscillation control signal;
Oscillation means for generating a clock signal for changing an output frequency based on an oscillation control signal which is an output of the phase frequency comparison means;
A PLL that generates a dot clock signal having a higher frequency based on a clock signal that has a predetermined frequency multiplication rate and is an output of the oscillation means;
A dot clock recovery circuit. LPF that removes the high frequency component of the synchronization signal;
A / D conversion means for A / D converting the output of the LPF;
Phase frequency comparison means for comparing the frequency of the output of the A / D conversion means and a dot clock signal described later to generate an oscillation control signal;
Oscillation means for generating a clock signal for changing an output frequency based on an oscillation control signal which is an output of the phase frequency comparison means;
A PLL that generates a dot clock signal having a higher frequency based on a clock signal that has a predetermined frequency multiplication rate and is an output of the oscillation means;
A dot clock recovery circuit. 3. The dot clock recovery circuit according to claim 1 , wherein a frequency multiplication rate of the PLL is greater than 1 and 100 or less . 3. The dot clock reproduction circuit according to claim 1, wherein the phase frequency comparison unit includes a phase adjustment circuit that adjusts the phase of the synchronization signal and the dot clock signal . The phase adjustment circuit, the dot clock reproducing circuit according to claim 4, characterized in that it comprises an adder and a limiter.

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